WO2023240998A1

WO2023240998A1 - Data packet processing method, communication chip and computer device

Info

Publication number: WO2023240998A1
Application number: PCT/CN2022/142206
Authority: WO
Inventors: 胡培金
Original assignee: Oppo广东移动通信有限公司
Priority date: 2022-06-15
Filing date: 2022-12-27
Publication date: 2023-12-21
Also published as: CN115086248A

Abstract

A data packet processing method, a communication chip and a computer device, which belong to the technical field of computers. The method is executed by means of a communication chip, wherein the communication chip comprises a modem and a hardware accelerator. The method comprises: by means of a modem, determining a data type corresponding to a received data packet, and storing the data packet in a first queue, which matches the priority of the data type, among a plurality of first queues, wherein the priorities of the plurality of first queues are different (201); and by means of a hardware accelerator, sequentially processing data packets in the plurality of first queues in descending order of the priorities (202). By means of the method, a data packet corresponding to a data type with a higher priority is processed earlier, such that the flexibility of processing the data packet is improved, and the processing time delay of the data packet corresponding to the high-priority data type is reduced.

Description

Data packet processing method, communication chip and computer equipment

This application claims priority to the Chinese patent application with application number 202210677669.9 and the invention name "Data Packet Processing Method, Communication Chip and Computer Equipment" submitted on June 15, 2022, the entire content of which is incorporated into this application by reference. .

Technical field

The embodiments of the present application relate to the field of computer technology, and in particular to a data packet processing method, communication chip and computer equipment.

Background technique

The communication chip can receive data packets sent by other communication chips and process the data packets. In the related technology, the communication chip processes the data packet according to the reception time of the data packet. The earlier the reception time, the earlier the time for processing the data packet. The processing method is relatively simple. As the number and types of data packets increase, there is an urgent need to provide a more flexible data packet processing method.

Contents of the invention

Embodiments of the present application provide a data packet processing method, a communication chip and a computer device, which can improve the flexibility of processing data packets. The technical solution is as follows:

According to one aspect of the embodiment of the present application, a data packet processing method is provided, the method is executed by a communication chip, the communication chip includes a modem and a hardware accelerator; the method includes:

Through the modem, the data type corresponding to the received data packet is determined, and the data packet is stored in a first queue matching the priority of the data type among a plurality of first queues, wherein the plurality of first queues Queues have different priorities;

Through the hardware accelerator, the data packets in the plurality of first queues are sequentially processed in order from high to low priority.

According to another aspect of the embodiment of the present application, a communication chip is provided, which includes a modem and a hardware accelerator;

The modem is configured to determine the data type corresponding to the received data packet, and store the data packet into a first queue matching the priority of the data type among a plurality of first queues, wherein the plurality of first queues A queue has different priorities;

The hardware accelerator is configured to sequentially process the data packets in the plurality of first queues in order from high to low priority.

According to another aspect of the embodiment of the present application, a data packet processing method is provided, which is executed by a computer device. The computer device includes a communication chip and an application processing chip. The application processing chip includes a plurality of target memories; the method include:

Through the communication chip, the data type corresponding to the received data packet is determined, and the data packet is stored in the first queue matching the priority of the data type among the plurality of first queues, from high to low according to the priority. In order, the data packets in the plurality of first queues are processed in sequence, wherein the priorities of the plurality of first queues are different;

Through the communication chip, the tag of the allocated target memory is added to the processed data packet, and the tagged data packet is stored in the second queue, where the target memory allocated to the data packet corresponding to the same data type is the same and different. The target memory allocated to the data packet corresponding to the data type is different, and the target memory allocated to the data packet corresponding to the data type with a higher priority has a higher priority;

Through the communication chip, the data packets in the second queue are stored in the target memory corresponding to the tag carried;

Through the application processing chip, the data packets in the plurality of target memories are processed based on the priorities of the plurality of target memories.

According to another aspect of the embodiment of the present application, a computer device is provided. The computer device includes a communication chip and an application processing chip. The application processing chip includes a plurality of target memories;

The communication chip is used to determine the data type corresponding to the received data packet, and store the data packet into the first queue matching the priority of the data type among the plurality of first queues, in order from high to high priority. Process the data packets in the plurality of first queues in sequence in a lower order, wherein the priorities of the plurality of first queues are different;

The communication chip is also used to add a tag of the allocated target memory to the processed data packet, and store the tagged data packet into the second queue, where the data packets corresponding to the same data type are allocated the same target memory. , the target memory allocated to the data packets corresponding to different data types is different, and the higher the priority of the target memory allocated to the data packet corresponding to the data type with a higher priority, the higher the priority;

The communication chip is also used to store the data packets in the second queue to the target memory corresponding to the tag carried;

The application processing chip is configured to process data packets in the multiple target memories based on priorities of the multiple target memories.

In the embodiment of the present application, the modem in the communication chip determines the queue used to store the data packet according to the data type corresponding to the data packet. The higher the priority of the corresponding data type, the priority of the queue used to store the data packet. The higher the level, the hardware accelerator in the communication chip prioritizes processing of data packets in the high-priority queue to determine the processing order of data packets based on the data type corresponding to the data packet, so that the corresponding data type has a higher priority. Packets are processed earlier, which improves the flexibility of processing data packets and reduces the processing delay of data packets corresponding to high-priority data types.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 shows a schematic structural diagram of a communication chip provided by an exemplary embodiment of the present application;

Figure 2 shows a flow chart of a data packet processing method provided by an exemplary embodiment of the present application;

Figure 3 shows a flow chart of another data packet processing method provided by an exemplary embodiment of the present application;

Figure 4 shows a flow chart of yet another data packet processing method provided by an exemplary embodiment of the present application;

Figure 5 shows a schematic diagram of a data packet processing process provided by an exemplary embodiment of the present application;

Figure 6 shows a schematic structural diagram of a computer device provided by an exemplary embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

"At least one" mentioned in this article means one or more, and "plurality" means two or more. "And/or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the related objects are in an "or" relationship.

The terms "first", "second", etc. in the description and claims of this application and the above description of the drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the application described herein can be practiced in sequences other than those illustrated or described herein.

It should be noted that the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application, All are authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the data packages involved in this application were obtained with full authorization.

FIG. 1 is a schematic structural diagram of a communication chip 100 provided by an embodiment of the present application. Referring to Figure 1, the communication chip 100 includes a modem 101 and a hardware accelerator 102. The modem 101 is used to determine the data type corresponding to the received data packet, and store the data packet into multiple first queues to match the priority of the data type. The hardware accelerator 102 is configured to sequentially process data packets in multiple first queues in order from high priority to low priority.

The communication chip 100 can run on any computer device to implement the data packet processing method provided by this application. Optionally, the computer device is a terminal or a server, where the terminal includes mobile phones, desktop computers, notebook computers, tablet computers, wearable devices, vehicle-mounted terminals, household appliances, intelligent robots and other types of terminals. Optionally, the communication chip 100 is connected to the application processing chip to send the processed data packet to the application processing chip for continued processing.

The data packet processing method provided by the embodiment of this application can be applied in autonomous driving scenarios. For example, autonomous vehicles are equipped with communication chips and application processing chips. In addition to the self-driving function, the self-driving vehicle also has other functions, such as audio playback function. Correspondingly, an autonomous vehicle will receive a variety of data packets corresponding to different data types during driving. For example, data packets containing autonomous driving data and data packets containing audio data, where the autonomous driving data refers to data related to the autonomous driving of the vehicle, such as vehicle control data or environmental data around the vehicle, etc. Since the data type of autonomous driving data is "delay-sensitive" and the data type of audio data is "non-delay-sensitive", the "delay-sensitive" has a higher priority than "non-delay-sensitive". , therefore, after the modem in the communication chip receives a data packet containing autonomous driving data, it stores the data packet in the high-priority first queue, and after receiving a data packet containing audio data, it stores the data packet to the first queue of low priority, so that when the hardware accelerator in the communication chip sequentially processes the data packets in multiple first queues in order from high to low priority, the data packets containing the autonomous driving data can Priority is given to processing, thereby reducing the processing delay of the data packet. The hardware accelerator sends the processed data packet to the application processing chip. After the application processing chip processes the data packet containing the self-driving data, it controls the driving of the self-driving vehicle based on the self-driving data. After processing the data packet containing audio data, , play the audio data therein.

The data packet processing method provided by the embodiment of the present application can also be applied in other scenarios, and the embodiment of the present application does not limit this.

Figure 2 shows a flow chart of a data packet processing method provided by an exemplary embodiment of the present application. Referring to Figure 2, the method is executed by a communication chip. The communication chip includes a modem and a hardware accelerator. The method includes:

201. The communication chip determines the data type corresponding to the received data packet through the modem, and stores the data packet into the first queue matching the priority of the data type among the multiple first queues, where the priority of the multiple first queues different.

Among them, the data type corresponding to the data packet is the data type to which the data packet belongs. Optionally, the data type includes "delay-sensitive type" and "non-delay-sensitive type". "Delay-sensitive" data packets have strict requirements on delay, that is, the processing of the data packet must meet low-latency conditions. If the processing delay of the data packet is high, it may cause serious impact. "Non-delay-sensitive" data packets do not have strict requirements on delay. That is to say, the data packet does not need to meet the low-delay conditions. Even if the processing delay of the data packet is high, it will not cause serious impact. . Among them, the priority of "delay-sensitive type" is higher than the priority of "non-delay-sensitive type".

Optionally, "delay-sensitive" data packets include data packets corresponding to URLLC (Ultra Reliable Low Latency Communication) data. Among them, URLLC data includes data related to application scenarios such as Internet of Vehicles, industrial control, and telemedicine. Optionally, "non-delay-sensitive" data packets include data packets corresponding to eMBB (Enhanced Mobile Broadband, enhanced mobile broadband) data. Among them, eMBB data includes data related to ultra-high-definition video, virtual reality, augmented reality and other application scenarios. The priority of URLLC data is higher than that of eMBB data.

Optionally, the first queue is a FIFO (First Input First Output) memory. The FIFO memory is a first-in, first-out dual-port buffer, including an input port and an output port. The first one enters the FIFO memory 's data is moved out first. Optionally, the first queue is set at any location on the communication chip, for example, in a modem, or in a hardware accelerator, which is not limited in the embodiment of the present application. The multiple first queues in the communication chip have different priorities. In the first queue with a higher priority, the data type corresponding to the stored data packet has a higher priority.

Optionally, the data packet carries the corresponding data type, and the modem calls MAC (Medium Access Control, media access control), RLC (Radio Link Control, wireless link layer control) and PDCP (Packet Data Convergence Protocol), The packet data aggregation protocol) unit sequentially parses the received data packets to obtain the data type corresponding to the data packets.

Optionally, the priority corresponding to each data type and the priority corresponding to each first queue are stored in the communication chip. Correspondingly, after the modem determines the data type corresponding to the received data packet, it stores the data packet in multiple first queues. The first queue in the queue that matches the priority of the data type includes: the modem determines the priority of the data type, then determines the first queue consistent with the priority among the multiple first queues, and stores the data packet in The first queue. For example, if the priority of the data type corresponding to the data packet is the first priority, then a first queue with a priority of the first priority is determined from multiple first queues, and the data packet is stored in the first queue. Among them, the priority corresponding to each data type can be set as needed, and the embodiment of the present application does not limit this.

In a possible implementation, the plurality of first queues include a third queue and a fourth queue, the third queue matches the priority of the URLLC data, and the fourth queue matches the priority of the eMBB data. Correspondingly, the communication chip stores the data packet through the modem to the first queue matching the priority of the data type among the plurality of first queues, including: the communication chip uses the modem to store the data packet when the data packet belongs to URLLC data. Store the data packet in the third queue; or, if the data packet belongs to eMBB data, store the data packet in the fourth queue.

For example, the third queue and the fourth queue are the URLLC queue and the eMBB queue respectively. The URLLC queue has a higher priority than the eMBB queue. The eMBB queue is used to store data packets corresponding to eMBB data, while the URLLC queue is used to store Data packets corresponding to URLLC data with higher priority.

In the embodiment of this application, since URLLC data is more sensitive to delay than eMBB data, the priority of URLLC data is set to be higher than the priority of eMBB data, and a fourth queue with a lower priority is used to store eMBB data. For the corresponding data packet, a third queue with a higher priority is used to store the data packet corresponding to the URLLC data, so that when the data packet is subsequently processed according to the priority of the queue, the data packet corresponding to the URLLC data can be processed earlier, thus reducing the Processing delay of URLLC data.

202. The communication chip uses the hardware accelerator to sequentially process multiple data packets in the first queue in order from high to low priority.

Among them, the hardware accelerator is used to perform arbitrary processing operations on the data packet, such as parsing the header of the data packet, verifying the data packet, filtering the data packet to discard data packets containing target data, etc. This paper The application examples do not limit this.

Each time the modem in the communication chip receives a data packet, it stores the data packet in the corresponding first queue, and the hardware accelerator in the communication chip monitors multiple first queues, as long as there are pending packets stored in the multiple first queues. Data packets, the hardware accelerator will process the data packets in multiple first queues in order from high to low priority. That is, when there is a data packet in the first queue with the highest priority, the hardware accelerator processes the data packet in the first queue. When there is no data packet in the first queue, the hardware accelerator processes the next data packet. A priority packet is queued first, and so on.

Wherein, for any first queue, the hardware accelerator processes the data packets in the first queue according to the first-in-first-out principle, that is, the data packets stored in the first queue first are processed first. Since the data packets in any first queue correspond to the same data type, and the data packets with earlier reception time are stored in the first queue earlier, therefore, the packets in the first queue are processed according to the first-in, first-out principle. Data packets enable multiple data packets corresponding to the same data type. The earlier the data packet is received, the earlier it will be processed.

In this embodiment of the present application, the modem in the communication chip determines the queue used to store the data packet according to the data type corresponding to the data packet. The higher the priority of the corresponding data type, the higher the priority of the queue used to store the data packet. The higher the priority, the hardware accelerator in the communication chip prioritizes processing of data packets in the high-priority queue to determine the processing order of data packets based on the data type corresponding to the data packet, so that the corresponding data type has a higher priority. Data packets are processed earlier, which improves the flexibility of processing data packets and reduces the processing delay of data packets corresponding to high-priority data types.

Based on the embodiment shown in Figure 2, Figure 3 shows a flow chart of a data packet processing method provided by an exemplary embodiment of the present application. Referring to Figure 3, the method is executed by a communication chip, and the communication chip includes Modem, hardware accelerator and DMA (Direct Memory Access) controller. In this embodiment, the communication chip will also store the processed data packets to the target memory in the application processing chip to facilitate the application processing chip. Processing continues on the packet in destination memory. The method includes:

301. The communication chip determines the data type corresponding to the received data packet through the modem, and stores the data packet into the first queue matching the priority of the data type among the multiple first queues, where the priority of the multiple first queues different.

For the implementation of the above step 301, please refer to the above step 201, which will not be described again here.

302. The communication chip uses the hardware accelerator to sequentially process multiple data packets in the first queue in order from high to low priority.

In a possible implementation, the hardware accelerator is used to verify the data packets of the target type. Accordingly, the communication chip uses the hardware accelerator to sequentially process multiple first queues in order from high to low priority. The data packets include: the communication chip uses the hardware accelerator to determine the packet type of each data packet in the multiple first queues in order from high to low priority, and the currently determined packet type is the target type. In this case, the current data packet is verified. Optionally, the hardware accelerator is specially used to verify the data packets of the target type. Therefore, the verification efficiency of the hardware accelerator is very high. Then the hardware accelerator is used to verify the data packets of the target type, and then the application processing chip After sending the data packet, the application processing chip does not need to verify the data packet, which improves the overall processing efficiency of the data packet.

Optionally, verification includes accuracy verification, validity verification, etc., where accuracy verification refers to verifying whether errors occur in the data packet during transmission, and validity verification refers to verifying the data packet. Whether it is valid, for example, verifying whether the data packet is within the validity period. Optionally, the verification also includes other types of verification, which are not limited in the embodiments of this application.

Among them, the target type can be set to any type as needed, such as IP (Internet Protocol) data packets, UDP (User Datagram Protocol) data packets, TCP (Transmission Control Protocol) ) data packets, etc., the embodiments of this application do not limit this.

303. The communication chip uses the hardware accelerator to add the tag of the allocated target memory to the processed data packet, and stores the tagged data packet in the second queue.

Among them, data packets corresponding to the same data type are allocated the same target memory, and data packets corresponding to different data types are allocated different target memories. Moreover, each target memory has a corresponding priority, and the data type with a higher priority corresponds to The higher the priority of the target memory allocated to the data packet.

For example, the target memory allocated for URLLC data packets (i.e., data packets containing URLLC data) is the same, and the target memory allocated for URLLC data packets and eMBB data packets (i.e., data packets containing eMBB data) is different, and due to the priority of URLLC data level is higher than the priority of eMBB data, so the priority of the target memory allocated by the URLLC data packet is higher than the priority of the target memory allocated by the eMBB data packet.

Optionally, the second queue is a FIFO memory. For example, the second queue is a PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) FIFO memory. Optionally, the second queue is set at any location on the communication chip, for example, in a hardware accelerator, which is not limited in the embodiment of the present application.

In a possible implementation, the communication chip uses a hardware accelerator to add a tag of the allocated target memory to the processed data packet, including: the communication chip determines the target field in the header of the processed data packet through the hardware accelerator; When the target field meets the field conditions corresponding to any data type, the tag of the target memory corresponding to the data type is added to the processed data packet.

Among them, the target field can be set to any field as needed. Optionally, the destination field includes source address, destination address, source port, and destination port. The field conditions corresponding to any data type are used to filter the data packets corresponding to that data type. That is, if the target field in the header of any data packet meets the field conditions corresponding to that data type, it means that the data packet corresponds to that data type. type of data.

Optionally, the field conditions corresponding to each data type and the tags of the corresponding target memory are stored in the hardware accelerator, and the target memory is the target memory allocated for the data packet corresponding to the data type. Optionally, the field conditions corresponding to each data type and the corresponding label of the target memory are sent by the modem to the hardware accelerator. For example, after determining the data type corresponding to the data packet, the modem sends the field condition corresponding to the data type and the tag of the target memory corresponding to the data type to the hardware accelerator.

In the embodiment of this application, the target field in the header of the processed data packet meets the field conditions corresponding to any data type, indicating that the data packet corresponds to this data type. In this case, add The tag of the target memory corresponding to this data type ensures the accuracy of the added tag.

Optionally, during the process of the hardware accelerator sequentially determining the packet type of each data packet in the plurality of first queues in order from high to low priority, if the currently determined packet type is other than the target type In the case of other types, the tag of the allocated target memory is directly added to the data packet. That is to say, the hardware accelerator is only used to verify the target type of data packets, but not other types of data packets. This can reduce the complexity of the hardware accelerator structure and ensure the processing efficiency of the hardware accelerator.

304. The communication chip calls the DMA controller through the hardware accelerator to store the data packets in the second queue into the target memory corresponding to the tag carried.

Optionally, the communication chip sequentially stores the data packets in the second queue into the target memory. That is, the data packets that enter the second queue first are stored in the target memory first.

In the embodiment of this application, the hardware accelerator is used to store data packets corresponding to the same data type into the same target memory, and to store data packets corresponding to different data types into different target memories, and the target memory with a higher priority stores the data packets. The higher the priority of the data type corresponding to the data packet, the easier it is to process the data packets in each target memory differently in the future according to the priority of the target memory, so as to realize the differential processing of the data packets corresponding to the data types of different priorities and improve the processing of data. Package flexibility.

Since the DMA controller can transmit data without occupying the processing resources of the central processor in the communication chip, it will not affect the work of the central processor. Moreover, since the DMA controller has high data transmission efficiency, the hardware The accelerator calls the DMA controller to transfer the data packet from the second queue to the target memory, thereby improving the efficiency of storing the data packet into the target memory.

Optionally, the target memory is a memory in an application processing chip. After the communication chip stores the data packet into the target memory through the hardware accelerator, the application processing chip continues to process the data packet in the target memory.

305. The communication chip uses the hardware accelerator to determine the timing duration of the current target timer each time it stores a data packet into the corresponding target memory. When the timing duration has reached the target timing duration, it sends an interrupt signal to the application processing chip. , and restart the target timer.

Among them, the target timer is a timer corresponding to the data type corresponding to the data packet, and the target timer of the timer corresponding to the data type with a higher priority is shorter.

Among them, the interrupt signal is used to request the application processing chip to process the data packets in the target memory, that is, to request the application processing chip to stop the operation currently being executed and instead process the data packets in the target memory. Since frequent interrupts will affect the processing efficiency of the application processing chip and increase the load on the application processing chip, the hardware accelerator uses a timer to control the frequency of interrupting the application processing chip. Only when the target timer's timing reaches the target timing, the hardware accelerator will That is, the interrupt signal is sent to the application processing chip only when the interval between the time when the data packet is stored in the target memory and the time when the interrupt signal was last sent reaches the target timing length, instead of just storing the data packet in the target memory. Sending an interrupt signal to the application processing chip effectively reduces the frequency of interrupting the application processing chip. In addition, the target timing duration of the timer corresponding to the higher priority data type is shorter, so that for the data packet corresponding to the higher priority data type, the hardware accelerator can send an interrupt signal to the application processing chip as early as possible, so that the application processing chip can Process data packets corresponding to high-priority data types in an efficient manner and reduce the processing delay of data packets corresponding to high-priority data types.

Optionally, the application processing chip includes a central processor, and the interrupt signal is used to request the central processor in the application processing chip to process the data packet in the target memory.

In the embodiment of the present application, corresponding data packets of different data types are stored separately, and multiple processing links on the data path (from the modem in the communication chip to the central processor in the application processing chip) prioritize processing of more recent data. Data packets corresponding to high-priority data types can reduce the processing delay of data packets corresponding to high-priority data types.

In the embodiment of this application, since the hardware accelerator is very efficient in data packet verification, the hardware accelerator is used to verify the data packet of the target type, and then sends the data packet to the application processing chip. The application processing chip does not need to The data packet is verified, which improves the processing efficiency of the data packet as a whole.

Figure 4 shows a flow chart of a data packet processing method provided by an exemplary embodiment of the present application. Referring to Figure 4, the method is executed by a computer device. The computer device includes a communication chip and an application processing chip. The application processing chip includes a plurality of target memory, the method includes:

401. The computer device determines the data type corresponding to the received data packet through the communication chip, and stores the data packet into the first queue matching the priority of the data type among the plurality of first queues, in order from high to low priority. In order, the data packets in multiple first queues are processed in sequence.

Among them, the priorities of multiple first queues are different.

402. The computer device adds a tag of the allocated target memory to the processed data packet through the communication chip, and stores the tagged data packet in the second queue.

Among them, the target memory allocated to the data packets corresponding to the same data type is the same, the target memory allocated to the data packets corresponding to different data types is different, and the target memory allocated to the data packet corresponding to the higher priority data type has priority. The higher the level.

403. The computer device stores the data packets in the second queue into the target memory corresponding to the tag carried through the communication chip.

For the implementation of steps 401-403, please refer to the above-mentioned embodiment shown in Figure 2 and Figure 3, which will not be described again here.

404. The computer device processes the data packets in the multiple target memories based on the priorities of the multiple target memories through the application processing chip.

In a possible implementation, the application processing chip includes a central processing unit (CPU), and the central processing unit includes a processing core. Correspondingly, the computer device processes the data packets in multiple target memories based on the priorities of the multiple target memories through the application processing chip, including: the computer device processes multiple data packets in sequence from high to low through the processing core. packets in the destination memory. That is, the computer device first processes the data packet in the highest priority target memory through the processing core, and then processes the data packet in the next target memory, and so on. Since the data type corresponding to the data packet stored in the target memory with a higher priority has a higher priority, the processing core sequentially processes the data packets in multiple target memories in order from high priority to low, so that the priority Data packets corresponding to higher-level data types are processed earlier, which can reduce the processing delay of data packets corresponding to high-priority data types.

In another possible implementation, the application processing chip includes a central processor. The central processor includes multiple processing cores with different processing capabilities. Each processing core is associated with a target memory, and the stronger the processing performance of the processing core, the higher the processing performance. The associated target memory has a higher priority. Correspondingly, the computer device processes the data packets in multiple target memories based on the priorities of the multiple target memories through the application processing chip, including: the computer device processes the data packets in the associated target memories through multiple processing cores. .

Among them, these multiple processing cores process data packets in the associated target memory in a parallel manner. That is to say, the processing cores have no influence on each other and each process the data packets in their associated target memories.

In this embodiment of the present application, the higher the priority of the data type corresponding to the data packet stored in the target memory, the higher the priority of the processing core, and the higher the priority of the associated target memory, so that Data packets corresponding to data types with higher priority can be processed by processing cores with stronger processing performance, thereby improving the processing efficiency of data packets corresponding to high-priority data types and reducing the processing of data packets corresponding to high-priority data types. time delay.

Figure 5 is a schematic diagram of a data packet processing process provided by an embodiment of the present application. Referring to Figure 5, the communication chip includes a modem, a first queue A, a first queue B, a hardware accelerator and a second queue, where the first queue A The priority of queue B is higher than the priority of queue B. The application processing chip includes target memory A, target memory B, and processing core A and processing core B. Among them, the priority of target memory A is higher than the priority of target memory B, the processing performance of processing core A is stronger than the processing performance of processing core B, and processing core A is associated with target memory A, and processing core B is associated with target memory B. . Correspondingly, the data packet processing process includes the following steps:

1. According to the data type corresponding to the received data packet, the modem stores the data packet into the first queue that matches the priority of the data type, that is, the first queue A or the first queue B.

2. The hardware accelerator first processes the data packets in the first queue A, adds the tag of the allocated target memory A to the processed data packets, and then stores the tagged data packets in the second queue. After the data packets in the first queue A are processed, the data packets in the first queue B are processed, and the tags of the allocated target memory B are added to the processed data packets, and then the tagged data packets are stored in Second queue.

3. The hardware accelerator calls the DMA controller to transfer the data packet in the second queue to the target memory corresponding to the tag carried, that is, the data packet carrying the tag of target memory A is transferred to target memory A, and the data packet carrying the tag is transferred to target memory A. The data packet of the tag of target memory B is transmitted to target memory B.

4. The processing core A in the application processing chip processes the data packets in the associated target memory A, and the processing core B processes the data packets in the associated target memory B.

Please refer to the above embodiments for specific implementation methods of each step, which will not be described again here.

In the embodiment of this application, the communication chip determines the queue used to store the data packet according to the data type corresponding to the data packet. The higher the priority of the corresponding data type, the higher the priority of the queue used to store the data packet. , and prioritize the processing of data packets in the high-priority queue to determine the processing order of data packets based on the data type corresponding to the data packet, so that data packets with higher priority of the corresponding data type are processed earlier, improving processing The flexibility of data packets and reducing the processing delay of data packets corresponding to high-priority data types. And the communication chip stores the processed data packets corresponding to the same data type into the same target memory, and stores the data packets corresponding to different data types into different target memories, and the data packets stored in the target memory with higher priority correspond to The higher the priority of the data type, the application processing chip will process the data packets in each target memory according to the priority of the target memory, so as to realize differential processing of data packets corresponding to data types with different priorities and improve the flexibility of data packet processing. .

Figure 6 shows a schematic structural diagram of a computer device 600 provided by an exemplary embodiment of the present application. Referring to Figure 6, the computer device 600 includes a communication chip 601 and an application processing chip 602. The application processing chip 602 includes multiple target memories 603. (Two target memories 603 are taken as an example in Figure 6).

The communication chip 601 is used to determine the data type corresponding to the received data packet, and store the data packet into the first queue matching the priority of the data type among the plurality of first queues, in order from high to low priority, Process data packets in multiple first queues in sequence, where the multiple first queues have different priorities.

The communication chip 601 is also used to add a tag of the allocated target memory 603 to the processed data packet, and store the tagged data packet into the second queue, where the target memory 603 allocated for the data packet corresponding to the same data type Similarly, the target memory 603 allocated to the data packets corresponding to different data types is different, and the target memory 603 allocated to the data packet corresponding to the data type with a higher priority has a higher priority.

The communication chip 601 is also used to store the data packets in the second queue into the target memory 603 corresponding to the tag carried.

The application processing chip 602 is configured to process data packets in multiple target memories 603 based on the priorities of the multiple target memories 603 .

For specific ways in which the communication chip 601 and the application processing chip 602 implement each function, please refer to the above method embodiments and will not be described again here.

The computer device 600 further includes a central processing unit. Optionally, the central processing unit includes one or more processing cores.

Optionally, the target memory includes random access memory (Random Access Memory, RAM), optionally, the target memory includes read-only memory (Read-Only Memory, ROM). Optionally, the target storage includes non-transitory computer-readable storage medium.

Optionally, computer device 600 also includes a display screen. The display screen is the display component used to display the user interface.

In addition, those skilled in the art can understand that the structure of the computer device 600 shown in the above figures does not constitute a limitation on the computer device 600. The computer device 600 includes more or fewer components than shown in the figures, or Combining certain parts, or different arrangements of parts. For example, the computer device 600 also includes components such as a microphone, a speaker, an input unit, a sensor, an audio circuit, a power supply, and a Bluetooth module, which will not be described again here.

The above serial numbers of the embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments. The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection of the present application. within the range.

Claims

A data packet processing method, executed by a communication chip, the communication chip including a modem and a hardware accelerator; the method includes:

Through the modem, the data type corresponding to the received data packet is determined, and the data packet is stored in a first queue matching the priority of the data type among a plurality of first queues, wherein the plurality of first queues Queues have different priorities;

Through the hardware accelerator, the data packets in the plurality of first queues are sequentially processed in order from high to low priority.
The method according to claim 1, wherein the communication chip further includes a direct memory access DMA controller, the method further includes:

Through the hardware accelerator, tags of the allocated target memory are added to the processed data packets, and the tagged data packets are stored in the second queue, where the target memories allocated to the data packets corresponding to the same data type are the same and different. The target memory allocated to the data packet corresponding to the data type is different, and the target memory allocated to the data packet corresponding to the data type with a higher priority has a higher priority;

Through the hardware accelerator, the DMA controller is called to store the data packets in the second queue into the target memory corresponding to the tag carried.
The method of claim 2, wherein the communication chip is connected to an application processing chip, and the target memory is located in the application processing chip, and the method further includes:

Through the hardware accelerator, each time a data packet is stored in the corresponding target memory, the timing duration of the current target timer is determined. When the timing duration has reached the target timing duration, a data packet is sent to the application processing chip. Interrupt the signal and restart the target timer;

Wherein, the target timer is a timer corresponding to the data type corresponding to the data packet, and the higher the priority data type, the shorter the target timing duration of the timer, and the interrupt signal is used to request the The application processing chip processes the data packets in the target memory.
The method according to claim 2, wherein adding a label of the allocated target memory to the processed data packet includes:

Determine the target field in the header of the data packet after the processing is completed;

When the target field satisfies the field condition corresponding to any data type, a tag of the target memory corresponding to the data type is added to the processed data packet.
The method according to claim 1, wherein the sequentially processing the data packets in the plurality of first queues in order from high to low priority includes:

In order of priority from high to low, the packet type of each data packet in the plurality of first queues is determined sequentially, and when the currently determined packet type is the target type, the current data packet is processed check.
The method according to claim 1, wherein the priority of ultra-reliable low-latency communication URLLC data is higher than the priority of enhanced mobile broadband eMBB data, and the plurality of first queues includes a third queue and a fourth queue, and the The third queue matches the priority of the URLLC data, and the fourth queue matches the priority of the eMBB data;

The storing of the data packet into the first queue matching the priority of the data type among the plurality of first queues includes:

In the case where the data packet belongs to the URLLC data, the data packet is stored in the third queue; or,

If the data packet belongs to the eMBB data, the data packet is stored in the fourth queue.
A communication chip, the communication chip includes a modem and a hardware accelerator;

The modem is configured to determine the data type corresponding to the received data packet, and store the data packet into a first queue matching the priority of the data type among a plurality of first queues, wherein the plurality of first queues A queue has different priorities;

The hardware accelerator is configured to sequentially process the data packets in the plurality of first queues in order from high to low priority.
A data packet processing method, executed by a computer device, the computer device including a communication chip and an application processing chip, the application processing chip including a plurality of target memories; the method includes:

Through the communication chip, the data type corresponding to the received data packet is determined, and the data packet is stored in the first queue matching the priority of the data type among the plurality of first queues, from high to low according to the priority. In order, the data packets in the plurality of first queues are processed in sequence, wherein the priorities of the plurality of first queues are different;

Through the communication chip, the tag of the allocated target memory is added to the processed data packet, and the tagged data packet is stored in the second queue, where the target memory allocated to the data packet corresponding to the same data type is the same and different. The target memory allocated to the data packet corresponding to the data type is different, and the target memory allocated to the data packet corresponding to the data type with a higher priority has a higher priority;

Through the communication chip, the data packets in the second queue are stored in the target memory corresponding to the tag carried;

Through the application processing chip, the data packets in the plurality of target memories are processed based on the priorities of the plurality of target memories.
The method of claim 8, wherein the application processing chip includes a central processing unit, and the central processing unit includes a processing core;

The application processing chip processes the data packets in the multiple target memories based on the priorities of the multiple target memories, including:

Through the processing core, the data packets in the multiple target memories are sequentially processed in order of priority from high to low.
The method according to claim 8, wherein the application processing chip includes a central processing unit, the central processing unit includes a plurality of processing cores with different processing performance, each of the processing cores is associated with one of the target memories, and The stronger the processing performance of the processing core, the higher the priority of the associated target memory;

The application processing chip processes the data packets in the multiple target memories based on the priorities of the multiple target memories, including:

The data packets in the associated target memory are respectively processed through multiple processing cores.
A computer device, the computer device includes a communication chip and an application processing chip, the application processing chip includes a plurality of target memories;

The communication chip is used to determine the data type corresponding to the received data packet, and store the data packet into the first queue matching the priority of the data type among the plurality of first queues, in order from high to high priority. Process the data packets in the plurality of first queues in sequence in a lower order, wherein the priorities of the plurality of first queues are different;

The communication chip is also used to add a tag of the allocated target memory to the processed data packet, and store the tagged data packet into the second queue, where the data packets corresponding to the same data type are allocated the same target memory. , the target memory allocated to the data packets corresponding to different data types is different, and the higher the priority of the target memory allocated to the data packet corresponding to the data type with a higher priority, the higher the priority;

The communication chip is also used to store the data packets in the second queue to the target memory corresponding to the tag carried;

The application processing chip is configured to process data packets in the multiple target memories based on priorities of the multiple target memories.