WO2023240985A1

WO2023240985A1 - Semiconductor device and manufacturing method therefor, and electronic apparatus

Info

Publication number: WO2023240985A1
Application number: PCT/CN2022/141099
Authority: WO
Inventors: 李永杰; 孟敬恒; 平延磊; 罗东
Original assignee: 北京超弦存储器研究院; 长鑫科技集团股份有限公司
Priority date: 2022-06-15
Filing date: 2022-12-22
Publication date: 2023-12-21
Also published as: CN117295327A

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic apparatus. The semiconductor device comprises: a substrate (10); a plurality of transistors (30), which are arranged on one side of the substrate (10) and arranged in a first direction and a second direction to form an array, wherein each transistor (30) comprises a semiconductor column (35) and a gate electrode (31), the semiconductor column (35) being arranged on the substrate (10), and the gate electrode (31) being arranged on a side wall of the semiconductor column (35); and a plurality of bit lines (20), which are arranged at intervals in the second direction and extend in the first direction, wherein the bit lines (20) are arranged between an upper surface of the substrate (10) and a row of semiconductor columns (35) arranged in the first direction, and the bit lines (20) are connected to the bottom ends of the semiconductor columns close to the substrate (10).

Description

Semiconductor devices and manufacturing methods thereof, electronic equipment

This application requires the priority of the Chinese patent application submitted to the China Patent Office on June 15, 2022, with the application number 202210682220.1 and the invention title "A semiconductor structure and its manufacturing method, DRAM and electronic equipment". Its content should be understood are incorporated by reference into this application.

Technical field

The present application relates to but is not limited to the field of semiconductor devices, and in particular, to a semiconductor device, a manufacturing method thereof, and electronic equipment.

Background technique

Transistors are widely used in semiconductor devices. For example, they can be used in dynamic random access memory (Dynamic Random Access Memory, DRAM). DRAM is a common system memory widely used in personal computers, notebooks and consumer electronics. The manufacturing of DRAM is also facing the evolution of technology nodes in order to improve competitiveness. For example, the design size of DRAM is continuously reduced, and the attempt of 4F ² architecture DRAM is put on the agenda. Compared with the 6F ² architecture, the 4F ² architecture can save 30% of the storage unit area with currently available new technologies, thus significantly increasing storage density and improving industrial competitiveness.

Summary of the invention

The following is an overview of the topics described in detail in this article. This summary is not intended to limit the scope of the application.

Embodiments of the present application provide a semiconductor device, including:

a substrate having an upper surface and a lower surface;

A plurality of transistors are arranged on one side of the substrate and are spaced on the substrate to form an array along a first direction and a second direction. The first direction and the second direction intersect and form a plane with The substrate is parallel; the transistor includes a semiconductor pillar and a gate electrode, the semiconductor pillar is arranged on the substrate and extends into a strip structure along a direction perpendicular to the substrate, and the gate electrode is arranged on On the sidewall of the semiconductor pillar;

A plurality of bit lines, spaced apart along the second direction and extending along the first direction; the bit lines are provided between the upper surface of the substrate and a row of semiconductor pillars arranged along the first direction, and the bit lines It is connected to the bottom end of the semiconductor pillar close to the substrate. In this embodiment of the present application, the semiconductor device may further include: a plurality of word lines, the plurality of word lines are arranged at intervals along the first direction and all extend along the second direction, and each of the word lines is connected to the first direction along the first direction. The gates of a plurality of transistors arranged in two directions are connected.

In this embodiment of the present application, the semiconductor device may further include:

A plurality of word line isolation trenches, the plurality of word line isolation trenches are spaced apart along the first direction and extend along the second direction, and separate the plurality of transistors arranged along the first direction, the word line isolation trench The tank is filled with isolation medium;

A plurality of bit line isolation trenches, the bit line isolation trench is located between a plurality of transistors spaced along the second direction and separates the plurality of bit lines arranged along the second direction.

In this embodiment of the present application, one end of the bit line isolation trench close to the substrate can extend into the substrate, the lower part of the bit line isolation trench is filled with isolation material, and a partial area of the gate is located above the isolation material in the bit line isolation trench.

In this embodiment of the present application, the semiconductor pillar may include a drain, a channel and a source in sequence, the gate surrounds the sidewalls of the channel, and there may be between the gate and the semiconductor pillar. A gate oxide layer is provided.

In this embodiment of the present application, the bit line may be formed by connecting multiple bit line units arranged along the first direction.

In the embodiment of the present application, the bit line material forming the bit line may be selected from any one or more of tungsten, copper, cobalt and titanium.

In the embodiment of the present application, the isolation medium may be selected from any one or more of silicon nitride, silicon dioxide, and silicon carbonitride.

In this embodiment of the present application, the gate electrode may extend to the sidewalls of the drain electrode and the sidewalls of the source electrode in a direction perpendicular to the substrate.

In this embodiment of the present application, the semiconductor device may further include an adhesion barrier layer. The adhesion barrier layer is disposed between the bottom end of the semiconductor pillar and the bit line and between the upper surface of the substrate and the bit line. Between the bit lines, the adhesion barrier layer includes an adhesion layer and a barrier layer sequentially arranged in a direction close to the bit lines.

In the embodiment of the present application, the material of the adhesion layer may be selected from any one or more of titanium and tantalum.

In this embodiment of the present application, the material of the barrier layer may be selected from any one or more of titanium nitride and tantalum nitride.

In this embodiment of the present application, the semiconductor device may further include a third dielectric protective layer, and the third dielectric protective layer may be disposed on the surface and side of the side of the semiconductor device opposite to the substrate.

In this embodiment of the present application, the material of the drain electrode may be selected from N-type heavily doped silicon.

In this embodiment of the present application, the material of the channel may be selected from P-type lightly doped silicon.

In this embodiment of the present application, the material of the source electrode may be selected from N-type heavily doped silicon.

In this embodiment of the present application, the cross section of the bit line unit perpendicular to the second direction may be "Σ"-shaped or bowl-shaped.

An embodiment of the present application also provides a method for manufacturing a semiconductor device as described above, including:

Provide a substrate having an upper surface and a lower surface, and a sacrificial layer and a semiconductor layer are sequentially disposed on the upper surface of the substrate;

A plurality of initial bit line isolation trenches arranged at intervals along the second direction and extending along the first direction and a plurality of word line isolation trenches arranged at intervals along the first direction and extending along the second direction are provided in the semiconductor layer, and The initial bit line isolation trench extends into the substrate, and the word line isolation trench exposes the sacrificial layer, and the initial bit line isolation trench and the word line isolation trench separate the semiconductor layer by multiple semiconductor pillars;

The sacrificial layer is removed, and the space vacated by the sacrificial layer forms a plurality of bit line unit slots arranged along the first direction and the second direction, and the plurality of bit line unit slots arranged along the first direction are connected together. , a plurality of bit line unit slots arranged along the second direction are spaced apart;

Filling the bit line cell slots with bit line material to form a plurality of bit lines spaced apart along the second direction and extending along the first direction;

A gate oxide layer and a gate electrode are arranged in sequence on the sidewalls of the semiconductor pillar, and the semiconductor pillar and the gate electrode constitute a transistor.

In the embodiment of the present application, a plurality of initial bit line isolation trenches arranged at intervals along the second direction and extending along the first direction and a plurality of initial bit line isolation trenches arranged at intervals along the first direction and extending along the second direction are provided in the semiconductor layer. an extended word line isolation trench, and the initial bit line isolation trench extends into the substrate, and the word line isolation trench exposes the sacrificial layer, the initial bit line isolation trench and the word line The isolation trench separates the semiconductor layer into a plurality of semiconductor pillars, which may include:

A plurality of initial bit line isolation trenches arranged at intervals along the second direction and extending along the first direction are provided in the semiconductor layer, and the initial bit line isolation trenches extend through the semiconductor layer and the sacrificial layer. In the substrate, a plurality of the initial bit line isolation trenches separate the semiconductor layer into a plurality of semiconductor walls, and the initial bit line isolation trenches are filled with isolation material;

A plurality of word line isolation trenches arranged in the first direction and extending in the second direction are provided in the plurality of semiconductor walls, and the word line isolation trenches penetrate the semiconductor layer and extend into the sacrificial layer, A plurality of the word line isolation trenches separate the plurality of semiconductor walls into a plurality of semiconductor pillars, the semiconductor pillars extend in a direction perpendicular to the substrate into a strip structure, and the strip structure has side walls and both ends, and the sidewalls of the semiconductor pillar in the direction perpendicular to the substrate include a drain, a channel and a source in sequence, and a plurality of the word line isolation trenches isolate a plurality of the initial bit lines. The trenches are interrupted to form multiple bit line isolation trenches.

In this embodiment of the present application, sequentially arranging a gate oxide layer and a gate electrode on the sidewall of the semiconductor pillar may include:

An interlayer dielectric layer is provided on the inner wall of the word line isolation trench;

Fill the word line isolation trench with isolation dielectric;

Remove the interlayer dielectric layer on the upper part of the inner side wall of the word line isolation trench, and retain the interlayer dielectric layer on the lower part of the inner side wall of the word line isolation trench and the inner bottom surface of the word line isolation trench; and remove the bit The isolation material in the upper part of the line isolation trench is retained, and the isolation material in the lower part of the bit line isolation trench is retained, and the space vacated by the interlayer dielectric layer and the isolation material is removed to form a gate trench;

A gate oxide layer is provided on the inner wall of the gate groove, and the gate material is filled in the gate groove to obtain a gate surrounding the channel sidewall of the semiconductor pillar, which will be arranged along the second direction. The gates of multiple transistors are connected to word lines.

In this embodiment of the present application, arranging a plurality of word line isolation trenches arranged in the first direction and extending in the second direction in the plurality of semiconductor walls may include:

A first dielectric protective layer covering the semiconductor wall and the initial bit line isolation trench is provided on the surface of the substrate;

The first dielectric protection layer is used as a hard mask for the plurality of semiconductor walls, and a plurality of word line isolation trenches arranged along the first direction and extending along the second direction are provided in the plurality of semiconductor walls.

In this embodiment of the present application, removing the sacrificial layer may include:

A second dielectric protective layer is provided on the inner wall of the word line isolation trench, and the second dielectric protective layer on the inner bottom surface of the word line isolation trench is removed, leaving the second dielectric protective layer on the inner wall of the word line isolation trench. dielectric protective layer;

Using the second dielectric protective layer on the inner wall of the word line isolation trench as a hard mask for the side wall of the semiconductor pillar, etch away the sacrificial layer under the word line isolation trench and remove it by side etching sacrificial layer beneath the semiconductor pillar.

In this embodiment of the present application, under the same etching conditions, the etching rate of the sacrificial layer is greater than the etching rate of the isolation material.

In this embodiment of the present application, the material of the sacrificial layer may be silicon germanium, and the isolation material may be selected from any one of silicon dioxide, silicon nitride, silicon carbonitride oxynitride, and silicon carbonitride. The etching liquid used to etch the sacrificial layer can be selected from any one or more of tetramethylammonium hydroxide, ammonia and hydrogen peroxide mixtures.

In this embodiment of the present application, filling the bit line cell slots with bit line material to form a plurality of bit lines spaced apart along the second direction and extending along the first direction may include:

An adhesion layer and a barrier layer are sequentially provided on the inner walls of the word line isolation trench and the bit line unit trench;

The word line isolation trench and the bit line unit trench are filled with bit line material, the bit line material in the bit line unit trench forms a bit line unit, and a plurality of bit line units arranged along the first direction are connected together to form a bit line;

Remove the bit line material in the word line isolation trench.

Embodiments of the present application also provide another method for manufacturing a semiconductor device as described above, including:

A semiconductor substrate is provided, a plurality of initial bit line isolation trenches arranged along a second direction and extending along a first direction are provided in the substrate, and an isolation material is filled in the initial bit line isolation trench, and the plurality of initial bit line isolation trenches are Initial bit line isolation trenches space the substrate into a plurality of semiconductor walls;

A plurality of word line isolation trenches arranged along the first direction and extending along the second direction are provided in the plurality of semiconductor walls, and the plurality of word line isolation trenches separate the plurality of semiconductor walls into a plurality of semiconductor pillars, The semiconductor pillar extends in a direction perpendicular to the substrate into a strip structure, the strip structure has sidewalls and two ends, and the sidewalls of the semiconductor pillar in the direction perpendicular to the substrate are sequentially It includes a drain, a channel and a source, and a plurality of the word line isolation trenches interrupts a plurality of the initial bit line isolation trenches to form a plurality of bit line isolation trenches;

The substrate exposed on the inner bottom surface of the word line isolation trench is etched, and the semiconductor pillars extending into the substrate and toward both sides of the word line isolation trench are formed below the word line isolation trench. A plurality of bit line unit slots extending below, and a plurality of bit line unit slots arranged along the first direction are connected together, and the plurality of bit line unit slots arranged along the second direction are spaced apart by the bit line isolation slots;

removing bit line material in the word line isolation trench;

Fill the word line isolation trench with isolation dielectric;

Remove the isolation material in the upper part of the bit line isolation trench, retain the isolation material in the lower part of the bit line isolation trench, and form a gate trench in the space vacated by removing the isolation material;

A gate oxide layer is provided on the inner wall of the gate groove, and the gate material is filled in the gate groove to obtain a gate surrounding the side walls of the channel of the semiconductor pillar. The semiconductor pillar and The gate electrode constitutes a transistor and connects the gate electrodes of a plurality of transistors arranged along the second direction to the word line.

In the embodiment of the present application, the substrate is etched with the inner bottom surface of the word line isolation trench exposed, and a formation is formed under the word line isolation trench that extends into the substrate and toward the word line. The multiple bit line unit trenches extending below the semiconductor pillars on both sides of the isolation trench may also include:

The bit line cell trench is etched to have a "Σ" shape or a bowl shape in cross section perpendicular to the second direction.

In the embodiment of the present application, when etching the bit line cell trench, under the same etching conditions, the etching rate of the substrate may be greater than the etching rate of the isolation material. In the embodiment of the present application , the material of the substrate may be silicon, the isolation material may be selected from any one or more of silicon dioxide, silicon nitride, silicon oxynitride and silicon nitride, etching the bit line The etching liquid used in the unit tank can be selected from any one or more of tetramethylammonium hydroxide, ammonia and hydrogen peroxide mixtures.

A second dielectric protective layer is provided on the inner wall of the word line isolation trench;

Remove the second dielectric protective layer on the inner bottom surface of the word line isolation trench to expose the substrate, and retain the second dielectric protective layer on the inner side wall of the word line isolation trench;

Using the second dielectric protective layer on the inner wall of the word line isolation trench as a hard mask for the side wall of the semiconductor pillar, the substrate exposed on the inner bottom surface of the word line isolation trench is etched. A plurality of bit line unit trenches are formed below the word line isolation trench and extend into the substrate and extend toward the bottom of the semiconductor pillars on both sides of the word line isolation trench, and a plurality of bit lines are arranged along a first direction. The cell slots are connected together, and a plurality of bit line unit slots arranged along the second direction are spaced apart by the bit line isolation slots.

In this embodiment of the present application, the word line isolation trench and the bit line unit trench are filled with bit line material, the bit line material in the bit line unit trench forms a bit line unit, and the bit line units are arranged along the first direction. Multiple bit line cells are connected together to form a bit line, which can include:

The word line isolation trench and the bit line unit trench are filled with bit line material, the bit line material in the bit line unit trench forms a bit line unit, and a plurality of bit line units arranged along the first direction are connected together to form A bit line.

An embodiment of the present application also provides an electronic device, including the semiconductor device as described above.

In this embodiment of the present application, the electronic device may include a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the application. Other advantages of the application can be realized and obtained by the solutions described in the specification and drawings.

Figure overview

1A is a schematic structural diagram of a semiconductor device according to an exemplary embodiment of the present application;

FIG. 1B is a schematic structural diagram of the semiconductor device shown in FIG. 1A from another angle;

FIG. 1C is a schematic structural diagram of the semiconductor device shown in FIG. 1A from another angle;

FIG. 1D is a schematic structural diagram of the semiconductor device shown in FIG. 1A from another angle;

Figure 2A is a schematic structural diagram of a semiconductor device according to another exemplary embodiment of the present application;

FIG. 2B is a schematic structural diagram of the semiconductor device shown in FIG. 2A from another angle;

FIG. 2C is a schematic structural diagram of the semiconductor device shown in FIG. 2A from another angle;

FIG. 2D is a schematic structural diagram of the semiconductor device shown in FIG. 2A from another angle;

Figure 3 is a partial enlarged view of a "Σ"-shaped bit line unit of a semiconductor device according to an exemplary embodiment of the present application;

Figure 4 is a process flow diagram of a manufacturing method of a semiconductor device according to an embodiment of the present application;

Figure 5 is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

6A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 6B is a schematic structural diagram of the intermediate product shown in Figure 6A from another angle;

Figure 6C is a schematic structural diagram of the intermediate product shown in Figure 6A from another angle;

7A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 7B is a schematic structural diagram of the intermediate product shown in Figure 7A from another angle;

Figure 7C is a schematic structural diagram of the intermediate product shown in Figure 7A from another angle;

8A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 8B is a schematic structural diagram of the intermediate product shown in Figure 8A from another angle;

Figure 8C is a schematic structural diagram of the intermediate product shown in Figure 8A from another angle;

9A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 9B is a schematic structural diagram of the intermediate product shown in Figure 9A from another angle;

Figure 9C is a schematic structural diagram of the intermediate product shown in Figure 9A from another angle;

10A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 10B is a schematic structural diagram of the intermediate product shown in Figure 10A from another angle;

Figure 10C is a schematic structural diagram of the intermediate product shown in Figure 10A from another angle;

11A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 11B is a schematic structural diagram of the intermediate product shown in Figure 11A from another angle;

Figure 11C is a schematic structural diagram of the intermediate product shown in Figure 11A from another angle;

12A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 12B is a schematic structural diagram of the intermediate product shown in Figure 12A from another angle;

Figure 12C is a schematic structural diagram of the intermediate product shown in Figure 12A from another angle;

13A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 13B is a schematic structural diagram of the intermediate product shown in Figure 13A from another angle;

Figure 13C is a schematic structural diagram of the intermediate product shown in Figure 13A from another angle;

14A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 14B is a schematic structural diagram of the intermediate product shown in Figure 14A from another angle;

Figure 14C is a schematic structural diagram of the intermediate product shown in Figure 14A from another angle;

Figure 15A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 15B is a schematic structural diagram of the intermediate product shown in Figure 15A from another angle;

Figure 15C is a schematic structural diagram of the intermediate product shown in Figure 15A from another angle;

16A is a schematic structural diagram of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

Figure 16B is a schematic structural diagram of the intermediate product shown in Figure 16A from another angle;

Figure 16C is a schematic structural diagram of the intermediate product shown in Figure 16A from another angle;

17 is a schematic structural diagram from different angles of an intermediate product obtained in an intermediate step of another manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

18 is a schematic structural diagram from different angles of an intermediate product obtained in an intermediate step of another manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

19 is a schematic structural diagram of an intermediate product obtained from an intermediate step of another manufacturing method of a semiconductor device according to an exemplary embodiment of the present application from different angles;

20 is a schematic structural diagram from different angles of an intermediate product obtained in an intermediate step of another manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

21 is a schematic structural diagram from different angles of an intermediate product obtained in an intermediate step of another manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

22 is a schematic structural diagram from different angles of an intermediate product obtained in an intermediate step of another manufacturing method of a semiconductor device according to an exemplary embodiment of the present application.

The meanings of the marking symbols in the drawings are:

10-substrate; 20-bit line; 21-bit line unit; 21'-bit line unit slot; 21"-bit line material; 30-transistor; 31-gate; 31'-gate slot; 31"- Gate material; 32-drain; 32'-drain layer; 33-channel; 33'-channel layer; 34-source; 34'-source layer; 35-semiconductor pillar; 40-word line; 50-word line isolation trench; 60-bit line isolation trench; 60'-initial bit line isolation trench; 70-interlayer dielectric layer; 80-isolation medium; 90-isolation material; 100-third dielectric protective layer; 110- Sacrificial layer; 120-first dielectric protective layer; 130-second dielectric protective layer; 140-interlayer dielectric layer.

Elaborate

In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.

The embodiments herein may be implemented in a number of different forms. Those of ordinary skill in the art can easily understand the fact that the implementation manner and content can be transformed into various forms without departing from the spirit and scope of the present application. Therefore, this application should not be construed as being limited only to the contents described in the following embodiments. If there is no conflict, the embodiments and features in the embodiments in this application can be combined with each other arbitrarily.

The scale of the drawings in this application can be used as a reference in actual processes, but is not limited thereto. For example: the width-to-length ratio of each film layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams, and one aspect of this application is not limited to the shapes or numerical values shown in the drawings.

In this manual, for convenience, "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", Words such as "outside" indicating the orientation or positional relationship are used to describe the positional relationship of the constituent elements with reference to the drawings, which are only for the convenience of describing this specification and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, Constructed and operated in a specific orientation and therefore should not be construed as limiting this application. The positional relationship of the constituent elements is appropriately changed depending on the direction in which each constituent element is described. Therefore, they are not limited to the words and phrases described in the specification, and may be appropriately replaced according to circumstances.

In this manual, unless otherwise explicitly stated or limited, the terms "setting" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood on a case-by-case basis.

In the description of the present application, ordinal numbers such as "first" and "second" are provided to avoid confusion of constituent elements and are not intended to limit the quantity.

In this specification, "film" and "layer" may be interchanged. For example, sometimes "dielectric protective layer" can be replaced by "dielectric protective film".

The dynamic random access memory of the ^4F2 architecture requires that the bit line be placed under the transistor. To reduce the transistor contact resistance and reduce the bit line resistance, both require the use of metal as the bit line, and the improvement of the contact resistance between the metal and the transistor has also become a concern. the key of.

An embodiment of the present application provides a semiconductor device, which includes:

a substrate having an upper surface and a lower surface;

A plurality of bit lines, spaced apart along the second direction and extending along the first direction; the bit lines are provided between the upper surface of the substrate and a row of semiconductor pillars arranged along the first direction, and the bit lines It is connected to the bottom end of the semiconductor pillar close to the substrate.

In this embodiment of the present application, the semiconductor device may further include: a plurality of word lines, the plurality of word lines are spaced apart along the first direction and extend along the second direction, and each of the word lines is connected to the second word line along the second direction. The gates of multiple transistors arranged in a direction are connected.

In this embodiment of the present application, the semiconductor pillar may include a drain electrode, a channel and a source electrode in sequence, the gate electrode surrounds the sidewall of the channel, and is disposed between the gate electrode and the semiconductor pillar. There is a gate oxide layer.

In this embodiment of the present application, the bit line may be formed by connecting multiple bit line units arranged along the first direction. 1A to 1D are schematic structural diagrams of a semiconductor device from different angles according to an exemplary embodiment of the present application; FIGS. 2A to 2D are schematic structural diagrams of a semiconductor device from different angles according to another exemplary embodiment of the present application. As shown in FIGS. 1A to 2D , in an exemplary embodiment, the semiconductor device may include: a substrate 10 , a plurality of bit lines 20 (Bit Line), a plurality of transistors 30 , and a plurality of word lines 40 (Word Line). ), a plurality of word line isolation trenches 50 and a plurality of bit line isolation trenches 60.

The substrate 10 has an upper surface and a lower surface.

The plurality of transistors 30 are disposed on a side of the bit line unit 21 away from the substrate 10 . Each transistor 30 corresponds to a bit line unit 21 . The plurality of transistors 30 are spaced apart along the first direction and the second direction. Arranged to form an array, the first direction and the second direction intersect and the formed plane is parallel to the substrate; each of the transistors 30 includes a semiconductor pillar 35 and a gate electrode 31, and the semiconductor pillar 35 is disposed on The bit line unit 21 extends in a direction perpendicular to the substrate 10 into a strip-shaped structure. The strip-shaped structure has side walls and two ends, and has side walls perpendicular to the substrate 10 . The wall includes a drain electrode 32, a channel 33 and a source electrode 34 in sequence. The gate electrode 31 surrounds the sidewall of the channel 33. A gate oxide layer is provided between the gate electrode 31 and the semiconductor pillar. (Also called gate insulation layer, not shown in the figure).

The plurality of bit lines 20 are disposed on one side of the substrate 10 , are spaced apart along the second direction, and extend along the first direction; each of the bit lines 20 includes a plurality of bit line units 21 , and the plurality of bit lines 20 include a plurality of bit line units 21 . The bit line units 21 are connected in the first direction to form a bit line. For example, the bit line 20 is disposed between the upper surface of the substrate 10 and a row of semiconductor pillars 35 arranged along the first direction, and the bit line 20 and the semiconductor pillar 35 are close to the substrate 10 Bottom connection.

The plurality of word lines 40 are spaced apart along the first direction and extend along the second direction. Each of the word lines 40 is connected to the gate electrodes 31 of the plurality of transistors 30 arranged along the second direction.

The word line isolation trenches 50 are spaced apart along the first direction and extend along the second direction. The word line isolation trenches 50 separate the transistors 30 and the word lines 40 in the first direction. , that is, the word line isolation trench 50 separates a plurality of transistors 30 and a plurality of word lines 40 arranged along the first direction; and, one end of the word line isolation trench 50 close to the substrate 10 ends at the On the surface of the bit line unit 21 , the word line isolation trench 50 is filled with an isolation medium 80 .

The bit line isolation trenches 60 are located between the plurality of transistors 30 spaced apart along the second direction and separate the plurality of bit lines 20 in the second direction, that is, the bit line isolation trenches 60 will be arranged along the second direction. A plurality of bit lines 20 are spaced apart; for example, one end of the bit line isolation trench 60 close to the substrate 10 may end in the substrate 10 , that is, the bit line isolation trench 60 extends into the substrate 10 . In the substrate 10 , the lower part of the bit line isolation trench 60 is filled with isolation material 90 , and part of the gate 31 , for example, the part of the gate 31 located on one side of the channel 33 , is located on the bit line isolation groove 60 . above the isolation material 90 in the groove 60 .

In the description of this application, the "first direction" may be the extension direction of the bit line of the semiconductor device; the "second direction" may be the extension direction of the word line of the semiconductor device; the first direction and the The second directions may be perpendicular to each other. The first direction and the second direction may be as shown in FIGS. 1A to 1C .

In this embodiment of the present application, the substrate may be a semiconductor substrate, for example, a single crystal silicon substrate, or a semiconductor on insulator (SOI) substrate, for example, silicon on sapphire (Silicon on Sapphire). On Sapphire (SOS) substrate, Silicon On Glass (SOG) substrate, silicon epitaxial layer or other semiconductor or optoelectronic material based on the base semiconductor, such as silicon-germanium (Si _1-x Ge _x , where x may be, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN) or indium phosphide (InP). The substrate may be doped or may be undoped.

In this embodiment of the present application, the word line may be formed by connecting gates of multiple transistors arranged along the second direction.

In the embodiment of the present application, as shown in Figure 1A, the plurality of bit line units 21 can be connected together in the first direction to form a bit line 20.

In the embodiment of the present application, the bit line material forming the bit line may be selected from any one or more of other metals such as tungsten, copper, cobalt, and titanium.

In this embodiment of the present application, the depth of the word line isolation trench and the bit line isolation trench may be the same or different. For example, the depth of the word line isolation trench may be smaller than the depth of the bit line isolation trench.

In this embodiment of the present application, the word line isolation trench may start from the surface on the opposite side of the semiconductor device and the substrate and end at the surface of the bit line unit. The bit line isolation trench may start from the surface of the side of the semiconductor device opposite the substrate. The surface of the semiconductor device on the opposite side to the substrate ends in the substrate, and at this time, the depth of the word line isolation trench is smaller than the depth of the bit line isolation trench. For example, when the thickness of the substrate is 750 μm, the depth of the word line isolation trench may be 150 nm, and the depth of the bit line isolation trench may be 300 nm.

In the embodiment of the present application, the isolation medium may be an isolation medium for self-aligned isolation, for example, it may be selected from any one of other media such as silicon nitride, silicon dioxide, and silicon carbonitride (for example, SiCN). Kind or variety. At this time, the isolation dielectric can be used for self-aligned isolation of the gate electrode.

In this embodiment of the present application, the material of the gate may be a work function metal, for example, it may be selected from titanium nitride (for example, TiN) and aluminum-titanium-based alloy (for example, TiAl), etc. any one or more.

In the embodiment of the present application, the material of the gate oxide layer may be selected from silicon dioxide, hafnium oxide (for example, HfO ₂ ), zirconium oxide (for example, ZrO) and aluminum oxide (for example, Al ₂ O ₃ ) any one or more.

The thickness of the gate oxide layer can be set according to actual electrical requirements, for example, it can be 2 nm to 5 nm.

In the embodiment of the present application, as shown in FIG. 1A , the gate electrode 31 can extend to the drain region and the source region where the drain electrode 32 and the source electrode 34 are located in the direction perpendicular to the substrate. , that is, the gate electrode 31 can extend to the sidewalls of the drain electrode 32 and the source electrode 34 in the direction perpendicular to the substrate. At this time, the gate electrode 31 can be connected with the drain electrode 34 . The electrode 32 and the source electrode 34 are effectively connected, and the gate electrode 31 is an effective gate electrode.

In the embodiment of the present application, the semiconductor device may further include an adhesion barrier layer (not shown in the figure) formed by an adhesion layer and a barrier layer. The adhesion barrier layer may be disposed between the drain electrode and the barrier layer of the transistor. Between the bit line and the substrate and the bit line, that is, the adhesion barrier layer may be disposed between the bottom end of the semiconductor pillar and the bit line and between the substrate and the bit line. between the upper surface of the base and the bit line; and, the barrier layer is in contact with the bit line, and the adhesion layer may be disposed between the drain of the transistor and the barrier layer and between the substrate and the between the barrier layers.

When the bit line is a metal bit line, the chemicals that form the metal bit line easily react with the silicon substrate. A barrier layer can be set up to prevent the reaction from occurring. However, the barrier layer does not have good adhesion to the silicon substrate and is easy to fall off, so An adhesion layer is provided between the silicon substrate and the barrier layer.

In the embodiment of the present application, the material of the adhesion layer may be selected from any one or more of titanium (Ti) and tantalum (Ta); the thickness of the adhesion layer may be 2 nm to 2.5 nm.

In the embodiment of the present application, the material of the barrier layer may be selected from any one or more of titanium nitride (for example, TiN) and tantalum nitride (for example, TaN); the thickness of the barrier layer may be 2nm to 2.5nm.

For example, when the material of the bit line is tungsten, the material of the barrier layer may be titanium nitride, and the material of the adhesion layer may be titanium; when the material of the bit line is copper, the material of the barrier layer may be titanium. The material of may be tantalum nitride, and the material of the adhesion layer may be tantalum.

In the embodiment of the present application, as shown in FIGS. 2A to 2D , the semiconductor device may further include a third dielectric protective layer 100 , and the third dielectric protective layer 100 is disposed on the side of the semiconductor device and in contact with the on the surface of the opposite side of the substrate 10 . The third dielectric protective layer 100 can protect the exposed gate and source of the transistor and prepare for subsequent Node Contact manufacturing.

In this embodiment of the present application, the material of the third dielectric protective layer may be selected from any one or more of silicon dioxide, silicon nitride, polycrystalline carbon, polycrystalline silicon and single crystal carbon.

In the embodiment of the present application, the isolation material may be selected from any one or more of silicon dioxide, silicon nitride, silicon oxycarbonitride (for example, SiOCN), and silicon carbonitride (for example, SiCN).

In this embodiment of the present application, the material of the drain electrode may be selected from N-type heavily doped silicon, for example, it may be phosphorus-doped silicon. The height of the drain can be

to

For example, it can be

In this embodiment of the present application, the material of the channel is selected from P-type lightly doped silicon, for example, it may be boron-doped silicon. The height of the channel can be

to

For example, it can be

In this embodiment of the present application, the material of the source electrode may be selected from N-type heavily doped silicon, for example, it may be phosphorus-doped silicon. The height of the source can be

to

For example, it can be

In the embodiment of the present application, as shown in FIGS. 1A to 2D , the lower part of the word line isolation trench 50 may be filled with an interlayer dielectric layer 70 for separating the bit line 20 and the word line 40 . The line isolation trench 50 is filled with isolation dielectric 80 above the interlayer dielectric layer 70 .

In this embodiment of the present application, the material of the interlayer dielectric layer may be selected from any one of silicon dioxide, silicon nitride, silicon oxycarbonitride (for example, SiOCN), and silicon carbonitride (for example, SiCN). or more. The interlayer dielectric layer covers part of the bit lines below the word line isolation trench, which can prevent potential metal in the metal bit lines from diffusing outward and causing metal contamination.

FIG. 3 is a partial enlarged view of a “Σ”-shaped bit line unit of a semiconductor device according to an exemplary embodiment of the present application. As shown in FIG. 3 , in this embodiment of the present application, the cross section of the bit line unit 21 perpendicular to the second direction may be “∑” shaped. When bit line material is used to form the bit line unit, the "Σ"-shaped bit line unit slot is more easily filled with the bit line material, thereby forming a "Σ"-shaped bit line unit, which is beneficial to improving the performance in the first direction. Connections between adjacent "Σ" shaped bit line cells.

In this embodiment of the present application, the width of the "Σ"-shaped groove in the first direction may be 40 nm to 45 nm, and the height in the direction perpendicular to the substrate may be 30 nm.

In this embodiment of the present application, the transistor may be a vertical all-around gate transistor (Vertical Gate All Around FET).

In this embodiment of the present application, the semiconductor device may include 900 transistors in the first direction, and may include 900 transistors in the second direction.

In this embodiment of the present application, the semiconductor device may be a dynamic random access memory (DRAM). The DRAM may further include a plurality of capacitors, and each capacitor is connected to the source of one of the transistors.

In this embodiment of the present application, the DRAM may adopt a 4F ² architecture.

In this embodiment of the present application, the DRAM may have a 1T1C structure.

The embodiment of the present application also provides a method for manufacturing a semiconductor device. The semiconductor device provided in the above embodiment of the present application can be manufactured by this method.

FIG. 4 is a process flow diagram of a manufacturing method of a semiconductor device according to an embodiment of the present application. As shown in Figure 4, the manufacturing method may include:

In the embodiment of the present application, the manufacturing method may include: S10: Provide a semiconductor substrate, the substrate has an upper surface and a lower surface, and a sacrificial layer, a drain layer, and a channel layer are sequentially provided on one side of the substrate. and a source layer, the drain layer, the channel layer and the source layer forming a semiconductor layer;

S20: Provide a plurality of initial bit line isolation trenches spaced apart along the second direction and extending along the first direction in the intermediate product obtained in step S10, and make the initial bit line isolation trench penetrate the source layer, the The channel layer, the drain layer and the sacrificial layer stop in the substrate (that is, the initial bit line isolation trench extends into the substrate), and in the initial bit line isolation trench Filling the isolation material, the plurality of initial bit line isolation trenches separate the drain layer, the channel layer and the source layer into a plurality of semiconductor walls;

S30: Provide a plurality of word line isolation trenches arranged at intervals along the first direction and extending along the second direction in the intermediate product obtained in step S20, and make the word line isolation trenches penetrate the source layer and the channel layer and the drain layer and stops in the sacrificial layer (that is, the word line isolation trenches extend into the sacrificial layer), and a plurality of the word line isolation trenches separate the plurality of semiconductor walls into a plurality of semiconductor pillars, each semiconductor pillar extends in a direction perpendicular to the substrate into a strip structure, the strip structure has side walls and two ends, and the semiconductor pillar extends in a direction perpendicular to the substrate The sidewalls include a drain, a channel and a source in sequence, and a plurality of the word line isolation trenches interrupt a plurality of the initial bit line isolation trenches to form a plurality of bit line isolation trenches;

S40: Remove the sacrificial layer below the word line isolation trench, and remove the sacrificial layer below the semiconductor pillar through side etching. The space vacated by the sacrificial layer forms a plurality of spaces arranged along the first direction and the second direction. The bit line unit slots, and the plurality of bit line unit slots arranged along the first direction can be connected together, and the plurality of bit line unit slots arranged along the second direction are spaced apart by the bit line isolation slots;

S50: Fill the word line isolation trench and the bit line unit trench with bit line material, the bit line material in the bit line unit trench forms a bit line unit, and multiple bit line units arranged along the first direction are connected to together form a bit line;

S60: Remove the bit line material in the word line isolation trench;

S70: Fill the word line isolation trench with isolation dielectric;

S80: Remove the isolation material in the upper part of the bit line isolation trench, retain the isolation material in the lower part of the bit line isolation trench, and form the gate trench by removing the space vacated by the isolation material;

S90: Set a gate oxide layer on the inner wall of the gate trench, and fill the gate trench with gate material to obtain a gate surrounding the channel sidewall of the semiconductor pillar. The semiconductor pillar and the gate electrode constitute a transistor, and the gate electrodes of a plurality of transistors arranged along the second direction are connected to the word line.

The semiconductor device manufacturing method of the embodiment of the present application provides a method of manufacturing metal bit lines in a semiconductor device. It uses a method of first forming a sacrificial layer and then removing the sacrificial layer to free up space for forming bit lines (i.e., bit line cell trenches). ), and the metal bit line can be formed by filling the bit line material and etching back, which greatly reduces the bit line resistance, thereby reducing the contact resistance of the transistor and improving the performance of the transistor.

In this embodiment of the present application, step S70 may include:

S71: Set an interlayer dielectric layer on the inner wall of the word line isolation trench;

S72: Fill the word line isolation trench with isolation dielectric;

At this time, step S80 includes: removing the interlayer dielectric layer on the upper part of the inner wall of the word line isolation trench, and retaining the interlayer dielectric layer on the lower part of the inner wall of the word line isolation trench and the inner bottom surface of the word line isolation trench. layer; and removing the isolation material in the upper part of the bit line isolation trench, retaining the isolation material in the lower part of the bit line isolation trench, and forming a gate trench in the space vacated by removing the interlayer dielectric layer and the isolation material.

In this embodiment of the present application, step S30 may include:

S31: Set a first dielectric protective layer on the surface of the intermediate product obtained in step S20, and make the first dielectric protective layer cover the semiconductor wall and the initial bit line isolation trench;

S32: Use the first dielectric protective layer as a hard mask for the plurality of semiconductor walls, and set a plurality of strips arranged along the first direction and extending along the second direction in the plurality of semiconductor walls of the intermediate product obtained in step S31. word line isolation trenches, and the word line isolation trenches penetrate the semiconductor layer and extend into the sacrificial layer, and the plurality of word line isolation trenches separate the plurality of semiconductor walls into a plurality of semiconductor pillars, so The semiconductor pillar extends in a direction perpendicular to the substrate into a strip structure, the strip structure has sidewalls and two ends, and the sidewalls of the semiconductor pillar in the direction perpendicular to the substrate sequentially include Drain, channel and source, and multiple word line isolation trenches interrupt multiple initial bit line isolation trenches to form multiple bit line isolation trenches;

At this time, step S80 may include: removing the interlayer dielectric layer on the upper part of the inner wall of the word line isolation trench, and retaining the interlayer dielectric layer on the lower part of the inner wall of the word line isolation trench and the inner bottom surface of the word line isolation trench. dielectric layer; and removing the first dielectric protective layer on the surface of the plurality of semiconductor pillars and the surface of the bit line isolation trench, and removing the isolation material on the upper part of the bit line isolation trench, while retaining the isolation on the lower part of the bit line isolation trench. material, and the space vacated by removing the interlayer dielectric layer and the isolation material forms a gate trench.

In this embodiment of the present application, step S40 may include:

S41: Set a second dielectric protective layer on the inner wall of the word line isolation trench, remove the second dielectric protective layer on the inner bottom surface of the word line isolation trench, and retain the second dielectric protective layer on the inner wall of the word line isolation trench. second dielectric protective layer;

S42: Use the second dielectric protective layer on the inner wall of the word line isolation trench as a hard mask for the side wall of the semiconductor pillar, etch away the sacrificial layer under the word line isolation trench, and etch the The sacrificial layer under the semiconductor pillar is etched away, and the space vacated by the sacrificial layer forms a plurality of bit line unit trenches arranged along the first direction and the second direction, and the plurality of bit line unit trenches arranged along the first direction are formed. Capable of being connected together, a plurality of bit line unit slots arranged along the second direction are spaced apart by the bit line isolation slots;

At this time, step S60 includes: removing the bit line material in the word line isolation trench and the second dielectric protective layer on the inner side wall of the word line isolation trench.

In this embodiment of the present application, step S50 may include:

S51: Arrange an adhesion layer and a barrier layer in sequence on the inner walls of the word line isolation trench and the bit line unit trench;

S52: Fill the word line isolation trench and the bit line unit trench with bit line material, the bit line material in the bit line unit trench forms a bit line unit, and multiple bit line units arranged along the first direction are connected to together form a bit line.

In this embodiment of the present application, step S90 may include: providing a gate oxide layer on the inner wall of the gate trench, and filling the gate trench with gate material to obtain a channel side surrounding the semiconductor pillar. The gate electrode on the wall connects the gate electrodes of the plurality of transistors arranged along the second direction to the word line.

Exemplarily, step S90 may include:

S91: Set a gate oxide layer on the inner wall of the gate trench, and fill the gate trench with gate material;

S92: Carve back the gate material in the gate trench to a certain depth to obtain a gate surrounding the channel sidewall of the semiconductor pillar. The semiconductor pillar and the gate constitute a transistor. The gates of the plurality of transistors arranged in two directions are connected to the word lines.

In the embodiment of the present application, step S90 or S92 may include: extending the gate electrode in a direction perpendicular to the substrate to the drain region and the source region where the drain electrode and the source electrode are located, even if The gate electrode extends to the sidewall of the drain electrode and the sidewall of the source electrode in a direction perpendicular to the substrate.

In the embodiment of the present application, the manufacturing method may also include: after S90,

S100: Set a third dielectric protective layer on the upper surface and side surfaces of the semiconductor device obtained in step S90.

5 to 16C are schematic structural diagrams of an intermediate product obtained in an intermediate step of a manufacturing method of a semiconductor device structure according to an exemplary embodiment of the present application. As shown in Figures 1A to 2D and 5 to 16C, in an exemplary embodiment, the manufacturing method may include:

S10: Provide a semiconductor substrate 10, and sequentially set the sacrificial layer 110, the drain layer 32', the channel layer 33' and the source layer 34' on one side of the substrate 10 to obtain the intermediate product as shown in Figure 5;

S20: Provide a plurality of initial bit line isolation trenches 60' arranged in the second direction and extending in the first direction in the intermediate product obtained in step S10, and make the initial bit line isolation trenches 60' penetrate the source layer 34', the channel layer 33', the drain layer 32' and the sacrificial layer 110 and stop in the substrate 10, and fill the initial bit line isolation trench 60' with isolation material 90 , the plurality of initial bit line isolation grooves 60' separate the drain layer 32', the channel layer 33' and the source layer 34' into a plurality of semiconductor walls, as shown in Figure 6A to Figure 6C Intermediates shown;

S31: Set the first dielectric protective layer 120 on the surface of the intermediate product obtained in step S20 to obtain the intermediate product as shown in Figures 7A to 7C;

S32: Using the first dielectric protection layer 120 as a hard mask for the plurality of semiconductor walls, a plurality of word line isolation trenches arranged along the first direction and extending along the second direction are provided in the intermediate product obtained in step S31. 50. A plurality of word line isolation trenches 50 separate the plurality of semiconductor walls into a plurality of semiconductor pillars. Each semiconductor pillar includes a drain 32, a channel 33 and a source 34, and a plurality of word lines The isolation trench 50 interrupts the plurality of initial bit line isolation trenches 60' to form a plurality of bit line isolation trenches 60, thereby obtaining the intermediate product as shown in Figures 8A to 8C;

S41: Set the second dielectric protective layer 130 on the inner wall of the word line isolation trench 50, and remove the second dielectric protective layer 130 on the inner bottom surface of the word line isolation trench 50, leaving the word line isolation trench 50. The second dielectric protective layer 130 on the inner side wall is used to obtain the intermediate product as shown in Figure 9A to Figure 9C;

S42: Use the second dielectric protective layer 130 on the inner wall of the word line isolation trench 50 as a hard mask for the sidewalls of the semiconductor pillars, etch away the sacrificial layer 110 below the word line isolation trench 50, and The sacrificial layer 110 under the semiconductor pillar is removed through side etching. The space vacated by the sacrificial layer 110 forms a plurality of bit line unit trenches 21' arranged along the first direction and the second direction. The plurality of bit line unit slots 21' arranged can be connected together, and the plurality of bit line unit slots 21' arranged along the second direction are spaced apart by the bit line isolation slots 60, resulting in the results shown in Figures 10A to 10C intermediate goods;

S51: Arrange an adhesion layer and a barrier layer (not shown in the figure) in sequence on the inner walls of the word line isolation trench 50 and the bit line unit trench 21';

S52: Fill the word line isolation trench 50 and the bit line unit trench 21' with bit line material 21". The bit line material 21" in the bit line unit trench 21' forms the bit line unit 21, and along the first A plurality of bit line units 21 arranged in different directions are connected to obtain an intermediate product as shown in Figures 11A to 11C;

S60: Remove the bit line material 21" in the word line isolation trench 50 and the second dielectric protective layer 130 on the inner wall of the word line isolation trench 50 to obtain the intermediate product as shown in Figures 12A to 12C;

S71: Set an interlayer dielectric layer 140 on the inner wall of the word line isolation trench 50 to obtain an intermediate product as shown in Figures 13A to 13C;

S72: Fill the word line isolation trench 50 with the isolation dielectric 80 to obtain the intermediate product as shown in Figures 14A to 14C;

S80: Remove the interlayer dielectric layer 140 on the upper part of the inner wall of the word line isolation trench 50, and retain the interlayer dielectric layer on the lower part of the inner wall of the word line isolation trench 50 and the inner bottom surface of the word line isolation trench 50. 140; and remove the first dielectric protective layer 120 on the surface of the plurality of semiconductor pillars and the surface of the bit line isolation trench 60, and remove the isolation material 90 on the upper part of the bit line isolation trench 60, leaving the bit line isolation trench 60 lower part of the isolation material 90, remove the interlayer dielectric layer 140 and the space vacated by the isolation material 90 to form a gate trench 31', and obtain the intermediate product as shown in Figure 15A to Figure 15C;

S91: Set a gate oxide layer on the inner wall of the gate groove 31', and fill the gate groove 31' with gate material 31" to obtain an intermediate product as shown in Figures 16A to 16C;

S92: Carve back the gate material 31" in the gate groove 31' to a certain depth to obtain the gate 31 surrounding the sidewall of the channel 33 of the semiconductor pillar 35 and make the gate 31 vertically Extending in the direction of the substrate 10 to the drain region and the source region where the drain electrode 32 and the source electrode 34 are located, and the semiconductor pillar and the gate electrode 31 constitute a transistor, arranged along the second direction The gates 31 of the plurality of transistors are connected to the word lines 40 to obtain the semiconductor device as shown in Figures 1A to 1D;

S100: Set a third dielectric protective layer 100 on the upper surface and side surfaces of the semiconductor device obtained in step S90 to obtain the semiconductor device as shown in FIGS. 2A to 2D.

In this embodiment of the present application, the sacrificial layer, the drain layer, the channel layer and the source layer may all be epitaxial layers. In step S10, epitaxial layers of the sacrificial layer, the drain layer, the channel layer and the source layer can be grown on the substrate using epitaxial equipment.

In the embodiment of the present application, in step S20, a self-aligned double patterning (SADP) process can be used to cut the initial bit line isolation trench in the intermediate product obtained in step S10.

In the embodiment of the present application, step S20 may also include: after filling the initial bit line isolation trench with isolation material, using a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) method to remove the isolation material in the initial bit line isolation trench. The surface of the material is ground flush with the surfaces of the plurality of semiconductor walls.

In the embodiment of the present application, in step S30 or S32, a SADP process may be used to cut the word line isolation trench in the intermediate product obtained in step S20. The word line isolation trench penetrates the source layer, the channel layer and the drain layer and stops in the sacrificial layer, but can slightly enter the sacrificial layer.

In this embodiment of the present application, the first dielectric protective layer serves as a hard mask for the plurality of semiconductor walls in step S32. In subsequent process steps (such as step S40), the first dielectric protective layer can also serve as a hard mask for the plurality of semiconductor walls. Used to protect the top of the semiconductor pillar.

In this embodiment of the present application, the material of the first dielectric protective layer may be selected from any one or more of silicon dioxide, silicon nitride, polycrystalline carbon, polycrystalline silicon and single crystal carbon.

In the embodiment of the present application, in step S40 or S42, the sacrificial layer below the word line isolation trench can be removed by wet etching or dry etching and selecting a high sacrificial layer/isolation material etching ratio, that is, in the same Under the etching conditions, the etching rate of the sacrificial layer is greater than the etching rate of the isolation material.

In this embodiment of the present application, the material of the sacrificial layer is silicon germanium (for example, SiGe). Silicon germanium is easy to remove. The use of silicon germanium to form a sacrificial layer facilitates subsequent removal of the sacrificial layer to free up bit line cell slots for filling bit line materials, which is beneficial to forming low-resistance bit lines, thereby reducing the contact resistance of the transistor and improving Transistor performance.

In this embodiment of the present application, the thickness of the sacrificial layer may be

to

For example, it can be

When the material of the sacrificial layer is silicon germanium and the isolation material is selected from any one or more of silicon dioxide, silicon nitride, silicon oxynitride and silicon carbonitride, the wet etching Or the etching liquid used in the dry etching may be any one or more of tetramethylammonium hydroxide (TMAH) and an ammonia/hydrogen peroxide mixture. The ammonia/hydrogen peroxide mixture (Ammonia-Peroxide Mixture, APM) may be a mixture of NH ₄ OH:H ₂ O ₂ :H ₂ O) in a ratio of 1:1:5.

When the isolation material is selected from any one or both of silicon dioxide and silicon nitride, TMAH and APM have higher etching selectivity for silicon germanium and the isolation material; when any one or both of TMAH and APM are used When the silicon germanium sacrificial layer is etched by wet etching or dry etching, the silicon germanium sacrificial layer can be completely removed and the isolation material in the bit line isolation trench can be prevented from being etched away, which is beneficial to subsequent formation. Low resistance bit lines, thereby improving transistor performance.

In this embodiment of the present application, the material of the second dielectric protective layer may be selected from any one or more of silicon dioxide, silicon nitride, polycrystalline carbon, polycrystalline silicon and single crystal carbon.

In this embodiment of the present application, the thickness of the second dielectric protective layer may be 5 nm to 9 nm, for example, it may be 5 nm, 7 nm or 9 nm.

In the embodiment of the present application, in step S41, a second dielectric protective layer can be provided on all exposed surfaces of the intermediate product obtained in step S30, and then the excess second dielectric protective layer is removed, leaving only the word line isolation trench. Second dielectric protective layer on the inner side wall.

In the embodiment of the present application, in step S51, a chemical vapor deposition (CVD) process may be used to sequentially deposit an adhesion layer and a barrier layer on the inner walls of the word line isolation trench and the bit line cell trench.

In the embodiment of the present application, in step S50 or S52, a CVD process may be used to deposit bit line material in the word line isolation trench and the bit line unit trench until the word line isolation trench and the bit line unit trench are filled entirely.

In the embodiment of the present application, step S50 or S52 may further include: after filling the word line isolation trench and the bit line cell trench with bit line material, using the CMP method to planarize the top of the bit line material.

In the embodiment of the present application, in step S60, the bit line material in the word line isolation trench can be removed by an etch back method.

S10': Provide a semiconductor substrate, provide a plurality of initial bit line isolation trenches arranged along the second direction and extending along the first direction in the substrate, and fill the initial bit line isolation trenches with isolation material, A plurality of the initial bit line isolation trenches separate the substrate into a plurality of semiconductor walls;

S20': Provide a plurality of word line isolation grooves arranged along the first direction and extending along the second direction in the plurality of semiconductor walls of the intermediate product obtained in step S10', and the plurality of word line isolation grooves will A plurality of semiconductor walls are spaced into a plurality of semiconductor pillars, each semiconductor pillar extends in a direction perpendicular to the substrate to form a strip structure, the strip structure has side walls and two ends, and the semiconductor pillars are The sidewalls in the direction perpendicular to the substrate include drains, channels and sources in sequence, and a plurality of the word line isolation trenches interrupt a plurality of the initial bit line isolation trenches to form a plurality of bit line isolation trenches. ;

S30': Perform side etching on the lower part of the word line isolation trench (that is, the exposed substrate), and form a groove below the word line isolation trench that extends into the substrate and toward the word line isolation trench. A plurality of bit line unit slots arranged along the first direction and the second direction extend below the semiconductor pillars on both sides, and the plurality of bit line unit slots arranged along the first direction can be connected together and arranged along the second direction. A plurality of bit line cell slots are spaced apart by the bit line isolation slots;

S40': Fill the word line isolation trench and the bit line unit trench with bit line material, the bit line material in the bit line unit trench forms a bit line unit, and connect multiple bit line units arranged along the first direction. Together they form a bit line;

S50’: Remove the bit line material in the word line isolation trench;

S60’: Fill the word line isolation trench with isolation dielectric;

S70’: Remove the isolation material in the upper part of the bit line isolation trench, retain the isolation material in the lower part of the bit line isolation trench, and form the gate trench by removing the space vacated by the isolation material;

S80': Set a gate oxide layer on the inner wall of the gate trench, and fill the gate trench with gate material to obtain a gate surrounding the channel sidewall of the semiconductor pillar. The semiconductor pillar and the gate electrode constitute a transistor, and the gate electrodes of a plurality of transistors arranged in the second direction are connected to the word line.

In the embodiment of the present application, step S30' may include etching the lower part of the word line isolation trench into a "Σ" shape or a bowl shape to form a "Σ" or bowl-shaped bit line cell trench. The line unit groove is etched to have a "Σ" shape or a bowl shape in cross section perpendicular to the second direction.

In this embodiment of the present application, when etching the bit line cell trench, under the same etching conditions, the etching rate of the substrate may be greater than the etching rate of the isolation material.

In this embodiment of the present application, step S20' may include:

S21': Set a first dielectric protective layer on the surface of the intermediate product obtained in step S10', and make the first dielectric protective layer cover the semiconductor wall and the initial bit line isolation trench;

S22': Use the first dielectric protective layer as a hard mask for the plurality of semiconductor walls, and set a plurality of semiconductor walls arranged along the first direction and along the second direction in the plurality of semiconductor walls of the intermediate product obtained in step S21'. Extended word line isolation trenches, a plurality of the word line isolation trenches separate the plurality of semiconductor walls into a plurality of semiconductor pillars, each semiconductor pillar extending into a strip structure along a direction perpendicular to the substrate, The strip structure has sidewalls and two ends, and the sidewalls of the semiconductor pillar in a direction perpendicular to the substrate include drains, channels and sources in sequence, and a plurality of the word line isolation trenches will A plurality of the initial bit line isolation trenches are interrupted to form a plurality of bit line isolation trenches;

At this time, step S70' may include: removing the first dielectric protective layer on the surface of the plurality of semiconductor pillars and the surface of the bit line isolation trench, and removing the isolation material on the upper part of the bit line isolation trench, leaving the bit line The isolation material in the lower part of the isolation trench is removed, and the space vacated by the isolation material forms a gate trench.

In this embodiment of the present application, step S30' may include:

S31': Set a second dielectric protective layer on the inner wall of the word line isolation trench; remove the second dielectric protective layer on the inner bottom surface of the word line isolation trench to expose the substrate and retain the word line a second dielectric protective layer on the inner wall of the isolation groove;

S32': Use the second dielectric protective layer on the inner wall of the word line isolation trench as a hard mask for the sidewalls of the semiconductor pillar, and mask the lower part of the word line isolation trench (ie, the exposed substrate) Perform side etching to form a plurality of semiconductor pillars extending into the substrate and extending toward the underside of the semiconductor pillars on both sides of the word line isolation trench and arranged along the first direction and the second direction under the word line isolation trench. The bit line unit slots, and the plurality of bit line unit slots arranged along the first direction can be connected together, and the plurality of bit line unit slots arranged along the second direction are spaced apart by the bit line isolation slots;

At this time, step S50' includes: removing the bit line material in the word line isolation trench and the second dielectric protective layer on the inner wall of the word line isolation trench.

In this embodiment of the present application, step S40' may include:

S41’: sequentially provide an adhesion layer and a barrier layer on the inner walls of the word line isolation trench and the bit line unit trench;

S42': Fill the word line isolation trench and the bit line unit trench with bit line material, the bit line material in the bit line unit trench forms a bit line unit, and connect multiple bit line units arranged along the first direction. together form a bit line.

In this embodiment of the present application, step S80' may include:

S81’: Set a gate oxide layer on the inner wall of the gate trench, and fill the gate trench with gate material;

S82': Carve back the gate material in the gate trench to a certain depth to obtain a gate surrounding the channel sidewall of the semiconductor pillar. The semiconductor pillar and the gate constitute a transistor. The gates of the plurality of transistors arranged in two directions are connected to the word lines.

In the embodiment of the present application, step S80' or step S82' may include extending the gate electrode in a direction perpendicular to the substrate to the drain region and the source region where the drain electrode and the source electrode are located. , even if the gate electrode extends to the sidewall of the drain electrode and the sidewall of the source electrode in a direction perpendicular to the substrate.

In this embodiment of the present application, the manufacturing method may further include: after step S80',

S90': Set a third dielectric protective layer on the upper surface and side surfaces of the semiconductor device obtained in step S80'.

17 to 22 are schematic structural diagrams of an intermediate product obtained in an intermediate step of another manufacturing method of a semiconductor device structure according to an exemplary embodiment of the present application. As shown in Figures 1A to 2D and Figures 17 to 22, in an exemplary embodiment, the manufacturing method may include:

S10': Provide a semiconductor substrate 10, and set a plurality of initial bit line isolation grooves 60' arranged along the second direction and extending along the first direction in the substrate 10 to obtain an intermediate product as shown in Figure 17; and filling the initial bit line isolation trenches 60' with isolation material 90. The multiple initial bit line isolation trenches 60' separate the substrate 10 into multiple semiconductor walls to obtain an intermediate product as shown in Figure 18 ;

S21': Set the first dielectric protective layer 120 on the surface of the intermediate product obtained in step S10', and make the first dielectric protective layer 120 cover the semiconductor wall and the initial bit line isolation trench 60';

S22': Use the first dielectric protective layer 120 as a hard mask for the plurality of semiconductor walls, and set a plurality of semiconductor walls arranged along the first direction and along the second direction in the plurality of semiconductor walls of the intermediate product obtained in step S21'. A plurality of word line isolation trenches 50 extending in a direction. The plurality of word line isolation trenches 50 separate the plurality of semiconductor walls into a plurality of semiconductor pillars. Each semiconductor pillar extends in a strip shape in a direction perpendicular to the substrate. structure, the strip-shaped structure has sidewalls and two ends, and the sidewalls of the semiconductor pillars in a direction perpendicular to the substrate include drains, channels and sources in sequence, and a plurality of the word lines are isolated The groove 50 interrupts the plurality of initial bit line isolation grooves 60' to form a plurality of bit line isolation grooves 60, thereby obtaining an intermediate product as shown in Figure 19;

S31': Set a second dielectric protective layer (not shown in the figure) on the inner wall of the word line isolation trench 50; remove the second dielectric protective layer on the inner bottom surface of the word line isolation trench to expose the liner. Bottom, retain the second dielectric protective layer on the inner wall of the word line isolation trench;

S32': Use the second dielectric protective layer on the inner wall of the word line isolation trench 50 as a hard mask for the sidewalls of the semiconductor pillars, and apply Side etching is performed on the bottom) to form a plurality of lines extending into the substrate and extending toward the bottom of the semiconductor pillars on both sides of the word line isolation trench 50 along the first direction and "Σ"-shaped bit line unit slots 21' arranged in the second direction, and the cross-section of the bit line unit slots 21' perpendicular to the second direction is "Σ" shaped, and arranged along the first direction. The plurality of bit line unit slots 21' can be connected together tip-to-tip, and the plurality of bit line unit slots 21' arranged along the second direction are spaced apart by the bit line isolation slots 60, resulting in an intermediate configuration as shown in Figure 20 Taste;

S41’: sequentially provide an adhesion layer and a barrier layer (not shown in the figure) on the inner walls of the word line isolation trench 50 and the bit line unit trench 21’;

S42': Fill the word line isolation trench 50 and the bit line unit trench 21' with bit line material 21", the bit line material 21" in the bit line unit trench 21' forms a bit line unit, and along the first Multiple bit line units arranged in different directions are connected together to form a bit line, resulting in an intermediate product as shown in Figure 21;

S50’: Remove the bit line material 21” in the word line isolation trench 50 and the second dielectric protective layer on the inner wall of the word line isolation trench 50 to obtain an intermediate product as shown in Figure 22;

S60’: Fill the word line isolation trench with isolation dielectric;

S70': Remove the first dielectric protective layer on the surface of the plurality of semiconductor pillars and the surface of the bit line isolation trench, remove the isolation material on the upper part of the bit line isolation trench, and retain the isolation material on the lower part of the bit line isolation trench. , removing the space vacated by the isolation material to form a gate trench;

S82': Carve back the gate material in the gate trench to a certain depth to obtain a gate surrounding the channel sidewall of the semiconductor pillar. The semiconductor pillar and the gate constitute a transistor, so The gate electrode extends in a direction perpendicular to the substrate to the drain region and the source region where the drain electrode and the source electrode are located, and the gate electrodes of a plurality of transistors arranged along the second direction are connected to the word line. , obtaining the semiconductor device shown in Figure 1A to Figure 1D;

S90': Set a third dielectric protective layer on the upper surface and side surfaces of the semiconductor device obtained in step S80', to obtain the semiconductor device shown in Figures 2A to 2D.

Steps S60' to S90' can be performed with reference to Figures 14A to 16C and 1A to 2D.

In this embodiment of the present application, in step S10', a SADP process may be used to cut the initial bit line isolation trench in the substrate.

In the embodiment of the present application, step S10' may also include: after filling the initial bit line isolation trench with isolation material, using the CMP method to grind the surface of the isolation material in the initial bit line isolation trench until it is consistent with a plurality of The surfaces of the semiconductor walls are flush.

In the embodiment of the present application, in step S20' or S22', a SADP process may be used to cut the word line isolation trench in the intermediate product obtained in step S10' or step S21'.

In this embodiment of the present application, the first dielectric protective layer serves as a hard mask for the plurality of semiconductor walls in step S22', and in subsequent process steps (such as step S30'), the first dielectric protective layer It can also be used to protect the top of the semiconductor pillar.

In this embodiment of the present application, the method of etching the lower part of the word line isolation trench into a "Σ" shape or a bowl shape in step S30' may be wet etching.

In this embodiment of the present application, the material of the substrate may be silicon, and the isolation material may be selected from any one or more of silicon dioxide, silicon nitride, silicon carbonitride oxynitride, and silicon carbonitride. Alternatively, the etching liquid used in the wet etching may be selected from any one or more of tetramethylammonium hydroxide and an ammonia/hydrogen peroxide mixture.

In the embodiment of the present application, in step S31', a second dielectric protective layer can be provided on all exposed surfaces of the intermediate product obtained in step S20', and then the excess second dielectric protective layer is removed, leaving only the word line isolation. A second dielectric protective layer on the inner side wall of the groove.

In this embodiment of the present application, in step S41', a CVD process may be used to sequentially deposit an adhesion layer and a barrier layer on the inner walls of the word line isolation trench and the bit line cell trench.

In the embodiment of the present application, in step S40' or S42', a CVD process may be used to deposit bit line material in the word line isolation trench and the bit line cell trench until the word line isolation trench and the bit line The cell slot is completely filled.

In the embodiment of the present application, step S40' or S42' may also include: after filling the word line isolation trench and the bit line cell trench with bit line material, using the CMP method to flatten the top of the bit line material. change.

In the embodiment of the present application, in step S50', the bit line material in the word line isolation trench can be removed by an etch back method.

An embodiment of the present application also provides an electronic device, including the semiconductor device provided in the above embodiment of the present application.

Although the embodiments disclosed in the present application are as above, the described contents are only used to facilitate the understanding of the present application and are not intended to limit the present application. Anyone skilled in the field to which this application belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the protection scope of this application must still be determined by The scope defined by the appended claims shall prevail.

Claims

A semiconductor device including:

a substrate having an upper surface and a lower surface;

A plurality of transistors are arranged on one side of the substrate and are spaced on the substrate to form an array along a first direction and a second direction. The first direction and the second direction intersect and form a plane with The substrate is parallel; the transistor includes a semiconductor pillar and a gate electrode, the semiconductor pillar is arranged on the substrate and extends into a strip structure along a direction perpendicular to the substrate, and the gate electrode is arranged on On the sidewall of the semiconductor pillar;

A plurality of bit lines, spaced apart along the second direction and extending along the first direction; the bit lines are provided between the upper surface of the substrate and a row of semiconductor pillars arranged along the first direction, and the bit lines It is connected to the bottom end of the semiconductor pillar close to the substrate.
The semiconductor device according to claim 1, further comprising: a plurality of word lines, the plurality of word lines are spaced apart along the first direction and extend along the second direction, each of the word lines is arranged along the second direction. The gates of multiple transistors are connected.
The semiconductor device according to claim 1 or 2, further comprising:

A plurality of word line isolation trenches, the plurality of word line isolation trenches are spaced apart along the first direction and extend along the second direction, and separate the plurality of transistors arranged along the first direction, the word line isolation trench The tank is filled with isolation medium;

A plurality of bit line isolation trenches, the bit line isolation trench is located between a plurality of transistors spaced along the second direction and separates the plurality of bit lines arranged along the second direction.
The semiconductor device according to claim 3, wherein one end of the bit line isolation trench close to the substrate extends into the substrate, the lower part of the bit line isolation trench is filled with isolation material, and the gate electrode A portion of the area is located above the isolation material in the bit line isolation trench.
The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor pillar includes a drain electrode, a channel and a source electrode in sequence, the gate electrode surrounds the sidewalls of the channel, and the A gate oxide layer is provided between the gate electrode and the semiconductor pillar.
The semiconductor device according to any one of claims 1 to 5, wherein the bit line is formed by connecting together a plurality of bit line units arranged in the first direction.
The semiconductor device according to any one of claims 1 to 6, wherein the bit line material forming the bit line is selected from any one or more of tungsten, copper, cobalt and titanium.
The semiconductor device according to claim 3 or 4, wherein the isolation medium is selected from any one or more of silicon nitride, silicon dioxide and silicon carbonitride.
The semiconductor device of claim 5 , wherein the gate electrode extends to sidewalls of the drain electrode and the source electrode in a direction perpendicular to the substrate.
The semiconductor device according to any one of claims 1 to 6, further comprising an adhesion barrier layer disposed between the bottom end of the semiconductor pillar and the bit line and between the liner and the bit line. Between the upper surface of the base and the bit line, the adhesion barrier layer includes an adhesion layer and a barrier layer sequentially arranged in a direction close to the bit line; and/or

The material of the adhesion layer is selected from any one or more of titanium and tantalum; and/or

The material of the barrier layer is selected from any one or more of titanium nitride and tantalum nitride.
The semiconductor device according to claim 5 or 9, wherein the material of the drain electrode is selected from N-type heavily doped silicon; and/or

The material of the channel is selected from P-type lightly doped silicon; and/or

The material of the source electrode is selected from N-type heavily doped silicon.
The semiconductor device according to claim 6, wherein a cross-section of the bit line unit perpendicular to the second direction is "Σ"-shaped or bowl-shaped.
A method for manufacturing a semiconductor device according to any one of claims 1 to 11, comprising:

Provide a substrate having an upper surface and a lower surface, and a sacrificial layer and a semiconductor layer are sequentially disposed on the upper surface of the substrate;

A plurality of initial bit line isolation trenches arranged at intervals along the second direction and extending along the first direction and a plurality of word line isolation trenches arranged at intervals along the first direction and extending along the second direction are provided in the semiconductor layer, and The initial bit line isolation trench extends into the substrate, and the word line isolation trench exposes the sacrificial layer, and the initial bit line isolation trench and the word line isolation trench separate the semiconductor layer by multiple semiconductor pillars;

The sacrificial layer is removed, and the space vacated by the sacrificial layer forms a plurality of bit line unit slots arranged along the first direction and the second direction, and the plurality of bit line unit slots arranged along the first direction are connected together. , a plurality of bit line unit slots arranged along the second direction are spaced apart;

Filling the bit line cell slots with bit line material to form a plurality of bit lines spaced apart along the second direction and extending along the first direction;

A gate oxide layer and a gate electrode are arranged in sequence on the sidewalls of the semiconductor pillar, and the semiconductor pillar and the gate electrode constitute a transistor.
The manufacturing method according to claim 13, wherein a plurality of initial bit line isolation trenches arranged at intervals along the second direction and extending along the first direction and a plurality of initial bit line isolation trenches arranged at intervals along the first direction are provided in the semiconductor layer. The word line isolation trench extends along the second direction, and the initial bit line isolation trench extends into the substrate, and the word line isolation trench exposes the sacrificial layer, and the initial bit line isolation trench and the word line isolation trenches space the semiconductor layer into a plurality of semiconductor pillars, including:

A plurality of initial bit line isolation trenches arranged at intervals along the second direction and extending along the first direction are provided in the semiconductor layer, and the initial bit line isolation trenches extend through the semiconductor layer and the sacrificial layer. In the substrate, a plurality of the initial bit line isolation trenches separate the semiconductor layer into a plurality of semiconductor walls, and the initial bit line isolation trenches are filled with isolation material;

A plurality of word line isolation trenches arranged in the first direction and extending in the second direction are provided in the plurality of semiconductor walls, and the word line isolation trenches penetrate the semiconductor layer and extend into the sacrificial layer, A plurality of the word line isolation trenches separate the plurality of semiconductor walls into a plurality of semiconductor pillars, the semiconductor pillars extend in a direction perpendicular to the substrate into a strip structure, and the strip structure has side walls and both ends, and the sidewalls of the semiconductor pillar in the direction perpendicular to the substrate include a drain, a channel and a source in sequence, and a plurality of the word line isolation trenches isolate a plurality of the initial bit lines. The trenches are interrupted to form multiple bit line isolation trenches.
The manufacturing method according to claim 14, wherein said sequentially arranging a gate oxide layer and a gate electrode on the sidewall of the semiconductor pillar includes:

An interlayer dielectric layer is provided on the inner wall of the word line isolation trench;

Fill the word line isolation trench with isolation dielectric;

Remove the interlayer dielectric layer on the upper part of the inner side wall of the word line isolation trench, and retain the interlayer dielectric layer on the lower part of the inner side wall of the word line isolation trench and the inner bottom surface of the word line isolation trench; and remove the bit The isolation material in the upper part of the line isolation trench is retained, and the isolation material in the lower part of the bit line isolation trench is retained, and the space vacated by the interlayer dielectric layer and the isolation material is removed to form a gate trench;

A gate oxide layer is provided on the inner wall of the gate groove, and the gate material is filled in the gate groove to obtain a gate surrounding the channel sidewall of the semiconductor pillar, which will be arranged along the second direction. The gates of multiple transistors are connected to word lines.
The manufacturing method according to claim 14 or 15, wherein said arranging a plurality of word line isolation trenches arranged along the first direction and extending along the second direction in the plurality of semiconductor walls includes:

A first dielectric protective layer covering the semiconductor wall and the initial bit line isolation trench is provided on the surface of the substrate;

The first dielectric protection layer is used as a hard mask for the plurality of semiconductor walls, and a plurality of word line isolation trenches arranged along the first direction and extending along the second direction are provided in the plurality of semiconductor walls.
The manufacturing method according to claim 14 or 15, wherein removing the sacrificial layer includes:

A second dielectric protective layer is provided on the inner wall of the word line isolation trench, and the second dielectric protective layer on the inner bottom surface of the word line isolation trench is removed, leaving the second dielectric protective layer on the inner wall of the word line isolation trench. dielectric protective layer;

Using the second dielectric protective layer on the inner wall of the word line isolation trench as a hard mask for the side wall of the semiconductor pillar, etch away the sacrificial layer under the word line isolation trench and remove it by side etching sacrificial layer beneath the semiconductor pillar.
The manufacturing method according to claim 17, wherein, under the same etching conditions, the etching rate of the sacrificial layer is greater than the etching rate of the isolation material; and/or

The material of the sacrificial layer is silicon germanium, and the isolation material is selected from any one or more of silicon dioxide, silicon nitride, silicon oxynitride and silicon nitride. The method used to etch the sacrificial layer is The etching liquid is selected from any one or more of tetramethylammonium hydroxide, ammonia and hydrogen peroxide mixture.
The manufacturing method according to any one of claims 13 to 18, wherein the bit line cell slots are filled with bit line material to form a plurality of bit lines spaced apart along the second direction and extending along the first direction. lines, including:

An adhesion layer and a barrier layer are sequentially provided on the inner walls of the word line isolation trench and the bit line unit trench;

The word line isolation trench and the bit line unit trench are filled with bit line material, the bit line material in the bit line unit trench forms a bit line unit, and a plurality of bit line units arranged along the first direction are connected together to form a bit line;

Remove the bit line material in the word line isolation trench.
A method for manufacturing a semiconductor device according to any one of claims 1 to 12, comprising:

A semiconductor substrate is provided, a plurality of initial bit line isolation trenches arranged along a second direction and extending along a first direction are provided in the substrate, and an isolation material is filled in the initial bit line isolation trench, and the plurality of initial bit line isolation trenches are Initial bit line isolation trenches space the substrate into a plurality of semiconductor walls;

A plurality of word line isolation trenches arranged along the first direction and extending along the second direction are provided in the plurality of semiconductor walls, and the plurality of word line isolation trenches separate the plurality of semiconductor walls into a plurality of semiconductor pillars, The semiconductor pillar extends in a direction perpendicular to the substrate into a strip structure, the strip structure has sidewalls and two ends, and the sidewalls of the semiconductor pillar in the direction perpendicular to the substrate are sequentially It includes a drain, a channel and a source, and a plurality of the word line isolation trenches interrupts a plurality of the initial bit line isolation trenches to form a plurality of bit line isolation trenches;

The substrate exposed on the inner bottom surface of the word line isolation trench is etched, and the semiconductor pillars extending into the substrate and toward both sides of the word line isolation trench are formed below the word line isolation trench. A plurality of bit line unit slots extending below, and a plurality of bit line unit slots arranged along the first direction are connected together, and the plurality of bit line unit slots arranged along the second direction are spaced apart by the bit line isolation slots;

The word line isolation trench and the bit line unit trench are filled with bit line material, the bit line material in the bit line unit trench forms a bit line unit, and a plurality of bit line units arranged along the first direction are connected together to form a bit line;

removing bit line material in the word line isolation trench;

Fill the word line isolation trench with isolation dielectric;

Remove the isolation material in the upper part of the bit line isolation trench, retain the isolation material in the lower part of the bit line isolation trench, and form a gate trench in the space vacated by removing the isolation material;

A gate oxide layer is provided on the inner wall of the gate groove, and the gate material is filled in the gate groove to obtain a gate surrounding the side walls of the channel of the semiconductor pillar. The semiconductor pillar and The gate electrode constitutes a transistor and connects the gate electrodes of a plurality of transistors arranged along the second direction to the word line.
The method of manufacturing a semiconductor device according to claim 20, wherein the substrate is etched to expose the inner bottom surface of the word line isolation trench, and a formation extending into the word line isolation trench is formed below the word line isolation trench. The substrate and a plurality of bit line unit trenches extending below the semiconductor pillars on both sides of the word line isolation trench also include:

Etching the bit line unit trench to have a "Σ" shape or a bowl shape in cross section perpendicular to the second direction and/or etching the bit line unit trench under the same etching conditions , the etching rate of the substrate is greater than the etching rate of the isolation material; and/or

The material of the substrate is silicon, and the isolation material is selected from any one or more of silicon dioxide, silicon nitride, silicon oxynitride, and silicon nitride. The bit line cell groove is etched. The etching liquid used is selected from any one or more of a mixture of tetramethylammonium hydroxide, ammonia and hydrogen peroxide.
The manufacturing method of a semiconductor device according to claim 20 or 21, wherein said arranging a plurality of word line isolation trenches arranged in the first direction and extending in the second direction in the plurality of semiconductor walls includes:

A first dielectric protective layer covering the semiconductor wall and the initial bit line isolation trench is provided on the surface of the substrate;

The first dielectric protection layer is used as a hard mask for the plurality of semiconductor walls, and a plurality of word line isolation trenches arranged along the first direction and extending along the second direction are provided in the plurality of semiconductor walls.
The method of manufacturing a semiconductor device according to claim 22, wherein the substrate is etched to expose the inner bottom surface of the word line isolation trench, and a formation extending into the word line isolation trench is formed below the word line isolation trench. The substrate and a plurality of bit line unit trenches extending below the semiconductor pillars on both sides of the word line isolation trench also include:

A second dielectric protective layer is provided on the inner wall of the word line isolation trench;

Remove the second dielectric protective layer on the inner bottom surface of the word line isolation trench to expose the substrate, and retain the second dielectric protective layer on the inner side wall of the word line isolation trench;

Using the second dielectric protective layer on the inner wall of the word line isolation trench as a hard mask for the side wall of the semiconductor pillar, the substrate exposed on the inner bottom surface of the word line isolation trench is etched. A plurality of bit line unit trenches are formed below the word line isolation trench and extend into the substrate and extend toward the bottom of the semiconductor pillars on both sides of the word line isolation trench, and a plurality of bit lines are arranged along a first direction. The cell slots are connected together, and a plurality of bit line unit slots arranged along the second direction are spaced apart by the bit line isolation slots.
The method of manufacturing a semiconductor device according to any one of claims 20 to 23, wherein the word line isolation groove and the bit line cell groove are filled with bit line material, and the bit line material in the bit line cell groove is The line material forms a bit line unit, and multiple bit line units arranged along the first direction are connected together to form a bit line, including:

An adhesion layer and a barrier layer are sequentially provided on the inner walls of the word line isolation trench and the bit line unit trench;

The word line isolation trench and the bit line unit trench are filled with bit line material, the bit line material in the bit line unit trench forms a bit line unit, and a plurality of bit line units arranged along the first direction are connected together to form A bit line.
An electronic device including the semiconductor device according to any one of claims 1 to 12.
The electronic device according to claim 25, comprising a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device or a mobile power supply.