WO2023240779A1 - 一种图小样本学习的存内计算方法、装置及电子设备 - Google Patents

一种图小样本学习的存内计算方法、装置及电子设备 Download PDF

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WO2023240779A1
WO2023240779A1 PCT/CN2022/112494 CN2022112494W WO2023240779A1 WO 2023240779 A1 WO2023240779 A1 WO 2023240779A1 CN 2022112494 W CN2022112494 W CN 2022112494W WO 2023240779 A1 WO2023240779 A1 WO 2023240779A1
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feature vector
binary feature
encoder
category
graph
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PCT/CN2022/112494
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English (en)
French (fr)
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尚大山
张握瑜
王少聪
李熠
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中国科学院微电子研究所
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the fields of machine learning and artificial intelligence, and in particular to an in-memory computing method, device and electronic equipment for graph small sample learning.
  • Memory Augmented Neural Network saves some task-related information in the external memory unit by introducing external memory units, which can be read from the external memory units when needed. This learning method can Effectively solve small sample learning problems.
  • MANN Memory Augmented Neural Network
  • CPU Central Processing Unit
  • DRAM Dynamic Random Access Memory
  • MANN still faces challenges in algorithm and hardware implementation.
  • memory enhancement networks composed of traditional deep learning algorithms (such as convolutional neural networks) can successfully process data in Euclidean space, such as images, text, etc.
  • traditional convolutional neural networks to construct memory enhancement networks.
  • the graph neural network can effectively extract the characteristics of graph data, and the memory enhancement network composed of it can realize small sample learning of graphs.
  • the memory enhancement network will face the parameter optimization problem that is time-consuming and energy-consuming.
  • the CAM-based external memory unit can reduce the delay and power consumption during retrieval
  • MANN's controller is still implemented using GPU, which results in a large amount of power consumption during the feature extraction process.
  • the controller and external memory use different device structures and peripheral circuit designs, it is difficult to integrate the two on the same chip, which limits the expansion of the MANN network.
  • the present application discloses an in-memory computing method, device and electronic device for graph small sample learning, and is used to provide an in-memory computing method and device for graph small sample learning.
  • this application provides an in-memory computing method for graph small sample learning, which is applied to a memory-enhanced graph network including interconnected controllers, encoders and external memory units.
  • the method includes:
  • the predicted category of the sample is determined based on the first binary feature vector and the second binary feature vector.
  • the in-memory computing method of graph small sample learning provided by this application is applied to a memory-enhanced graph network including interconnected controllers, encoders and external memory units.
  • the encoding can be Initialize the parameters of the controller, divide the graph data set into a training set and a test set, randomly select a preset category and a preset number of support sets in the training set, and input the support set to the controller and
  • the encoder obtains a first binary feature vector, stores the first binary feature vector and the label corresponding to the first binary feature vector into the external memory unit, and randomly selects it from the training set
  • a query set of the preset category and the preset number the query set is input to the controller and the encoder to obtain a second binary feature vector, based on the first binary feature vector and
  • the second binary feature vector determines the prediction category of the sample, which can quickly determine the sample category, reduce time and energy consumption, and improve the reliability and stability of the memory-enhanced graph network.
  • determining the prediction category of the sample based on the first binary feature vector and the second binary feature vector includes:
  • the predicted category of the sample is determined based on the feature similarity.
  • the method further includes:
  • the parameters of the encoder are updated based on the prediction error value.
  • a preset category and a preset number of support sets are randomly selected from the training set, and the support set is input to the controller and the encoder to obtain the first Binary feature vectors, including:
  • a preset category and a preset number of the support set are randomly selected from the training set, the support set is input to the controller, and the graph data set is processed through the echo state graph network of the controller. Feature extraction to obtain node features of the graph data set;
  • the node features are input to the encoder, and the node features are converted into the first binary feature vector through the binary neural network of the encoder.
  • determining the feature similarity between the first binary feature vector and the second binary feature vector includes:
  • a dot product formula is used to calculate the feature similarity between the first binary feature vector and the second binary feature vector.
  • the categories of the training set and the test set do not overlap.
  • this application also provides an in-memory computing device for graph small sample learning, applied in a memory enhancement graph network including interconnected controllers, encoders and external memory units.
  • the device includes:
  • An initialization module used to initialize the parameters of the encoder and divide the graph data set into a training set and a test set;
  • a first acquisition module configured to randomly select a preset category and a preset number of support sets in the training set, input the support set to the controller and the encoder, and obtain a first binary feature vector ;
  • a first storage module configured to store the first binary feature vector and the label corresponding to the first binary feature vector into the external memory unit
  • a second acquisition module is used to randomly select a query set of the preset category and the preset number in the training set, and input the query set to the controller and the encoder to obtain a second second acquisition module.
  • value eigenvector
  • a first determination module configured to determine the prediction category of the sample based on the first binary feature vector and the second binary feature vector.
  • the device further includes:
  • the third obtaining module is used to randomly select a preset category and a preset number of the support set in the test set, input the support set to the controller and the encoder, and obtain the first Binary feature vector;
  • a second storage module configured to store the first binary feature vector and the label corresponding to the first binary feature vector into the external memory unit
  • the fourth obtaining module is used to randomly select one of the preset categories and the preset number of the query set in the test set, and input the query set to the controller and the encoder to obtain the third query set.
  • a second determination module configured to determine the prediction category of the sample based on the first binary feature vector and the second binary feature vector.
  • the first determining module includes:
  • the first determination sub-module is used to determine the feature similarity between the first binary feature vector and the second binary feature vector
  • the second determination sub-module is used to determine the predicted category of the sample based on the feature similarity.
  • the device further includes:
  • a third determination module configured to determine a prediction error value according to the prediction category and the label during the training of the memory enhancement graph network
  • An update module configured to update parameters of the encoder based on the prediction error value.
  • the first obtaining module includes:
  • a conversion submodule configured to input the node features to the encoder, and convert the node features into the first binary feature vector through the binary neural network of the encoder.
  • the first determining sub-module includes:
  • a calculation unit configured to use a dot product formula to calculate the feature similarity between the first binary feature vector and the second binary feature vector when performing retrieval.
  • the categories of the training set and the test set do not overlap.
  • the beneficial effects of the in-memory computing device for graph small sample learning provided in the second aspect are the same as the beneficial effects of the in-memory computing method for graph small sample learning described in the first aspect or any possible implementation of the first aspect, and are not discussed here. To elaborate.
  • the present application also provides an electronic device, including: one or more processors; and one or more machine-readable media having instructions stored thereon, which when executed by the one or more processors , causing the device to perform the in-memory computing device for graph small sample learning described in any possible implementation manner of the second aspect.
  • the beneficial effects of the electronic device provided in the third aspect are the same as the beneficial effects of the in-memory computing device for graph small sample learning described in the second aspect or any possible implementation of the second aspect, and will not be described again here.
  • Figure 1 shows a schematic structural diagram of a memory enhancement graph network provided by an embodiment of the present application
  • Figure 2 shows a schematic flow chart of an in-memory computing method for graph small sample learning provided by an embodiment of the present application
  • Figure 3 shows a schematic flow chart of another in-memory computing method for graph small sample learning provided by an embodiment of the present application
  • Figure 4 shows a schematic diagram of in-memory computing hardware for implementing graph small sample learning provided by an embodiment of the present application
  • Figure 5 shows a structural flow chart of an in-memory computing device for small sample learning provided by an embodiment of the present application
  • Figure 6 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • Figure 1 shows a schematic structural diagram of a memory enhancement graph network provided by an embodiment of the present application.
  • the memory enhancement graph network includes a controller 101, an encoder 102 and an external memory unit 103 that are connected to each other.
  • FIG. 2 shows a schematic flowchart of an in-memory computing method for graph small sample learning provided by an embodiment of the present application, which is applied to a memory enhancement graph network including interconnected controllers, encoders and external memory units, as shown in Figure
  • the in-memory calculation method of small sample learning in this figure includes:
  • Step 201 Initialize the parameters of the encoder and divide the graph data set into a training set and a test set.
  • the categories of the training set and the test set do not overlap.
  • Step 202 Randomly select a preset category and a preset number of support sets from the training set, input the support set to the controller and the encoder, and obtain a first binary feature vector.
  • a preset category and a preset number of the support set can be randomly selected from the training set, the support set is input to the controller, and the echo state diagram network of the controller is used to
  • the graph data set performs feature extraction to obtain node features of the graph data set; further, the node features are input to the encoder, and the node features are converted into Convert to the first binary feature vector.
  • Step 203 Store the first binary feature vector and the label corresponding to the first binary feature vector in the external memory unit.
  • Step 204 Randomly select a query set of the preset category and the preset number from the training set, and input the query set to the controller and the encoder to obtain a second binary feature vector.
  • Step 205 Determine the prediction category of the sample based on the first binary feature vector and the second binary feature vector.
  • the devices used to implement in-memory computing are not limited to random access memory (RRAM) devices, but also include flash memory (Flash), ferroelectric field effect transistors (FeFET), and non-volatile magnetic random devices.
  • flash memory Flash
  • FeFET ferroelectric field effect transistors
  • MRAM non-volatile magnetic random devices.
  • Non-volatile devices such as memory (MRAM).
  • the in-memory computing method for graph small sample learning is applied to a memory-enhanced graph network including interconnected controllers, encoders, and external memory units.
  • the parameters of the encoder can be initialized. , divide the graph data set into a training set and a test set, randomly select a preset category and a preset number of support sets in the training set, input the support set to the controller and the encoder, and obtain a first binary feature vector, store the first binary feature vector and the label corresponding to the first binary feature vector in the external memory unit, and randomly select one of the preset categories in the training set and the preset number of query sets, input the query set to the controller and the encoder to obtain a second binary feature vector, based on the first binary feature vector and the second binary feature vector
  • the feature vector determines the prediction category of the sample, which can quickly determine the sample category, reduce time and energy consumption, and improve the reliability and stability of the memory-enhanced graph network.
  • Figure 3 shows a schematic flowchart of another in-memory computing method for graph small sample learning provided by the embodiment of the present application, applied to memory enhancement graphs including interconnected controllers, encoders and external memory units.
  • the in-memory calculation method of small sample learning in this figure includes:
  • Step 301 Initialize the parameters of the encoder and divide the graph data set into a training set and a test set.
  • the parameters of the encoder can be initialized, and the graph data set can be divided into a training set and a test set, and the categories of the training set and the test set do not overlap.
  • Step 302 Randomly select a preset category and a preset number of support sets from the training set, input the support set to the controller and the encoder, and obtain a first binary feature vector.
  • a preset category and a preset number of the support set can be randomly selected from the training set, the support set is input to the controller, and the echo state diagram network of the controller is used to
  • the graph data set performs feature extraction to obtain the node features of the graph data set; the node features are input to the encoder, and the node features are converted into the node features through the binary neural network of the encoder.
  • the first binary feature vector is
  • the controller can use an echo state graph network and use a random matrix to extract node features of the graph.
  • the node state iteration process is as shown in formula (1).
  • the characteristics of the i-th node at the t-th time step are: Expressed as:
  • u i represents the input information of the i-th node
  • the input matrix W in is multiplied by the node state X i to obtain u i
  • N(i) represents the i-th node
  • the set of neighbor nodes of a node, the input matrix W in and the hidden matrix W h are random matrices, and ⁇ represents the leakage rate.
  • the encoder can use a layer of binary neural network to convert the node features output by the echo state diagram network into binary feature vectors, and store them in the external memory unit for forward propagation of the encoder.
  • Step 303 Store the first binary feature vector and the label corresponding to the first binary feature vector in the external memory unit.
  • the external memory unit can store the first binary feature vector of the node and its corresponding label.
  • a Support Set (support set) can be selected at any time from the training set, where the support set consists of m categories, and n samples are randomly selected from each category.
  • the second binary feature vector can be obtained from the samples in the support set through the controller and the encoder, and the second binary feature vector and its corresponding label can be stored in an external memory unit.
  • Step 304 Randomly select a query set of the preset category and the preset number from the training set, and input the query set to the controller and the encoder to obtain a second binary feature vector.
  • the query set (Query set) can be randomly selected from the training set, where the categories of the query set and the support set are the same, n samples are selected from the remaining samples in these m categories, and the samples of the query set are passed through the control
  • the encoder and encoder obtain the second binary feature vector.
  • Step 305 Determine the prediction category of the sample based on the first binary feature vector and the second binary feature vector.
  • the feature similarity between the first binary feature vector and the second binary feature vector can be determined; further, the prediction category of the sample is determined based on the feature similarity.
  • a dot product formula can be used to calculate the feature similarity between the first binary feature vector and the second binary feature vector, as shown in formula (4):
  • Step 306 In the process of training the memory enhancement graph network, determine a prediction error value according to the prediction category and the label.
  • the prediction error value can be calculated based on the predicted categories and true categories of the query set.
  • Step 307 Update parameters of the encoder based on the prediction error value.
  • parameters in the encoder can be adjusted based on the prediction error value to improve learning capabilities.
  • Step S1 Randomly select a preset category and a preset number of the support set in the test set, input the support set to the controller and the encoder, and obtain the first binary feature vector .
  • Step S2 Store the first binary feature vector and the label corresponding to the first binary feature vector in the external memory unit.
  • Step S3 Randomly select one of the preset categories and the preset number of the query set from the test set, and input the query set to the controller and the encoder to obtain a second binary feature vector.
  • Step S4 Determine the prediction category of the sample based on the first binary feature vector and the second binary feature vector.
  • Figure 4 shows a schematic diagram of in-memory computing hardware for implementing graph small sample learning provided by the embodiment of the present application.
  • the controller includes a random RRAM (random access memory) array
  • the encoder includes a Programming RRAM array
  • the external memory unit includes a programmable RRAM array, wherein the external memory unit can store the content input by the encoder, and the external memory unit can retrieve the content in the encoder.
  • the randomness of the resistance change of the main variable memory device in the process of acquiring the set (SET) is used to implement the random matrix (input matrix W in and hidden matrix W h ) in the controller, and the binary state of the resistive variable memory device is used to implement encoding.
  • the binary weights in the device and the eigenvectors and labels of the external memory units are used to realize random matrices and binary matrices on the same memristor array by taking advantage of the randomness and binary resistance state characteristics of the memristor device. Due to the memristor The device has the ability to be rewritable, so the hardware implementation of the memory-enhanced graph network has reconfigurable characteristics.
  • the in-memory computing method for graph small sample learning is applied to a memory-enhanced graph network including interconnected controllers, encoders, and external memory units.
  • the parameters of the encoder can be initialized. , divide the graph data set into a training set and a test set, randomly select a preset category and a preset number of support sets in the training set, input the support set to the controller and the encoder, and obtain a first binary feature vector, store the first binary feature vector and the label corresponding to the first binary feature vector in the external memory unit, and randomly select one of the preset categories in the training set and the preset number of query sets, input the query set to the controller and the encoder to obtain a second binary feature vector, based on the first binary feature vector and the second binary feature vector
  • the feature vector determines the prediction category of the sample, which can quickly determine the sample category, reduce time and energy consumption, and improve the reliability and stability of the memory-enhanced graph network.
  • Figure 5 shows a schematic structural diagram of an in-memory computing device for graph small sample learning provided by an embodiment of the present application, which is applied to a memory enhancement graph network including interconnected controllers, encoders and external memory units, as shown in Figure As shown in 5, the in-memory computing device 400 for small sample learning in this figure includes:
  • Initialization module 401 is used to initialize the parameters of the encoder and divide the graph data set into a training set and a test set;
  • the first acquisition module 402 is used to randomly select a preset category and a preset number of support sets in the training set, input the support set to the controller and the encoder, and obtain the first binary feature vector;
  • Storage module 403 configured to store the first binary feature vector and the label corresponding to the first binary feature vector into the external memory unit;
  • the second obtaining module 404 is used to randomly select a query set of the preset category and the preset number in the training set, and input the query set to the controller and the encoder to obtain a second query set.
  • Binary feature vector
  • the first determination module 405 is configured to determine the prediction category of the sample based on the first binary feature vector and the second binary feature vector.
  • the device further includes:
  • the third obtaining module is used to randomly select a preset category and a preset number of the support set in the test set, input the support set to the controller and the encoder, and obtain the first Binary feature vector;
  • a second storage module configured to store the first binary feature vector and the label corresponding to the first binary feature vector into the external memory unit
  • the fourth obtaining module is used to randomly select one of the preset categories and the preset number of the query set in the test set, and input the query set to the controller and the encoder to obtain the third query set.
  • a second determination module configured to determine the prediction category of the sample based on the first binary feature vector and the second binary feature vector.
  • the first determining module includes:
  • the first determination sub-module is used to determine the feature similarity between the first binary feature vector and the second binary feature vector
  • the second determination sub-module is used to determine the predicted category of the sample based on the feature similarity.
  • the device further includes:
  • a third determination module configured to determine a prediction error value according to the prediction category and the label during the training of the memory enhancement graph network
  • An update module configured to update parameters of the encoder based on the prediction error value.
  • the first obtaining module includes:
  • a conversion submodule configured to input the node features to the encoder, and convert the node features into the first binary feature vector through the binary neural network of the encoder.
  • the first determining sub-module includes:
  • a calculation unit configured to use a dot product formula to calculate the feature similarity between the first binary feature vector and the second binary feature vector when performing retrieval.
  • the categories of the training set and the test set do not overlap.
  • the in-memory computing device for graph small sample learning is applied in a memory-enhanced graph network including interconnected controllers, encoders and external memory units.
  • the parameters of the encoder can be initialized. , divide the graph data set into a training set and a test set, randomly select a preset category and a preset number of support sets in the training set, input the support set to the controller and the encoder, and obtain a first binary feature vector, store the first binary feature vector and the label corresponding to the first binary feature vector in the external memory unit, and randomly select one of the preset categories in the training set and the preset number of query sets, input the query set to the controller and the encoder to obtain a second binary feature vector, based on the first binary feature vector and the second binary feature vector
  • the feature vector determines the prediction category of the sample, which can quickly determine the sample category, reduce time and energy consumption, and improve the reliability and stability of the memory-enhanced graph network.
  • the present application provides an in-memory computing device for graph small sample learning, which is applied to the memory computing device for graph small sample learning as shown in any one of Figures 1 to 4, including a controller and at least one detection circuit electrically connected to the controller.
  • the calculation method is not repeated here to avoid repetition.
  • the electronic device in the embodiment of the present application may be a device, or may be a component, integrated circuit, or chip in a terminal.
  • the device may be a mobile electronic device or a non-mobile electronic device.
  • the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a handheld computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (personal digital assistant).
  • UMPC ultra-mobile personal computer
  • PDA personal digital assistant
  • non-mobile electronic devices can be servers, network attached storage (Network Attached Storage, NAS), personal computers (personal computers, PC), televisions (television, TV), teller machines or self-service machines, etc., this application The examples are not specifically limited.
  • the electronic device in the embodiment of the present application may be a device with an operating system.
  • the operating system may be an Android operating system, an IOS operating system, or other possible operating systems, which are not specifically limited in the embodiments of this application.
  • FIG. 6 shows a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application.
  • the electronic device 500 includes a processor 510 .
  • the above-mentioned processor 510 can be a general central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more control units.
  • the application program is implemented on an integrated circuit.
  • the above-mentioned electronic device 500 may further include a communication line 540 .
  • Communication line 540 may include a path for communicating information between the above-mentioned components.
  • the above-mentioned electronic device may also include a communication interface 520.
  • a communication interface 520 There may be one or more communication interfaces 520 .
  • Communication interface 520 may use any transceiver-like device for communicating with other devices or communication networks.
  • the electronic device may also include a memory 530 .
  • the memory 530 is used to store computer execution instructions for executing the solution of the present application, and is controlled by the processor for execution.
  • the processor is used to execute computer execution instructions stored in the memory, thereby implementing the method provided by the embodiment of the present application.
  • the memory 530 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (random access memory, RAM) or a Other types of dynamic storage devices for information and instructions, which may also be electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or Other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store desired information in the form of instructions or data structures Program code and any other medium capable of being accessed by a computer, without limitation.
  • the memory 530 may exist independently and be connected to the processor 510 through the communication line 540. Memory 530 may also be integrated with processor 510.
  • the computer-executed instructions in the embodiments of the present application may also be called application codes, which are not specifically limited in the embodiments of the present application.
  • the processor 510 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 6 .
  • the terminal device may include multiple processors, such as the first processor 5101 and the second processor 5102 in Figure 6.
  • processors can be a single-core processor or a multi-core processor.
  • Figure 7 is a schematic structural diagram of a chip provided by an embodiment of the present application. As shown in FIG. 7 , the chip 600 includes one or more (including two) processors 510 .
  • the chip also includes a communication interface 520 and a memory 530.
  • the memory 530 can include a read-only memory and a random access memory, and provides operating instructions and data to the processor. Part of the memory may also include non-volatile random access memory (NVRAM).
  • NVRAM non-volatile random access memory
  • memory 530 stores the following elements, execution modules or data structures, or a subset thereof, or an extended set thereof.
  • the corresponding operation is performed by calling the operation instructions stored in the memory (the operation instructions can be stored in the operating system).
  • the processor 510 controls the processing operations of any one of the terminal devices.
  • the processor 510 may also be called a central processing unit (CPU).
  • memory 530 may include read-only memory and random access memory and provide instructions and data to the processor. Portion of memory 530 may also include NVRAM.
  • the memory, communication interface and memory are coupled together through a bus system.
  • the bus system may also include a power bus, a control bus, a status signal bus, etc.
  • the various buses are labeled bus system 640 in FIG. 7 .
  • the method disclosed in the above embodiment of the present application can be applied in a processor or implemented by the processor.
  • the processor may be an integrated circuit chip that has signal processing capabilities.
  • each step of the above method can be completed by instructions in the form of hardware integrated logic circuits or software in the processor.
  • the above-mentioned processor can be a general-purpose processor, digital signal processing (DSP), ASIC, off-the-shelf programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic. devices, discrete hardware components.
  • DSP digital signal processing
  • ASIC application-the-shelf programmable gate array
  • FPGA field-programmable gate array
  • Each method, step and logical block diagram disclosed in the embodiment of this application can be implemented or executed.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • the steps of the method disclosed in conjunction with the embodiments of the present application can be directly implemented by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other mature storage media in this field.
  • the storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.
  • a computer-readable storage medium is provided. Instructions are stored in the computer-readable storage medium. When the instructions are executed, the functions performed by the terminal device in the above embodiments are realized.
  • a chip is provided.
  • the chip is used in terminal equipment.
  • the chip includes at least one processor and a communication interface.
  • the communication interface is coupled to at least one processor.
  • the processor is used to run instructions to implement the above embodiment as shown in Figure 1. Functions performed by in-memory computing methods for sample learning.
  • the computer program product includes one or more computer programs or instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user equipment, or other programmable device.
  • the computer program or instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another.
  • the computer program or instructions may be transmitted from a website, computer, A server or data center transmits via wired or wireless means to another website site, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media.
  • the available media may be magnetic media, such as floppy disks, hard disks, and magnetic tapes; they may also be optical media, such as digital video discs (DVDs); they may also be semiconductor media, such as solid state drives (solid state drives). ,SSD).

Abstract

一种图小样本学习的存内计算方法、装置及电子设备，涉及机器学习及人工智能领域，开发记忆增强图网络模型实现图小样本学习功能并采用存内计算架构进行硬件实现。方法包括:将编码器的参数进行初始化处理，将图数据集分为训练集和测试集;在训练集中随机选取一个预设类别和预设数量的支持集，将支持集输入至控制器和编码器获得第一二值特征向量;将第一二值特征向量和第一二值特征向量对应的标签存储至外部记忆单元中;在训练集中随机选取一个预设类别和预设数量的查询集，将查询集输入至控制器和编码器获得第二二值特征向量;基于第一二值特征向量和第二二值特征向量确定样本的预测类别，可以快速确定样本类别。

Description

一种图小样本学习的存内计算方法、装置及电子设备
本申请要求于2022年06月15日提交中国专利局、申请号为202210681923.2、申请名称为“一种图小样本学习的存内计算方法、装置及电子设备”的中国专利优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及机器学习及人工智能领域，尤其涉及一种图小样本学习的存内计算方法、装置及电子设备。
背景技术
随着机器学习及人工智能领域的发展，深度学习在人工智能和机器学习中占据极其重要的部分，大数据时代的到来加快了深度学习的发展。但是在实际的开放环境中，数据的获取和标注均是十分耗时耗力的，神经网络需要在有限的样本数量下提高泛化能力。
记忆增强网络(Memory Augmented Neural Network，MANN)通过引入外部记忆单元，将一些与任务相关的信息保存在外部记忆单元中，在需要的时候可以从外部记忆单元中进行读取，这种学习方法可以有效解决小样本学习问题。在MANN的硬件实现上，可以采用传统的数字电路中央处理器(Central Processing Unit，CPU)加动态随机存取存储器(Dynamic Random Access Memory,DRAM)的方式，但是由于受到冯诺依曼瓶颈的限制，大量数据的存取会导致高延时和高功耗的问题。尽管基于内容可寻址存储器(Content-addressable Memory,CAM)的外部记忆单元能高速并行地进行检索，MANN在算法和硬件实现上仍面临挑战。
在算法上，由传统的深度学习算法(如卷积神经网络)构成的记忆增强网络能够成功处理欧式空间中的数据，如图像、文本等。但是在位于非欧空间中的图数据上，采用传统卷积神经网络构建记忆增强网络的效果较差。这是由于图数据是不规则的，图中节点间相互连接的特点。图神经网络能够有效提取图数据特征，由其构成的记忆增强网络能实现图的小样本学习，但是该记忆增强 网络会面临耗时耗能的参数优化问题。
在硬件实现上，尽管基于CAM的外部记忆单元能够降低检索时的延时和功耗，MANN的控制器仍然采用GPU实现，在特征提取的过程中导致大量的功耗。此外，由于控制器和外部记忆采用不同的器件结构和外围电路设计，很难将二者集成到同一块芯片上，这限制了MANN网络的扩展。
发明内容
有鉴于此，本申请公开了图小样本学习的存内计算方法、装置及电子设备，用于提供一种图小样本学习的存内计算方法和装置。
第一方面，本申请提供一种图小样本学习的存内计算方法，应用于包括相互连接的控制器、编码器和外部记忆单元的记忆增强图网络中，所述方法包括：
将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集；
在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量；
将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中；
在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量；
基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
采用上述技术方案的情况下，本申请提供的图小样本学习的存内计算方法，应用于包括相互连接的控制器、编码器和外部记忆单元的记忆增强图网络中，可以通过将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集，在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量，将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中，在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量，基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别，可以快速确 定样本类别，降低耗时降低耗能，提高记忆增强图网络的可靠性和稳定性。
在一种可能的实现方式中，所述基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别，包括：
确定所述第一二值特征向量和所述第二二值特征向量的特征相似度；
基于所述特征相似度确定样本的预测类别。
在一种可能的实现方式中，在基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别之后，所述方法还包括：
在对所述记忆增强图网络进行训练的过程中，根据所述预测类别和所述标签确定预测误差值；
基于所述预测误差值更新所述编码器的参数。
在一种可能的实现方式中，所述在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量，包括：
在所述训练集中随机选取一个预设类别和预设数量的所述支持集，将所述支持集输入至所述控制器，通过所述控制器的回声状态图网络对所述图数据集进行特征提取，获得所述图数据集的节点特征；
将所述节点特征输入至所述编码器，通过所述编码器的二值神经网络，将所述节点特征转换为所述第一二值特征向量。
在一种可能的实现方式中，所述确定所述第一二值特征向量和所述第二二值特征向量的特征相似度，包括：
在进行检索时，采用点乘公式计算所述第一二值特征向量和所述第二二值特征向量的所述特征相似度。
在一种可能的实现方式中，所述训练集和所述测试集的类别不交叉。
第二方面，本申请还提供一种图小样本学习的存内计算装置，应用于包括相互连接的控制器、编码器和外部记忆单元的记忆增强图网络中，所述装置包括：
初始化模块，用于将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集；
第一获得模块，用于在所述训练集中随机选取一个预设类别和预设数量的 支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量；
第一存储模块，用于将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中；
第二获得模块，用于在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量；
第一确定模块，用于基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
在一种可能的实现方式中，所述装置还包括：
第三获得模块，用于在所述测试集中随机选取一个预设类别和预设数量的所述支持集，将所述支持集输入至所述控制器和所述编码器，获得所述第一二值特征向量；
第二存储模块，用于将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中；
第四获得模块，用于在所述测试集中随机选取一个所述预设类别和所述预设数量的所述查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量；
第二确定模块，用于基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
在一种可能的实现方式中，所述第一确定模块包括：
第一确定子模块，用于确定所述第一二值特征向量和所述第二二值特征向量的特征相似度；
第二确定子模块，用于基于所述特征相似度确定样本的预测类别。
在一种可能的实现方式中，所述装置还包括：
第三确定模块，用于在对所述记忆增强图网络进行训练的过程中，根据所述预测类别和所述标签确定预测误差值；
更新模块，用于基于所述预测误差值更新所述编码器的参数。
在一种可能的实现方式中，所述第一获得模块包括：
获得子模块，用于在所述训练集中随机选取一个预设类别和预设数量的所述支持集，将所述支持集输入至所述控制器，通过所述控制器的回声状态图网络对所述图数据集进行特征提取，获得所述图数据集的节点特征；
转换子模块，用于将所述节点特征输入至所述编码器，通过所述编码器的二值神经网络，将所述节点特征转换为所述第一二值特征向量。
在一种可能的实现方式中，所述第一确定子模块包括：
计算单元，用于在进行检索时，采用点乘公式计算所述第一二值特征向量和所述第二二值特征向量的所述特征相似度。
在一种可能的实现方式中，所述训练集和所述测试集的类别不交叉。
第二方面提供的图小样本学习的存内计算装置的有益效果与第一方面或第一方面任一可能的实现方式描述的图小样本学习的存内计算方法的有益效果相同，此处不做赘述。
第三方面，本申请还提供一种电子设备，包括：一个或多个处理器；和其上存储有指令的一个或多个机器可读介质，当由所述一个或多个处理器执行时，使得所述装置执行第二方面任一可能的实现方式描述的图小样本学习的存内计算装置。
第三方面提供的电子设备的有益效果与第二方面或第二方面任一可能的实现方式描述的图小样本学习的存内计算装置的有益效果相同，此处不做赘述。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图进行说明：
图1示出了本申请实施例提供的一种记忆增强图网络的结构示意图；
图2示出了本申请实施例提供的一种图小样本学习的存内计算方法的流程示意图；
图3示出了本申请实施例提供的另一种图小样本学习的存内计算方法的流程示意图；
图4示出了本申请实施例提供的一种实现图小样本学习的存内计算硬件示意图；
图5示出了本申请实施例提供的一种图小样本学习的存内计算装置的结构流程图；
图6为本申请实施例提供的一种电子设备的硬件结构示意图；
图7为本申请实施例提供的芯片的结构示意图。
具体实施方式
本申请的核心是提供了一种图小样本学习的存内计算方法。图1示出了本申请实施例提供的一种记忆增强图网络的结构示意图，如图1所示，所述记忆增强图网络包括相互连接的控制器101、编码器102和外部记忆单元103。
图2示出了本申请实施例提供的一种图小样本学习的存内计算方法的流程示意图，应用于包括相互连接的控制器、编码器和外部记忆单元的记忆增强图网络中，如图2所示，该图小样本学习的存内计算方法包括：
步骤201：将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集。
在本申请中，所述训练集和所述测试集的类别不交叉。
步骤202：在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量。
在本申请中，可以在所述训练集中随机选取一个预设类别和预设数量的所述支持集，将所述支持集输入至所述控制器，通过所述控制器的回声状态图网络对所述图数据集进行特征提取，获得所述图数据集的节点特征；进一步的，将所述节点特征输入至所述编码器，通过所述编码器的二值神经网络，将所述节点特征转换为所述第一二值特征向量。
步骤203：将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中。
步骤204：在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量。
步骤205：基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
需要说明的是，在本申请中，存内计算实现使用的器件不限于随机存取存 储器(RRAM)器件，也包括闪存(Flash)，铁电场效应晶体管(FeFET)，非易失性的磁性随机存储器(MRAM)等非易失性器件。
本申请实施例提供的图小样本学习的存内计算方法，应用于包括相互连接的控制器、编码器和外部记忆单元的记忆增强图网络中，可以通过将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集，在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量，将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中，在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量，基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别，可以快速确定样本类别，降低耗时降低耗能，提高记忆增强图网络的可靠性和稳定性。
可选的，图3示出了本申请实施例提供的另一种图小样本学习的存内计算方法的流程示意图，应用于包括相互连接的控制器、编码器和外部记忆单元的记忆增强图网络中，参见图3，该图小样本学习的存内计算方法包括：
步骤301：将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集。
在本申请中，可以将所述编码器的参数进行初始化，将图数据集划分为训练集和测试集，训练集和测试集的类别不交叉。
步骤302：在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量。
在本申请中，可以在所述训练集中随机选取一个预设类别和预设数量的所述支持集，将所述支持集输入至所述控制器，通过所述控制器的回声状态图网络对所述图数据集进行特征提取，获得所述图数据集的节点特征；将所述节点特征输入至所述编码器，通过所述编码器的二值神经网络，将所述节点特征转换为所述第一二值特征向量。
可选的，控制器可以采用回声状态图网络，利用随机矩阵提取图的节点特征，节点状态迭代过程如公式(1)所示，第t时间步下的第i个节点的特征
Figure PCTCN2022112494-appb-000001
表示为：
Figure PCTCN2022112494-appb-000002
Figure PCTCN2022112494-appb-000003
其中，
Figure PCTCN2022112494-appb-000004
表示第i个节点在(t-1)时间步的节点特征，u i表示第i个节点的输入信息，输入矩阵W in与节点状态X i相乘得到u i；N(i)表示第i个节点的邻居节点集合，输入矩阵W in和隐藏矩阵W h是随机矩阵，α表示泄露率。
可选的，编码器可以采用一层二值神经网络，将回声状态图网络输出的节点特征转化为二值特征向量，并存储到外部记忆单元中，在编码器前向传播的
Figure PCTCN2022112494-appb-000005
步骤303：将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中。
在本申请中，外部记忆单元可以存储节点的第一二值特征向量及其对应的标签。
在本申请中，在训练时，可以从训练集中随时选取一个Support Set(支持集)，其中，支持集由m个类别，每个类别随机选取n个样本组成。可以将支持集中的样本通过控制器和编码器获得第二二值特征向量，并且将该第二二值特征向量及其对应的标签存储到外部记忆单元中。
步骤304：在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量。
进一步的，可以在训练集中随机选取查询集(Query set)，其中，查询集和支持集的类别相同，从这m个类别中剩下的样本中选取n个样本，将查询集的样本通过控制器和编码器获得第二二值特征向量。
步骤305：基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
在本申请中，可以确定所述第一二值特征向量和所述第二二值特征向量的特征相似度；进一步的，基于所述特征相似度确定样本的预测类别。
具体的，在进行检索时，可以采用点乘公式计算所述第一二值特征向量和所述第二二值特征向量的所述特征相似度，如公式(4)所示：
Dot product(A，B)＝A·B。
步骤306：在对所述记忆增强图网络进行训练的过程中，根据所述预测类别和所述标签确定预测误差值。
在本申请中，可以根据查询集的预测类别和真实类别计算预测误差值。
步骤307：基于所述预测误差值更新所述编码器的参数。
在本申请中，可以基于预测误差值对编码器中的参数进行调整，以提高学习能力。
在本申请中，在推理时，可以执行以下步骤：
步骤S1：在所述测试集中随机选取一个预设类别和预设数量的所述支持集，将所述支持集输入至所述控制器和所述编码器，获得所述第一二值特征向量。
步骤S2：将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中。
步骤S3：在所述测试集中随机选取一个所述预设类别和所述预设数量的所述查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量。
步骤S4：基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
图4示出了本申请实施例提供的一种实现图小样本学习的存内计算硬件示意图，如图4所示，控制器中包括随机RRAM(随机存取存储器)阵列，编码器中包括可编程RRAM阵列，外部记忆单元中包括可编程RRAM阵列，其中，外部记忆单元可以存储编码器输入的内容，外部记忆单元可以对编码器中的内容进行检索。利用主变存储器件在获取集合(SET)过程中的阻值变化的随机性实现控制器中的随机矩阵(输入矩阵W in和隐藏矩阵W h)，利用阻变存储器件的二值状态实现编码器中的二值权重和外部记忆单元的特征向量和标签，利用忆阻器器件的随机性和二值阻态特性，在同一忆阻器阵列上实现了随机矩阵和二值矩阵，由于忆阻器器件具备可擦写的能力，是的记忆增强图网络的硬件实现具备了可重构特性。
本申请实施例提供的图小样本学习的存内计算方法，应用于包括相互连接 的控制器、编码器和外部记忆单元的记忆增强图网络中，可以通过将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集，在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量，将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中，在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量，基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别，可以快速确定样本类别，降低耗时降低耗能，提高记忆增强图网络的可靠性和稳定性。
图5示出了本申请实施例提供的一种图小样本学习的存内计算装置的结构示意图，应用于包括相互连接的控制器、编码器和外部记忆单元的记忆增强图网络中，如图5所示，该图小样本学习的存内计算装置400包括：
初始化模块401，用于将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集；
第一获得模块402，用于在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量；
存储模块403，用于将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中；
第二获得模块404，用于在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量；
第一确定模块405，用于基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
在一种可能的实现方式中，所述装置还包括：
第三获得模块，用于在所述测试集中随机选取一个预设类别和预设数量的所述支持集，将所述支持集输入至所述控制器和所述编码器，获得所述第一二值特征向量；
第二存储模块，用于将所述第一二值特征向量和所述第一二值特征向量对 应的标签存储至所述外部记忆单元中；
第四获得模块，用于在所述测试集中随机选取一个所述预设类别和所述预设数量的所述查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量；
第二确定模块，用于基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
在一种可能的实现方式中，所述第一确定模块包括：
第一确定子模块，用于确定所述第一二值特征向量和所述第二二值特征向量的特征相似度；
第二确定子模块，用于基于所述特征相似度确定样本的预测类别。
在一种可能的实现方式中，所述装置还包括：
第三确定模块，用于在对所述记忆增强图网络进行训练的过程中，根据所述预测类别和所述标签确定预测误差值；
更新模块，用于基于所述预测误差值更新所述编码器的参数。
在一种可能的实现方式中，所述第一获得模块包括：
获得子模块，用于在所述训练集中随机选取一个预设类别和预设数量的所述支持集，将所述支持集输入至所述控制器，通过所述控制器的回声状态图网络对所述图数据集进行特征提取，获得所述图数据集的节点特征；
转换子模块，用于将所述节点特征输入至所述编码器，通过所述编码器的二值神经网络，将所述节点特征转换为所述第一二值特征向量。
在一种可能的实现方式中，所述第一确定子模块包括：
计算单元，用于在进行检索时，采用点乘公式计算所述第一二值特征向量和所述第二二值特征向量的所述特征相似度。
在一种可能的实现方式中，所述训练集和所述测试集的类别不交叉。
本申请实施例提供的图小样本学习的存内计算装置，应用于包括相互连接的控制器、编码器和外部记忆单元的记忆增强图网络中，可以通过将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集，在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量，将所述第一二值特征向量和所述第一 二值特征向量对应的标签存储至所述外部记忆单元中，在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量，基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别，可以快速确定样本类别，降低耗时降低耗能，提高记忆增强图网络的可靠性和稳定性。
本申请提供的一种图小样本学习的存内计算装置，应用于包括控制器以及与控制器电连接的至少一个检测电路的如图1至图4任一所示的图小样本学习的存内计算方法，为避免重复，这里不再赘述。
本申请实施例中的电子设备可以是装置，也可以是终端中的部件、集成电路、或芯片。该装置可以是移动电子设备，也可以为非移动电子设备。示例性的，移动电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、车载电子设备、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，非移动电子设备可以为服务器、网络附属存储器(Network Attached Storage，NAS)、个人计算机(personal computer，PC)、电视机(television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
本申请实施例中的电子设备可以为具有操作系统的装置。该操作系统可以为安卓(Android)操作系统，可以为IOS操作系统，还可以为其他可能的操作系统，本申请实施例不作具体限定。
图6示出了本申请实施例提供的一种电子设备的硬件结构示意图。如图6所示，该电子设备500包括处理器510。
如图6所示，上述处理器510可以是一个通用中央处理器(central processing unit，CPU)，微处理器，专用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制本申请方案程序执行的集成电路。
如图6所示，上述电子设备500还可以包括通信线路540。通信线路540可包括一通路，在上述组件之间传送信息。
可选的，如图6所示，上述电子设备还可以包括通信接口520。通信接口520可以为一个或多个。通信接口520可使用任何收发器一类的装置，用于与其他设备或通信网络通信。
可选的，如图6所示，该电子设备还可以包括存储器530。存储器530用于存储执行本申请方案的计算机执行指令，并由处理器来控制执行。处理器用于执行存储器中存储的计算机执行指令，从而实现本申请实施例提供的方法。
如图6所示，存储器530可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器530可以是独立存在，通过通信线路540与处理器510相连接。存储器530也可以和处理器510集成在一起。
可选的，本申请实施例中的计算机执行指令也可以称之为应用程序代码，本申请实施例对此不作具体限定。
在具体实现中，作为一种实施例，如图6所示，处理器510可以包括一个或多个CPU，如图6中的CPU0和CPU1。
在具体实现中，作为一种实施例，如图6所示，终端设备可以包括多个处理器，如图6中的第一处理器5101和第二处理器5102。这些处理器中的每一个可以是一个单核处理器，也可以是一个多核处理器。
图7是本申请实施例提供的芯片的结构示意图。如图7所示，该芯片600包括一个或两个以上(包括两个)处理器510。
可选的，如图7所示，该芯片还包括通信接口520和存储器530，存储器530可以包括只读存储器和随机存取存储器，并向处理器提供操作指令和数据。存储器的一部分还可以包括非易失性随机存取存储器(non-volatile random access memory，NVRAM)。
在一些实施方式中，如图7所示，存储器530存储了如下的元素，执行模块或者数据结构，或者他们的子集，或者他们的扩展集。
在本申请实施例中，如图7所示，通过调用存储器存储的操作指令(该操 作指令可存储在操作系统中)，执行相应的操作。
如图7所示，处理器510控制终端设备中任一个的处理操作，处理器510还可以称为中央处理单元(central processing unit，CPU)。
如图7所示，存储器530可以包括只读存储器和随机存取存储器，并向处理器提供指令和数据。存储器530的一部分还可以包括NVRAM。例如应用中存储器、通信接口以及存储器通过总线系统耦合在一起，其中总线系统除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图7中将各种总线都标为总线系统640。
如图7所示，上述本申请实施例揭示的方法可以应用于处理器中，或者由处理器实现。处理器可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器可以是通用处理器、数字信号处理器(digital signal processing，DSP)、ASIC、现成可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
一方面，提供一种计算机可读存储介质，计算机可读存储介质中存储有指令，当指令被运行时，实现上述实施例中由终端设备执行的功能。
一方面，提供一种芯片，该芯片应用于终端设备中，芯片包括至少一个处理器和通信接口，通信接口和至少一个处理器耦合，处理器用于运行指令，以实现上述实施例中由图小样本学习的存内计算方法执行的功能。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机程序或指令。在计算机上加载 和执行所述计算机程序或指令时，全部或部分地执行本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、终端、用户设备或者其它可编程装置。所述计算机程序或指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机程序或指令可以从一个网站站点、计算机、服务器或数据中心通过有线或无线方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是集成一个或多个可用介质的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，例如，软盘、硬盘、磁带；也可以是光介质，例如，数字视频光盘(digital video disc，DVD)；还可以是半导体介质，例如，固态硬盘(solid state drive，SSD)。
尽管在此结合各实施例对本申请进行了描述，然而，在实施所要求保护的本申请过程中，本领域技术人员通过查看附图、公开内容、以及所附权利要求书，可理解并实现公开实施例的其他变化。在权利要求中，“包括”(comprising)一词不排除其他组成部分或步骤，“一”或“一个”不排除多个的情况。单个处理器或其他单元可以实现权利要求中列举的若干项功能。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
尽管结合具体特征及其实施例对本申请进行了描述，显而易见的，在不脱离本申请的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本申请的示例性说明，且视为已覆盖本申请范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包括这些改动和变型在内。

Claims (10)

  1. 一种图小样本学习的存内计算方法，其特征在于，应用于包括相互连接的控制器、编码器和外部记忆单元的记忆增强图网络中，所述方法包括：
    将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集；
    在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量；
    将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中；
    在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量；
    基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
  2. 根据权利要求1所述的方法，其特征在于，在所述将图数据集分为训练集和测试集之后，所述方法还包括：
    在所述测试集中随机选取一个预设类别和预设数量的所述支持集，将所述支持集输入至所述控制器和所述编码器，获得所述第一二值特征向量；
    将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中；
    在所述测试集中随机选取一个所述预设类别和所述预设数量的所述查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量；
    基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
  3. 根据权利要求1或2所述的方法，其特征在于，所述基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别，包括：
    确定所述第一二值特征向量和所述第二二值特征向量的特征相似度；
    基于所述特征相似度确定样本的预测类别。
  4. 根据权利要求1所述的方法，其特征在于，在基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别之后，所述方法还包括：
    在对所述记忆增强图网络进行训练的过程中，根据所述预测类别和所述标 签确定预测误差值；
    基于所述预测误差值更新所述编码器的参数。
  5. 根据权利要求1所述的方法，其特征在于，所述在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量，包括：
    在所述训练集中随机选取一个预设类别和预设数量的所述支持集，将所述支持集输入至所述控制器，通过所述控制器的回声状态图网络对所述图数据集进行特征提取，获得所述图数据集的节点特征；
    将所述节点特征输入至所述编码器，通过所述编码器的二值神经网络，将所述节点特征转换为所述第一二值特征向量。
  6. 根据权利要求3所述的方法，其特征在于，所述确定所述第一二值特征向量和所述第二二值特征向量的特征相似度，包括：
    在进行检索时，采用点乘公式计算所述第一二值特征向量和所述第二二值特征向量的所述特征相似度。
  7. 根据权利要求1所述的方法，其特征在于，所述训练集和所述测试集的类别不交叉。
  8. 一种图小样本学习的存内计算装置，其特征在于，应用于包括相互连接的控制器、编码器和外部记忆单元的记忆增强图网络中，所述装置包括：
    初始化模块，用于将所述编码器的参数进行初始化处理，将图数据集分为训练集和测试集；
    第一获得模块，用于在所述训练集中随机选取一个预设类别和预设数量的支持集，将所述支持集输入至所述控制器和所述编码器，获得第一二值特征向量；
    第一存储模块，用于将所述第一二值特征向量和所述第一二值特征向量对应的标签存储至所述外部记忆单元中；
    第二获得模块，用于在所述训练集中随机选取一个所述预设类别和所述预设数量的查询集，将所述查询集输入至所述控制器和所述编码器获得第二二值特征向量；
    第一确定模块，用于基于所述第一二值特征向量和所述第二二值特征向量确定样本的预测类别。
  9. 根据权利要求7所述的装置，其特征在于，所述第一确定模块包括：
    第一确定子模块，用于确定所述第一二值特征向量和所述第二二值特征向量的特征相似度；
    第二确定子模块，用于基于所述特征相似度确定样本的预测类别；
    所述装置还包括：
    第三确定模块，用于在对所述记忆增强图网络进行训练的过程中，根据所述预测类别和所述标签确定预测误差值；
    更新模块，用于基于所述预测误差值更新所述编码器的参数。
  10. 一种电子设备，其特征在于，包括：一个或多个处理器；和其上存储有指令的一个或多个机器可读介质，当由所述一个或多个处理器执行时，使得所述装置执行权利要求8-9任一所述的图小样本学习的存内计算装置。
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