WO2023240540A1

WO2023240540A1 - Optical computing method and system, and controller and storage medium

Info

Publication number: WO2023240540A1
Application number: PCT/CN2022/099179
Authority: WO
Inventors: 谢青; 云全新; 颜旭
Original assignee: 深圳华大基因科技有限公司; 深圳华大生命科学研究院
Priority date: 2022-06-16
Filing date: 2022-06-16
Publication date: 2023-12-21

Abstract

The present disclosure relates to an optical computing method and system, and a controller and a storage medium. The optical computing system comprises: an analog-to-digital converter array, which is configured to convert into a digital signal a current that is generated when a polymer is translocated with respect to nanopores; and an optical computing chip, which is configured to identify the arrangement of polymer units in the polymer according to the digital signal. The optical computing chip which has better computing power than a GPU in the present disclosure is applied to nanopore-based polymer sequencing, thereby optimizing the computing speed of the optical computing chip in "identifying polymer units in a valid signal" when a plurality of nanopores generate data in parallel.

Description

Optical computing methods and systems, controllers and storage media

Technical field

The present disclosure relates to the field of sequencing analysis of polymer units in polymers, and in particular to an optical computing method and system, a controller and a storage medium.

Background technique

RELATED ART A type of measurement system used to estimate a target sequence of polymer units in a polymer using nanopores. Such systems translocate the polymer relative to the nanopore by allowing the polymer monomers to pass through the nanopore. Changes in physical properties such as the current generated by the unit are used to determine the arrangement of polymer units in the polymer through methods such as artificial neural networks.

Contents of the invention

According to one aspect of the present disclosure, an optical computing system is provided, including:

an analog-to-digital converter array configured to convert an electrical current generated upon translocation of the polymer relative to the nanopore into a digital signal;

An optical computing chip configured to identify the arrangement of polymer units in a polymer based on digital signals.

In some embodiments of the present disclosure, the optical computing chip is configured to determine whether the digital signal is a valid signal, and by identifying the valid signal, identify the arrangement of polymer units in the polymer.

In some embodiments of the present disclosure, the optical computing system further includes:

A controller configured to split the digital signal output by each analog-to-digital converter in the analog-to-digital converter array into multiple sub-signals, and add a corresponding identification to each sub-signal, wherein the identification includes a time stamp and Analog-to-digital converter identification;

The first cache includes a plurality of sub-cache, is arranged between the analog-to-digital converter array and the optical computing chip, and is configured to store the sub-signal after adding the corresponding identifier; in the case where one sub-cache in the first cache stores the sub-signal, Switch the sub-buffer and output the sub-signal in the sub-buffer to the optical computing chip.

The second cache is disposed between the first cache and the optical computing chip, and is configured to cache the sub-signals output by the first cache and then output them to the optical computing chip;

Wherein, the controller is further configured to set the bandwidth of each sub-signal output of the second cache to the optical computing chip to be higher than the computing operating frequency of the optical computing chip.

In some embodiments of the present disclosure, the optical computing chip includes:

A first computing chip configured to determine whether the digital signal is a valid signal;

A second computing chip is configured to identify the arrangement of polymer units in the polymer by identifying valid signals.

The third cache is disposed between the first computing chip and the second computing chip, and is configured to store valid signals calculated by the first computing chip.

In some embodiments of the present disclosure, the third buffer is a plurality of parallel buffer arrays corresponding to the analog-to-digital converter array.

In some embodiments of the present disclosure, the controller is further configured to place the sub-signals of multiple consecutive timestamps from the same nanopore in the third cache in the same section in time sequence; or by referencing the pointer , the sub-signals from the same nanopore in the third buffer are sequentially entered into the optical computing chip.

In some embodiments of the present disclosure, the second buffer is a plurality of parallel buffer arrays corresponding to the analog-to-digital converter array.

In some embodiments of the present disclosure, the controller is further configured to place multiple consecutive timestamp sub-signals from the same nanopore in the second cache in the same section in time sequence; or by referencing a pointer , the sub-signals from the same nanopore in the second buffer are sequentially entered into the optical computing chip.

In some embodiments of the present disclosure, the analog-to-digital converter array is an analog-to-digital converter array that includes a plurality of analog-to-digital converters.

In some embodiments of the present disclosure, the length of the sub-signal in the first buffer is less than or equal to the sequence length processed by the optical computing chip configuration.

In some embodiments of the present disclosure, the transmission bandwidth of the first cache to the optical computing chip is equal to the computing speed of the optical computing chip.

In some embodiments of the present disclosure, the controller is further configured to use the end data of the previous sub-signal and the subsequent sub-signal when the length of the current sub-signal in the first buffer is less than the sequence length configured to be processed by the optical computing chip. At least one of the starting data of the sub-signal complements the current sub-signal, so that the length of the current sub-signal in the first buffer is equal to the sequence length processed by the optical computing chip configuration.

a light source configured to output unmodulated light for use in calculations;

A first digital-to-analog conversion array configured to receive external input data and convert the external input data into a first analog signal;

a modulator array configured to form tensor data based on the light output by the light source and the first analog signal;

The weight data cache is configured to store the weight data of the multiplication matrix;

a second digital-to-analog conversion array configured to convert the weight data into a second analog signal;

An optoelectronic matrix multiplication module is configured to perform a matrix multiplication operation according to the tensor data and the second analog signal to implement optical path calculation.

According to another aspect of the present disclosure, a light calculation method is provided, including:

The current generated when the polymer translocates relative to the nanopore is converted into a digital signal by an analog-to-digital converter array;

Controlled light computing chips identify the arrangement of polymer units in the polymer based on digital signals.

In some embodiments of the present disclosure, controlling the light computing chip to identify the arrangement of polymer units in the polymer according to the digital signal includes: controlling the light computing chip to determine whether the digital signal is a valid signal, and by identifying the valid signal, identifying The arrangement of polymer units in a polymer.

In some embodiments of the present disclosure, the light calculation method further includes:

Split the digital signal output by each analog-to-digital converter in the analog-to-digital converter array into multiple sub-signals, and add a corresponding identification to each sub-signal, wherein the identification includes a time stamp and an analog-to-digital converter identification;

Control the first cache to store the sub-signal with the corresponding identifier added, and when a sub-cache in the first cache stores the sub-signal, switch the sub-cache and output the sub-signal in the sub-cache to the optical computing chip, wherein, The first cache includes multiple sub-caches.

After buffering the sub-signals output from the first buffer through the second buffer, output them to the optical computing chip;

The bandwidth of each sub-signal output from the second cache to the optical computing chip is set to be higher than the computing operating frequency of the optical computing chip.

In some embodiments of the present disclosure, the control light computing chip determines whether the digital signal is a valid signal, and by identifying the valid signal, identifying the arrangement of polymer units in the polymer includes:

Control the first computing chip to determine whether the digital signal is a valid signal;

The effective signal calculated by the first computing chip is stored in the third cache;

A second computing chip is controlled to identify the arrangement of polymer units in the polymer by identifying valid signals.

Sub-signals from multiple consecutive timestamps in the third buffer from the same nanopore are placed in the same section in time sequence.

Through the reference pointer, the sub-signals from the same nanopore in the third buffer are sequentially entered into the optical computing chip.

Place the sub-signals of multiple consecutive timestamps from the same nanopore in the second cache in the same section in time sequence;

In some embodiments of the present disclosure, the optical computing method further includes: sequentially entering the sub-signals from the same nanopore in the second cache into the optical computing chip by referencing a pointer.

Set the sub-signal length in the first cache to be less than or equal to the sequence length processed by the optical computing chip configuration;

The transmission bandwidth of the first buffer to the optical computing chip is set equal to the computing speed of the optical computing chip.

When the length of the current sub-signal in the first cache is less than the length of the sequence configured to be processed by the optical computing chip, at least one of the end data of the previous sub-signal and the beginning data of the next sub-signal is used to complement the current sub-signal, This makes the current sub-signal length in the first buffer equal to the sequence length processed by the optical computing chip configuration.

According to another aspect of the present disclosure, a controller is provided, including:

a first control module for converting the current generated when the polymer is translocated relative to the nanopore into a digital signal through an analog-to-digital converter array;

The second control module is used to control the optical computing chip to identify the arrangement of polymer units in the polymer according to the digital signal.

Memory, used to store instructions;

A processor, configured to execute the instructions, causing the controller to perform operations for implementing the optical computing method described in any of the above embodiments.

According to another aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the methods described in any of the above embodiments are implemented. Light calculation method.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the drawings needed to be used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings in the following description are only for the purpose of describing the embodiments or related technologies. For some disclosed embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting any creative effort.

Figure 1 is a schematic diagram of some embodiments of an optical computing system of the present disclosure.

FIG. 2 is a schematic diagram of other embodiments of the optical computing system of the present disclosure.

Figure 3 is a schematic diagram of some further embodiments of the optical computing system of the present disclosure.

Figure 4 is a schematic diagram of other embodiments of the optical computing system of the present disclosure.

Figure 5 is a schematic diagram of some further embodiments of the optical computing system of the present disclosure.

Figure 6 is a schematic diagram of cache segmentation setting and ordering in some embodiments of the present disclosure.

Figures 7a, 7b, 7c and 7d are schematic diagrams of sub-signals in some embodiments of the present disclosure.

Figure 8 is a schematic diagram of some further embodiments of the optical computing system of the present disclosure.

Figure 9 is a schematic diagram of some embodiments of the light computing method of the present disclosure.

Figure 10 is a schematic diagram of some embodiments of a controller of the present disclosure.

Figure 11 is a schematic structural diagram of some other embodiments of the controller of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application or uses. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this disclosure.

The relative arrangement of components and steps, numerical expressions, and numerical values set forth in these examples do not limit the scope of the disclosure unless otherwise specifically stated.

At the same time, it should be understood that, for convenience of description, the dimensions of various parts shown in the drawings are not drawn according to actual proportional relationships.

Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered part of the authorized specification.

In all examples shown and discussed herein, any specific values are to be construed as illustrative only and not as limiting. Accordingly, other examples of the exemplary embodiments may have different values.

It should be noted that similar reference numerals and letters refer to similar items in the following figures, so that once an item is defined in one figure, it does not need further discussion in subsequent figures.

The inventors discovered through research that the present invention involves the analysis of measurements taken from polymer units in a polymer (such as, but not limited to, a polynucleotide) during its translocation relative to a nanopore.

RELATED ART A type of measurement system used to estimate a target sequence of polymer units in a polymer using nanopores. Such systems translocate the polymer relative to the nanopore by allowing the polymer monomers to pass through the nanopore. Changes in physical properties such as the current generated by the unit are used to determine the arrangement of polymer units in the polymer through methods such as artificial neural networks. Such measurement systems using nanopores hold considerable promise, particularly in the field of sequencing polynucleotides such as DNA or RNA, and have been the subject of recent developments.

Protein peptide chains can also be sequenced through nanopores, and related technologies disclose single-molecule peptide sequencing methods based on nanopore technology. Under the action of Hel308 DNA helicase, the DNA-peptide conjugate is pulled through the MspA nanopore. At this time, the nanopore will generate a unique ladder-like current signal in the ion flow. Through the supporting identification software, the current signal can be accurately identified and the current median value can be analyzed to retroactively confirm the sequence information.

Related technology can identify polymer sequencing signals through neural networks. Related art discloses the use of machine learning techniques using recurrent neural networks (RNN) to analyze polymer signals passing through nanopores and derive posterior probability matrices, each posterior probability matrix representing: prior to the corresponding measurement of the polymer unit. In terms of different corresponding historical sequences of measurement results, the posterior probabilities of multiple different changes in the corresponding historical sequences of polymer units generate new polymer unit sequences. The analysis may include performing convolution on a set of consecutive measurements using a trained feature detector such as a convolutional neural network to derive a series of feature vectors on which the RNN operates.

The current signal given by the nanopore is not always an effective signal of the polymer unit passing through the nanopore, but the comparison document does not give the process and structure for identifying effective signals. Taking DNA as an example, identifying effective signals and identifying the base sequences in the signals require a lot of computing power. The displacement speed of DNA in nanopores reaches 420nt/s, and the array usually has more than 1,000 nanopores. Artificial neural networks are used, including CNN, RNN, LSTM, Transformer, etc., which require a large number of matrix operations and operators.

The inventor found through research that the GPU computing power of the related technology is not enough. The computing power of a single GPU core is at the 10-100G Flops level. The GPU computing power of the related technology is not enough to support the real-time analysis of data generated by tens of thousands of nanopores to achieve effective signals. Base calling in recognition and efficient signaling.

In view of at least one of the above technical problems, the present disclosure provides an optical computing method and system, a controller and a storage medium. The present disclosure is described below through specific embodiments.

Figure 1 is a schematic diagram of some embodiments of an optical computing system of the present disclosure. As shown in Figure 1, the optical computing system of the present disclosure includes an analog-to-digital converter array 100, a nanohole array 300 and an optical computing chip 200, wherein:

The analog-to-digital converter ADC array 100 is configured to convert the electric current generated when the polymer translocates relative to the nanopore into a digital signal.

Optical computing chip 200 is configured to identify the arrangement of polymer units in a polymer based on digital signals.

In some embodiments of the present disclosure, the optical computing chip 200 may be configured to determine whether the digital signal is a valid signal, and by identifying the valid signal, identify the arrangement of polymer units in the polymer.

The above embodiments of the present disclosure process the signals generated by the nanohole array and the ADC array through an optical computing chip, determine whether the signal is a valid signal through the optical computing chip that can accelerate matrix multiplication, and identify the arrangement of polymer units in the polymer.

The reason for the invalid signal is that 1) no nucleic acid sequence passes through the nanopore, 2) there is a nucleic acid sequence passing through the nanopore, but it does not continue to move under the action of the electric field, resulting in a stable potential difference on both sides of the membrane as well as electromagnetic interference and impurities in the pore. An unstable signal is produced.

In some embodiments of the present disclosure, the optical computing chip 200 can be configured to filter out unstable signals through low-pass filtering and then remove invalid signals based on potential differences. The method in the above embodiments of the present disclosure has a small amount of calculation but low accuracy. .

In other embodiments of the present disclosure, the optical computing chip 200 can also be configured to perform inference on the signal after training the model through a classifier or neural network to realize the identification of effective signals.

In some embodiments of the present disclosure, the optical computing chip 200 is configured to identify the bases in the effective signal from the electrical signal collected through the nanopore. The algorithm used is usually trained by a neural network. The model of the neural network can be a recursive neural network. Network (RNN), convolutional neural network (CNN), long short-term memory (LSTM), and Transformer, etc., by collecting multiple polymer unit sequences that determine the target sequence or its complementary sequence from the self-containment Measurement results are obtained through training. Using the resulting model inference, the target sequence of the newly measured polymer unit can be estimated by identifying effective signal inferences from the electrical signals collected through the nanopore. During the inference estimation process, each model measurement relies on a k-mer (k polymer unit) model to process the input signal sequence into observations of k-mer states. By model, each model's k-mer type and input sequence are processed into multidimensional k-mer states and produce an estimate of the polymer unit sequence.

In some embodiments of the present disclosure, the optical computing chip 200 may include a wavelength routing based photon matrix vector multiplier.

In some embodiments of the present disclosure, the optical computing chip 200 may include an all-optical diffraction neural network implemented on an optical waveguide and/or an optical chip.

In some embodiments of the present disclosure, the optical computing chip 200 provides an optoelectronic processing device with a segmented optical modulator including three or more segments, which can improve the analog-to-digital conversion accuracy of the Mach-Zehnder interferometer. The optical waveguide device, the data to be processed includes vector element values of the input vector and matrix element values of the model matrix associated with the neural network model, and the processed data includes between different subsets based on the vector element values and different corresponding preprocessing vectors Element-wise vector multiplication to compute multiple intermediate vectors.

The above-mentioned embodiments of the present disclosure apply optical computing chips with computing capabilities better than GPUs to nanopore-based polymer sequencing, optimizing the optical computing chip to "identify effective signals" and "recognize effective signals" when multiple nanopores generate data in parallel. Computational speed of "polymer units" in the effective signal.

The above embodiments of the present disclosure use nanopores as a type of measurement system for estimating a target sequence of polymer units in a polymer. This type of system has multiple nanopores and multiple ADC units. When the polymer is compared to the nanometer When the hole is translocated, the generated current is converted into a digital signal through the ADC unit array.

FIG. 2 is a schematic diagram of other embodiments of the optical computing system of the present disclosure. As shown in Figure 2, the optical computing system of the present disclosure includes an analog-to-digital converter array 100, a nanohole array 300, an optical computing chip 200, a first buffer 400, a controller and an output sequence signal buffer 500, wherein:

In some embodiments of the present disclosure, the controller may include system controller 610 and ADC array controller 620, where:

The ADC array controller 620 is used to control the analog-to-digital converter array 100, the nanohole array 300 and the first cache 400.

System controller 610 is used to control various component modules of the system.

In some embodiments of the present disclosure, the controllers (system controller 610 and ADC array controller 620) are configured to split the digital signal output by each analog-to-digital converter in the analog-to-digital converter array into Multiple sub-signals, and add corresponding identification to each sub-signal, where the identification includes a time stamp and an analog-to-digital converter identification.

The function of adding time and ADC identification in the above embodiments of the present disclosure is to allow the segmented sub-signals to be spliced according to the time stamp and ADC identification to form a complete signal after the bases are identified by the optical computing chip.

In some embodiments of the present disclosure, the first cache 400 includes a plurality of sub-cache, is disposed between the analog-to-digital converter array and the optical computing chip, and is configured to store the sub-signal after adding the corresponding identification; in the first cache When one sub-buffer stores a sub-signal, the sub-buffer is switched and the sub-signal in the sub-buffer is output to the optical computing chip.

In some embodiments of the present disclosure, the first cache 400 may be configured such that the storage ratio of a sub-cache in the first cache is greater than a predetermined value, the remaining storage space is less than a preset value, or data of a preset size is written. In the case of , switch the sub-buffer and output the sub-signal in the sub-buffer to the optical computing chip, that is, when a sub-buffer is close to overflow, switch the sub-buffer and output the sub-buffer in the sub-buffer that is nearly full. The sub-signals are output to the optical computing chip.

In some embodiments of the present disclosure, the analog-to-digital converter array 110 may be an analog-to-digital converter array including a plurality of analog-to-digital converters.

In some embodiments of the present disclosure, the length of the sub-signal in the first cache 400 is less than or equal to the sequence length processed by the optical computing chip configuration.

In some embodiments of the present disclosure, the transmission bandwidth from the first cache 400 to the optical computing chip is equal to the computing speed of the optical computing chip.

In some embodiments of the present disclosure, the first cache 400 may be a ping-pong cache.

In some embodiments of the present disclosure, the controller may also be configured to use the end data of the previous sub-signal and the following sub-signal when the length of the current sub-signal in the first buffer is less than the sequence length configured to be processed by the optical computing chip. At least one of the starting data of a segment of sub-signals complements the current sub-signal, so that the length of the current sub-signal in the first buffer is equal to the sequence length processed by the optical computing chip configuration.

In the above embodiments of the present disclosure, the output signal of the signal output unit of each ADC unit enters the ping-pong buffer. After preliminary segmentation, it is divided into multiple sub-signals. Each sub-signal is added with a corresponding identifier. The identifier can be a timestamp + ADC. logo. When the length of the sub-signal < the sequence length N processed by the optical computing chip configuration, the end of the previous sub-signal and the signal in the front section of the next sub-signal can be used to complete the sequence up to N.

Figure 3 is a schematic diagram of some further embodiments of the optical computing system of the present disclosure. As shown in FIG. 3 , the optical computing system of the present disclosure includes an analog-to-digital converter array 100 , a nanohole array 300 , an optical computing chip 200 , a first buffer 400 , a controller, and an output sequence signal buffer 500 . In some embodiments of the present disclosure, the first cache 400 may be a ping-pong cache.

In some embodiments of the present disclosure, sub-matrix-vector multiplication (MVM) mainly includes three categories, namely matrix calculation based on (single/multiple) plane light conversion (PLC), Mach-Zehnder interferometer (MZI) network-based Matrix calculations, and matrix calculations based on wavelength division multiplexing (WDM).

This disclosure takes the MZI and WDM methods as an example. The output vector length of MZI and WDM is generally less than 100 and is mainly used for integrated photon matrix computing chips.

In some embodiments of the present disclosure, the optical computing chip can have a built-in cache, so that the sequence length N processed by the optical computing chip is configured to include multiple vectors of length L.

Compared with the embodiment of Figure 2, the embodiment of Figure 3 also provides a specific structure of the optical computing chip 200. As shown in Figure 3, the optical computing chip 200 includes an optical computing chip controller 201, a weight data cache 202, and a light source. 203. A first digital-to-analog conversion array 204, a modulator array 205, a plurality of second digital-to-analog conversion arrays 206, a plurality of photoelectric matrix multiplication modules 207 and an analog-to-digital conversion array 208, wherein:

Light source 203 is configured to output unmodulated light for calculation.

The first digital-to-analog conversion array (first DAC array) 204 is configured to receive external input data and convert the external input data into a first analog signal.

The modulator array 205 is configured to form tensor data to be subjected to a matrix multiplication operation according to the light output by the light source and the first analog signal.

The weight data cache 202 is configured to store the weight data of the multiplication matrix.

In some embodiments of the present disclosure, the weight data cache 202 is configured so that when the model used for inference is switched according to the sample type, the weight of the artificial neural network in the corresponding optical computing chip 200 can also be changed accordingly, for Store weights.

The second digital-to-analog conversion array (second DAC array) 206 is configured to convert the weight data into a second analog signal.

The photoelectric matrix multiplication module 207 is configured to perform a matrix multiplication operation according to the tensor data and the second analog signal to implement optical path calculation.

As shown in FIG. 3 , the optical computing chip controller 201 of the optical computing chip 200 is configured through the system control 610 so that the chip performs matrix calculations at a certain speed.

The photoelectric matrix multiplication module 207 is configured to perform optical calculations of matrix and waveguide vectors. Through changes in digital signals, it can determine the binding, membrane penetration, via holes, and exit holes of the DNA single strand corresponding to the digital signals, and identify effective signals. , and identify the base sequence in the effective signal.

In some embodiments of the present disclosure, the optoelectronic matrix multiplication module 207 may be configured for matrix calculation based on a Mach-Zehnder interferometer (MZI) network and matrix calculation based on wavelength division multiplexing (WDM). The tensor propagates through multiple photoelectric matrix multiplication modules through the optical path to implement multiple matrix multiplication operations. Among them, the coefficients of matrix multiplication are derived from the machine learning model. Since optical path calculation is used, this step can save computing power and calculation time. The calculation results are output to the system controller 610 through the ADC array 208 .

In some embodiments of the present disclosure, due to the fast speed of the optical computing process, it is necessary to coordinate the cooperative work of each of the first DAC array 204, the second DAC array 206, and the ADC array 208. The involved optical paths, circuit switches, and data transfer are performed by optical The computing chip controller 201 executes.

In some embodiments of the present disclosure, the system controller 610 is configured to process the result data output by the ADC array, and output the result data to the output according to the settings of the library and the information of the nanopore 300 and the analog-to-digital converter array 100 Sequence signal buffer 500.

In some embodiments of the present disclosure, the cache of the output sequence signal cache 500 does not have to be a cache, but the speed of writing data must match the speed of the output results of the optical computing chip.

In some embodiments of the present disclosure, a nanopore array 300 composed of 256×256 nanopores is used to read DNA single-stranded fragments, and the array 100 composed of multiple ADC units reads under the control of the ADC array controller 620 The current signals obtained from the plurality of nanopores in the nanopore array 100 are taken and converted into digital signals. Under the control of the system controller 610 or the ADC array controller 620, the digital signal obtained by the ADC array is added with a sampling time stamp and a corresponding ADC identifier, forming multiple sub-signals that enter the ping-pong cache 400.

In some embodiments of the present disclosure, the ping-pong cache 400 may have more than one sub-cache, and the ADCs in the ADC array may have a one-to-one or one-to-many relationship.

In some embodiments of the present disclosure, when multiple nanopores correspond to one ADC (for example, 256×256 nanopores correspond to 128×128 ADC units), the generated subsequence includes both the ADC identifier and System time identifier.

In some embodiments of the present disclosure, four nanopores correspond to one ADC. During the sequencing process, it is determined whether the DNA has passed through the holes, and the ADC detects the nanopores with through-hole signals, which can improve the utilization rate of the ADC.

In some embodiments of the present disclosure, since the corresponding relationship between the nanopore and the ADC is dynamically determined according to the sequence via situation during the sequencing process, the system controller 610 or the ADC array controller 620 will record the time when switching the corresponding relationship. , thereby corresponding the signal in a specific time period to the nanopore signal.

In some embodiments of the present disclosure, as shown in Figure 6, for ADC1, the sub-signals of a specific time period t0-t3 correspond to coming from the nanopore A, and for ADC1, the sub-signals of a specific time period t4-t7 correspond to coming from the nanopore B. Therefore, ADC1+timestamp (t0-t1), ADC1+timestamp (t1-t2), and ADC1+timestamp (t2-t3) are three consecutive sub-signals from nanopore A. The ADC1+ timestamp (t4-t5), ADC1+ timestamp (t5-t6), and ADC1+ timestamp (t6-t7) are three consecutive sub-signals from nanopore B.

In some embodiments of the present disclosure, the length of the signal collected by the ADC is generally longer than the length of the sequence processed by the optical computing chip. When the signal collected by the ADC is transferred to the ping-pong storage, the signal can be segmented so that the length of the sub-signal in the ping-pong buffer is consistent with the sequence length configured to be processed by the optical computing chip. When a buffer of the ping-pong buffer is close to overflowing, the buffer is switched and the sub-signals in the full buffer are output to the optical computing chip. The transmission bandwidth is consistent with the computing speed of the optical computing chip, thus maximizing the use of the optical computing chip. Calculate ability.

The above embodiments of the present disclosure add ping-pong buffers and caches between the ADC array and the optical chip that can accelerate the multiplication matrix operation, making full use of the computing power of the optical computing chip, making the generation and calculation of digital signals more efficient and faster.

Figure 4 is a schematic diagram of other embodiments of the optical computing system of the present disclosure. Figure 5 is a schematic diagram of some further embodiments of the optical computing system of the present disclosure. Compared with the embodiments of Figures 2 and 3, in the embodiments of Figures 4 and 5, the optical computing system includes an analog-to-digital converter array 100, a nanohole array 300, an optical computing chip 200, a first cache 400, a control In addition to the processor and output sequence signal buffer 500, the system controller 610 and the ADC array controller 620, a second buffer 700 may also be included, wherein:

The second cache 700 is disposed between the first cache 400 and the optical computing chip 200, and is configured to cache the sub-signals output by the first cache and then output them to the optical computing chip.

The controller (system controller 610 and ADC array controller 620) may also be configured to set the bandwidth of each sub-signal output of the second buffer to the optical computing chip to be higher than the computing operating frequency of the optical computing chip.

In some embodiments of the present disclosure, the first cache 400 may be a ping-pong cache; the second cache 700 may be a cache.

The above embodiments of the present disclosure add a cache (103) between the ping-pong cache and the optical computing chip, thereby ensuring that switching of the ping-pong cache will not affect the computing speed of the optical computing chip. First, this disclosure sets the output bandwidth of the cache to be consistent with the read speed of the optical computing chip; second, this disclosure sets the high-speed write bandwidth to be higher than the sub-storage output bandwidth of the ping-pong storage. Therefore, the optical computing chip of the present disclosure can continuously read the cache without being affected by ping-pong memory cache switching.

In some embodiments of the present disclosure, the second buffer 700 is a plurality of parallel buffer arrays corresponding to the analog-to-digital converter array 100 .

In some embodiments of the present disclosure, the controller may also be configured to place multiple consecutive timestamp sub-signals from the same nanopore in the second cache in the same section in time sequence; or by reference Pointer, the sub-signals from the same nanopore in the second buffer are entered into the optical computing chip in sequence.

In some embodiments of the present disclosure, each sub-signal carries the identification of the nanopore ADC, so instead, the signals from the same nanopore ADC in the cache are stored in adjacent order through an algorithm, or by reference Pointer to ensure that sub-signals from the same ADC enter the optical computing chip in order.

In some embodiments of the present disclosure, the signal from the same nanopore ADC in the cache can be determined through the identification of the ADC identification and the system time.

In some embodiments of the present disclosure, the cache can also be an array controlled by a controller to ensure correspondence between adjacent nanopores.

In some embodiments of the present disclosure, the sub-signal with the signal identification mark is directly written into the cache of a specific and matching optical computing element. The cache implementation can be an on-chip or off-chip linear SRAM, GDDR, HBM, etc. Storage devices, or customized storage devices with special structures through FPGA and ASIC.

In some embodiments of the present disclosure, the frequency at which each cached sub-signal is output to the DAC array on the optical computing chip is consistent with the computing operating frequency of the optical computing element (i.e., the DAC array on the optical computing chip, the modulator array, the optoelectronic matrix multiplication unit and The minimum value of the maximum operating frequency of the ADC array is consistent.

In some embodiments of the present disclosure, the output bandwidth (output frequency) of cache data is higher than the computing operating frequency of the optical computing chip to ensure that the computing power of the optical computing chip is maximized. Among them, the frequency at which each cached sub-signal is output to the DAC array on the optical computing chip refers to the output bandwidth from the last cache.

In some embodiments of the present disclosure, due to different implementation principles of optical computing components from various manufacturers, the computing operating frequency may change in real time or be a fixed value. When changing in real time, the speed at which the optical computing element reads the cache will also change in real time. Therefore, it is necessary to ensure that the output bandwidth (output frequency) of the cache data is higher than the computing operating frequency of the optical computing chip.

In some embodiments of the present disclosure, the cache may be a FIFO cache capable of storing multiple sub-signals simultaneously.

In the above embodiments of the present disclosure, the cache segmentation can be set and sorted so that sub-signals with multiple consecutive timestamps from the same nanopore are placed in the same section in time sequence, or in the form of a register linked list pointer. Ensure that the sub-signals can be output continuously.

The above-described embodiments of the present disclosure provide ping-pong buffers and caches that match the speed of optical computing chips. The above-mentioned embodiments of the present disclosure greatly improve the accuracy of the operations of "identifying effective signals" and "identifying polymer units in effective signals" through optimized cache structures.

Figure 6 is a schematic diagram of cache segmentation setting and ordering in some embodiments of the present disclosure. As shown in Figure 6, for ADC1, the sub-signals of a specific time period t0-t3 correspond to nanopore A, while for ADC1, the sub-signals of a specific time period t4-t7 correspond to nanopore B. Therefore, ADC1+timestamp (t0-t1), ADC1+timestamp (t1-t2), and ADC1+timestamp (t2-t3) are three consecutive sub-signals from nanopore A. The ADC1+ timestamp (t4-t5), ADC1+ timestamp (t5-t6), and ADC1+ timestamp (t6-t7) are three consecutive sub-signals from nanopore B. The ADC3+ timestamp (t0-t1), ADC3+ timestamp (t1-t2), and ADC3+ timestamp (t2-t3) are three consecutive sub-signals from nanopore C. ADC2+timestamp (t0-t1), ADC2+timestamp (t1-t2), and ADC2+timestamp (t2-t3) are three consecutive sub-signals from nanopore D.

In the above embodiments of the present disclosure, since the corresponding relationship between the nanopore and the ADC is dynamically determined according to the sequence via situation during the sequencing process, the system will record the time when switching the corresponding relationship. This allows the signal of a specific time period to be correlated with the nanopore signal.

In some embodiments of the present disclosure, ADC identification + time stamp is equivalent to nanopore identification.

In some embodiments of the present disclosure, whether only a nanopore identifier (nanopore A or nanopore B) is added for the "situation in which multiple nanopores correspond to one ADC", there is no need to add an ADC identifier, and it can also be ensured that the same nanopore Sub-signals with multiple consecutive timestamps are placed in the same section in time sequence.

Figures 7a, 7b, 7c and 7d are schematic diagrams of sub-signals in some embodiments of the present disclosure. As shown in Figure 7a, the sub-signal may include a nanopore identification, an ADC identification, a timestamp and a sub-signal of length N.

In other embodiments of the present disclosure, as shown in Figure 7b, the ADC identification + time stamp may be equivalent to the nanopore identification. Thus, the sub-signal may include an ADC identification, a timestamp and a sub-signal of length N.

As shown in Figure 7c and Figure 7d, in addition to the timestamp and ADC identification, the sub-signals entering the cache can also include the end data of the previous sub-signal of the same ADC (the sub-signal of the previous timestamp) or the following sub-signal. Start data and send it to linear cache. Among them, in the embodiment of Figure 7c, the sub-signals entering the cache include timestamps, ADC identifiers, data at the end (N-n) of the previous sub-signal of the same ADC, and sub-signals with a length of this timestamp of n.

In the embodiment of Figure 7d, the sub-signals entering the cache include a timestamp, an ADC identifier, a sub-signal with a length of this timestamp of n, and the data of the beginning (N-n) of the next sub-signal.

Therefore, there is a repeated signal between the sub-signals of the present disclosure, which can reduce signal validity segment errors and base recognition errors caused by sub-signal truncation.

Figure 8 is a schematic diagram of some further embodiments of the optical computing system of the present disclosure. Compared with the embodiment of Figure 4 and Figure 5, in the embodiment of Figure 8, the optical computing system includes an analog-to-digital converter array 100, a nanohole array 300, a first buffer 400, a controller and an output sequence signal buffer 500. In addition to the system controller 610 and the ADC array controller 620, it may also include a first computing chip 210 and a second computing chip 220, wherein:

In some embodiments of the present disclosure, as shown in Figure 8, the optical computing chip 200 shown in any embodiment of Figures 1 to 5 may include a first computing chip 210 and a second computing chip 220, wherein:

The first computing chip 210 is configured to determine whether the digital signal is a valid signal.

The second computing chip 220 is configured to identify the arrangement of polymer units in the polymer by identifying valid signals.

In some embodiments of the present disclosure, the first computing chip 210 and the second computing chip 220 may be implemented as the specific structure of the optical computing chip 200 in the embodiment of FIG. 3 or FIG. 5 .

In some embodiments of the present disclosure, one of the first computing chip 210 and the second computing chip 220 (usually the first computing chip 210) may be replaced with a GPU chip.

The above embodiments of the present disclosure can use the first computing chip 210 and the second computing chip 220 to be connected in series to solve the problems of "identifying effective signals" and "identifying bases in effective signals" respectively, thereby improving signal processing efficiency.

In some embodiments of the present disclosure, as shown in Figure 8, the optical computing system may further include a third cache 800, wherein:

The third cache 800 is disposed between the first computing chip and the second computing chip, and is configured to store valid signals calculated by the first computing chip.

In some embodiments of the present disclosure, the first cache 400 may be a ping-pong cache; the second cache 700 and the third cache 800 may be caches.

In some embodiments of the present disclosure, the segmented cache can be changed to multiple parallel multiple cache arrays corresponding to the ADC or nanopore.

In some embodiments of the present disclosure, the cache array may be arranged one-to-one, many-to-one, or one-to-many with the analog-to-digital converters 100 in the ADC array.

In some embodiments of the present disclosure, in addition to the timestamp and ADC identification, the sub-signals entering the cache 800 also include the end data of the previous sub-signal or the beginning data of the next sub-signal of the same ADC, and are sent to the linear cache. Therefore, there is a repeated signal between the sub-signals of the present disclosure, which can reduce signal validity segment errors and base recognition errors caused by sub-signal truncation.

On the basis of the above embodiments of the present disclosure (such as the embodiments in Figures 1 to 8), the nanopores used for DNA sequencing are changed to nanopores used for detecting protein peptides, and corresponding adaptations are made on the ADC, This enables it to generate a ladder-like current signal when the "DNA-peptide" conjugate passes through the nanopore. By loading the supporting artificial neural network model and corresponding weight data on the optical computing chip, the current signal can be identified and the current can be analyzed. The median value is analyzed to retrospectively confirm the information of the "DNA-peptide" sequence. The role of DNA is to combine with the nanopore structure, allowing single-stranded DNA to pass through the nanopore and guide the coupled peptide segment to follow the DNA. through nanopores.

In the above embodiments of the present disclosure, multiple optical computing chips are jointly used to detect effective signals and identify polymer units in the effective signals.

The above-described embodiments of the present disclosure separate the operations of "identifying effective signals" and "identifying polymer units in effective signals", which greatly improves the efficiency of signal processing.

The above-mentioned embodiments of the present disclosure respectively solve the problems of "identifying effective signals" and "identifying bases in effective signals" by using optical computing chips in series, which greatly improves signal processing efficiency. The algorithm used for "identifying valid signals" is simple, but requires a high degree of parallelism; the algorithm used for "identifying bases in valid signals" is usually more complex. The steps for identifying effective signals in nanopore sequencing generally require simultaneous processing of digital signals generated by multiple nanopores and ADC units. Judging from development trends, the number of nanopores in a single device can exceed 10,000.

The above embodiments of the present disclosure enrich the effective signals through the step of "identifying effective signals", so that the "identifying bases in effective signals" can work more effectively and improve the efficiency of the entire system. The present disclosure can increase the proportion of effective signals in the buffer, thereby allowing more computing resources such as optical computing coprocessors to be used to identify bases in the effective signals.

Figure 9 is a schematic diagram of some embodiments of the light computing method of the present disclosure. Preferably, this embodiment can be executed by the optical computing system of the present disclosure or the controller of the present disclosure. The method may include at least one of steps 91 to 92, wherein:

Step 91: Convert the current generated when the polymer is translocated relative to the nanopore into a digital signal through an analog-to-digital converter array.

Step 92: Control the light computing chip to identify the arrangement of polymer units in the polymer according to the digital signal.

In some embodiments of the present disclosure, step 92 may include controlling the light computing chip to determine whether the digital signal is a valid signal, and by identifying the valid signal, identify the arrangement of polymer units in the polymer.

In some embodiments of the present disclosure, the optical computing method may further include: dividing the digital signal output by each analog-to-digital converter in the analog-to-digital converter array into a plurality of sub-signals, and providing each sub-signal with Add a corresponding identifier, wherein the identifier includes a time stamp and an analog-to-digital converter identifier; control the first cache to store the sub-signal after adding the corresponding identifier, and switch the sub-cache when a sub-cache in the first cache stores the sub-signal , and output the sub-signals in the sub-cache to the optical computing chip, where the first cache includes a plurality of sub-cache.

In some embodiments of the present disclosure, the optical computing method may further include: the storage ratio of a sub-cache in the first cache is greater than a predetermined value, the remaining storage space is less than a preset value, or writing data of a preset size In the case of , switch the sub-buffer and output the sub-signal in the sub-buffer to the optical computing chip, that is, when a sub-buffer is close to overflow, switch the sub-buffer and output the sub-buffer in the sub-buffer that is nearly full. The sub-signals are output to the optical computing chip.

In some embodiments of the present disclosure, the optical computing method may further include: buffering the sub-signals output by the first buffer through the second buffer, and then outputting them to the optical computing chip; outputting each sub-signal of the second buffer to The bandwidth of the optical computing chip is set higher than the computing operating frequency of the optical computing chip.

In some embodiments of the present disclosure, step 92 of the embodiment of Figure 9 may include: controlling the first computing chip to determine whether the digital signal is a valid signal; storing the valid signal calculated by the first computing chip through a third cache; controlling A second computing chip identifies the arrangement of polymer units in the polymer by identifying the valid signal.

In some embodiments of the present disclosure, the optical calculation method may further include: placing multiple consecutive time-stamped sub-signals from the same nanopore in the third buffer in the same section in time sequence.

In some embodiments of the present disclosure, the optical computing method may further include: sequentially entering the sub-signals from the same nanopore in the third buffer into the optical computing chip by referencing a pointer.

In some embodiments of the present disclosure, the optical calculation method may further include: placing multiple consecutive time-stamped sub-signals from the same nanopore in the second cache in the same section in time sequence.

In some embodiments of the present disclosure, the optical computing method may further include: sequentially entering the sub-signals from the same nanopore in the second cache into the optical computing chip by referencing a pointer.

In some embodiments of the present disclosure, the optical computing method may further include: setting the length of the sub-signal in the first cache to be less than or equal to the sequence length configured and processed by the optical computing chip; transmitting the first cache to the optical computing chip The bandwidth is set equal to the computing speed of the optical computing chip.

In some embodiments of the present disclosure, the optical computing method may further include: when the length of the current sub-signal in the first buffer is less than the length of the sequence configured to be processed by the optical computing chip, using the end data of the previous sub-signal and At least one of the starting data of the subsequent sub-signal complements the current sub-signal, so that the length of the current sub-signal in the first buffer is equal to the sequence length processed by the optical computing chip configuration.

Figure 10 is a schematic diagram of some embodiments of a controller of the present disclosure. As shown in Figure 10, the controller of the present disclosure may include a first control module 101 and a second control module 102, wherein:

The first control module 101 is used to convert the current generated when the polymer is translocated relative to the nanopore into a digital signal through an analog-to-digital converter array.

In some embodiments of the present disclosure, the first control module 101 may be implemented as the ADC array controller 620 of the embodiments of FIGS. 2-5 and 8 .

The second control module 102 is used to control the optical computing chip to identify the arrangement of polymer units in the polymer according to the digital signal.

In some embodiments of the present disclosure, the second control module 102 is used to control the optical computing chip to determine whether the digital signal is a valid signal, and to identify the arrangement of polymer units in the polymer by identifying the valid signal.

In some embodiments of the present disclosure, the second control module 102 may be implemented as the system controller 610 and the optical computing chip controller 201 of the embodiments of FIGS. 2-5 and 8 .

In some embodiments of the present disclosure, the controller may be configured to perform operations for implementing the optical computing method described in any of the above embodiments (eg, the embodiment of FIG. 9 ).

Figure 11 is a schematic structural diagram of some other embodiments of the controller of the present disclosure. As shown in FIG. 11 , the controller includes a memory 111 and a processor 112 .

The memory 111 is used to store instructions, and the processor 112 is coupled to the memory 111. The processor 112 is configured to execute and implement the optical computing method described in the above embodiments (such as the embodiment of Figure 9) based on the instructions stored in the memory.

As shown in Figure 11, the controller also includes a communication interface 113 for information exchange with other devices. At the same time, the controller also includes a bus 114, through which the processor 112, the communication interface 113, and the memory 111 complete communication with each other.

The memory 111 may include high-speed RAM memory, or may also include non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 111 may also be a memory array. The storage 111 may also be divided into blocks, and the blocks may be combined into virtual volumes according to certain rules.

Additionally, the processor 112 may be a central processing unit (CPU), or may be an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present disclosure.

The controller described in Figure 10 or Figure 11 of the present disclosure can be implemented as the system controller 610, the ADC array controller 620 and the optical computing chip controller 201 of the embodiments of Figures 2 to 5 and Figure 8.

According to another aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the implementation is as described in any of the above embodiments (for example, FIG. The light calculation method described in Embodiment 9).

In some embodiments of the present disclosure, the computer-readable storage medium may be a non-transitory computer-readable storage medium.

It should be understood by those skilled in the art that embodiments of the present disclosure may be provided as methods, apparatuses, or computer program products. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable non-transitory storage media (including, but not limited to, disk memory, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein. .

The disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each process and/or block in the flowchart illustrations and/or block diagrams, and combinations of processes and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device produce a use A device for realizing the functions specified in one process or multiple processes of the flowchart and/or one block or multiple blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions The device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device. Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

The controller described above may be implemented as a general-purpose processor, programmable logic controller (PLC), digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or any appropriate combination thereof.

Up to this point, the present disclosure has been described in detail. To avoid obscuring the concepts of the present disclosure, some details that are well known in the art have not been described. Based on the above description, those skilled in the art can completely understand how to implement the technical solution disclosed here.

Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by instructing the relevant hardware through a program. The program can be stored in a non-transitory computer-readable storage medium. , the storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

The description of the present disclosure has been presented for the purposes of illustration and description, and is not intended to be exhaustive or to limit the disclosure to the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure and design various embodiments with various modifications as are suited to the particular use contemplated.

Claims

An optical computing system including:

an analog-to-digital converter array configured to convert an electrical current generated upon translocation of the polymer relative to the nanopore into a digital signal;

An optical computing chip configured to identify the arrangement of polymer units in a polymer based on digital signals.
The optical computing system of claim 1, wherein:

The optical computing chip is configured to determine whether the digital signal is a valid signal, and by identifying the valid signal, the arrangement of the polymer units in the polymer is identified.
The optical computing system of claim 2, further comprising:

A controller configured to split the digital signal output by each analog-to-digital converter in the analog-to-digital converter array into multiple sub-signals, and add a corresponding identification to each sub-signal, wherein the identification includes a time stamp and Analog-to-digital converter identification;

The first cache includes a plurality of sub-cache, is arranged between the analog-to-digital converter array and the optical computing chip, and is configured to store the sub-signal after adding the corresponding identifier; in the case where one sub-cache in the first cache stores the sub-signal, Switch the sub-buffer and output the sub-signal in the sub-buffer to the optical computing chip.
The optical computing system of claim 3, further comprising:

The second cache is disposed between the first cache and the optical computing chip, and is configured to cache the sub-signals output by the first cache and then output them to the optical computing chip;

Wherein, the controller is further configured to set the bandwidth of each sub-signal output of the second cache to the optical computing chip to be higher than the computing operating frequency of the optical computing chip.
The optical computing system according to claim 4, wherein the optical computing chip includes:

A first computing chip configured to determine whether the digital signal is a valid signal;

A second computing chip is configured to identify the arrangement of polymer units in the polymer by identifying valid signals.
The optical computing system of claim 5, further comprising:

The third cache is disposed between the first computing chip and the second computing chip, and is configured to store valid signals calculated by the first computing chip.
The optical computing system of claim 6, wherein:

The third buffer is a plurality of parallel buffer arrays corresponding to the analog-to-digital converter array;

and / or,

The controller is further configured to place multiple consecutive sub-signals from the same nanopore in the third cache in the same section in time sequence; or to place the sub-signals from the same nanopore in the third cache by referencing the pointer. The sub-signals from the nanopore enter the optical computing chip sequentially.
The optical computing system according to any one of claims 4-7, wherein:

The second buffer is a plurality of parallel buffer arrays corresponding to the analog-to-digital converter array;

and / or,

The controller is further configured to place multiple consecutive sub-signals from the same nanopore in the second cache in the same section in time sequence; or to place the sub-signals from the same nanopore in the second cache through a reference pointer. The sub-signals from the nanopore enter the optical computing chip sequentially.
The optical computing system according to any one of claims 3-7, wherein:

The analog-to-digital converter array is an analog-to-digital converter array including a plurality of analog-to-digital converters;

and / or,

The length of the sub-signal in the first cache is less than or equal to the sequence length configured to be processed by the optical computing chip;

and / or,

The transmission bandwidth from the first cache to the optical computing chip is equal to the computing speed of the optical computing chip.
The optical computing system according to any one of claims 3-7, wherein:

The controller is further configured to use at least one of the end data of the previous sub-signal and the beginning data of the next sub-signal when the length of the current sub-signal in the first buffer is less than the sequence length configured to be processed by the optical computing chip. The current sub-signal is complemented so that the length of the current sub-signal in the first buffer is equal to the sequence length configured and processed by the optical computing chip.
The optical computing system according to any one of claims 1-7, wherein the optical computing chip includes:

a light source configured to output unmodulated light for use in calculations;

A first digital-to-analog conversion array configured to receive external input data and convert the external input data into a first analog signal;

a modulator array configured to form tensor data based on the light output by the light source and the first analog signal;

The weight data cache is configured to store the weight data of the multiplication matrix;

a second digital-to-analog conversion array configured to convert the weight data into a second analog signal;

An optoelectronic matrix multiplication module is configured to perform a matrix multiplication operation according to the tensor data and the second analog signal to implement optical path calculation.
A light calculation method including:

The current generated when the polymer translocates relative to the nanopore is converted into a digital signal by an analog-to-digital converter array;

Controlled light computing chips identify the arrangement of polymer units in the polymer based on digital signals.
The optical computing method according to claim 12, wherein controlling the optical computing chip to identify the arrangement of polymer units in the polymer according to the digital signal includes:

The light computing chip is controlled to determine whether the digital signal is a valid signal, and by identifying the valid signal, the arrangement of the polymer units in the polymer is identified.
The light calculation method according to claim 13, further comprising:

Split the digital signal output by each analog-to-digital converter in the analog-to-digital converter array into multiple sub-signals, and add a corresponding identification to each sub-signal, wherein the identification includes a time stamp and an analog-to-digital converter identification;

Control the first cache to store the sub-signal with the corresponding identifier added, and when the storage ratio of a sub-cache in the first cache is greater than a predetermined value, switch the sub-cache and output the sub-signal in the sub-cache to the optical computing A chip, wherein the first cache includes a plurality of sub-cache.
The optical computing system of claim 14, further comprising:

After buffering the sub-signals output from the first buffer through the second buffer, output them to the optical computing chip;

The bandwidth of each sub-signal output from the second cache to the optical computing chip is set to be higher than the computing operating frequency of the optical computing chip.
The optical computing method according to claim 15, wherein the controlling the optical computing chip determines whether the digital signal is a valid signal, and by identifying the valid signal, identifying the arrangement of polymer units in the polymer includes:

Control the first computing chip to determine whether the digital signal is a valid signal;

The effective signal calculated by the first computing chip is stored in the third cache;

A second computing chip is controlled to identify the arrangement of polymer units in the polymer by identifying valid signals.
The light calculation method according to claim 16, further comprising:

Place multiple consecutive timestamp sub-signals from the same nanopore in the third cache in the same section in time sequence;

or,

Through the reference pointer, the sub-signals from the same nanopore in the third buffer are sequentially entered into the optical computing chip.
The light calculation method according to any one of claims 15-17, further comprising:

Place the sub-signals of multiple consecutive timestamps from the same nanopore in the second cache in the same section in time sequence;

or,

By referencing the pointer, the sub-signals from the same nanopore in the second buffer are sequentially entered into the optical computing chip.
The light calculation method according to any one of claims 14-17, further comprising:

Set the sub-signal length in the first cache to be less than or equal to the sequence length processed by the optical computing chip configuration;

The transmission bandwidth of the first buffer to the optical computing chip is set equal to the computing speed of the optical computing chip.
The light calculation method according to any one of claims 14-17, further comprising:

When the length of the current sub-signal in the first cache is less than the length of the sequence configured to be processed by the optical computing chip, at least one of the end data of the previous sub-signal and the beginning data of the next sub-signal is used to complement the current sub-signal, This makes the current sub-signal length in the first buffer equal to the sequence length processed by the optical computing chip configuration.
A controller including:

A first control module for converting the current generated when the polymer is translocated relative to the nanopore into a digital signal through an analog-to-digital converter array;

The second control module is used to control the optical computing chip to identify the arrangement of polymer units in the polymer according to the digital signal.
A controller including:

Memory, used to store instructions;

A processor, configured to execute the instructions, causing the controller to perform operations for implementing the optical computing method according to any one of claims 12-20.
A computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the optical computing method according to any one of claims 12-20 is implemented.