WO2023236579A1 - 用于被测逆变器的电负载仿真器 - Google Patents

用于被测逆变器的电负载仿真器 Download PDF

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Publication number
WO2023236579A1
WO2023236579A1 PCT/CN2023/076140 CN2023076140W WO2023236579A1 WO 2023236579 A1 WO2023236579 A1 WO 2023236579A1 CN 2023076140 W CN2023076140 W CN 2023076140W WO 2023236579 A1 WO2023236579 A1 WO 2023236579A1
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iut
ele
voltage
output
ref
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PCT/CN2023/076140
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English (en)
French (fr)
Inventor
潘宣霖
赖斯纳马塞尔
舒伯特米夏埃尔
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臻驱科技（上海）有限公司
上海临港电力电子研究有限公司
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Priority to CN202380012533.9A priority Critical patent/CN117616291A/zh
Publication of WO2023236579A1 publication Critical patent/WO2023236579A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • G01R31/42—AC power supplies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2846—Fault-finding or characterising using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
    • G01R31/2848—Fault-finding or characterising using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms using simulation

Definitions

  • the present disclosure relates to an electrical load simulator for an inverter under test.
  • Inverters are widely used to drive electrical loads such as electric motors or power networks.
  • IUT inverter under test
  • the first option consists of using a test bench consisting of electrical loads.
  • the test bench is a motor test bench that includes a matched motor and a load motor coupled to the matched motor.
  • the inverter is connected to its matching motor.
  • the matched motor is coupled to a load motor that can provide the required torque load and absorb the mechanical power generated by the matched motor.
  • This setup makes it possible to test the inverter under nearly real-life usage conditions, but it is expensive, inflexible, and time-consuming for testing different inverters and motors.
  • the second method is to use an electrical load emulator (ELE) to test the inverter.
  • ELE can be a motor simulator that simulates the electrical behavior of a real motor.
  • PHL Power Hardware-in-the-Loop
  • some advantages of motor simulators include:
  • Motor simulators can speed up the drive system design process to a great extent, especially in terms of global collaboration. For example, if a European motor manufacturer plans to integrate an inverter into the drive system, it may be necessary for the supplier to send test samples of the motor or inverter to set up a motor test bench. The motor should be finished Fully designed and fully manufactured.
  • Document US2021/0036646A1 discloses embodiments related to a motor simulator of an inverter under test (IUT), the motor simulator comprising: a voltage follower inverter for at least partially canceling the output voltage of the IUT; and an output
  • the current control unit is used to control the output current of the IUT based on the estimated current of the simulation target motor.
  • ELEs involve complex control strategies, complex filter structures, or electrically isolated power supplies. This results in a more complex hardware topology, higher cost and weight, and reduced ELE portability.
  • An example of an ELE that is particularly useful for simulating the dynamic operation of electrical loads is simulating power transients in the load over different time periods.
  • the present invention relates to a low-cost ELE that can be built with standard, low-number components while being able to simulate load transients.
  • the present invention provides an electrical load emulator (ELE) for an inverter under test (IUT), wherein the IUT output voltage V IUT at the IUT output is used to employ multiple IUTs separated by IUT rising and falling edges. Voltage state, the ELE output voltage at the ELE output is used to adopt multiple ELE voltage states separated by ELE rising edges and falling edges, and wherein each IUT voltage state corresponds to at least one ELE state.
  • the ELE includes a current sensor for measuring the IUT output current IUT , a coupling filter for connecting the ELE to the IUT, and a voltage sensing unit for sensing the IUT's output voltage V IUT .
  • the ELE also includes a control unit for determining a reference current I REF corresponding to the simulated electrical load based on the sensed IUT output voltage V IUT and comparing the reference current with the measured IUT output current I IUT .
  • the characteristics of ELE are:
  • control unit is used to control the output voltage of the ELE to synchronously follow the output voltage of the IUT such that the IUT is on each rising and/or falling edge between two subsequent IUT voltage states are respectively followed by a corresponding ELE rising and/or falling edge between two subsequent ELE voltage states;
  • the control unit is used, with respect to its corresponding IUT rising edge, to set the subsequent The rising edge of ELE is delayed by one rising edge time;
  • control unit is used to delay the subsequent ELE falling edge by a falling edge time relative to its corresponding IUT falling edge.
  • each phase coupling filter of the ELE of the present invention may include at least one series inductor LF , more preferably, only the series inductor LF .
  • the ELE inverter of the present invention has a two-level topology or a multi-level topology.
  • the ELE inverter of the present invention is used to be powered by a DC power source shared with the IUT.
  • the ELE control unit of the present invention is used for:
  • the reference current I REF is compared to the measured IUT output current I REF and asynchronously to the IUT output voltage V IUT to calculate the time delay of the rising or falling edge.
  • control unit is used for:
  • a reference current IREF corresponding to the simulated electrical load is determined based on the IUT output voltage V IUT periodically measured at the second frequency F2.
  • the second frequency F2 is located between one-third of the switching frequency of the IUT and 300 MHz, further preferably between the switching frequency of the IUT and 100 MHz, further preferably between 2 and 50 MHz, and further preferably Preferably between 3 and 10 MHz;
  • the reference current I REF is compared with the measured IUT output current I IUT , and the time delay of the rising edge or falling edge is calculated periodically at the third frequency F3.
  • the third frequency F3 is preferably lower than or equal to the second frequency F2, further preferably between 100 Hz and 100 MHz, further preferably between 1 kHz and 20 MHz, further preferably between 10 kHz and 10 MHz, further preferably between 1 MHz and 5 MHz. between.
  • the present invention provides a method for controlling an electrical load emulator (ELE) used to test an inverter under test (IUT), wherein the IUT output voltage V IUT at the IUT output terminal is used to test an inverter under test (IUT).
  • ELE electrical load emulator
  • the method includes:
  • I REF is basically equal to I IUT
  • the output voltage of the ELE is controlled to follow the output voltage V IUT of the IUT synchronously, so that each IUT rising edge and/or falling edge between two subsequent IUT voltage states corresponds to two a follow-up ELE voltage states between the rising and/or falling edges of ELE.
  • the present invention also provides a programmable hardware for controlling an electrical load emulator (ELE).
  • the electrical load emulator (ELE) is used for testing the inverter under test (IUT).
  • the programmable hardware is used for causing the ELE to execute method according to the invention.
  • the programmable hardware is a programmable logic device, such as FPGA, EPROM or microcontroller.
  • Figure 1 schematically represents a system consisting of an ELE and an IUT according to the invention, in which power connections are represented by continuous lines and control signal connections are represented by dashed lines;
  • Figure 2 illustrates a three-phase ELE inverter connected to a three-phase IUT through a coupling filter
  • Figure 3 schematically represents a single-phase coupling filter connected to the IUT and ELE, which single-phase coupling filter only consists of components connected in series;
  • Figure 4 is a graph of the output variables of IUT and ELE and the reference current IREF changing with time when I REF is basically equal to I IUT ;
  • Figure 5 is a graph of the output variables of IUT and ELE and the reference current IREF changing with time when I REF is higher than I IUT ;
  • Figure 6 is a graph of the output variables of IUT and ELE and the reference current IREF changing with time when I REF is lower than I IUT .
  • first, second, third and similar terms in the description and claims are used to distinguish similar elements and are not necessarily used to describe a sequence or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
  • the terms “about” or “approximately” are synonyms and are used to indicate that the value modified by the term has a range of understanding associated with it, where the range may be +20%, +15%, +10%, +5% or +1%.
  • the term “substantially” is used to indicate that a result (e.g., a measured value) is close to a target value, where close can mean, for example, that the result is within 80% of the value, within 90% of the value, within 95% of the value , or within 99% of this value.
  • Substantially equal values are understood to mean values that differ by up to 20%, or 10%, or 5%, or 1%.
  • FIG 1 shows an example of an electrical load simulator (1) of the invention, here called ELE, coupled to an inverter under test (2), here called IUT.
  • the ELE (1) consists of an ELE inverter (7) and a coupling filter (4) for connecting the ELE inverter (7) to the IUT (2).
  • a DC power supply (8) is connected to the IUT (2) and provides power to it.
  • ELE (1) is used to share DC power supply (8) with IUT (2).
  • the DC power supply (8) can be downsized since it should only provide the combined losses of ELE(1) and IUT(2), which is usually less than the combined losses of IUT(1) and ELE(2) considered individually. Peak power is much lower.
  • the ELE (1) of the present invention may be used to connect to a DC power source of the ELE that is separate from the DC power source (8) that powers the IUT.
  • the ELE of the present invention includes a current sensor (3).
  • the current sensor (3) is used to measure the IUT output current I IUT flowing out from the IUT output terminal and generate a signal representing the measured IUT output current I IUT .
  • Current sensor output signal can be installed at the IUT output or built into the ELE inverter (7).
  • the ELE includes a voltage sensing unit (5) for sensing the IUT output voltage V IUT at the IUT output terminal and generating a voltage sensing unit output signal representing the sensed IUT output voltage V IUT .
  • the voltage sensing unit (5) may include a voltage comparator coupled or connected to the IUT output, and the voltage sensing unit output signal represents a comparison between the IUT output voltage V IUT and a given threshold.
  • ELE(1) is used to determine an estimated IUT output voltage based at least on the voltage sensing unit output signal from the voltage comparator. Even better, ELE(1) is used to determine the estimated IUT output voltage based on a combination of the voltage sensing unit output signal and a current sensor output signal representative of the measured IUT output current IUT .
  • ELE(1) is used to periodically determine the estimated IUT output voltage V IUT at a first frequency F1.
  • the voltage sensing unit (5) may include a voltage measurement sensor for measuring the amplitude of the IUT output voltage V IUT , and the output signal of the voltage sensing unit represents V IUT .
  • the voltage sensing unit (5) may include an edge detector (preferably an emulated edge detector) for continuously operating and detecting the rising and falling edges of the IUT output voltage V IUT .
  • the ELE (1) also includes a control unit (6) connected to the ELE inverter (7) as well as the current sensor (3) and the voltage sensing unit (5).
  • the control unit (6) is used to receive the current sensor output signal and the voltage sensing unit output signal, and output the current I IUT according to the measured IUT and the induced IUT output voltage V IUT (i.e.
  • the ELE inverter (7) is controlled based on the voltage sensing unit output signal and the current sensor output signal).
  • ELE(1) is used to simulate the load of the IUT, where the IUT output voltage V IUT at the IUT output terminal (10) is a switching output voltage (i.e., it takes multiple IUT voltage states separated by IUT rising edges and IUT falling edges). IUT falling and rising edges correspond to transients in the IUT output voltage caused by changes in the state of the IUT switch (i.e., the IUT switch moves from the open position to the closed position, or vice versa).
  • Figure 4 shows an example of the time variation of the IUT output voltage V IUT .
  • the V IUT shown in FIG. 4 can be generated by one phase leg of the two-level inverter shown in FIG. 2 .
  • the amplitude of the first IUT voltage state is null, while the amplitude of the second IUT voltage state is equal to the output voltage of the DC power supply (8) used to power the IUT (2).
  • the first IUT voltage state can be DC- or low, while the second IUT voltage state can be DC+ or high.
  • the IUT voltage state (2s) is separated by the IUT rising edge (2r) and the IUT falling edge (2f).
  • the voltage and current signals represented in Figure 4 are idealized signals and do not limit the scope of the present invention. In real situations, these signals consisting of V IUT and V ELE may contain noise, ripples, and the rising and falling edges of IUT and ELE have finite slopes, which is not represented in Figure 4. Parasitic delays are also not represented in Figure 4.
  • V IUT can also include more than two IUT voltage states, for example, if the IUT has a multi-level topology.
  • an IUT can have a neutral-point-clamped topology in which the IUT output voltage VIUT switches between DC-potential, zero-potential, and DC+-potential.
  • the IUT may be a polyphase IUT including multiple IUT inverter phase legs, each phase leg providing an IUT output voltage at a respective IUT output (10) to which it is connected.
  • the switching output voltage of the IUT can include modulation, PWM (such as variable switching frequency PWM), or direct torque control.
  • the ELE (1) of the present invention includes an ELE inverter (7).
  • the ELE inverter (7) includes at least one ELE inverter phase pin (7l) with several switching units (7s). It can have one, two, three, four or more ELE inverter phase legs.
  • Figure 2 shows an example of the ELE inverter (7) of the present invention including three two-stage ELE inverter phase legs (7l), where each phase leg includes two ELE switching units (7s), where the ELE inverter The center nodes of the converter phase pins are connected to the respective ELE output terminals (9).
  • the ELE output terminal (9) is used to
  • the ELE inverter (7) is connected to the coupling filter (4).
  • the ELE inverter (7) may also be a multi-level inverter (for providing more than two ELE output voltages VELE voltage levels).
  • ELE(1) is used to command the ELE switching unit (7s) to provide an ELE output voltage V ELE on each ELE output terminal (9), which takes multiple times in time consisting of ELE rising edges (1r) and ELE falling edges ( 1f) Separate ELE voltage states (1s) (i.e. ELE voltage levels). Therefore, the output voltage V ELE of ELE is a switched output voltage.
  • the falling and rising edges of ELE correspond to the ELE output voltage transient after the ELE inverter switching state changes, while the ELE voltage state corresponds to the specific state of the ELE switching unit (7s).
  • FIG 4 an example of the change of the ELE output voltage V ELE with time is shown. This is a two-level voltage at one terminal (9) of ELE.
  • the ELE output voltage V ELE represented in Figure 4 is an idealized signal and should not limit the scope of the present invention. Possible noise, ripple, and other spurious signal components in VELE are not represented.
  • the rising edge (1r) and falling edge (1f) of ELE have finite slopes, which is also not shown in Figure 4.
  • V ELE may also include more than two ELE voltage states, for example if the ELE inverter (7) has a multi-level topology.
  • ELE(1) is used to provide the ELE output voltage V ELE , where each IUT voltage state (2s) corresponds to a substantially equal ELE voltage state (1s), thereby connecting the ELE output terminal (9) and the IUT output terminal (10)
  • the voltages on the coupling filter (4) can be basically canceled.
  • ELE(1) is used to provide an ELE output voltage VELE , where the number of different ELE voltage states is the same as the number of different IUT voltage states.
  • ELE(1) may include a multi-level ELE inverter adapted to provide more different ELE voltage states (1 s) than more different IUT voltage states (2 s).
  • ELE(1) can be used to command the switching unit (7s) to provide only a smaller number of ELE voltage states (1s), where each of the smaller number of ELE voltage states is essentially Equal to one of the different IUT voltage states (2s).
  • the ELE (1) includes a coupling filter (4) connecting the ELE output (9) and the IUT output (10).
  • the ELE coupling filter (4) of the present invention may include one or more phases, and preferably there is no cross-coupling between phases.
  • Each phase of the coupling filter (4) includes at least one series inductor L F , preferably only one series inductor L F .
  • each phase of the coupling filter (4) only includes components connected in series, as shown in Figure 3, so that the filter current IF passing through the coupling filter is equal to the IUT output current flowing out of the IUT output terminal (10) I IUT and the ELE output current I ELE entering the ELE output terminal (9).
  • the control unit (6) of the ELE (1) is configured to determine the reference current I REF corresponding to the simulated electrical load based on the voltage sensing unit output signal representing the measured output voltage V IUT of the IUT.
  • the simulated electrical load can be a motor or a power network.
  • ELE(1) may include a model of the simulated electrical load, for example, a motor model for determining the relationship between the phase currents of the simulated motor and the phase voltages of the simulated motor.
  • the phase current of the simulated motor is the calculated reference current I REF
  • the phase voltage of the simulated motor is the measured IUT output voltage V IUT .
  • the control unit (6) in the ELE (1) is used to periodically determine the reference current I REF at the second frequency F2.
  • the second frequency F2 is equal to the first frequency F1.
  • the second frequency F2 may be between one-third and 300MHz of the switching frequency of the IUT, further preferably between the switching frequency of the IUT and 100MHz, further preferably between 2 and 50MHz, further preferably Preferably, between 3 and 10 MHz.
  • control unit (6) includes a discrete-time calculation circuit for receiving the output signal of the voltage sensing unit and periodically determining the reference current I at the second frequency F2 REF . In the ELE of the present invention, this can be accomplished asynchronously to changes in the IUT voltage state at the IUT output.
  • the control unit (6) in the ELE (1) is also used to compare the reference current IREF with the measured IUT output current IIUT, preferably periodically at a third frequency F3.
  • the control unit (6) is used to compare the latest value of the reference current IREF with the instantaneous value of the IUT output current IIUT.
  • the latest value of the reference current IREF is determined by the control unit (6); the instantaneous value of the IUT output current IIUT is measured by the current sensor (3).
  • the third frequency F3 is lower than or equal to the second frequency F2.
  • the third frequency F3 is between 100Hz and 100MHz, further preferably between 1kHz and 20MHz, further preferably between 10kHz and 10MHz, further preferably between 1MHz and 5MHz.
  • the third frequency F3 is higher than the switching frequency of the IUT, or higher than the frequency at which the IUT refreshes the IUT output current target.
  • I REF is basically equal to I IUT
  • the control unit (6) can enter the voltage following mode, that is, control the ELE output Voltage V ELE synchronously follows the IUT output voltage V IUT such that each IUT rising and/or falling edge between two subsequent IUT voltage states follows the corresponding ELE rising edge and/or falling edge between two subsequent ELE voltage states, respectively. /or falling edge.
  • Figure 4 illustrates an example of this mode of operation of the ELE.
  • the current sensor (3) measures the output current IIUT of the IUT and compares it with the reference current I REF calculated by the control unit (6) at time instants Ti1 , Ti2 , Ti3 , Ti4 .
  • I REF is substantially equal to I IUT
  • the control unit (6) is used to command the ELE switching unit (7s) of the ELE inverter (7) to follow the IUT output voltage synchronously with the ELE output voltage, i.e., ELE (1)
  • the ELE output voltage V ELE used to set the ELE voltage state at each instant of time to be substantially equal to the ongoing IUT voltage state.
  • ELE is used to track the IUT output voltage V IUT with the ELE output voltage V ELE by synchronizing V ELE to one of the ELE voltage states that is substantially equal to the ongoing IUT voltage state.
  • I IUT switches from a high IUT voltage state to a low IUT voltage state, which state is detected by the voltage sensing unit of the ELE, and the ELE is used to respectively
  • the control unit (6) is used to control the ELE voltage state taken by V ELE to synchronously follow the IUT voltage state taken by V IUT . In this case, each IUT voltage state and its synchronously following ELE voltage state are represented as "corresponding”. Likewise, if IREF is substantially equal to I IUT , the control unit (6) is used to control the rising edge and falling edge of ELE taken by V ELE to respectively follow the rising edge and falling edge of IUT taken by I IUT synchronously. In this case, each IUT rising or falling edge and its synchronously following ELE rising or falling edge are represented as "corresponding".
  • Figure 3 shows a single phase of the coupling filter connected to one phase of the IUT and one phase of the ELE.
  • the ELE voltage state assumed by V ELE synchronously follows the IUT voltage state assumed by V IUT .
  • the coupling filter (4) only includes a series inductor LF , in which the parasitic resistance RP of the inductor LF is preferably negligible.
  • the control unit (6) may include a continuous time logic unit for receiving the voltage sensing unit output.
  • the output signal of the voltage sensing unit is a continuous edge detection signal representing the rising edge and falling edge of the IUT.
  • the rising edge and falling edge of the IUT are detected by the voltage sensing unit (5).
  • the continuous time logic unit may be used to control the ELE inverter and the ELE output voltage V ELE to synchronously follow the IUT output voltage V IUT based on the continuous edge detection signal.
  • the continuous-time logic unit can be an emulation circuit that runs continuously in time, such as an EPROM or FPGA, while the output signal of the voltage sensing unit can be generated by a comparator in the sensing unit that also runs continuously in time.
  • Using continuous time logic circuits in combination with comparators minimizes the parasitic delays associated with sensing and control in ELEs compared to using (for example) discrete time control circuits.
  • edge detection is much faster than the actual voltage amplitude determination or measurement, and controlling the ELE inverter (7) based on the edge detection signal to copy the IUT output signal is much faster than based on the voltage amplitude measurement.
  • the ELE of the present invention may include continuous-time logic circuitry for tracking or quickly replicating the IUT output signal, combined with slower-reacting discrete-time control circuitry for determining the reference current I REF .
  • I REF is higher than I IUT
  • the control unit (6) is used to delay the subsequent ELE rising edge by one rising edge time relative to its corresponding IUT rising edge (2r).
  • the subsequent ELE rising edge is the one that occurs after the measured IUT output current is compared with the reference current, and the control unit (6) calculates the rising edge time delay to be applied.
  • ELE(1) is used to compare the reference current I REF with the measured IUT output current I IUT , and periodically calculate the time delay of the rising edge or falling edge at the third frequency F3.
  • the control unit (6) compares I REF with I IUT and calculates the time delays applied to the rising edges of times Ti1, Ti2, Ti3, Ti4.
  • the control unit (6) is used to delay the first occurring ELE rising edge (1r) relative to its corresponding IUT rising edge (2r), so that the IUT output current is quickly adjusted to be close to the reference current.
  • the voltage and current signals represented in Figure 5 are idealized signals and do not limit the scope of the present invention. In real situations, these signals consisting of V IUT and V ELE may include noise, ripples, and the rising and falling edges of IUT and ELE have finite slopes, which is not shown in Figure 5. Parasitic delays are also not shown in Figure 5.
  • the delayed rising edge of ELE (1r) is compared in the control unit (6) to produce the result It occurs after I REF >I IUT , preferably the first rising edge of ELE (1r) that occurs after comparison by the control unit (6).
  • the corresponding ELE rising edge (1r) is the ELE rising edge that may occur synchronously with the IUT rising edge (2r).
  • the IUT output voltage therefore assumes an IUT voltage state that is higher than the ELE voltage state assumed by the ELE output voltage and the filter voltage V F is positive,
  • the IUT output current I IUT increases.
  • the coupling filter (4) only includes a series inductor L F , and the parasitic resistance R P of the inductor L F is negligible, V F ⁇ L F *dI IUT /dt, and dI IUT /dt>0, because V F is positive.
  • ⁇ I REF -I IUT ⁇ is the absolute value of the difference between the reference current and the measured IUT current
  • ⁇ V ELE -V IUT ⁇ is the absolute value of the difference between ELE and IUT output voltage, that is, on the following ELE rising edge ( During the time delay ⁇ t between 1r) and its corresponding IUT rising edge (2r), ⁇ V ELE -V IUT ⁇ is the absolute value between the voltages related to the ELE and IUT voltage states.
  • I REF is lower than I IUT
  • the control unit (6) is used to delay one of the subsequent ELE falling edges by a falling edge time relative to its corresponding IUT falling edge (2f), as shown in Figure 6 .
  • ELE(1) is used to compare the reference current I REF with the measured IUT output current I IUT and calculate the rising edge or falling edge time delay, which is periodic at the third frequency F3 sexual applications.
  • the subsequent ELE falling edge is the ELE falling edge that occurs after the measured IUT output current is compared with the reference current, and the time delay of the falling edge to be applied is calculated by the control unit (6).
  • control unit (6) compares I REF with I IUT and calculates the time delays of the falling edges applied at times Ti1, Ti2, Ti3, Ti4.
  • the control unit (6) is used to delay the first displayed ELE falling edge (1f) relative to its corresponding IUT falling edge (2f), as shown in Figure 6, so that the IUT output current is quickly adjusted close to the reference current .
  • the voltage and current signals represented in FIG. 6 are idealized signals and do not limit the scope of the present invention. In real situations, these signals consisting of V IUT and V ELE may include noise, ripple, and the rising and falling edges of IUT and ELE have finite slopes, which is not shown in Figure 6. Parasitic delays are also not shown in Figure 6.
  • the IUT output voltage V IUT is synchronous, except that the falling edge of ELE (1f) is delayed by the falling edge time relative to its corresponding IUT falling edge (2r).
  • the delayed ELE falling edge (1f) occurs after the control unit (6) comparison produces the result I REF ⁇ I IUT .
  • the IUT output voltage therefore takes a IUT voltage state, its voltage is lower than the ELE voltage state adopted by the ELE output voltage, and the filter voltage VF is negative, the IUT output current I IUT decreases.
  • ⁇ I REF -I IUT ⁇ is the absolute value of the difference between the reference current and the measured IUT current
  • ⁇ V ELE -V IUT ⁇ is the absolute value of the difference between the ELE and IUT output voltages, that is, at the falling edge of ELE below
  • ⁇ V ELE -V IUT ⁇ is the absolute value between the voltages associated with the ELE and IUT voltage states.

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  • Inverter Devices (AREA)

Abstract

一种用于被测逆变器IUT（2）的电负载仿真器ELE（1），其中IUT输出端（10）的IUT输出电压VIUT用于采取多个IUT电压状态，该多个IUT电压状态由上升沿和下降沿分开，而ELE输出端的ELE输出电压用于采取多个ELE电压状态，该多个ELE电压状态由上升沿和下降沿分开，并且其中每个IUT电压状态对应至少一个ELE电压状态。ELE（1）包括一个用于测量IUT输出电流IIUT的电流传感器（3），一个用于将ELE（1）连接到IUT（2）的耦合滤波器（4），一个用于测量IUT输出电压VIUT的电压感应单元（5），以及一个控制单元（6），用于根据测量的IUT输出电压VIUT来确定对应于仿真电负载的参考电流IREF，并将参考电流IREF与测量的IUT输出电流IIUT进行比较。

Description

用于被测逆变器的电负载仿真器 技术领域
本公开内容涉及一种用于被测逆变器的电负载仿真器。
背景技术
逆变器被广泛用于驱动电负载，如电动机或电力网络。为了测试被测逆变器(IUT)通常有两种选择。第一种选择包括使用由电力负载组成的测试台。例如，在逆变器用于驱动电机的情况下，测试台是一个电机测试台，包括一个匹配的电机和一个耦合到匹配电机的负载电机。在测试期间，逆变器与其匹配的电机相连接。匹配的电机与负载电机耦合，负载电机可以提供所需的扭矩负载并吸收匹配电机产生的机械功率。这种设置可以在几乎真实的使用情况下测试逆变器，但对于测试不同的逆变器和电机来说，它是昂贵的，不灵活的，而且很费时间。
第二种方法是使用电负载仿真器(ELE)来测试逆变器。例如，ELE可以是一个电机仿真器，它可以仿真真实电机的电气行为。这种测试方法属于电力硬件在环测试(PHiL)的类别。例如，电机仿真器的一些优点包括：
-灵活性：对于电机测试台来说，每次在应用新的电机之前，都应该改变测试设置并进行校准。这是一个大问题，因为一个逆变器制造商通常为几十种不同的电机制造逆变器。相比之下，电机仿真器可以使用相同的硬件设置来仿真几乎所有种类的电机。要测试一个新的电机，只需要在电机仿真器的软件中稍作改变；
-安全性：由于电机仿真器没有任何机械部件，所以在测试时没有动能或振动。因此，与电机测试台相比，使用电机仿真器的测试更安全。同时，可以对故障情况进行非破坏性的测试；
-加速设计过程：电机仿真器可以在很大程度上加速传动系统的设计进程，特别是在全球合作方面。例如，如果欧洲的电机制造商计划将逆变器集成到传动系统中，那么可能需要由供应商发送电机或逆变器的测试样品，以建立电机测试台。电机应该是已经完 全设计好和完全制造好的。
在使用电机仿真器时，电机制造商只需要发出详细的电机数据。使用电机仿真器的测试台可以在一小时内开始运行，并在同一天发回测试结果。因此，在电机的设计阶段已经可以测试传动系统，这反过来又有助于设计传动系统的专用电机。
已经有电力负荷仿真器系统，并在市场上有售。文件US2021/0036646A1披露了与被测逆变器(IUT)的电机仿真器有关的实施方案，该电机仿真器包括：电压跟随器逆变器，用于至少部分抵消IUT的输出电压的；以及输出电流控制单元，用于根据仿真目标电机的估计电流来控制IUT的输出电流。
尽管有这些优势，但大多数已知的ELE涉及复杂的控制策略、复杂的滤波器结构、或电隔离电源。这导致了更复杂的硬件拓扑结构，更高的成本和重量，以及降低了ELE的便携性。一个尤其适用于仿真电力负载的动态运行的ELE的例子，为仿真负载在不同时间段的功率瞬变。
需要一种适合动态仿真电力负载、并降低复杂性和成本的ELE。本发明涉及一种低成本的ELE，它可以用标准的、数量较少的部件来建造，同时能够仿真负载瞬态。
发明内容
本发明由独立权利要求书定义。从属权利要求书定义了有利的实施方案。
本发明提供了一种用于被测逆变器(IUT)的电负载仿真器(ELE)，其中在IUT输出端的IUT输出电压VIUT用于采用多个由IUT上升沿和下降沿分开的IUT电压状态，在ELE输出端的ELE输出电压用于采用由ELE上升沿和下降沿分隔的多个ELE电压状态，并且其中每个IUT电压状态对应至少一个ELE状态。ELE包括一个用于测量IUT输出电流IIUT的电流传感器，一个用于将ELE连接到IUT的耦合滤波器，以及一个用于感应IUT的输出电压VIUT的电压感应单元。ELE还包括一个控制单元，该单元用于根据感应到的IUT输出电压VIUT来确定与仿真电负载相对应的参考电流IREF，并将参考电流与测量的IUT输出电流IIUT进行比较。ELE的特点是：
-如果IREF基本等于IIUT，则控制单元用于控制ELE的输出电压，以同步跟随IUT的输出电压，从而使得IUT在两个后续IUT电压状态之间的每个上升沿和/或下降沿都分别被两个后续ELE电压状态之间的相应的ELE上升沿和/或下降沿所跟随；
-如果IREF高于IIUT，则控制单元用于，相对于其相应的IUT上升沿而言，将随后的 ELE上升沿延迟一个上升沿时间；
-如果IREF低于IIUT，则控制单元用于，相对于其相应的IUT下降沿而言，将随后的ELE下降沿延迟一个下降沿时间。
优选的，本发明的ELE的每相耦合滤波器可以包括至少一个串联电感LF，更优选的，仅有串联电感LF。
优选的是，本发明的ELE逆变器有一个两级拓扑结构或多级拓扑结构。
优选的是，本发明的ELE逆变器用于由一个与IUT共享的直流电源来供电。
优选地，本发明的ELE的控制单元用于：
根据测量的IUT输出电压VIUT，来确定对应于仿真电负载的参考电流IREF；
将参考电流IREF与测量的IUT输出电流IREF进行比较，并与IUT输出电压VIUT异步地来计算上升沿或下降沿的时间延迟。
优选的，控制单元用于：
基于周期性地以第二频率F2测量的IUT输出电压VIUT，来确定对应于仿真电负载的参考电流IREF。其中，优选的，第二频率F2位于IUT的开关频率的三分之一和300MHz之间，进一步优选为IUT的开关频率和100兆赫之间，更进一步优选为2至50兆赫之间，更进一步优选为3至10兆赫之间；
将参考电流IREF与测量的IUT输出电流IIUT进行比较，并周期性地以第三频率F3计算上升沿或下降沿的时间延迟。其中第三频率F3优选低于或等于第二频率F2，进一步优选为100赫兹和100兆赫之间，进一步优选为1kHz和20MHz之间，进一步优选为10kHz和10MHz之间，进一步优选为1MHz和5MHz之间。
本发明提供了一种用于控制电负载仿真器(ELE)的方法，该电负载仿真器(ELE)用于测试被测逆变器(IUT)，其中IUT输出端的IUT输出电压VIUT用于采用由IUT上升沿和下降沿分隔的多个IUT电压状态，该方法包括：
-感测IUT输出端处的IUT输出电压VIUT；
-基于感测的IUT输出电压VIUT，确定与仿真电负载相对应的参考电流IREF；
-测量IUT输出电流IIUT；
-将参考电流IREF与测量的IUT的输出电流IIUT进行比较。
-如果IREF基本等于IIUT，则控制ELE的输出电压同步跟随IUT的输出电压VIUT，这样，两个后续IUT电压状态之间的每个IUT上升沿和/或下降沿，都分别对应两个后续的 ELE电压状态之间的ELE的上升沿和/或下降沿。
-如果IREF高于IIUT，则相对于其相应的IUT上升沿而言，将随后的ELE上升沿延迟一个上升沿时间；
-如果IREF低于IIUT，则相对于其相应的IUT下降沿而言，将随后的ELE下降沿延迟一个下降沿时间。
本发明还提供了一种可编程硬件，用于控制电负载仿真器(ELE)，电负载仿真器(ELE)用于测试被测逆变器(IUT)，该可编程硬件用于使ELE执行根据本发明的方法。其中，该可编程硬件是可编程逻辑装置，如FPGA、EPROM或微控制器。
附图说明
本发明的设备、系统和方法的特征、层面(aspects)和优点将从以下的描述、从属权利要求和附图中得到更好的理解。其中：
图1示意性地表示一个由根据本发明的ELE和IUT组成的系统，其中电力连接用连续线表示，控制信号连接用虚线表示；
图2示意了一个三相ELE逆变器通过耦合滤波器与三相IUT连接；
图3示意性地表示连接到IUT和ELE的单相耦合滤波器，该单相耦合滤波器只包括串联的元件；
图4是当IREF基本等于IIUT时，IUT和ELE的输出变量以及参考电流IREF随时间变化的曲线图；
图5是当IREF高于IIUT时，IUT和ELE的输出变量以及参考电流IREF随时间变化的曲线图；
图6是当IREF低于IIUT时，IUT和ELE的输出变量以及参考电流IREF随时间变化的曲线图。
附图既没有按比例绘制，也不是成比例的。一般来说，相同的部件在图中用相同的参考数字表示。
具体实施方式
用于描述特定实施方案的术语并不意味着对本发明的限制。正如本文所使用的，单数形式的"a"、"an"和"the"旨在也包括复数形式，除非上下文明确指出。术语"和/或"包括 一个或多个相关列出的项目的任何和所有的组合。可以理解的是，术语"包括"和/或"包括"指明了所述特征的存在，但不排除存在或增加一个或多个其他特征。可以进一步理解的是，当一个方法的特定步骤被称为另一步骤的后续时，它可以直接跟随所述另一步骤，或者在执行特定步骤之前可以执行一个或多个中间步骤，除非另有说明。同样，可以理解的是，当描述结构或部件之间的连接时，除非另有规定，否则这种连接可以直接或通过中间结构或部件来建立。
本发明将就特定的实施方案并参照某些附图进行描述，但本发明并不局限于此，而仅由权利要求书所限定。所描述的附图只是示意性的，并且是非限制性的。在附图中，为了达到说明的目的，一些元素的尺寸可能被夸大了，并且没有按比例绘制。
在本说明书和权利要求书中所使用的术语"包括"，并不排除其他元素或步骤。
此外，说明书和权利要求中的术语第一、第二、第三和类似的术语用于区分类似的元素，不一定用于描述顺序或时间顺序。应该理解的是，这样使用的术语在适当的情况下是可以互换的，这里描述的本发明的实施方案能够以相比于这里的描述或说明的其他顺序来操作。
术语"大约"或"近似"等是同义词，用于表示由该术语修饰的值有一个与之相关的理解范围，其中该范围可以是+20％、+15％、+10％、+5％或+1％。术语"基本"用于表示结果(例如，测量值)接近目标值，其中接近可以意味着，例如，结果在该值的80％以内，在该值的90％以内，在该值的95％以内，或在该值的99％以内。实质上相等的值可以理解为最多相差20％，或10％，或5％或1％的值。
下文将参照附图对本发明进行更充分的描述，附图中显示了本发明的实施方案。在附图中，为了清楚起见，系统、部件、层和区域的绝对和相对尺寸可能被夸大了。可以参考本发明的可能理想化的实施例和中间结构的示意图和/或横截面图示来描述实施例。在说明书和附图中，类似的数字指的是整个类似的元素。相对术语及其衍生物应理解为指当时描述的方向或所讨论的图中所示的方向。这些相对术语是为了描述的方便，并不要求该系统以特定的方向构造或操作，除非另有说明。
电负载仿真器(ELE)
图1表示本发明的电负载仿真器(1)的一个例子，这里称为ELE，它与这里称为IUT的被测逆变器(2)耦合。ELE(1)包括一个ELE逆变器(7)和一个耦合滤波器(4)，耦合滤波器(4)用于将ELE逆变器(7)连接到IUT(2)。
如图1所示，一个直流电源(8)与IUT(2)相连并向其提供电力。在图1所示的 本发明的一个例子中，ELE(1)用于与IUT(2)共享直流电源(8)。在这种情况下，可以缩小直流电源(8)的规模，因为它应该只提供ELE(1)和IUT(2)的综合损耗，这通常比单独考虑的IUT(1)和ELE(2)的峰值功率低得多。在另一个例子中，本发明的ELE(1)可以用于连接到ELE的直流电源，该直流电源与对IUT供电的直流电源(8)是分开的。
电流传感器
如图1所示，本发明的ELE包括一个电流传感器(3)，该电流传感器(3)用于测量从IUT输出端流出的IUT输出电流IIUT，并产生代表所测IUT输出电流IIUT的电流传感器输出信号。例如，电流传感器(3)可以安装在IUT输出端或内置在ELE逆变器(7)中。
电压感应单元
ELE包括一个电压感应单元(5)，该电压感应单元(5)用于在IUT输出端感应IUT输出电压VIUT，并产生一个代表所感应的IUT输出电压VIUT的电压感应单元输出信号。
例如，电压感应单元(5)可以包括与IUT输出端耦合或连接的电压比较器，并且电压感应单元输出信号代表IUT输出电压VIUT与给定阈值之间的比较。在这个例子中，ELE(1)用于至少根据来自电压比较器的电压感应单元输出信号来确定一个估计的IUT输出电压。更好的是，ELE(1)用于基于电压传感单元输出信号与代表测量的IUT输出电流IIUT的电流传感器输出信号相结合来确定估计的IUT输出电压。这允许ELE(1)更准确地确定IUT输出电压，因为ELE可以用于同时基于导电的IUTIGBT的压降(例如，以及基于IUTIGBT的反并联二极管的正向电压)来确定IUT输出电压VIUT。优选地，ELE(1)用于以第一频率F1周期性地确定估计的IUT输出电压VIUT。
在另一个例子中，电压感应单元(5)可以包括一个电压测量传感器，电压测量传感器用于测量IUT输出电压VIUT的振幅，并且电压感应单元的输出信号代表VIUT。在另一个例子中，电压感应单元(5)可以包括一个边缘检测器(最好是一个仿真边缘检测器)，用于连续工作并检测IUT输出电压VIUT的上升沿和下降沿。
ELE(1)还包括一个控制单元(6)，控制单元(6)与ELE逆变器(7)以及电流传感器(3)和电压感应单元(5)相连。控制单元(6)用于接收电流传感器输出信号和电压感应单元输出信号，并根据测量的IUT输出电流IIUT和感应的IUT输出电压VIUT(即 根据电压感应单元输出信号和电流传感器输出信号)来控制ELE逆变器(7)。
被测逆变器(IUT)
ELE(1)用于仿真IUT的负载，其中IUT输出端(10)的IUT输出电压VIUT是一个开关输出电压(即采取多个由IUT上升沿和IUT下降沿分开的IUT电压状态)。IUT下降沿和上升沿对应于由IUT开关的状态变化引起的IUT输出电压的瞬态(即IUT开关从打开位置转移到关闭位置，或反之亦然)。
图4显示了IUT输出电压VIUT随时间变化的一个例子。图4中表示的VIUT可以由图2中表示的两级逆变器的一个相位脚(phaseleg)产生。在图4中，有一个第一IUT电压状态(2s)和第二IUT电压状态(2s)，对应于IUT输出电压大致恒定的时间区间。第一IUT电压状态的振幅为空，而第二IUT电压状态的振幅等于用于向IUT(2)供电的直流电源(8)的输出电压。一般来说，第一IUT电压状态可以是直流-或低电位，而第二个IUT电压状态可以是直流+或高电位。IUT电压状态(2s)由IUT上升沿(2r)和IUT下降沿(2f)分开。当然，技术人员应很容易认识到，图4中表示的电压和电流信号是理想化的信号，并不限制本发明的范围。在实际情况下，由VIUT和VELE组成的这些信号可能包含噪声、波纹，而且IUT和ELE的上升沿和下降沿具有有限的斜率，这在图4中没有表示。图4中也没有表示寄生延迟。VIUT也可以包括两个以上的IUT电压状态，例如，如果IUT有一个多级拓扑结构。例如，IUT可以有一个中性点钳制的拓扑结构，其中IUT输出电压VIUT在直流-电位、零电位和直流+电位之间切换。如图2所示，IUT可以是一个包括多个IUT逆变器相位脚的多相IUT，每个相位脚在与其相连的各自IUT输出端(10)提供IUT输出电压。
IUT的开关输出电压可以包括以下调制，PWM(如可变开关频率PWM)，或直接扭矩控制。
ELE逆变器(7)
本发明的ELE(1)包括一个ELE逆变器(7)。该ELE逆变器(7)包括至少一个具有若干开关单元(7s)ELE逆变器相位脚(7l)。它可以有一个、两个、三个、四个或更多的ELE逆变器相位脚。图2表示本发明的ELE逆变器(7)包括三个两级ELE逆变器相位脚(7l)一个例子，其中，每个相位脚包括两个ELE开关单元(7s)，其中ELE逆变器相位脚的中心节点连接到各自的ELE输出端子(9)。ELE输出端子(9)用于将 ELE逆变器(7)连接到耦合滤波器(4)。ELE逆变器(7)也可以是一个(用于提供两个以上的ELE输出电压VELE的电压等级)多电平逆变器。
ELE(1)用于命令ELE开关单元(7s)在每个ELE输出端(9)上提供一个ELE输出电压VELE，它采取多个在时间上由ELE上升沿(1r)和ELE下降沿(1f)分开的ELE电压状态(1s)(即ELE电压水平)。因此，ELE的输出电压VELE是一个切换的输出电压。ELE下降沿和上升沿对应于ELE逆变器开关状态变化后的ELE输出电压瞬变，而ELE电压状态对应于ELE开关单元(7s)的特定状态。
在图4中，表示了一个ELE输出电压VELE随时间变化的例子。这是在ELE的一个端子(9)的两级电压。与IUT(2)一样，技术人员应很容易认识到，图4中表示的ELE输出电压VELE是一个理想化的信号，不应限制本发明的范围。VELE中可能存在的噪声、纹波和其他寄生信号成分没有表示出来。ELE的上升沿(1r)和下降沿(1f)具有有限的斜率，这在图4中也没有表示出来。VELE也可以包括两个以上的ELE电压状态，例如，如果ELE逆变器(7)有一个多级拓扑结构。
ELE和IUT电压状态
ELE(1)用于提供ELE输出电压VELE，其中每个IUT电压状态(2s)对应一个基本相等的ELE电压状态(1s)，从而使连接ELE输出端(9)和IUT输出端(10)的耦合滤波器(4)上的电压可以基本抵消。优选地，ELE(1)用于提供ELE输出电压VELE，其中不同ELE电压状态的数量与不同IUT电压状态的数量相同。
ELE(1)可以包括一个多级ELE逆变器，该多级逆变器适合于提供更多不同的ELE电压状态(1s)，而不是更多不同的IUT电压状态(2s)。在这种情况下，ELE(1)可以用于命令开关单元(7s)只提供较少数量的ELE电压状态(1s)，其中，较少数量的ELE电压状态中的每个ELE电压状态基本上等于不同的IUT电压状态(2s)中的一个。
耦合滤波器(4)
如图2和3所示，ELE(1)包括一个连接ELE输出端(9)和IUT输出端(10)的耦合滤波器(4)。本发明的ELE的耦合滤波器(4)可以包括一个或多个相位，各相位之间最好没有交叉耦合。耦合滤波器(4)的每一相至少包括一个串联的电感LF，最好是只有串联的电感LF。优选的是，耦合滤波器(4)的每一相只包括串联的元件，如图3所示，这样穿过耦合滤波器的滤波电流IF等于从IUT输出端(10)流出的IUT输出电流 IIUT和进入ELE输出端(9)的ELE输出电流IELE。
控制单元(6)
ELE(1)的控制单元(6)用于根据表示测量的IUT的输出电压VIUT的电压感应单元输出信号来确定与仿真电负荷相对应的参考电流IREF。例如，仿真电负载可以是一个电机或一个电力网络。ELE(1)可以包括仿真电负载的模型，例如，用于确定仿真电机的相电流与仿真电机的相电压的关系的电机模型。在这种情况下，仿真电机的相电流是计算出的参考电流IREF，而仿真电机的相电压是测量的IUT输出电压VIUT。优选地，ELE(1)中的控制单元(6)用于以第二频率F2周期性地确定参考电流IREF。优选地，第二频率F2等于第一频率F1。进一步优选地，第二频率F2可以是IUT的开关频率的三分之一至300MHz之间，进一步优选地，在IUT的开关频率和100MHz之间，进一步优选地，在2到50MHz之间，进一步优选地，在3到10MHz之间。
在本发明的ELE的一个例子中，控制单元(6)包括一个离散时间计算电路，该离散时间计算电路用于接收电压感应单元的输出信号，并周期性地以第二频率F2确定参考电流IREF。在本发明的ELE中，这可以与IUT输出端上的IUT电压状态的变化异步实现。
论文《IEEETRANSACTIONSONPOWERELECTRONICS》的VOL.33,NO.8,AUGUST2018,pp.6926-6935(数字对象识别器10.1109/TPEL.2017.2759662)描述了电压感应技术的例子，这些技术可以在本发明中实现对IUT输出电压UIUT的传感。
ELE(1)中的控制单元(6)还用于将参考电流IREF与测量的IUT输出电流IIUT进行比较，最好是周期性地以第三频率F3进行比较。优选地，控制单元(6)用于将参考电流IREF的最新值与IUT输出电流IIUT的瞬时值进行比较。参考电流IREF的最新值由控制单元(6)确定；IUT输出电流IIUT的瞬时值由电流传感器(3)测量。优选地，第三频率F3低于或等于第二频率F2。进一步优选地，第三频率F3在100Hz和100MHz之间，进一步优选地在1kHz和20MHz之间，进一步优选地在10kHz和10MHz之间，进一步优选地在1MHz和5MHz之间。进一步优选地，第三频率F3高于IUT的开关频率、或高于IUT刷新IUT输出电流目标的频率。
IREF基本上等于IIUT
如果IREF基本等于IIUT，则控制单元(6)可以进入电压跟随模式，即控制ELE输出 电压VELE同步跟随IUT输出电压VIUT，从而使两个后续IUT电压状态之间的每个IUT上升沿和/或下降沿分别跟随两个后续ELE电压状态之间的相对应的ELE上升沿和/或下降沿。图4说明了ELE的这种操作模式的一个例子。在这个例子中，电流传感器(3)测量IUT的输出电流IIUT，并与控制单元(6)在时间瞬时Ti1、Ti2、Ti3、Ti4所计算的参考电流IREF相比较。在这种情况下，IREF基本上等于IIUT，并且控制单元(6)用于命令ELE逆变器(7)的ELE开关单元(7s)以ELE输出电压同步跟随IUT输出电压，即，ELE(1)用于在每个时间瞬间将ELE电压状态的ELE输出电压VELE设置为基本上等于正在进行的IUT电压状态。换句话说，ELE用于以ELE输出电压VELE跟踪IUT输出电压VIUT，方法是将VELE同步设置在ELE电压状态中的一个，该状态基本上等于正在进行的IUT电压状态。这在图4中有说明，其中，在时间瞬间Tf1，IIUT从一个高的IUT电压状态切换到一个低的IUT电压状态，该状态被ELE的电压感应单元检测到，并且ELE用于分别从相应的高ELE电压状态同步切换到相应的低ELE电压状态，其中高ELE电压状态和低ELE电压状态基本上等于它们相应的高IUT电压状态和低IUT电压状态。
如果IREF基本上等于IIUT，控制单元(6)用于控制VELE所采取的ELE电压状态同步跟随VIUT所采取的IUT电压状态。在这种情况下，每个IUT电压状态和其同步跟随的ELE电压状态被表示为"相对应"。同样，如果IREF基本上等于IIUT，控制单元(6)用于控制VELE所采取的ELE上升沿和下降沿分别同步地跟随IIUT采取的IUT上升沿和下降沿。在这种情况下，每个IUT的上升沿或下降沿和其同步跟随的ELE上升沿或下降沿被表示为"相对应"。
图3表示耦合滤波器的单相与IUT的一个相位和ELE的一个相位相连。当IREF基本等于IIUT时，由VELE采取的ELE电压状态同步跟随由VIUT采取的IUT电压状态。这导致VIUT≈VELE，并且滤波器电压(VF＝VIUT-VELE)基本上在所有时间都被抵消，并且滤波器电流IF基本上保持不变。在本发明的一个例子中，耦合滤波器(4)只包括一个串联的电感LF，其中电感LF的寄生电阻RP最好可以忽略不计。在这种情况下，VF＝RP*IIUT+LF*dIIUT/dt≈LF*dIIUT/dt≈0，因此dIIUT/dt＝0。
控制单元的离散和连续操作
为了在ELE处于电压跟随模式时尽量减少IUT和ELE上升沿之间的寄生时间的延迟，控制单元(6)可以包括一个连续时间逻辑单元，该逻辑单元用于接收电压感应单元输 出信号，其中电压感应单元输出信号是代表IUT上升沿和下降沿的连续沿检测信号，IUT上升沿和下降沿由电压感应单元(5)检测。例如，连续时间逻辑单元可以用于根据连续沿检测信号控制ELE逆变器和ELE输出电压VELE以同步跟随IUT输出电压VIUT。例如，连续时间逻辑单元可以是一个在时间上连续运行的仿真电路，如EPROM或FPGA，而电压感应单元的输出信号可以由感应单元中的比较器产生，该比较器也在时间上连续运行。与使用(例如)离散时间控制电路相比，使用连续时间逻辑电路与比较器相结合，可以最大限度地减少与ELE中的感应和控制有关的寄生延迟。
一般来说，边缘检测比实际的电压幅度测定或测量快得多，根据边缘检测信号控制ELE逆变器(7)复制IUT输出信号比根据电压幅度测量值快得多。
例如，本发明的ELE可以包括用于跟踪或快速复制IUT输出信号的连续时间逻辑电路，并与反应较慢的离散时间控制电路相结合，离散时间控制电路用于确定参考电流IREF。
IREF高于IIUT
如果IREF高于IIUT，如图5所示，则控制单元(6)用于相对于其相应的IUT上升沿(2r)而言，将后续的ELE上升沿延迟一个上升沿时间。在目前情况下，后续的ELE上升沿是在测量的IUT输出电流与参考电流比较后出现的ELE上升沿，控制单元(6)则计算出要应用的上升沿时间延迟。优选地，ELE(1)用于将参考电流IREF与测量的IUT输出电流IIUT进行比较，并以第三频率F3周期性计算上升沿或下降沿的时间延迟。在图5的例子中，控制单元(6)将IREF与IIUT进行比较，并计算出应用在时间Ti1、Ti2、Ti3、Ti4的上升沿的时间延迟。优选地，如图5所示，控制单元(6)用于相对于其相应的IUT上升沿(2r)延迟首次出现的ELE上升沿(1r)，以便IUT输出电流被快速调整至接近参考电流。当然，技术人员应很容易认识到，图5中表示的电压和电流信号是理想化的信号，并不限制本发明的范围。在实际情况下，由VIUT和VELE组成的这些信号可能包括噪声、波纹，而且IUT和ELE的上升沿和下降沿具有有限的斜率，这在图5中没有显示。图5中也没有显示寄生延迟。
如果IREF高于IIUT，则控制单元(6)优选地用于控制ELE输出电压VELE同步跟随IUT输出电压VIUT，如同在IREF＝IIUT的情况下，除了ELE上升沿(1r)相对于其相应的IUT上升沿(2r)被上升沿时间延迟。延迟的ELE上升沿(1r)是在控制单元(6)进行比较产生结果 IREF>IIUT后出现的，最好是在控制单元(6)进行比较后第一次出现的ELE上升沿(1r)。在本文中，如果ELE处于电压跟踪模式，相应的ELE上升沿(1r)是可能与IUT上升沿(2r)同步出现的ELE上升沿。
在ELE和IUT的上升沿之间的上升沿时间延迟的期间，IUT输出电压因此采取一个IUT电压状态，其电压高于ELE输出电压所采取的ELE电压状态，且滤波器电压VF为正，IUT输出电流IIUT增加。在这种情况下，以及在本发明的例子中，其中耦合滤波器(4)只包括一个串联的电感LF，并且电感LF的寄生电阻RP可以忽略不计，VF≈LF*dIIUT/dt，并且dIIUT/dt>0，因为VF是正的。在这种情况下，控制单元(6)最好用于相对于其相应的IUT上升沿(2r)，将随后的ELE上升沿(1r)延迟一个上升沿时间Δt＝LF*│IREF-IIUT│/│VELE-VIUT│。其中│IREF-IIUT│是参考电流和测量的IUT电流之差的绝对值，其中│VELE-VIUT│是ELE和IUT输出电压之差的绝对值，即在下面的ELE上升沿(1r)和其相应的IUT上升沿(2r)之间的时间延迟Δt期间，│VELE-VIUT│是ELE和IUT电压状态相关的电压之间的绝对值。
IREF低于IIUT
如果IREF低于IIUT，则控制单元(6)用于相对于其相应的IUT下降沿(2f)而言，将后续的ELE下降沿之一延迟一个下降沿时间，如图6所示。优选地，ELE(1)用于将参考电流IREF与测量的IUT输出电流IIUT进行比较，并计算出上升沿或下降沿时间延迟，上升沿或下降沿时间延迟在第三频率F3下周期性应用。在本文中，后续的ELE下降沿是在测量的IUT输出电流与参考电流比较之后发生的ELE下降沿，并且由控制单元(6)计算要应用的下降沿的时间延迟。在图6的例子中，控制单元(6)将IREF与IIUT进行比较，并计算在Ti1、Ti2、Ti3、Ti4时间所应用的下降沿的时间延迟。优选地，控制单元(6)用于相对于其相应的IUT下降沿(2f)来延迟首次显示的ELE下降沿(1f)，如图6所示，以便IUT输出电流被迅速调整到接近参考电流。当然，技术人员应很容易认识到，图6中表示的电压和电流信号是理想化的信号，并不限制本发明的范围。在实际情况下，由VIUT和VELE组成的这些信号可能包括噪声、波纹，而且IUT和ELE的上升沿和下降沿具有有限的斜率，这在图6中没有显示。图6中也没有显示寄生延迟。
如果IREF低于IIUT，控制单元(6)最好用于控制ELE输出电压VELE，使其与IREF＝IIUT 情况下的IUT输出电压VIUT同步，除了ELE的下降沿(1f)相对于其相应的IUT的下降沿(2r)来说，被下降沿时间延迟了。延迟的ELE下降沿(1f)是在控制单元(6)比较产生结果IREF<IIUT之后发生的，在ELE和IUT下降沿之间的这个下降沿时间延迟期间，IUT输出电压因此采取了一个IUT电压状态，其电压低于ELE输出电压采取的ELE电压状态，且滤波器电压VF为负，IUT输出电流IIUT减少。在这种情况下，以及在本发明的例子中，其中耦合滤波器(4)只包括一个串联的电感LF，并且电感LF的寄生电阻RP可以忽略不计，VF≈LF*dIIUT/dt，并且dIIUT/dt<0，因为VF是负的。在这种情况下，控制单元(6)最好用于相对于其相应的IUT下降沿(2f)，将随后的ELE下降沿(1f)延迟一个下降沿时间Δt＝LF*│IREF-IIUT│/│VELE-VIUT│。其中│IREF-IIUT│是参考电流和测量的IUT电流之差的绝对值，其中│VELE-VIUT│是ELE和IUT输出电压之差的绝对值，即在下面的ELE下降沿(1f)和其相应的IUT下降沿(2f)之间的时间延迟Δt期间，│VELE-VIUT│是ELE和IUT电压状态相关的电压之间的绝对值。
在解释从属权利要求时，应当理解"包括"一词并不排除存在除特定权利要求中所列的元素或行为之外的其他元素或行为；在一个元素前面的"a"或"an"一词并不排除多个此类元素的存在；权利要求中的任何参考符号并不限制其范围；若干"手段"可由相同或不同的项目或可实施的结构或功能表示；除非特别说明，任何公开的装置或其部分可以一起组合或分离成进一步的部分。当一项权利要求提及另一项权利要求时，这可能表明通过结合各自的特征而可以实现协同优势。但是，仅仅是在相互不同的权利要求中叙述了某些措施这一事实，并不表明这些措施的组合也不能被用来发挥优势。因此，本实施例可以包括权利要求的所有工作组合，其中每项权利要求原则上可以指任何前面的权利要求，除非被上下文明确排除。
虽然本发明在下文中参照具体实施例进行了描述，但这是为了明确而不是限制本发明。技术人员需要明白，在不偏离本发明范围的情况下，对所披露的特征进行各种修改和不同组合是可能的。
附图标记

Claims (8)

  1. 一种用于被测逆变器(IUT)(2)的电负载仿真器(ELE)(1)，其中，在IUT输出端的IUT输出电压VIUT用于采取多个IUT电压状态，所述多个IUT电压状态由IUT的上升沿和下降沿分开，而在ELE输出端的ELE输出电压用于采取多个ELE电压状态，所述多个ELE电压状态由ELE的上升沿和下降沿分开，而其中每个IUT电压状态对应于至少一个ELE电压状态，并且其中ELE包括：
    -电流传感器(3)，用于测量IUT的输出电流IIUT；
    -耦合滤波器(4)，用于连接ELE和IUT；
    -电压感应单元(5)，用于感应IUT的输出电压VIUT；
    -控制单元(6)，用于：根据感知的IUT输出电压VIUT，来确定对应于仿真电负载的参考电流IREF；比较参考电流IREF和测量的IUT输出电流IIUT；
    其特征在于，
    如果IREF基本等于IIUT，则控制单元(6)用于控制ELE输出电压同步跟随IUT输出电压，从而使两个后续IUT电压状态之间的每个IUT上升沿和/或下降沿分别跟随两个后续ELE电压状态之间的相应的ELE上升沿和/或下降沿；
    如果IREF高于IIUT，则控制单元(6)用于则相对于其相应的IUT上升沿而言，将后续的ELE上升沿延迟一个上升沿时间；
    如果IREF低于IIUT，则控制单元(6)用于相对于其相应的IUT下降沿而言，将后续的ELE下降沿延迟一个下降沿时间。
  2. 根据权利要求1所述的ELE，其中耦合滤波器(4)的每一相至少包括一个串联电感LF，最好只有串联电感LF。
  3. 根据权利要求1或2所述的ELE，包括一个ELE逆变器(7)，所述逆变器(7)具有两级拓扑结构或多级拓扑结构。
  4. 根据前述任意项权利要求所述的ELE，其中，ELE逆变器(7)用于由一个与IUT(2)共享的直流电源(8)提供。
  5. 根据前述任一项权利要求所述的ELE，其中，控制单元(6)用于：
    -根据测量的IUT输出电压VIUT，确定对应于仿真电负载的参考电流IREF；
    -将参考电流IREF与测量的IUT输出电流IIUT进行比较，并计算与IUT输出电压VIUT异步的上升沿或下降沿的时间延迟。
  6. 根据前述任一项权利要求所述的ELE，其中，控制单元(6)用于：
    -根据在第二频率F2下周期性测量的IUT输出电压VIUT，确定对应于仿真电负载的参考电流IREF，其中，第二频率F2优选在IUT的开关频率的三分之一和300MHz之间，进一步优选在IUT的开关频率和100MHz之间，优选在2MHz和50MHz之间，优选在3MHz和10MHz之间；
    -将参考电流IREF与测量的IUT输出电流IIUT进行比较，并周期性以第三频率F3计算上升沿或下降沿的时间延迟，其中第三频率F3优选低于或等于第二频率F2，并且其中第三频率F3优选在100Hz和100MHz之间，优选在1kHz和20MHz之间，优选在10kHz和10MHz之间，优选在1MHz和5MHz之间。
  7. 根据前述任意项权利要求的一种控制电负载仿真器(ELE)(1)的方法，用于测试被测逆变器(IUT)(2)，其中在IUT输出端的IUT输出电压VIUT用于采取多个IUT电压状态，所述多个IUT电压状态由IUT上升沿和下降沿分开，所述方法包括:
    -在IUT输出端感应IUT的输出电压VIUT；
    -根据感知的IUT输出电压VIUT，确定与仿真电负载相对应的参考电流IREF；
    -测量IUT的输出电流IIUT；
    -将参考电流IREF与测量的IUT输出电流IIUT进行比较；
    -如果IREF基本等于IIUT，则控制ELE输出电压同步跟随IUT输出电压VIUT，从而使两个后续IUT电压状态之间的每个IUT上升沿和/或下降沿分别跟随两个后续ELE电压状态之间的相应的ELE上升沿和/或下降沿；
    -如果IREF高于IIUT，则相对于其相应的IUT上升沿而言，将后续的ELE上升沿延迟一个上升沿时间；
    -如果IREF低于IIUT，则相对于其相应的IUT下降沿而言，将后续的ELE下降沿延迟一个下降沿时间。
  8. 一种用于控制电负载仿真器(ELE)的可编程硬件，电负载仿真器(ELE)用于测试被测逆变器(IUT)，所述可编程硬件用于使ELE执行根据权利要求7所述的方法，其中，所述可编程硬件是一种可编程逻辑装置，如FPGA、EPROM或微控制器。
PCT/CN2023/076140 2022-06-09 2023-02-15 用于被测逆变器的电负载仿真器 WO2023236579A1 (zh)

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