WO2023236537A1 - 发光芯片组件、显示面板、显示装置及制备方法 - Google Patents

发光芯片组件、显示面板、显示装置及制备方法 Download PDF

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Publication number
WO2023236537A1
WO2023236537A1 PCT/CN2023/071783 CN2023071783W WO2023236537A1 WO 2023236537 A1 WO2023236537 A1 WO 2023236537A1 CN 2023071783 W CN2023071783 W CN 2023071783W WO 2023236537 A1 WO2023236537 A1 WO 2023236537A1
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WO
WIPO (PCT)
Prior art keywords
light
emitting
line
electrode
semiconductor layer
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PCT/CN2023/071783
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English (en)
French (fr)
Inventor
王斌
萧俊龙
范春林
汪庆
周睿
Original Assignee
重庆康佳光电技术研究院有限公司
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Publication of WO2023236537A1 publication Critical patent/WO2023236537A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a light-emitting chip component, a display panel, a display device and a preparation method.
  • Micro Light Emitting Diode (English: Micro Light Emitting Diode, abbreviated as: Micro LED) is an emerging display technology with the characteristics of fast response speed, autonomous emission, high contrast, long service life, and high photoelectric efficiency.
  • Micro LED chips are first prepared on the growth substrate, and then the Micro LED chips are transferred from the growth substrate to the backplane. Therefore, how to improve the transfer yield is an urgent problem that needs to be solved.
  • the purpose of this application is to provide a light-emitting chip component, a display panel, a display device and a preparation method, aiming to solve the problem of improving transfer yield.
  • a light-emitting chip component including:
  • a plurality of light-emitting units each of which is arranged at intervals on the substrate, and the light-emitting units include a first semiconductor layer, a light-emitting layer and a second semiconductor layer that are stacked in sequence;
  • a first electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer
  • the second electrode line includes an interconnection line and a contact line, the interconnection line is electrically connected to the contact line; wherein at least part of the first semiconductor of the light-emitting unit is provided with the contact line, and is provided with a certain Each of the light-emitting units of the contact line is interconnected through the interconnection line.
  • the above-mentioned light-emitting chip assembly includes a substrate, a plurality of light-emitting units, first electrodes and second electrode lines. Each light-emitting unit is arranged at intervals on the substrate.
  • the light-emitting unit includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer that are stacked in sequence. layer,
  • the first electrode is disposed on the second semiconductor layer and is electrically connected to the second semiconductor layer.
  • the second electrode line includes an interconnection line and a contact line. The interconnection line and the contact line are electrically connected. At least part of the first semiconductor surrounding the light-emitting unit A contact line is provided, and each light-emitting unit provided with the contact line is interconnected through an interconnection line.
  • the second electrode line is used to connect multiple light-emitting units into one, forming a stable structure.
  • the multiple light-emitting units can maintain a fixed size gap and restrain each other, thereby improving the stability of the light-emitting unit and reducing the gap between the actual position and the ideal position of the light-emitting unit. deviation, thereby improving the transfer yield of the light-emitting unit.
  • the present application also provides a display panel, including a backplane provided with a plurality of first electrode lines and a plurality of the light-emitting chip components provided above, each of the first electrode lines and a plurality of the above-mentioned light-emitting chip assemblies.
  • the corresponding first electrodes in the light-emitting chip assembly are connected.
  • a plurality of first electrode lines are provided on the back panel.
  • Each first electrode line is connected to a corresponding first electrode in a plurality of light-emitting chip assemblies.
  • the light-emitting unit can be selected through the first electrode line and the second electrode line. Perform composite luminescence.
  • the present application also provides a display device, including a driving circuit and the display panel provided above.
  • the driving circuit is connected to the first electrode line and the second electrode line respectively.
  • the above display device is connected to the first electrode line and the second electrode line respectively through the driving circuit, and can automatically select and control the light-emitting unit to emit composite light.
  • this application also provides a method for preparing a light-emitting chip assembly, including:
  • An isolation trench extending to the substrate is opened on the second semiconductor layer to form a plurality of light-emitting units spaced apart from each other;
  • a second electrode line is formed on the substrate, the second electrode line includes an interconnection line and a contact line, the interconnection line is electrically connected to the contact line; wherein at least part of the first semiconductor of the light-emitting unit
  • the contact lines are arranged around, and each of the light-emitting units provided with the contact lines are interconnected through the interconnection lines.
  • the above-mentioned preparation method of the light-emitting chip component first forms a first semiconductor layer, a light-emitting layer, and a second semiconductor layer on a substrate in sequence, and then opens an isolation trench extending to the substrate on the second semiconductor layer to form a plurality of spaced-apart light-emitting units. , and prepare a first electrode on the second semiconductor layer, and form a second electrode line on the substrate.
  • the second electrode line includes an interconnection line and a contact line, and the interconnection line and the contact line are electrically connected; wherein, at least part of the light-emitting unit Contact lines are provided around the first semiconductor, and each light-emitting unit provided with the contact lines is interconnected through the interconnection lines.
  • Multiple light-emitting units are connected together through second electrode lines to form a stable structure.
  • the multiple light-emitting units can maintain a fixed size gap and restrain each other, thereby improving the stability of the light-emitting unit and reducing the gap between the actual position and the ideal position of the light-emitting unit. deviation, thereby improving the transfer yield of the light-emitting unit.
  • this application also provides a method for preparing a display panel, including:
  • the light-emitting unit peeled off from the backplane is bonded to the backplane, so that the first electrode line is connected to the first electrode in the light-emitting unit.
  • the above method for preparing a display panel provides a backplane provided with first electrode lines and a light-emitting chip assembly.
  • the light-emitting chip assembly includes a substrate, a plurality of light-emitting units, first electrodes and second electrode lines. Each light-emitting unit is spaced on the substrate. Arranged, the light-emitting unit includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer that are stacked in sequence. The first electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer.
  • the second electrode line includes an interconnection The circuit and the contact circuit, the interconnection circuit and the contact circuit are electrically connected, at least part of the first semiconductor of the light-emitting unit is provided with a contact circuit, and each light-emitting unit provided with the contact circuit is interconnected through the interconnection circuit, which is a light-emitting unit While disposing the second electrode, the second electrode lines are used to connect the plurality of light-emitting units into one body to form a stable structure. Control the alignment of the light-emitting chip assembly with the backplane, and peel off the light-emitting unit with the contact line from the light-emitting chip assembly.
  • a fixed size gap can be maintained between the multiple light-emitting units and they can restrain each other, which can improve the efficiency of the light-emitting unit. Stability reduces the deviation between the actual position where the light-emitting unit falls and the ideal position, thereby improving the transfer yield of the light-emitting unit.
  • Figure 1 is a cross-sectional view of a light-emitting chip assembly in an embodiment of the present application
  • Figure 2 is a top view of a light-emitting chip assembly in an embodiment of the present application
  • Figure 3 is a schematic diagram of a contact circuit in an embodiment of the present application.
  • Figure 4 is a schematic diagram of a contact circuit in an embodiment of the present application.
  • Figure 5 is a schematic diagram of a contact circuit in an embodiment of the present application.
  • Figure 6 is a cross-sectional view of a light-emitting chip assembly in an embodiment of the present application.
  • Figure 7 is a top view of a display panel in an embodiment of the present application.
  • Figure 8 is a flow chart of a method for manufacturing a light-emitting chip component in an embodiment of the present application
  • Figure 9 is a schematic structural diagram of the light-emitting chip assembly after step S802 is executed in an embodiment of the present application.
  • Figure 10 is a schematic structural diagram of the light-emitting chip assembly after step S804 is executed in an embodiment of the present application;
  • Figure 11 is a schematic structural diagram of the light-emitting chip assembly after step S806 is executed in an embodiment of the present application;
  • Figure 12 is a schematic structural diagram of the light-emitting chip assembly after step S808 is executed in an embodiment of the present application;
  • Figure 13 is a schematic structural diagram of the light-emitting chip assembly after covering the reinforcing structure in an embodiment of the present application
  • FIG. 14 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present application.
  • the Micro LED chip is first prepared on the growth substrate, and then the Micro LED chip is aligned with the backplane, and a laser is used to peel the Micro LED chip from the growth substrate.
  • the Micro LED chip falls on the growth substrate under the action of gravity.
  • the backplane is bonded to the backplane to transfer the Micro LED chip from the growth substrate to the backplane.
  • Micro LED chips are prone to positional deviation during the free fall process, causing the actual position of the Micro LED chip to fall on the backplane to deviate from the ideal position, affecting the transfer yield of Micro LED chips.
  • the present application provides a light-emitting chip assembly 100 , which includes a substrate 10 , a plurality of light-emitting units 20 , a first electrode 30 and a second electrode line 40 .
  • Each light-emitting unit 20 is arranged at intervals on the substrate 10 .
  • the light-emitting unit 20 includes a first semiconductor layer 21 , a light-emitting layer 22 and a second semiconductor layer 23 that are stacked in sequence.
  • the first electrode 30 is provided on the second semiconductor layer 23 and is electrically connected to the second semiconductor layer 23 .
  • the second electrode line 40 includes an interconnection line 41 and a contact line 42, and the interconnection line 41 and the contact line 42 are electrically connected. At least some of the light-emitting units 20 are provided with contact lines 42 around the first semiconductor 21 , and each light-emitting unit 20 provided with the contact lines 42 is interconnected through the interconnection lines 41 .
  • the above-mentioned light-emitting chip assembly includes a substrate 10, a plurality of light-emitting units 20, a first electrode 30 and a second electrode line 40. Each light-emitting unit 20 is arranged at intervals on the substrate 10.
  • the light-emitting unit 20 includes a first semiconductor layer stacked in sequence. 21.
  • the first electrode 30 is provided on the second semiconductor layer 23 and is electrically connected to the second semiconductor layer 23.
  • the second electrode line 40 includes an interconnection line 41 and a contact line 42.
  • the interconnection line 41 is electrically connected to the contact line 42.
  • At least part of the first semiconductor 21 of the light-emitting unit 20 is provided with a contact line 42 around the first semiconductor 21, and each light-emitting unit 20 provided with the contact line 42 is interconnected through the interconnection line 41.
  • the second electrode lines 40 are used to connect the plurality of light-emitting units 20 into one body to form a stable structure. In this way, during the process of the light-emitting unit 20 falling from the substrate 10, the multiple light-emitting units 20 can maintain a fixed size gap and restrain each other, thereby improving the stability of the light-emitting unit 20 and reducing the actual risk of the light-emitting unit 20 falling. The deviation between the position and the ideal position further improves the transfer yield of the light-emitting unit 20 .
  • the substrate 10 includes but is not limited to a sapphire substrate for supporting and providing a surface for epitaxial growth to form the first semiconductor layer 21 , the light-emitting layer 22 and the second semiconductor layer 23 .
  • the first semiconductor layer 21 includes, but is not limited to, an N-type doped GaN layer, used to provide electrons for recombination luminescence;
  • the second semiconductor layer 23 includes, but is not limited to, a P-type doped GaN layer, used to provide holes for recombination luminescence.
  • the light-emitting layer 22 includes a plurality of alternately stacked quantum wells and quantum barriers.
  • the quantum wells include but are not limited to undoped InGaN layers.
  • the quantum barriers include but are not limited to undoped GaN layers.
  • the quantum barriers confine electrons and holes to Recombination light emission occurs in the quantum well.
  • the first electrode 30 includes but is not limited to Ni layer, Ag layer, etc.
  • the second electrode line 40 includes but is not limited to Cr layer, Ni layer, Au layer, etc.
  • the first electrode 30 and the second electrode line 40 are used to provide light to the light-emitting unit 20 A current is injected to drive electrons and holes into the light-emitting layer 22 .
  • the number of contact lines 42 is less than or equal to the number of light-emitting units 20 .
  • the number of contact lines 42 is less than the number of light-emitting units 20, some of the light-emitting units 20 are provided with contact lines around them. There is no contact line 42 around the other part of the light-emitting unit 20 .
  • the light-emitting unit 20 with contact lines 42 around it can be placed adjacent to the light-emitting unit 20 with contact lines 42 around it, or it can be placed adjacent to the light-emitting unit 20 without contact lines 42 around it, or it can also be placed adjacent to the light-emitting unit 20 with contact lines 42 around it.
  • the light-emitting units 20 of the line 42 and the light-emitting units 20 that are not in contact with the line 42 are arranged adjacent to each other.
  • the light-emitting units 20 with contact lines 42 around them are arranged in a row or a column, and the light-emitting units 20 without contact lines 42 around them are also arranged in a row or a column, and the light-emitting units 20 with contact lines 42 around them are not connected with the surrounding ones.
  • the light-emitting units 20 contacting the circuit 42 are arranged side by side or staggered.
  • the light-emitting units 20 with contact lines 42 around them and the light-emitting units 20 without contact lines 42 around them are arranged in a row or a column, and are arranged separately or alternately along the row or column direction. This layout is compact and saves space.
  • each light-emitting unit 20 is provided with contact lines 42 around it.
  • the light-emitting chip assembly 100 further includes a buffer layer 50.
  • the buffer layer 50 is disposed between the substrate 10 and the plurality of light-emitting units 20, that is, the buffer layer 50 is laid on the substrate 10.
  • a plurality of light emitting units 20 are arranged on the buffer layer 50 at intervals.
  • the buffer layer 50 includes but is not limited to an undoped GaN layer, which is used to alleviate the lattice mismatch caused by the epitaxial growth of the heterogeneous substrate and improve the crystal quality of the first semiconductor layer 21 .
  • each light-emitting unit 20 has a step 24 extending from the substrate 10 to the first semiconductor layer 21 , and the contact line 42 extends to the step 24 and does not contact the light-emitting layer 22 .
  • each light-emitting unit 20 has a step 24 extending from the substrate 10 to the first semiconductor layer 21 , so that the contact line 42 can extend to the step 24 , thereby increasing the contact between the contact line 42 and the light-emitting unit 20
  • the area and the strength of the contact line 42 are helpful for the contact line 42 to limit the movement of the light-emitting unit 20 and improve the stability of the light-emitting unit 20 .
  • the contact line 42 extending onto the step 24 includes a ring line arranged along the edge of the first semiconductor layer 21 .
  • the contact lines 42 extending to the step 24 include at least two strip lines, and the at least two strip lines are spaced apart along the edge of the first semiconductor layer 21 .
  • the first semiconductor layer 21 includes a first straight side A, a second straight side B, a third straight side C and a fourth straight side D connected in sequence, and two strip lines are respectively provided on the first straight side A and the fourth straight side.
  • the extension direction of side C is parallel (not shown).
  • the two strip lines can also be disposed on the second straight side B and the fourth straight side D respectively, and are perpendicular to the extension directions of the second straight side B and the fourth straight side D (such as As shown in Figure 4), or the extension of two strip lines parallel to the extension direction of the second straight side B and the fourth straight side D (not shown in the figure).
  • the four strip lines may be respectively disposed on the first straight side A, the second straight side B, the third straight side C and the fourth straight side C.
  • the straight side D (as shown in Figure 5), and perpendicular to the extension direction of the respective straight sides.
  • the arrangement of the above-mentioned strip lines increases the contact area between the contact lines 42 and the light-emitting units 20, improves the strength of the contact lines 42, and improves the stability during the subsequent large-volume transfer of the above-mentioned light-emitting units 20.
  • the interconnection line 41 includes a main line 411 and a plurality of branch lines 412 .
  • the plurality of branch lines 412 correspond to a plurality of contact lines 42 one-to-one.
  • the two ends of each branch line 412 They are respectively connected to the corresponding contact lines 42 and the main line 411, that is, one end of each branch line 412 is connected to the corresponding contact line 42, and the other end is connected to the main line 411.
  • the interconnection line 41 is composed of a main line 411 and a plurality of branch lines 412, which facilitates wiring on the substrate 10 and enables multiple light-emitting units 20 to be integrated and spaced apart from each other.
  • multiple branch lines 412 are parallel to each other, and the main line 411 and the branch lines 412 are perpendicular to each other, which can minimize the length and difficulty of wiring while achieving electrical connection.
  • the contact line 42 is a ring line.
  • the shape of the contact line 42 is consistent with the orthographic projection shape of the light emitting unit 20 on the substrate 10 .
  • the contact line 42 is in the shape of a square ring.
  • the contact line 42 will be circular.
  • the orthographic projection shape of the first electrode 30 on the second semiconductor layer 23 is consistent with the shape of the contact line 42, so that the distance between the first electrode 30 and the second electrode line 40 is the same in all directions, which is conducive to uniform current injection.
  • the light-emitting unit 20 improves the uniformity of the composite light emitted by the light-emitting unit 20. For example, if the contact line 42 is in the shape of a square ring, then the orthographic projection shape of the first electrode 30 on the second semiconductor layer 23 is a rectangle. For another example, if the contact line 42 is in the shape of a circular ring, then the orthographic projection shape of the first electrode 30 on the second semiconductor layer 23 is circular.
  • an end of the interconnection line 41 away from the contact line 42 is provided with a pad 43 . Since the bonding pad 43 is provided at an end of the interconnection line 41 away from the contact line 42, the bonding pad 43 is located in an area far away from the light-emitting unit 20. A large area of the bonding pad 43 can be designed in this area, thereby improving the reliability of welding and reducing the alignment accuracy. .
  • the light-emitting chip assembly 100 further includes a reinforcing structure 60 , which is disposed at least between two adjacent light-emitting units 20 and covers the second electrode line 40 .
  • a reinforcing structure 60 is added on the second electrode line 40 between two adjacent light-emitting units 20 .
  • the reinforcing structure 60 can cooperate with the second electrode line 40 to block the opposite direction between the two adjacent light-emitting units 20 . Movement to further improve the stability of the light emitting unit 20 .
  • the reinforcing structure 60 can fix and support the second electrode line 40 , especially after the light-emitting unit 20 is peeled off from the substrate 10 .
  • the reinforcing structure 60 covers the substrate 10 and surrounds a plurality of opening areas 61 , and the light-emitting units 20 are disposed in the opening areas 61 .
  • the reinforcing structure 60 forms a plurality of opening areas 61 on the substrate 10, and the light-emitting unit 20 is disposed in the opening area 61.
  • the light-emitting unit 20 is completely surrounded by the reinforcing structure 60, and the stability is optimized.
  • the reinforcing structure 60 is formed of polymer material.
  • the reinforcing structure 60 is black glue material.
  • the reinforcing structure 60 is made of black plastic material, which has the effect of reducing pixel crosstalk.
  • the present application also provides a display panel.
  • the display panel includes a backplane provided with a plurality of first electrode lines 70 and a plurality of light-emitting chip assemblies 100 .
  • Each first electrode line 70 Connected to the corresponding first electrodes 30 in the plurality of light-emitting chip assemblies 100 .
  • the light-emitting chip assembly 100 is the light-emitting chip assembly provided in the above embodiment, and will not be described in detail here.
  • first electrode lines 70 are provided on the back panel.
  • Each first electrode line 70 is connected to the first electrode 30 in the corresponding light-emitting unit 20 in the plurality of light-emitting chip assemblies 100.
  • Through the first electrode lines 70 and the second electrode line 40 can select the light-emitting unit to perform composite light emission.
  • multiple light-emitting chip assemblies 100 are arranged at intervals along the first direction A, and the multiple light-emitting units 20 in each light-emitting chip assembly 100 are arranged at intervals along the second direction B.
  • the second direction B intersects the first direction A.
  • the plurality of light-emitting chip assemblies 100 are arranged at intervals along the first direction A, and the plurality of light-emitting units 20 in each light-emitting chip assembly 100 are arranged at intervals along the second direction B that intersects the first direction A, and emit light.
  • the units 20 are distributed in an array to facilitate layout and wiring of the display panel.
  • the second direction B and the first direction A are perpendicular to each other.
  • each light-emitting chip assembly 100 extends along the second direction B, and each first electrode line 70 extends along the first direction A.
  • the interconnection lines 41 in each light-emitting chip assembly 100 extend along the second direction B, and the plurality of light-emitting units 20 in each light-emitting chip assembly 100 are arranged at intervals along the second direction B to facilitate interconnection.
  • the lines 41 connect each light-emitting unit 20 in the same light-emitting chip assembly 100 into one body.
  • Each first electrode line 70 extends along the first direction A, and cooperates with multiple light-emitting chip assemblies 100 to be arranged at intervals along the first direction A, so as to facilitate connecting a light-emitting unit 20 of different light-emitting chip assemblies 100 to the same first electrode line. 70.
  • the second electrode lines 40 and/or the first electrode lines 70 connected to different light-emitting units 20 are different.
  • any one of the light-emitting units 20 can be selected and controlled to emit composite light.
  • the present application also provides a display device (not shown), which includes a driver
  • the circuit and the display panel, the driving circuit are connected to the first electrode line and the second electrode line respectively.
  • the display panel is the display panel provided in the above embodiment, which will not be described in detail here.
  • the above display device is connected to the first electrode line and the second electrode line respectively through the driving circuit, and can automatically select and control the light-emitting unit to emit composite light.
  • the present application also provides a method for manufacturing a light-emitting chip component, which is suitable for preparing the light-emitting chip component provided in the above embodiment.
  • the preparation method includes the following steps:
  • step S802 a first semiconductor layer, a light-emitting layer, and a second semiconductor layer are sequentially formed on the substrate.
  • step S802 includes: using MOCVD (English: Metal-organic Chemical Vapor Deposition, Chinese: Metal Organic Compound Chemical Vapor Deposition) technology to sequentially grow a first semiconductor layer, a light-emitting layer, and a second semiconductor layer on the substrate.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • Chinese Metal Organic Compound Chemical Vapor Deposition
  • the preparation method further includes: growing a buffer layer on the substrate.
  • step S802 includes: sequentially growing a first semiconductor layer, a light-emitting layer, and a second semiconductor layer on the buffer layer.
  • FIG. 9 is a schematic structural diagram of the light-emitting chip assembly after step S802 is executed.
  • the buffer layer 50 , the first semiconductor layer 21 , the light-emitting layer 22 and the second semiconductor layer 23 are sequentially stacked on the substrate 10 .
  • Step S804 Open isolation trenches extending to the substrate on the second semiconductor layer to form a plurality of light-emitting units spaced apart from each other.
  • step S804 includes: opening isolation trenches extending to the buffer layer on the second semiconductor layer to form a plurality of light-emitting units spaced apart from each other.
  • step S804 includes: using a yellow light process to form a patterned photoresist on the second semiconductor layer; using an etching process to remove the second semiconductor layer, the light-emitting layer, and the first semiconductor layer that are not covered by the photoresist.
  • An isolation trench extending to the buffer layer is formed on the second semiconductor layer to form a plurality of light-emitting units spaced apart from each other; the photoresist is removed.
  • the yellow light process includes: spin-coating the photoresist; exposing the photoresist through a mask; and developing the exposed photoresist to realize patterning of the photoresist.
  • the preparation method further includes: forming a step extending from the substrate to the first semiconductor layer at the edge of each light-emitting unit.
  • a yellow light process and an etching process are used to remove the second semiconductor layer and the light-emitting layer at the edge of each light-emitting unit, so that a step extending from the substrate to the first semiconductor layer can be formed at the edge of each light-emitting unit.
  • FIG. 10 is a schematic structural diagram of the light-emitting chip assembly after step S804 is executed.
  • an isolation trench 80 extending to the buffer layer 50 is opened on the second semiconductor layer 23 to form a plurality of light-emitting units 20 spaced apart from each other.
  • Each light-emitting unit 20 includes a first semiconductor layer sequentially stacked on the buffer layer 40 21.
  • Light emitting layer 22 and second semiconductor layer 23 And the edge of each light-emitting unit 20 has a step 24 extending from the buffer layer 50 to the first semiconductor layer 21 .
  • Step S806 prepare a first electrode on the second semiconductor layer.
  • step S806 includes: using a yellow light process to form a photoresist on the substrate and each light-emitting unit, with an opening extending to the second semiconductor layer in each light-emitting unit provided in the photoresist; using electron beam evaporation
  • the plating technology deposits metal material on the photoresist and in the opening; the photoresist and the metal material on the photoresist are removed, and the metal material in the opening is left to form the first electrode.
  • FIG. 11 is a schematic structural diagram of the light-emitting chip assembly after step S806 is executed. Referring to FIG. 11 , a first electrode 30 is formed on the second semiconductor layer 23 of each light-emitting unit 20 .
  • Step S808 forming a second electrode line on the substrate.
  • the second electrode line includes an interconnection line and a contact line.
  • the interconnection line is electrically connected to the contact line.
  • At least part of the first semiconductor of the light-emitting unit is provided with a contact line around it, and is provided with Each light-emitting unit of the contact line is interconnected through the interconnection line.
  • step S808 includes: using a yellow light process to form a photoresist on the substrate and each light-emitting unit.
  • the photoresist is provided with an opening extending to the substrate.
  • the opening includes a first area provided around each light-emitting unit and Connecting the second areas of each first area; using electron beam evaporation technology to deposit metal material on the photoresist and in the opening; removing the photoresist and the metal material on the photoresist, leaving the metal material in the opening to form a third Two electrode wires.
  • FIG. 12 is a schematic structural diagram of the light-emitting chip assembly after step S808 is executed. Referring to FIG. 12 , a second electrode line 40 is formed on the substrate 10 , and the second electrode line 40 is arranged around the light-emitting unit 20 .
  • the preparation method further includes: covering the reinforcing structure on the substrate.
  • Figure 13 is a schematic structural diagram of the light-emitting chip assembly after covering the reinforcing structure.
  • the reinforcing structure 60 covers the substrate 10 and surrounds a plurality of opening areas 61 , and the light-emitting units 20 are disposed in the opening areas 61 .
  • the above-mentioned preparation method of the light-emitting chip component first forms a first semiconductor layer, a light-emitting layer, and a second semiconductor layer on a substrate in sequence, and then opens an isolation trench extending to the substrate on the second semiconductor layer to form a plurality of spaced-apart light-emitting units. , and prepare a first electrode on the second semiconductor layer, and form a second electrode line on the substrate.
  • the second electrode line includes an interconnection line and a contact line, and the interconnection line and the contact line are electrically connected; wherein, at least part of the light-emitting unit Contact lines are provided around the first semiconductor, and each light-emitting unit provided with the contact lines is interconnected through the interconnection lines.
  • Multiple light-emitting units are connected together through second electrode lines to form a stable structure.
  • the multiple light-emitting units can maintain a fixed size gap and restrain each other, thereby improving the stability of the light-emitting unit and reducing the gap between the actual position and the ideal position of the light-emitting unit. deviation, thereby improving the transfer yield of the light-emitting unit.
  • the present application also provides a method for manufacturing a display panel, which is suitable for preparing the display panel provided in the above embodiment.
  • the preparation method includes the following steps:
  • Step S1402 Provide a backplane and a light-emitting chip assembly provided with first electrode lines.
  • the light-emitting chip assembly includes a substrate, a plurality of light-emitting units and second electrode lines. Multiple light-emitting units are spaced apart from each other. Each light-emitting unit includes a first semiconductor layer, a light-emitting layer, a second semiconductor layer and a first electrode arranged in sequence on the substrate.
  • the second electrode line is provided on the substrate.
  • the second electrode line includes interconnection lines and a plurality of contact lines. Each contact line is disposed around the first semiconductor layer in the corresponding light emitting unit and is connected to the interconnection line.
  • Step S1404 Control the alignment of the light-emitting chip assembly with the backplane, and peel the light-emitting unit provided with the contact line from the light-emitting chip assembly.
  • the first electrode in the light-emitting unit provided with the contact line in the light-emitting assembly is arranged opposite to the first electrode line on the backplane, so that the light-emitting unit provided with the contact line can fall after being peeled off from the light-emitting chip assembly. Bonding is performed on the first electrode wire.
  • step S1406 the light-emitting unit peeled off from the backplane is bonded to the backplane, so that the first electrode line is connected to the first electrode in the light-emitting unit.
  • the first electrode in the light-emitting unit peeled off on the backplane is bonded to the first electrode line on the backplane.
  • An electrical connection is formed between an electrode line.
  • the above method for preparing a display panel provides a backplane provided with first electrode lines and a light-emitting chip assembly.
  • the light-emitting chip assembly includes a substrate, a plurality of light-emitting units, first electrodes and second electrode lines. Each light-emitting unit is spaced on the substrate. Arranged, the light-emitting unit includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer that are stacked in sequence. The first electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer.
  • the second electrode line includes an interconnection The circuit and the contact circuit, the interconnection circuit and the contact circuit are electrically connected, at least part of the first semiconductor of the light-emitting unit is provided with a contact circuit, and each light-emitting unit provided with the contact circuit is interconnected through the interconnection circuit, which is a light-emitting unit While disposing the second electrode, the second electrode lines are used to connect the plurality of light-emitting units into one body to form a stable structure. Control the alignment of the light-emitting chip assembly with the backplane, and peel off the light-emitting unit with the contact line from the light-emitting chip assembly.
  • a fixed size gap can be maintained between the multiple light-emitting units and they can restrain each other, which can improve the efficiency of the light-emitting unit. Stability reduces the deviation between the actual position where the light-emitting unit falls and the ideal position, thereby improving the transfer yield of the light-emitting unit.

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Abstract

本申请涉及一种发光芯片组件、显示面板、显示装置及制备方法。发光芯片组件包括：基板；多个发光单元，各所述发光单元于所述基板上间隔排布，所述发光单元包括依次层叠设置的第一半导体层、发光层和第二半导体层；第一电极，设于所述第二半导体层上，且与所述第二半导体层电连接；以及第二电极线，包括互连线路和接触线路，所述互连线路与所述接触线路电连接；其中，至少部分所述发光单元的第一半导体周围设置有所述接触线路，且设置有所述接触线路的各所述发光单元透过所述互连线路实现互连。

Description

发光芯片组件、显示面板、显示装置及制备方法
相关申请
本申请要求2022年6月6日申请的，申请号为2022106309441，名称为“发光芯片组件、显示面板、显示装置及制备方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本发明涉及半导体技术领域，尤其涉及一种发光芯片组件、显示面板、显示装置及制备方法。
背景技术
微型发光二极管(英文：Micro Light Emitting Diode，简称：Micro LED)是新兴的显示技术，具有响应速度快、自主发光、对比度高、使用寿命长、光电效率高等特点。
在Micro LED的制程中，先在生长基板上制备Micro LED芯片，再将Micro LED芯片从生长基板转移到背板上。因此，如何提高转移良率是亟需解决的问题。
发明内容
鉴于上述现有技术的不足，本申请的目的在于提供一种发光芯片组件、显示面板、显示装置及制备方法，旨在解决转移良率提高的问题。
一种发光芯片组件，包括：
基板；
多个发光单元，各所述发光单元于所述基板上间隔排布，所述发光单元包括依次层叠设置的第一半导体层、发光层和第二半导体层；
第一电极，设于所述第二半导体层上，且与所述第二半导体层电连接；以及
第二电极线，包括互连线路和接触线路，所述互连线路与所述接触线路电连接；其中，至少部分所述发光单元的第一半导体周围设置有所述接触线路，且设置有所述接触线路的各所述发光单元透过所述互连线路实现互连。
上述发光芯片组件，包括基板、多个发光单元、第一电极和第二电极线，各发光单元于基板上间隔排布，发光单元包括依次层叠设置的第一半导体层、发光层和第二半导体层， 第一电极设于第二半导体层上，且与第二半导体层电连接，第二电极线包括互连线路和接触线路，互连线路与接触线路电连接，至少部分发光单元的第一半导体周围设置有接触线路，且设置有接触线路的各发光单元透过互连线路实现互连，在为发光单元设置第二电极的同时，利用第二电极线将多个发光单元连成一体，形成稳定结构。这样发光单元从基板上下落的过程中，多个发光单元之间可以保持固定的尺寸间隙，并且相互进行牵制，从而提高发光单元的稳定性，减小发光单元落下的实际位置与理想位置之间的偏差，进而提高发光单元的转移良率。
基于同样的发明构思，本申请还提供一种显示面板，包括设有多条第一电极线的背板和多个上述提供的发光芯片组件，每条所述第一电极线与多个所述发光芯片组件中对应的第一电极连接。
上述显示面板，背板上设有多条第一电极线，每条第一电极线与多个发光芯片组件中对应的第一电极连接，通过第一电极线和第二电极线可以选择发光单元进行复合发光。
基于同样的发明构思，本申请还提供一种显示装置，包括驱动电路和上述提供的显示面板，所述驱动电路分别与所述第一电极线、所述第二电极线连接。
上述显示装置，通过驱动电路分别与第一电极线、第二电极线连接，可以自动选择并控制发光单元复合发光。
基于同样的发明构思，本申请还提供一种发光芯片组件的制备方法，包括：
在基板上依次形成第一半导体层、发光层、第二半导体层；
在所述第二半导体层上开设延伸至所述基板的隔离槽，形成多个彼此间隔的发光单元；
在所述第二半导体层上制备第一电极；
在所述基板上形成第二电极线，所述第二电极线包括互连线路和接触线路，所述互连线路与所述接触线路电连接；其中，至少部分所述发光单元的第一半导体周围设置有所述接触线路，且设置有所述接触线路的各所述发光单元透过所述互连线路实现互连。
上述发光芯片组件的制备方法，先在基板上依次形成第一半导体层、发光层、第二半导体层，再在第二半导体层上开设延伸至基板的隔离槽，形成多个彼此间隔的发光单元，并在第二半导体层上制备第一电极，在基板上形成第二电极线，第二电极线包括互连线路和接触线路，互连线路与接触线路电连接；其中，至少部分发光单元的第一半导体周围设置有接触线路，且设置有接触线路的各发光单元透过互连线路实现互连。通过第二电极线将多个发光单元连成一体，形成稳定结构。这样发光单元从基板上下落的过程中，多个发光单元之间可以保持固定的尺寸间隙，并且相互进行牵制，从而提高发光单元的稳定性，减小发光单元落下的实际位置与理想位置之间的偏差，进而提高发光单元的转移良率。
基于同样的发明构思，本申请还提供一种显示面板的制备方法，包括：
提供一设有第一电极线的背板和上述提供的发光芯片组件；
控制所述发光芯片组件与所述背板对位，并将设置有所述接触线路的发光单元自所述发光芯片组件剥离；
将剥离至所述背板上的发光单元与所述背板进行键合，使所述第一电极线与所述发光单元中的第一电极连接。
上述显示面板的制备方法，提供一设有第一电极线的背板和发光芯片组件，发光芯片组件包括基板、多个发光单元、第一电极和第二电极线，各发光单元于基板上间隔排布，发光单元包括依次层叠设置的第一半导体层、发光层和第二半导体层，第一电极设于第二半导体层上，且与第二半导体层电连接，第二电极线包括互连线路和接触线路，互连线路与接触线路电连接，至少部分发光单元的第一半导体周围设置有接触线路，且设置有接触线路的各发光单元透过互连线路实现互连，在为发光单元设置第二电极的同时，利用第二电极线将多个发光单元连成一体，形成稳定结构。控制发光芯片组件与背板对位，并将设置有接触线路的发光单元自发光芯片组件剥离，此时多个发光单元之间可以保持固定的尺寸间隙，并且相互进行牵制，可以提高发光单元的稳定性，减小发光单元落下的实际位置与理想位置之间的偏差，进而提高发光单元的转移良率。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据公开的附图获得其他的附图。
图1为本申请一实施例中的发光芯片组件的剖面图；
图2为本申请一实施例中的发光芯片组件的俯视图；
图3为本申请一实施例中的接触线路的示意图；
图4为本申请一实施例中的接触线路的示意图；
图5为为本申请一实施例中的接触线路的示意图；
图6为本申请一实施例中的发光芯片组件的剖面图；
图7为本申请一实施例中的显示面板的俯视图；
图8为本申请一实施例中的发光芯片组件的制备方法的流程图；
图9为本申请一实施例中的步骤S802执行之后的发光芯片组件的结构示意图；
图10为本申请一实施例中的步骤S804执行之后的发光芯片组件的结构示意图；
图11为本申请一实施例中的步骤S806执行之后的发光芯片组件的结构示意图；
图12为本申请一实施例中的步骤S808执行之后的发光芯片组件的结构示意图；
图13为本申请一实施例中的覆盖加强结构之后的发光芯片组件的结构示意图；
图14为本申请一实施例中的显示面板的制备方法的流程图。
附图标记说明：
100-发光芯片组件；
10-基板；
20-发光单元，21-第一半导体层，22-发光层，23-第二半导体层，24-台阶；
30-第一电极；
40-第二电极线，41-互连线路，411-主干线，412-分支线，42-接触线路，43-焊盘；
50-缓冲层；
60-加强结构，61-开口区域；
70-第一电极线；
80-隔离槽。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本申请。
在现有的Micro LED的制程中，先在生长基板上制备Micro LED芯片，再将Micro LED芯片与背板对位，采用激光将Micro LED芯片从生长基板剥离，Micro LED芯片在重力作用下落在背板上与背板进行键合，从而将Micro LED芯片从生长基板转移到背板上。 然而，Micro LED芯片在自由下落的过程中容易出现位置偏移，导致Micro LED芯片落在背板上的实际位置与理想位置存在偏差，影响Micro LED芯片的转移良率。
基于此，本申请希望提供一种能够解决上述技术问题的方案，其详细内容将在后续实施例中得以阐述。
参阅图1和图2，本申请提供一种发光芯片组件100，该发光芯片组件100包括基板10、多个发光单元20、第一电极30和第二电极线40。各发光单元20于基板10上间隔排布，发光单元20包括依次层叠设置的第一半导体层21、发光层22和第二半导体层23。第一电极30设于第二半导体层23上，且与第二半导体层23电连接。第二电极线40包括互连线路41和接触线路42，互连线路41与接触线路42电连接。其中，至少部分发光单元20的第一半导体21周围设置有接触线路42，且设置有接触线路42的各发光单元20透过互连线路41实现互连。
上述发光芯片组件，包括基板10、多个发光单元20、第一电极30和第二电极线40，各发光单元20于基板10上间隔排布，发光单元20包括依次层叠设置的第一半导体层21、发光层22和第二半导体层23，第一电极30设于第二半导体层23上，且与第二半导体层23电连接，第二电极线40包括互连线路41和接触线路42，互连线路41与接触线路42电连接，至少部分发光单元20的第一半导体21周围设置有接触线路42，且设置有接触线路42的各发光单元20透过互连线路41实现互连，在为发光单元20设置第二电极的同时，利用第二电极线40将多个发光单元20连成一体，形成稳定结构。这样发光单元20从基板10上下落的过程中，多个发光单元20之间可以保持固定的尺寸间隙，并且相互进行牵制，从而提高发光单20元的稳定性，减小发光单元20落下的实际位置与理想位置之间的偏差，进而提高发光单元20的转移良率。
具体地，基板10包括但不限于蓝宝石衬底，用于起到支撑作用，并提供外延生长的表面，以形成第一半导体层21、发光层22和第二半导体层23。第一半导体层21包括但不限于N型掺杂的GaN层，用于提供复合发光的电子；第二半导体层23包括但不限于P型掺杂的GaN层，用于提供复合发光的空穴。发光层22包括交替层叠的多个量子阱和量子垒，量子阱包括但不限于未掺杂的InGaN层，量子垒包括但不限于未掺杂的GaN层，量子垒将电子和空穴限制在量子阱中进行复合发光。第一电极30包括但不限于Ni层、Ag层等，第二电极线40包括但不限于Cr层、Ni层、Au层等，第一电极30和第二电极线40用于向发光单元20注入电流，驱动电子和空穴注入发光层22。
接触线路42的数量小于或等于发光单元20的数量。
当接触线路42的数量小于发光单元20的数量时，一部分发光单元20的周围设有接 触线路42，另一部分发光单元20的周围没有接触线路42。周围设有接触线路42的发光单元20可以与周围设有接触线路42的发光单元20相邻设置，也可以与周围没有接触线路42的发光单元20相邻设置，还可以分别与周围设有接触线路42的发光单元20、周围没有接触线路42的发光单元20相邻设置。例如，周围设有接触线路42的各发光单元20排成一行或者一列，周围没有接触线路42的各发光单元20也排成一行或者一列，且周围设有接触线路42的发光单元20与周围没有接触线路42的发光单元20并排设置或者错位设置。又如，周围设有接触线路42的各发光单元20与周围没有接触线路42的各发光单元20排成一行或者一列，且沿行方向或者列方向分开设置或者交替设置。这样布局紧凑，节省空间。
当接触线路42的数量等于发光单元20的数量时，每个发光单元20的周围设有接触线路42。
示例性地，如图1所示，该发光芯片组件100包括还包括缓冲层50，缓冲层50设置在衬底10和多个发光单元20之间，即缓冲层50铺设在衬底10上，多个发光单元20间隔设置在缓冲层50上。
具体地，缓冲层50包括但不限于未掺杂的GaN层，用于缓解异质衬底外延生长产生的晶格失配，提高第一半导体层21的晶体质量。
在一些实施例中，如图1所示，每个发光单元20的边缘具有自基板10延伸至第一半导体层21的台阶24，接触线路42延伸至台阶24上且不与发光层22接触。
上述实施例中，每个发光单元20的边缘具有自基板10延伸至第一半导体层21的台阶24，使得接触线路42可以延伸至台阶24上，从而增大接触线路42与发光单元20的接触面积、以及接触线路42的强度，有利于接触线路42限制发光单元20的移动，提高发光单元20的稳定性。
在一种实现方式中，延伸至台阶24上的接触线路42包括沿第一半导体层21的边缘设置的环形线路。
在另一种实现方式中，延伸至台阶24上的接触线路42包括至少两个条形线路，至少两个条形线路沿第一半导体层21的边缘间隔设置。例如，第一半导体层21包括依次连接的第一直边A、第二直边B、第三直边C和第四直边D，两个条形线路分别设置在第一直边A和第三直边C上，且与第一直边A和第二直边C的延伸方向垂直(如图3所示)，或者两个条形线路的延伸方向与第一直边A和第二直边C的延伸方向平行(图未示)。
在另一种实现方式中，两个条形线路还可分别设置在第二直边B和第四直边D上，且与第二直边B和第四直边D的延伸方向垂直(如图4所示)，或者两个条形线路的延伸方 向与第二直边B和第四直边D的延伸方向平行(图未示)。
在另一种实现方式中，当接触线路42包括四个条形线路的时候，四个条形线路可分别设置在第一直边A、第二直边B、第三直边C和第四直边D上(如图5所示)，且垂直于各自设置的直边的延伸方向。
上述条形线路的设置，增大了接触线路42与发光单元20的接触面积，提升了接触线路42的强度，更可提升后续对上述若干发光单元20进行巨量转移时的稳定性。
在一些实施例中，如图2所示，互连线路41包括主干线411和多条分支线412，多条分支线412与多个接触线路42一一对应，每条分支线412的两端分别与对应的接触线路42和主干线411连接，即每条分支线412的一端连接对应的接触线路42，另一端连接主干线411。互连线路41由主干线411和多条分支线412组成，方便在基板10上布线，实现多个发光单元20连成一体且彼此间隔。
具体地，如图2所示，多条分支线412相互平行，主干线411与分支线412相互垂直，可以在实现电连接的情况下，最大程度减小布线的长度和难度。
示例性地，如图2所示，接触线路42为环形线路。接触线路42的形状与发光单元20在基板10上的正投影形状一致。例如，发光单元20在基板10上的正投影为矩形，则接触线路42呈方环形。又如，发光单元20在基板10上的正投影为圆形，则接触线路42呈圆环形。
进一步地，第一电极30在第二半导体层23上的正投影形状与接触线路42的形状一致，使得第一电极30在各个方向上与第二电极线40的距离相同，有利于电流均匀注入发光单元20，提高发光单元20复合发光的均匀性。例如，接触线路42呈方环形，则第一电极30在第二半导体层23上的正投影形状为矩形。又如，接触线路42呈圆环形，则第一电极30在第二半导体层23上的正投影形状为圆形。
在一些实施例中，如图2所示，互连线路41远离接触线路42的一端设有焊盘43。由于焊盘43设置在互连线路41远离接触线路42的一端，因此焊盘43位于远离发光单元20的区域，这个区域可以设计大面积焊盘43，从而提高焊接的可靠性，降低对位精度。
在一些实施例中，如图6所示，该发光芯片组件100还包括加强结构60，加强结构60至少设置在相邻两个发光单元20之间，并覆盖第二电极线40。
上述实施例中，在相邻两个发光单元20之间的第二电极线40上增设加强结构60，加强结构60可以与第二电极线40配合，阻挡相邻两个发光单元20之间相对移动，进一步提高发光单元20的稳定性。而且加强结构60可以对第二电极线40起到固定和支撑的作用，特别是在发光单元20从基板10上剥离之后。
示例性地，如图6所示，加强结构60覆盖在基板10上且围成多个开口区域61，发光单元20设置在开口区域61内。
上述实施例中，加强结构60在基板10上形成多个开口区域61，发光单元20设置在开口区域61内，发光单元20完全被加强结构60围住，稳定性达到最佳。
具体地，加强结构60采用高分子材料形成。
示例性地，加强结构60为黑色胶材。
上述实施例中，加强结构60为黑色胶材，具有降低像素串扰的作用。
基于同样的发明构思，参阅图7，本申请还提供一种显示面板，该显示面板包括设有多条第一电极线70的背板和多个发光芯片组件100，每条第一电极线70与多个发光芯片组件100中对应的第一电极30连接。
具体地，发光芯片组件100为上述实施例提供的发光芯片组件，在此不再详述。
上述显示面板，背板上设有多条第一电极线70，每条第一电极线70与多个发光芯片组件100中对应的发光单元20中的第一电极30连接，通过第一电极线70和第二电极线40可以选择发光单元进行复合发光。
在一些实施例中，如图7所示，多个发光芯片组件100沿第一方向A间隔排布，每个发光芯片组件100中的多个发光单元20沿第二方向B间隔排布，第二方向B与第一方向A相交。
上述实施例中，多个发光芯片组件100沿第一方向A间隔排布，每个发光芯片组件100中的多个发光单元20沿与第一方向A相交的第二方向B间隔排布，发光单元20以阵列的形式分布，方便显示面板的布局和走线。
示例性地，如图7所示，第二方向B与第一方向A相互垂直。
进一步地，如图7所示，每个发光芯片组件100中的互连线路41沿第二方向B延伸，每条第一电极线70沿第一方向A延伸。
上述实施例中，每个发光芯片组件100中的互连线路41沿第二方向B延伸，配合每个发光芯片组件100中的多个发光单元20沿第二方向B间隔排布，方便互连线路41将同一个发光芯片组件100中的每个发光单元20连成一体。每条第一电极线70沿第一方向A延伸，配合多个发光芯片组件100沿第一方向A间隔排布，方便将不同发光芯片组件100的一个发光单元20接入同一条第一电极线70。这样不同发光单元20接入的第二电极线40和/或第一电极线70不同，通过第一电极线40和第二电极线70，可以选择并控制其中任意一个发光单元20复合发光。
基于同样的发明构思，本申请还提供一种显示装置(图未示出)，该显示装置包括驱动 电路和显示面板，驱动电路分别与第一电极线、第二电极线连接。
具体地，显示面板为上述实施例提供的显示面板，在此不再详述。
上述显示装置，通过驱动电路分别与第一电极线、第二电极线连接，可以自动选择并控制发光单元复合发光。
基于同样的发明构思，参阅图8，本申请还提供一种发光芯片组件的制备方法，适用于制备上述实施例提供的发光芯片组件，该制备方法包括如下步骤：
步骤S802，在基板上依次形成第一半导体层、发光层、第二半导体层。
具体地，该步骤S802包括：采用MOCVD(英文：Metal-organic Chemical Vapor Deposition，中文：金属有机化合物化学气相沉淀)技术在基板上依次生长第一半导体层、发光层、第二半导体层。
示例性地，步骤S802之前，该制备方法还包括：在基板上生长缓冲层。
相应地，该步骤S802包括：在缓冲层上依次生长第一半导体层、发光层、第二半导体层。
图9为步骤S802执行之后的发光芯片组件的结构示意图。参阅图9，缓冲层50、第一半导体层21、发光层22和第二半导体层23依次层叠在基板10上。
步骤S804，在第二半导体层上开设延伸至基板的隔离槽，形成多个彼此间隔的发光单元。
在基板上生长缓冲层之后，该步骤S804包括：在第二半导体层上开设延伸至缓冲层的隔离槽，形成多个彼此间隔的发光单元。
具体地，该步骤S804包括：采用黄光工艺在第二半导体层形成图形化的光刻胶；采用刻蚀工艺去除未覆盖光刻胶的第二半导体层、发光层、第一半导体层，在第二半导体层上开设延伸至缓冲层的隔离槽，形成多个彼此间隔的发光单元；去除光刻胶。
进一步地，黄光工艺包括：旋涂光刻胶；透过掩膜版对光刻胶进行曝光；对曝光后的光刻胶进行显影，从而实现光刻胶的图形化。
示例性地，步骤S804之后，该制备方法还包括：在每个发光单元的边缘形成自基板延伸至第一半导体层的台阶。
具体地，采用黄光工艺和刻蚀工艺去除每个发光单元的边缘的第二半导体层和发光层，即可在每个发光单元的边缘形成自基板延伸至第一半导体层的台阶。
图10为步骤S804执行之后的发光芯片组件的结构示意图。参阅图10，在第二半导体层23上开设延伸至缓冲层50的隔离槽80，形成多个彼此间隔的发光单元20，每个发光单元20包括依次层叠在缓冲层40上的第一半导体层21、发光层22和第二半导体层23， 并且每个发光单元20的边缘具有自缓冲层50延伸至第一半导体层21的台阶24。
步骤S806，在第二半导体层上制备第一电极。
具体地，该步骤S806包括：采用黄光工艺在基板和每个发光单元上形成光刻胶，光刻胶中设有延伸至每个发光单元中的第二半导体层的开口；采用电子束蒸镀技术在光刻胶上和开口内沉积金属材料；去除光刻胶和光刻胶上的金属材料，开口内的金属材料留下形成第一电极。
图11为步骤S806执行之后的发光芯片组件的结构示意图。参阅图11，每个发光单元20的第二半导体层23上形成一个第一电极30。
步骤S808，在基板上形成第二电极线，第二电极线包括互连线路和接触线路，互连线路与接触线路电连接，至少部分发光单元的第一半导体周围设置有接触线路，且设置有接触线路的各发光单元透过互连线路实现互连。
具体地，该步骤S808包括：采用黄光工艺在基板和每个发光单元上形成光刻胶，光刻胶中设有延伸至基板的开口，开口包括围绕每个发光单元设置的第一区域和连通各个第一区域的第二区域；采用电子束蒸镀技术在光刻胶上和开口内沉积金属材料；去除光刻胶和光刻胶上的金属材料，开口内的金属材料留下形成第二电极线。
图12为步骤S808执行之后的发光芯片组件的结构示意图。参阅图12，在基板10上形成第二电极线40，第二电极线40围绕发光单元20设置。
在一些实施例中，步骤S808之后，该制备方法还包括：在基板上覆盖加强结构。
图13为覆盖加强结构之后的发光芯片组件的结构示意图。参阅图13，加强结构60覆盖在基板10上且围成多个开口区域61，发光单元20设置在开口区域61内。
上述发光芯片组件的制备方法，先在基板上依次形成第一半导体层、发光层、第二半导体层，再在第二半导体层上开设延伸至基板的隔离槽，形成多个彼此间隔的发光单元，并在第二半导体层上制备第一电极，在基板上形成第二电极线，第二电极线包括互连线路和接触线路，互连线路与接触线路电连接；其中，至少部分发光单元的第一半导体周围设置有接触线路，且设置有接触线路的各发光单元透过互连线路实现互连。通过第二电极线将多个发光单元连成一体，形成稳定结构。这样发光单元从基板上下落的过程中，多个发光单元之间可以保持固定的尺寸间隙，并且相互进行牵制，从而提高发光单元的稳定性，减小发光单元落下的实际位置与理想位置之间的偏差，进而提高发光单元的转移良率。
基于同样的发明构思，参阅图14，本申请还提供一种显示面板的制备方法，适用于制备上述实施例提供的显示面板，该制备方法包括如下步骤：
步骤S1402，提供一设有第一电极线的背板和发光芯片组件。
其中，发光芯片组件包括基板、多个发光单元和第二电极线。多个发光单元彼此间隔设置。每个发光单元包括依次设置在基板上的第一半导体层、发光层、第二半导体层和第一电极。第二电极线设置在基板上。第二电极线包括互连线路和多个接触线路。每个接触线路围绕对应的发光单元中的第一半导体层设置，并与互连线路连接。
步骤S1404，控制发光芯片组件与背板对位，并将设置有接触线路的发光单元自发光芯片组件剥离。
具体地，将发光组件中设置有接触线路的发光单元中的第一电极与背板上的第一电极线相对设置，以使设置有接触线路的发光单元自发光芯片组件剥离之后，可以落在第一电极线上进行键合。
步骤S1406，将剥离至背板上的发光单元与背板进行键合，使第一电极线与发光单元中的第一电极连接。
具体地，将剥离至背板上的发光单元中的第一电极与背板上的第一电极线进行键合，在剥离至背板上的发光单元中的第一电极与背板上的第一电极线之间形成电连接。
上述显示面板的制备方法，提供一设有第一电极线的背板和发光芯片组件，发光芯片组件包括基板、多个发光单元、第一电极和第二电极线，各发光单元于基板上间隔排布，发光单元包括依次层叠设置的第一半导体层、发光层和第二半导体层，第一电极设于第二半导体层上，且与第二半导体层电连接，第二电极线包括互连线路和接触线路，互连线路与接触线路电连接，至少部分发光单元的第一半导体周围设置有接触线路，且设置有接触线路的各发光单元透过互连线路实现互连，在为发光单元设置第二电极的同时，利用第二电极线将多个发光单元连成一体，形成稳定结构。控制发光芯片组件与背板对位，并将设置有接触线路的发光单元自发光芯片组件剥离，此时多个发光单元之间可以保持固定的尺寸间隙，并且相互进行牵制，可以提高发光单元的稳定性，减小发光单元落下的实际位置与理想位置之间的偏差，进而提高发光单元的转移良率。
应当理解的是，本发明的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本发明所附权利要求的保护范围。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说， 在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (11)

  1. 一种发光芯片组件，包括：
    基板；
    多个发光单元，各所述发光单元于所述基板上间隔排布，所述发光单元包括依次层叠设置的第一半导体层、发光层和第二半导体层；
    第一电极，设于所述第二半导体层上，且与所述第二半导体层电连接；以及
    第二电极线，包括互连线路和接触线路，所述互连线路与所述接触线路电连接；其中，至少部分所述发光单元的第一半导体周围设置有所述接触线路，且设置有所述接触线路的各所述发光单元透过所述互连线路实现互连。
  2. 如权利要求1所述的发光芯片组件，其中，所述发光单元的边缘具有自所述基板延伸至所述第一半导体层的台阶，所述接触线路延伸至所述台阶上且不与所述发光层接触。
  3. 如权利要求2所述的发光芯片组件，其中，延伸至所述台阶上的接触线路包括沿所述第一半导体层的边缘设置的环形线路；或者，
    延伸至所述台阶上的接触线路包括至少两个条形线路，所述至少两个条形线路沿所述第一半导体层的边缘间隔设置。
  4. 如权利要求1所述的发光芯片组件，其中，还包括：
    加强结构，至少设置在相邻两个所述发光单元之间，并覆盖所述第二电极线。
  5. 如权利要求4所述的发光芯片组件，其中，所述加强结构覆盖在所述基板上且围成多个开口区域，所述发光单元设置在所述开口区域内。
  6. 一种显示面板，包括设有多条第一电极线的背板和多个如权利要求1-5任一项所述的发光芯片组件，每条所述第一电极线与多个所述发光芯片组件中对应的第一电极连接。
  7. 如权利要求6所述的显示面板，其中，多个所述发光芯片组件沿第一方向间隔排布，每个所述发光芯片组件中的多个发光单元沿第二方向间隔排布，所述第二方向与所述第一方向相交。
  8. 如权利要求7所述的显示面板，其中，每个所述发光芯片组件中的互连线路沿所述第二方向延伸，每条所述第一电极线沿所述第一方向延伸。
  9. 一种显示装置，包括驱动电路和如权利要求6所述的显示面板，所述驱动电路分别与所述第一电极线、所述第二电极线连接。
  10. 一种发光芯片组件的制备方法，包括：
    在基板上依次形成第一半导体层、发光层、第二半导体层；
    在所述第二半导体层上开设延伸至所述基板的隔离槽，形成多个彼此间隔的发光单元；
    在所述第二半导体层上制备第一电极；
    在所述基板上形成第二电极线，所述第二电极线包括互连线路和接触线路，所述互连线路与所述接触线路电连接；其中，至少部分所述发光单元的第一半导体周围设置有所述接触线路，且设置有所述接触线路的各所述发光单元透过所述互连线路实现互连。
  11. 一种显示面板的制备方法，包括：
    提供一设有第一电极线的背板和如权利要求1所述的发光芯片组件；
    控制所述发光芯片组件与所述背板对位，并将设置有所述接触线路的发光单元自所述发光芯片组件剥离；
    将剥离至所述背板上的发光单元与所述背板进行键合，使所述第一电极线与所述发光单元中的第一电极连接。
PCT/CN2023/071783 2022-06-06 2023-01-11 发光芯片组件、显示面板、显示装置及制备方法 WO2023236537A1 (zh)

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CN114373839A (zh) * 2020-10-14 2022-04-19 京东方科技集团股份有限公司 发光二极管芯片及其制备方法和显示装置
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