WO2023236282A1 - 一种高分辨率变频阻尼振荡信号发生器 - Google Patents

一种高分辨率变频阻尼振荡信号发生器 Download PDF

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WO2023236282A1
WO2023236282A1 PCT/CN2022/102607 CN2022102607W WO2023236282A1 WO 2023236282 A1 WO2023236282 A1 WO 2023236282A1 CN 2022102607 W CN2022102607 W CN 2022102607W WO 2023236282 A1 WO2023236282 A1 WO 2023236282A1
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waveform
damped oscillation
fpga
output
bit
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PCT/CN2022/102607
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French (fr)
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孙正
汤海波
张炎
黄学军
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苏州泰思特电子科技有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/28—Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/005—Testing of electric installations on transport means
    • G01R31/006—Testing of electric installations on transport means on road vehicles, e.g. automobiles or trucks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/40—Arrangements for reducing harmonics

Definitions

  • This application belongs to the technical field of system internal conduction immunity testing in the field of automotive electronics, and in particular relates to a high-resolution frequency conversion damping oscillation signal generator.
  • Electric drive systems used in new energy vehicle power usually include high-power, high-frequency switching devices, inductive loads, etc.
  • variable frequency damped oscillation pulse As a typical waveform, variable frequency damped oscillation pulse is listed as a test item by many car manufacturers.
  • the variable frequency damped oscillation pulse generator includes a signal generator and a radio frequency power amplifier.
  • For the variable frequency damped oscillation pulse signal generator Geely standard CEVT8888790454-1 4.1.3 Radiated disturbance gives the waveform formula of variable frequency damped oscillation pulse:
  • p 1 is the peak current amplitude
  • p 2 is the time constant
  • p 3 is the initial frequency
  • p 4 is the amplitude attenuation constant
  • p 5 is the frequency attenuation constant
  • the initial frequency p3 of the damped oscillation wave is 3MHz, but the leading edge of the waveform is only 3.49ns.
  • the bandwidths of these two parameters are very different.
  • the existing technology is implemented by using high-speed CPLD and high-speed D/A converter. In order to meet the requirement of 3.49ns on the rising edge of the waveform, the conversion rate of the D/A converter must reach at least 1GHz, which also requires the data port of the CPLD. It must also work above 1GHz. The demand for such high-bandwidth devices will bring about two problems:
  • this application designs a high-resolution, low-cost, and easy-to-process variable-frequency damped oscillation wave signal generator.
  • the data extraction method is as follows:
  • the high-resolution variable frequency damped oscillation signal generator also includes a MOSFET drive circuit.
  • the MOSFET drive circuit includes a transistor, a pulse transformer, and a rectifier diode.
  • the FPGA emits The PWM signal controls the transistor, which drives the pulse transformer.
  • the square wave pulse generated by the pulse transformer passes through the rectifier diode and generates a driving waveform between the G pole and the S pole of the MOSFET switch.
  • the output of the variable frequency damped oscillation signal needs to be controlled by timing, and the timing control is as follows.
  • T4 the start time for the FPGA to send out the PWM signal as T1
  • T2 the start time for the damped oscillation waveform output as T2
  • T3 the end time for the damped oscillation waveform output as T3
  • the MOSFET is absolutely turned off.
  • the time of the off state is T4, where T1 is determined by calculating the delay of each device in the MOSFET drive circuit,
  • the FPGA starts driving the 14-bit D/A converter at time 0. From time 0 to T2, the output waveform of the 14-bit D/A converter maintains the initial value.
  • the time period of the MOSFET switch output damped oscillation waveform is T1 ⁇ T3, where T1 ⁇ T2 is the leading part of the waveform, and T2 ⁇ T3 is the subsequent part of the waveform.
  • the MOSFET switch is a SiC material MOSFET.
  • the cost of the device used in the present invention is relatively low, the cost of the device is relatively low, and this working frequency can use double-sided boards, unlike high-speed devices that use multi-layer boards, which greatly reduces the difficulty of development and the processing technology is simple and easy. accomplish. According to the overall calculation, the cost is only 20% of the high-speed device solution, which greatly reduces the production cost.
  • This embodiment provides a high-resolution variable frequency damped oscillation signal generator.
  • the schematic diagram is shown in Figure 1, which includes: an FPGA, a 14-bit D/A converter, and a MOSFET switch.
  • the FPGA receives an externally transmitted damped oscillation waveform.
  • the data is converted into an analog waveform through the 14-bit D/A converter at a conversion rate of 100MHz, and then processed by filtering and operational amplifier, and output through the MOSFET switch.
  • the data extraction method is as follows:
  • the D/A converter used in this system is 14-bit
  • the output waveform of the D/A converter is inverted.
  • the extracted data also needs to be processed in the following way: the first data of the waveform data array is replaced with the peak value.
  • the purpose of this is to make the starting point of the waveform output by the 14-bit D/A converter be at the peak value, not at the middle value. In order to adjust the waveform at the subsequent op amp.
  • the FPGA device selected in this embodiment contains a phase-locked loop, a bidirectional RAM and a PCI standard interface.
  • the external communication interface in Figure 1 of this embodiment is the PCI standard interface.
  • the external controller writes the data array s 1 (t) into the bidirectional RAM of the FPGA through the PCI interface.
  • the bidirectional RAM can be used to write and read data at the same time to ensure the timeliness of data transmission.
  • the FPGA uses internal phase-locked loops and counters. Drive the 14-bit D/A converter at a rate of 100MHz, and through the RC filter circuit composed of R1 and C1, the waveform obtained at the output end of the 14-bit D/A converter 1 in Figure 1 is the waveform 1 in Figure 2.
  • U3/R4 -(U1/R2+U2/R3)
  • U3 -U1-U2
  • U1 is the waveform of the output terminal 1 of the 14-bit D/A converter
  • U2 is the waveform of the voltage-U0 of the input terminal 2 of R3
  • U3 is the output terminal of the op amp.
  • the waveform of 3 is as the waveform 3 of Figure 2.
  • the function of the op amp addition operation is to reduce the waveform at the output terminal 1 of the 14-bit D/A converter from the reference voltage U0 to 0V, and reverse the waveform.
  • Accelerated front edge processing is the key to achieving 3.49ns on the rising edge of the damped oscillation waveform in this embodiment.
  • the specific operation is as follows: use MOSFET as the switch. After the switch is turned on, R5 and C2 form an RC filter. In the S of the MOSFET switch in Figure 1 The final output damped oscillation waveform is generated at pole 4, which corresponds to waveform 4 in Figure 2.
  • the rising edge of the waveform depends on the RC filter and the speed of MOSFET switching.
  • the parameters of the RC filter are selected with a cutoff bandwidth of about 200MHz, which can filter the rising edge of the waveform without affecting the subsequent waveform, because the subsequent waveform frequency ⁇ 3MHz, far less than the cutoff frequency.
  • the turn-on speed of ordinary MOSFETs is difficult to reach 5ns.
  • This embodiment uses a MOSFET switch made of SiC material with low input capacitance, and the turn-on speed can reach 2ns.
  • the high-resolution frequency variable damping oscillation signal generator of this embodiment also includes a MOSFET drive circuit.
  • the MOSFET drive circuit includes a transistor, a pulse transformer T, and a rectifier diode.
  • the FPGA sends a PWM signal to control the transistor.
  • the PWM signal corresponds to the Waveform 5, the transistor drives the pulse transformer.
  • the pulse transformer uses 15V power supply to generate a 15V square wave pulse signal on the secondary side of the transformer. This level can effectively drive the MOSFET without damaging the MOSFET.
  • the square wave pulse generated by the driving pulse transformer passes through the rectifier diode, and a driving waveform is generated between the G pole and S pole of the MOSFET switch, corresponding to the waveform 6 in Figure 2; when the voltage amplitude between the G pole and S pole of the MOSFET switch When it is greater than 10V, the MOSFET switch can maintain conduction, so the duty cycle of the PWM signal needs to be adjusted so that the minimum amplitude of the sawtooth wave generated at the rectifier diode 6 is not less than 10V.
  • variable frequency damping oscillation signal in this embodiment needs to be controlled by timing.
  • the timing control is as follows:
  • T1 is determined by calculating the delay of each device in the MOSFET drive circuit.
  • the FPGA starts driving the 14-bit D/A converter at time 0.
  • the output waveform U1 of the 14-bit D/A converter maintains the initial value, such as Waveform 1 in Figure 2.
  • the op amp output waveform U3 and the output waveform U1 of the 14-bit D/A converter are consistent in timing.
  • the drive signal of the switch needs to be given before T2. If the signal is given too early, it will cause the output waveform to have a flat top at the peak; signal If given too late, the peak value of the output waveform will not reach the maximum value.
  • the FPGA sends out a PWM signal, and the MOSFET switch starts to output a damped oscillation waveform at T2, such as waveform 4 in Figure 2, and reaches the peak value at T2 time.
  • the FPGA stops sending out the PWM signal, and at T4
  • the output level is adjusted to the value of the initial state.
  • the delay can be adjusted through the internal phase-locked loop of the FPGA to ensure the time accuracy of the PWM drive signal.
  • the time period of the MOSFET switch output damped oscillation waveform is T1 ⁇ T3, where T1 ⁇ T2 is the leading part of the waveform, and T2 ⁇ T3 is the subsequent part of the waveform.
  • the waveform at the S pole 4 of the MOSFET switch is output after passing through the resistor R6.
  • the final output variable frequency damping oscillation waveform is shown in Figure 3.

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Abstract

本申请涉及一种高分辨率变频阻尼振荡信号发生器，其特征在于，包括FPGA，14位D/A转换器，MOSFET开关，所述FPGA接收外部传送的阻尼振荡波形数据,以100MHz的转换率通过所述14位D/A转换器把数据转换成模拟波形,再通过滤波、运放处理，通过MOSFET开关输出。本发明在使用低带宽器件(数据转换率100MHz)的前提下，实现了波形上升沿3.49ns的效果。使用了14位的D/A转换器，很好的保证了输出波形低压、低频时波形的精度，使得测试效果一致性更好。且由于本发明使用的器件工作频率相对较低，器件成本相对也很低，而且该工作频率可以使用双面板，不像高速器件那样要使用多层板，使开发难度大幅降低，加工工艺简单、易实现。

Description

一种高分辨率变频阻尼振荡信号发生器 技术领域
本申请属于汽车电子领域系统内部传导抗扰度测试技术领域，尤其是涉及一种高分辨率变频阻尼振荡信号发生器。
背景技术
新能源汽车动力使用的电驱动系统通常包含高功率、高频开关器件、感性负载等,电流在极短时间内的跳动以及大功率半导体开关的快速移动会发出强烈的辐射以及电磁干扰。所以与传统车载电子设备相比,新能源汽车的电子设备的EMC测试需要增加更多的射频传导/辐射骚扰的测试。
变频阻尼振荡脉冲作为一种典型的波形被众多车厂列为测试项目，变频阻尼振荡脉冲发生器包含信号发生器和射频功放，对于变频阻尼振荡脉冲信号发生器，吉利标准CEVT8888790454-1中4.1.3辐射骚扰给出了变频阻尼振荡脉冲的波形公式：
Figure PCTCN2022102607-appb-000001
其中，p 1为峰值电流幅度，p 2为时间常数，
Figure PCTCN2022102607-appb-000002
为初始上升沿时间，p 3为初始频率，p 4为幅度衰减常数，p 5为频率衰减常数，
Figure PCTCN2022102607-appb-000003
为幅度阻尼因数，
Figure PCTCN2022102607-appb-000004
为频率阻尼因数。
从公式可以看出，阻尼振荡波的幅度和频率都是在周期内持续变化的。取p 1＝0.4A，p 2＝6.28*10^8，p 3＝3MHz，p 4＝40，p 5＝60，变频阻尼振荡脉冲的前沿：
Tr＝ln(9)/p2＝2.19/(6.28*10^8)＝3.49ns，
阻尼振荡波的初始频率p 3为3MHz,可是波形的前沿却只有3.49ns,这两个参数的带宽相差很大。现有的技术是用高速的CPLD加上高速D/A转换器实现，为了满足波形上升沿3.49ns的要求,D/A转换器的转换速率至少要达到1GHz,这也就要求CPLD的数据端口也要工作在1GHz以上。如此高带宽的器件需求会带来两个问题:
(1)转换速率在1GHz以上的D/A转换器,大部分都是8位的,极少数是10位的。10位数据的分辨率也只有1024,分辨率低会造成阻尼振荡波低频部分(低频分量电压幅度也低)畸变,这会给测试结果带来不确定性。
(2)高速器件不容易购买,且开发工具比较复杂；PCB需要用多层板,布线工艺和加工工艺要求很高,开发难度大,成本高。
发明内容
为解决现有技术中的不足，本申请设计了一种高分辨率、低成本、容易加工的变频阻尼振荡波信号发生器。
本发明解决上述技术问题所采用的技术方案是：
一种高分辨率变频阻尼振荡信号发生器，包括FPGA，14位D/A转换器，MOSFET开关，所述FPGA接收外部传送的阻尼振荡波形数据,以100MHz的转换率通过所述14位D/A转换器把数据转换成模拟波形,再通过滤波、运放处理，通过MOSFET开关输出。
优选地，本发明的高分辨率变频阻尼振荡信号发生器，外部传送的阻尼振荡波形数据进入FPGA前，需要进行数据提取，数据提取方法 如下：
根据公式:
Figure PCTCN2022102607-appb-000005
提取阻尼振荡波形数据，其中，p 1为峰值电流幅度，p 2为时间常数，
Figure PCTCN2022102607-appb-000006
为初始上升沿时间，p 3为初始频率，p 4为幅度衰减常数，p 5为频率衰减常数，
Figure PCTCN2022102607-appb-000007
为幅度阻尼因数，
Figure PCTCN2022102607-appb-000008
为频率阻尼因数，提取波形数据的公式为s 1(t)＝8192-s(t)。
将提取的波形数据s 1(t)写入所述FPGA，通过FPGA驱动所述14位D/A转换器,阻尼振荡波形经滤波、运放加法运算后反相。
优选地，本发明的高分辨率变频阻尼振荡信号发生器，阻尼振荡波形反相后经过所述MOSFET开关输出，并经过RC滤波器后输出最终波形，所述RC滤波器的截止带宽为200MHz。
优选地，本发明的高分辨率变频阻尼振荡信号发生器，所述的高分辨率变频阻尼振荡信号发生器还包括MOSFET驱动电路，所述MOSFET驱动电路包括三极管、脉冲变压器、整流二极管，FPGA发出PWM信号控制三极管，三极管驱动脉冲变压器，脉冲变压器产生的方波脉冲经过整流二极管，在所述MOSFET开关的G极和S极之间产生驱动波形。
优选地，本发明的高分辨率变频阻尼振荡信号发生器，变频阻尼振荡信号的输出需要经过时序控制，所述时序控制如下。
设定FPGA开始驱动14位D/A转换器的时间为0，FPGA发出PWM信号的开始时间为T1，阻尼振荡波形输出的开始时间为T2，阻尼振荡波形输出的结束时间为T3，MOSFET绝对关断状态的时间为T4，其中T1通过 计算MOSFET驱动电路各个器件的时延确定，
FPGA在时间为0时开始驱动14位D/A转换器，在时间0～T2处，14位D/A转换器的输出波形保持初始值。
在T1和T2时间段之间，FPGA发出PWM信号，所述MOSFET开关在T2处开始输出阻尼振荡波形，并在T2时间达到峰值，在T3时FPGA停止发出PWM信号，在T4时FPGA驱动14位D/A转换器，把输出电平调为初始状态的值。
MOSFET开关输出阻尼振荡波形的时间段为T1～T3，其中T1～T2是波形前沿部分，T2～T3是波形后续部分。
优选地，本发明的高分辨率变频阻尼振荡信号发生器，所述MOSFET开关为SiC材料MOSFET。
本发明的有益效果是：本发明在使用低带宽器件(数据转换率100MHz)的前提下,实现了波形上升沿3.49ns的效果。使用了14位的D/A转换器，而常规设备使用的高速D/A最高是10位的，所以本发明的波形幅度的分辨率是普通设备的2^14/2^10＝16倍，这很好的保证了输出波形低压、低频时波形的精度，使得测试效果一致性更好。
由于本发明使用的器件工作频率相对较低，器件成本相对也很低，而且这个工作频率可以使用双面板，不像高速器件那样要使用多层板，使开发难度大幅降低，加工工艺简单、易实现。总体核算，成本只有高速器件方案的20％，大大降低了生产成本。
附图说明
下面结合附图和实施例对本申请的技术方案进一步说明。
图1是本申请实施例的结构原理图；
图2是本申请实施例的结构原理图对应的时序控制模拟波形图；
图3是本申请实施例最终输出的波形图。
具体实施方式
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
下面将参考附图并结合实施例来详细说明本申请的技术方案。
实施例
本实施例提供一种高分辨率变频阻尼振荡信号发生器，原理图如图1所示，包括：包括FPGA，14位D/A转换器，MOSFET开关，所述FPGA接收外部传送的阻尼振荡波形数据,以100MHz的转换率通过所述14位D/A转换器把数据转换成模拟波形,再通过滤波、运放处理，通过MOSFET开关输出。
本实施例的高分辨率变频阻尼振荡信号发生器，外部传送的阻尼振荡波形数据进入FPGA前，首先需要进行数据提取，数据提取方法如下：
使用Matlab软件根据吉利标准CEVT8888790454-1中的公式
Figure PCTCN2022102607-appb-000009
提取阻尼振荡波形数据，其中，p 1为峰值电流幅度，p 2为时间常数，
Figure PCTCN2022102607-appb-000010
为初始上升沿时间，p 3为初始频率，p 4为幅度衰减常 数，p 5为频率衰减常数，
Figure PCTCN2022102607-appb-000011
为幅度阻尼因数，
Figure PCTCN2022102607-appb-000012
为频率阻尼因数。
因为本系统使用的D/A转换器是14位的，为了保证波形的完整性，14位的波形数据需要给正、负峰各自预留50％，即2^13＝8192，所以提取数据时系数取值为：p 1取值8192，时间t步进率为10ns，步进段数为2000,提取波形数据的公式为s 1(t)＝8192-s(t),这样是为了把14位D/A转换器的输出波形反相。
提取后的数据还需要经过以下方式处理：波形数据数组的第一个数据用峰值取代，这样做的目的是为了让14位D/A转换器输出的波形起点在峰值，而不是在中间值，以便在后面运放处调节波形。
本实施例选用的FPGA器件内含锁相环、双向RAM以及PCI标准接口，本实施例图1中的外部通讯接口即PCI标准接口。外部的控制器通过PCI接口把数据数组s 1(t)写入FPGA的双向RAM，使用双向RAM可以同时写入和读取数据，保证数据传输的时效性，FPGA通过内部锁相环和计数器，以100MHz的速率驱动14位D/A转换器，经过R1和C1组成的RC滤波电路，在图1的14位D/A转换器输出端①得到的波形如图2的波形①。图1中14位D/A转换器输出端①的波形和R3输入端②电压-U0的波形通过运放做加法运算，R3输入端②电压-U0的波形如图2中的波形②，根据公式：
U3/R4＝-(U1/R2+U2/R3),
取R2＝R3＝R4，则U3＝-U1-U2,其中，U1为14位D/A转换器输出端①的波形，U2为R3输入端②电压-U0的波形，U3为运放输出端③的波形， U3对应的波形如图2的波形③。运放加法运算的作用是把14位D/A转换器输出端①处波形由基准电压U0降为0V，并把波形反向。
加速前沿处理是本实施例实现阻尼振荡波形上升沿3.49ns的关键之处，具体操作如下：使用MOSFET作为开关，开关导通后，由R5和C2组成RC滤波，在图1的MOSFET开关的S极④处产生最终输出的阻尼振荡波形，对应图2中波形④。波形的上升沿取决于RC滤波和MOSFET开关的速度，RC滤波器的参数选择截止带宽200MHz左右，可以对波形上升沿起到滤波效果，又不会对后面的波形产生影响，因为后续波形频率<3MHz,远小于截止频率。
普通MOSFET的开通速度很难达到5ns，本实施例选用了一款输入电容低的SiC材料的MOSFET开关，导通速度可以达到2ns。
本实施例的高分辨率变频阻尼振荡信号发生器还包括MOSFET驱动电路，所述MOSFET驱动电路包括三极管、脉冲变压器T、整流二极管，FPGA发出PWM信号控制三极管，所述PWM信号对应图2中的波形⑤，三极管驱动脉冲变压器，脉冲变压器采用15V供电可以在变压器次级产生15V的方波脉冲信号，这个电平可以有效地驱动MOSFET且不会损坏MOSFEET。驱动脉冲变压器产生的方波脉冲经过整流二极管，在所述MOSFET开关的G极和S极之间产生驱动波形，对应图2中的波形⑥；当MOSFET开关的G极和S极之间电压幅度大于10V时，MOSFET开关可以维持导通，所以需要调整PWM信号的占空比，使整流二极管⑥处产生的锯齿波最低幅度不小于10V。
此外，本实施例的变频阻尼振荡信号的输出需要经过时序控制， 所述时序控制如下：
设定FPGA开始驱动14位D/A转换器的时间为0，FPGA发出PWM信号的开始时间为T1，阻尼振荡波形输出的开始时间为T2，阻尼振荡波形输出的结束时间为T3，MOSFET绝对关断状态的时间为T4，其中T1通过计算MOSFET驱动电路各个器件的时延确定。
FPGA在时间为0时开始驱动14位D/A转换器，根据s 1(t)的数据处理方法，在时间0～T2处，14位D/A转换器的输出波形U1保持初始值，如图2中的波形①。运放输出波形U3和14位D/A转换器的输出波形U1时序上保持一致。
为了使MOSFET开关的S极④处产生的阻尼振荡波形在T2时间达到峰值，需要在T2之前给出开关的驱动信号，信号给的过早，会导致输出波形在峰值处有平顶现象；信号给的晚，会导致输出波形峰值不能达到最大值。
因此，T2时间之前，FPGA发出PWM信号，所述MOSFET开关在T2处开始输出阻尼振荡波形，如图2中的波形④，并在T2时间达到峰值，在T3时FPGA停止发出PWM信号，在T4时FPGA驱动14位D/A转换器，把输出电平调为初始状态的值。此外，可以通过FPGA内部锁相环调节延时，保证给出PWM驱动信号的时间精度。
由于T4时间MOSFET开关处于断开状态，运放输出端③的波形变化不会影响MOSFET开关的S极④处波形。MOSFET开关输出阻尼振荡波形的时间段为T1～T3，其中T1～T2是波形前沿部分，T2～T3是波形后续部分。
MOSFET开关的S极④处波形经过电阻R6后输出，最终输出的变频阻尼振荡波形如图3所示。
以上述依据本申请的理想实施例为启示，通过上述的说明内容，相关工作人员完全可以在不偏离本项申请技术思想的范围内，进行多样的变更以及修改。本项申请的技术性范围并不局限于说明书上的内容，必须要根据权利要求范围来确定其技术性范围。

Claims (6)

  1. 一种高分辨率变频阻尼振荡信号发生器，其特征在于，包括FPGA，14位D/A转换器，MOSFET开关，所述FPGA接收外部传送的阻尼振荡波形数据,以100MHz的转换率通过所述14位D/A转换器把阻尼振荡波形数据转换成模拟波形,再通过滤波、运放处理，通过MOSFET开关输出。
  2. 根据权利要求1所述的高分辨率变频阻尼振荡信号发生器，其特征在于，外部传送的阻尼振荡波形数据进入FPGA前，需要进行数据提取，数据提取方法如下：
    根据公式：
    Figure PCTCN2022102607-appb-100001
    提取阻尼振荡波形数据，其中，p 1为峰值电流幅度，p 2为时间常数，
    Figure PCTCN2022102607-appb-100002
    为初始上升沿时间，p 3为初始频率，p 4为幅度衰减常数，p 5为频率衰减常数，
    Figure PCTCN2022102607-appb-100003
    为幅度阻尼因数，
    Figure PCTCN2022102607-appb-100004
    为频率阻尼因数，提取波形数据的公式为s 1(t)＝8192-s(t)；
    将提取的波形数据s 1(t)写入所述FPGA，通过FPGA驱动所述14位D/A转换器,阻尼振荡波形经滤波、运放加法运算后反相。
  3. 根据权利要求2所述的高分辨率变频阻尼振荡信号发生器，其特征在于，阻尼振荡波形反相后经过所述MOSFET开关输出，并经过RC滤波器后输出最终波形，所述RC滤波器的截止带宽为200MHz。
  4. 根据权利要求1所述的高分辨率变频阻尼振荡信号发生器，其特征在于，所述的高分辨率变频阻尼振荡信号发生器还包括MOSFET驱动电路，所述MOSFET驱动电路包括三极管、脉冲变压器、整流二极 管，FPGA发出PWM信号控制三极管，三极管驱动脉冲变压器，脉冲变压器产生的方波脉冲经过整流二极管，在所述MOSFET开关的G极和S极之间产生驱动波形。
  5. 根据权利要求4所述的高分辨率变频阻尼振荡信号发生器，其特征在于，变频阻尼振荡信号的输出需要经过时序控制，所述时序控制如下：
    设定FPGA开始驱动14位D/A转换器的时间为0，FPGA发出PWM信号的开始时间为T1，阻尼振荡波形输出的开始时间为T2，阻尼振荡波形输出的结束时间为T3，MOSFET绝对关断状态的时间为T4，其中T1通过计算MOSFET驱动电路各个器件的时延确定；
    FPGA在时间为0时开始驱动14位D/A转换器，在时间0～T2处，14位D/A转换器的输出波形保持初始值；
    在T2时间之前，FPGA发出PWM信号，所述MOSFET开关在T2处开始输出阻尼振荡波形，并在T2时间达到峰值，在T3时FPGA停止发出PWM信号，在T4时FPGA驱动14位D/A转换器，把输出电平调为初始状态的值；
    MOSFET开关输出阻尼振荡波形的时间段为T1～T3，其中T1～T2是波形前沿部分，T2～T3是波形后续部分。
  6. 根据权利要求1-5任一项所述的高分辨率变频阻尼振荡信号发生器，其特征在于，所述MOSFET开关为SiC材料MOSFET。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1135684A (en) * 1966-11-09 1968-12-04 Standard Telephones Cables Ltd Analogue-to-digital converters
CN2672660Y (zh) * 2003-12-05 2005-01-19 华为技术有限公司 一种产生模拟阻尼振荡波的电路
CN102230914A (zh) * 2011-03-31 2011-11-02 厦门安锐捷电子科技有限公司 一种基于电磁谐振的金属材料的无损检测方法
CN208334443U (zh) * 2018-05-04 2019-01-04 珠海华网科技有限责任公司 高压振荡波发生器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1135684A (en) * 1966-11-09 1968-12-04 Standard Telephones Cables Ltd Analogue-to-digital converters
CN2672660Y (zh) * 2003-12-05 2005-01-19 华为技术有限公司 一种产生模拟阻尼振荡波的电路
CN102230914A (zh) * 2011-03-31 2011-11-02 厦门安锐捷电子科技有限公司 一种基于电磁谐振的金属材料的无损检测方法
CN208334443U (zh) * 2018-05-04 2019-01-04 珠海华网科技有限责任公司 高压振荡波发生器

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