WO2023236103A1

WO2023236103A1 - Method of metal integration for fabricating integrated device

Info

Publication number: WO2023236103A1
Application number: PCT/CN2022/097621
Authority: WO
Inventors: Yijian Chen; Daniele Leonelli; Yanxiang Liu
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2022-06-08
Filing date: 2022-06-08
Publication date: 2023-12-14

Abstract

The fabrication of integrated devices, for example, integrated semiconductor devices is disclosed. The method for metal integration can be used in a process flow for fabricating such an integrated device. The method is based on patterning different spacers and defining different metal structures using the spacers in two separated steps. In particular, metal structures of a first metal material (61) are processed in a different step than metal structure of a second metal material (91).

Description

A METHOD OF METAL INTEGRATION FOR FABRICATING AN INTEGRATED DEVICE

TECHNICAL FIELD

The present disclosure relates to the fabrication of integrated devices, for example, of integrated semiconductor devices. The disclosure presents a method for metal integration, which can be used in a process flow for fabricating such an integrated device.

BACKGROUND

Advanced back end of line (BEOL) patterning in a process flow for fabricating an integrated device may use a metal pitch of less than 21 nm. For such advanced patterning, the edge placement error (EPE) is critical, and full self-aligned vias are required to ensure robust connections between different metal levels. However, it may be observed that there is no sufficient EPE margin for such advanced patterning when deep ultraviolet (DUV) patterning technologies are used, because it is not possible to scale the EPE margin below 5 nm due to intrinsic technology limitations.

Besides the metal lines scaling, one of the major bottlenecks in BEOL functionality is the via patterning and its alignment. Several examples of self-aligned via and fully self-aligned-via (FSAV) schemes have been implemented by major foundries, in order to mitigate the EPE limit. All implemented solutions use a single hard mask material. The solutions may achieve good results down to the 5 nm node (with a metal pitch of 28 nm) , but only if extreme ultraviolet (EUV) technology is implemented. This is, because of the single hard mask material used for protecting neighboring metal lines and relaxing the EPE requirements. However, there is no solution for metal pitches smaller than 21 nm, because it is hard to achieve the EPE below 5 nm.

SUMMARY

In view of the above, this disclosure aims to provide an improved solution for metal integration, which can be used in a process flow for fabricating integrated devices. An objective is to provide a solution for various metal pitches, as an example, also for metal pitches below 21 nm. An additional objective is to address situations where the EPE margin is below 5 nm.

These and other objectives are achieved by the solution of this disclosure as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

This disclosure proposes a dual material hardmask process for metal integration, which allows a protecting for neighboring metal lines during the BEOL metallization process.

A first aspect of this disclosure provides a method of metal integration for fabricating an integrated device, the method comprising forming a first structure and a second structure from a common layer on a substrate, wherein the first structure and the second structure are separated from each other along a first direction and extend each into a second direction; forming a first spacer and a second spacer on the substrate, wherein the first spacer and the second spacer extend each into the second direction, the first spacer lining the first structure on two sides of the first structure, and the second spacer lining the second structure on two sides of the second structure; forming a third spacer and a fourth spacer on the substrate, wherein the third spacer and the fourth spacer extend each into the second direction, the third spacer lining the first spacer on two sides of the first spacer, and the fourth spacer lining the second spacer on two sides of the second spacer; forming a fifth spacer between the third spacer and the fourth spacer; forming a plurality of first gaps by selectively removing the third spacer, the fourth spacer, the first structure, and the second structure; depositing a first metal material into the first gaps; forming a plurality of second gaps by selectively removing the first spacer and the second spacer; depositing a first dielectric material into the second gaps; forming a plurality of trenches in the first dielectric material in the second gaps; and depositing a second metal material into the trenches.

The first structure and the second structure may be repeated at given pitch. The first structure and the second structure may be part of a unit cell of the integrated device, wherein the unit cell may be repeated one or more times. The first structure may be a first conductive structure, for instance, a first metal structure. The second structure may be a second conductive structure, for instance, a second metal structure. The first structure and the second structure may accordingly be made from the same conductive layer, for instance, a metal layer. The first structure and the second structure may also be nitride-based structures, for example, silicon nitride structures, or may be carbon-based structures, for example, amorphous carbon (a-C) structures.

By forming the various spaces, and by using these spacers to process structures from the first metal material and the second metal material, respectively, a solution for various metal pitches is enabled, also for metal pitches below 21 nm. DUV technology may be used, EUV technology being possible but not required.

In an implementation form of the first aspect, the method further comprises, after selectively removing the third spacer, the fourth spacer, the first structure, and the second structure: depositing a first filler material into the first gaps; and removing the first filler material to reopen the first gaps; wherein the first metal material is deposited into the reopened first gaps.

In an implementation form of the first aspect, the method further comprises, before selectively removing the first spacer and the second spacer: selectively forming one or more openings in the third spacer, or in the fourth spacer, or in the first filler material, respectively; and extending the openings into the substrate; wherein the depositing of the first metal material into the first gaps includes depositing the first metal material into the openings that extend into the substrate, in order to form one or more first vias.

The first vias can accordingly be processed in a self-aligned manner.

In an implementation form of the first aspect, the method further comprises, before depositing the second metal material into the trenches: extending one or more of the trenches through the first dielectric material and into the substrate; wherein the depositing of the second metal material into the trenches includes depositing the second metal material into the trenches that extend into the substrate, in order to form one or more second vias.

The second vias can accordingly be processed in a self-aligned manner.

In an implementation form of the first aspect, the one or more openings are formed in the third spacer, or in the fourth spacer, or in the first filler material by: lithographic patterning; a first selective etch of the third spacer, or the fourth spacer, or the first filler material, to form the one or more openings; and a second selective etch of the substrate to extend the one or more openings into the substrate.

In an implementation form of the first aspect, the method further comprises, before selectively removing the third spacer or the fourth spacer, or before removing the first filler material: covering a part of the third spacer, or of the fourth spacer, or of the first filler material with a protective layer, in order to prevent the removal of this part of the third spacer, or the fourth spacer, or the first filler material.

In an implementation form of the first aspect, the method further comprises, before selectively removing the first spacer and the second spacer: recessing the first metal material in the first gaps; and depositing a first hard mask material into the first gaps onto the recessed first metal material.

In an implementation form of the first aspect, the one or more trenches are extended into the substrate by: depositing a second filler material into the plurality of trenches; lithographic patterning; a first selective etch of the second filler material in the one or more trenches; a second selective etch of the dielectric material to extend the one or more trenches through the dielectric material and into the substrate; and removing the second filler material.

In an implementation form of the first aspect, the method further comprises, after depositing the second metal material into the trenches: selectively removing a part of the second metal material; and depositing a second dielectric material to where the second metal material was selectively removed.

In an implementation form of the first aspect, the selectively removing of the part of the second metal material comprises: lithographic patterning to expose only the part of the second metal material; and a selective metal etch of the exposed second metal material.

In an implementation form of the first aspect, the method comprises, before depositing the second metal material into the trenches: forming a third dielectric material in a part of the trenches, in order to prevent the deposition of the second metal material into this part of the trenches.

In an implementation form of the first aspect, the method further comprises: recessing the exposed second metal material; and depositing a second hard mask material onto the recessed second metal material.

In an implementation form of the first aspect a material of the first spacer and the second spacer on the one hand, and a material of the third spacer and the fourth spacer on the other hand, are different materials; and/or the first metal material and the second metal material are different materials.

In an implementation form of the first aspect, the first metal material and/or the second metal material comprises at least one of ruthenium, copper, molybdenum, cobalt, and tungsten.

In an implementation form of the first aspect, the method further comprises, the substrate comprises at least one of a middle of line (MOL) and BEOL layer.

In an implementation form of the first aspect, the first dielectric material comprises silicon nitride and/or a dielectric used in the MOL layer.

In an implementation form of the first aspect, the substrate comprises one or more integrated electrical circuits; and the first structure and/or the second structure is a power rail of at least one of the integrated electrical circuits in the substrate.

A second aspect of this disclosure provides an integrated device obtainable by the method according to the first aspect or any implementation form of the first aspect.

The integrated device of the second aspect may have a metal pitch below 21 nm. However, also other metal pitches, for example, metal pitches below 32 nm are possible.

According to the above, the solution of this disclosure proposes a new metal integration scheme, which allows to fabricate different metal structures (e.g., narrow metal lines) with a small metal pitch below 21 nm, even when using DUV technology not EUV technology. This is, in particular, achieved by implementing the novel spacer-defined patterning scheme (using the first to fifths spacers) to define the metal structures in two separated steps. The first metal material may be etched (or trench filled) and the second metal material may be defined by a metal fill process in a different step. After the metal deposition, the metals may be recessed or an area selective deposition (ASD) can be implemented to define two separated materials for hard masks utilized for the FSAV process.

The solution of this disclosure provides at least the following advantages:

● Narrow metal structures can be integrated using DUV, which can be achieved by separating the integration of the first metal material and the second metal material in two separated process sequences.

● The EPE margin can be improved for advanced BEOL metallization (e.g., for metal pitch below 21 nm) , which may be achieved by using a different material hard mask on top of neighboring metal structures, so that it is possible to achieve a real FSAV thanks to a high etch selectivity of the hard mask materials.

● The metal structure capacitances can be reduced, since the neighboring metal structures may be not on the same level, but may be slightly staggered or with marginal overlap at the side.

BRIEF DESCRIPTION OF DRAWINGS

The above described aspects and implementation forms will be explained in the following description of embodiments in relation to the enclosed drawings, in which

FIG. 1-9 show a method for fabricating an integrated device according to this disclosure.

FIG. 10-29 show a first exemplary method for fabricating an integrated device according to this disclosure.

FIG. 30-49 show a second exemplary method for fabricating an integrated device according to this disclosure

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1-9 shows a method for fabricating an integrated device according to this disclosure. In particular, consecutive processing steps of the method are shown. Each figure shows an intermediate state of the integrated device after the processing step, respectively, performed in this figure. All figures show a sectional view of the integrated device, wherein the integrated device is illustrated along the x-axis (x-direction) and z-axis (z-direction) as indicated by the coordinate system in the lower left corner of the figures. Some of the figures also show a top view of the integrated device, wherein the integrated devices is illustrated along the x-axis (x-direction) and y-axis (y-direction) of the coordinate system, as indicated in the upper left corner of the figures.

FIG. 1 shows that in a first step of the method, a first structure 11 and a second structure 11 are formed from a common layer on a substrate 13. The first structure 11 and the second structure 12 may be made of metal, or silicon nitride, or amorphous carbon, and are separated from each other along a first direction, (the x-direction in the coordinate system indicated on the lower left) , and extend each into a second direction (the y-direction) . The first structure 11 and the second structure 12 may define a core of the integrated device. The substrate 13 may comprise an interlayer dielectric, which is arranged on a semiconductor substrate, for instance, a silicon-based substrate or an amorphous silicon substrate.

A minimum feature size of the method may be defined as F. As shown in FIG. 1, the first structure 11 and the second structure 12 may, respectively, have width (along the first direction) of 3F. A pitch between the first structure 11 and the second structure 12 may be 14F, with an 11F distance between these metal structures. Notably, more than two

metal structures

11, 12 can be fabricated in this way, for example, a plurality of

metal structures

11, 12 arranged with the pitch mentioned. The method may show any two

metals structures

11, 12 of this plurality of

metal structures

11, 12. Notably, the first structure 11 and the second structure 12 may be formed by resist deposition, then lithography (exposure) , then resist development, and then a pattern transfer to the underneath substrate 13.

FIG. 2 shows that in a further step of the method, a first spacer 21 and a second spacer 22 are formed on the substrate 13. The first spacer 21 and the second spacer 22 each extend into the second direction. The first spacer 21 lines the first structure 11 on two sides of the first structure 11, e.g., the first spacer 21 sandwiches the first structure 11 in the first direction. The second spacer 22 lines the second structure 12 on two sides of the second structure 12, e.g., the second spacer 22 sandwiches the second structure 12 in the first direction. The first and

second spacer

21, 22 may be formed by deposition of a spacer material and subsequent etch of that spacer material. The first spacer 21 and the second spacer 22 may have a width in the first direction of 3F on each side of the first structure 11 and the second structure 12, respectively.

FIG. 3 shows that in a further step of the method, a third spacer 31 and a fourth spacer 32 are formed on the substrate 13. The third spacer 31 and the fourth spacer 32 extend each into the second direction. The third spacer 31 lines the first spacer 21 on two sides of the first spacer 21, e.g., the third spacer 31 sandwiches the first spacer 21 and the first structure 11 in the first direction. The fourth spacer 32 lines the second spacer 22 on two sides of the second spacer 22, e.g., the fourth spacer 32 sandwiches the second spacer 22 and the second structure 12 in the first direction. The third and

fourth spacer

31, 32 may be formed by deposition of a second spacer material and subsequent etch of that second spacer material. The third spacer 31 and the fourth spacer 32 may have a width in the first direction of 1F on each side of the first spacer 21 and the second spacer 22, respectively.

FIG. 4 shows that in a further step of the method, a fifth spacer 41 is formed between the third spacer 31 and the fourth spacer 32 –and thereby also between the first spacer 21 and the second spacer 22, and between the first structure 11 and the second structure 12, respectively. In particular, the fifth spacer 41 can be formed by performing a gap fill, wherein all gaps on the substrate 13 are filled with, for instance, the same spacer material as used for the first spacer 21 and the second spacer 22. Then a planarization step (e.g., chemical mechanical polishing (CMP) ) may be performed to planarize the surface of the intermediate integrated device.

FIG. 5 shows that in a further step of the method, a plurality of first gaps 51 are formed by selectively removing the third spacer 31, the fourth spacer 32, the first structure 11, and the second structure 12. This step may be referred to as a spacer and core pull. FIG. 5 shows both the top view and sectional view of the intermediate integrated device, and the dashed line illustrates the position of the cut for the sectional view. This is the same in all other figures which show both views.

FIG. 6 shows that in a further step of the method, a first metal material 61 is deposited into the first gaps 51. The first metal material 61 may be referred to as metal A, and the step may comprise a metal A fill and subsequent CMP.

FIG. 7 shows that in a further step of the method, a plurality of second gaps 71 are formed by selectively removing the first spacer 21 and the second spacer 22. This step may this be referred to as a spacer pull step. The second gaps 71 are formed between the locations where the first metal material 61 has been deposited.

FIG. 8 shows that in a further step of the method, a first dielectric material 81 is deposited into the second gaps 71, and that a plurality of trenches 82 are formed in the first dielectric material 81 in the second gaps 71. The trenches 82 may each extend into the second direction, and may be formed in between the locations (in the first direction) where the first material 61 has been deposited.

FIG. 9 shows that in a further step of the method, a second metal material 91 is deposited into the trenches 82. The second metal material 91 may be referred to as metal B, and the step may comprise a metal B fill and subsequent CMP.

It can be seen from the figures illustrating the method, that a pitch between all metal structures (formed by the metal A and the metal B, respectively) in the intermediate integrated device shown in FIG. 9 is much smaller than the initial pitch of 14F. The pitch after the step of FIG. 9 may, for example, be 3F.

FIG. 10-29 show a first exemplary method for fabricating an integrated device according to this disclosure, in particular, show steps that happen after the steps of the method shown in FIG. 1-4. That, is the first exemplary method comprises the steps shown in FIG. 1-4 and the steps shown in FIG. 10-29. A repeated description of the former is omitted.

FIG. 10 shows that in a further step of the first exemplary method, a lithographic patterning is performed. The lithographic patterning may be referred to as via patterning, since it may be used for patterning one or more first vias. In particular, the intermediate integrated device is covered with a resist 101 or the like, which is then selectively developed and removed to open a certain area 102 of the underlying device for further processing. For instance, as shown, a part of the first spacer 21 and the third spacer 31 is exposed. It is also possible to expose a part of the second spacer 22 and the fourth spacer 32 in a similar manner (not shown) .

FIG. 11 shows that in a further step of the first exemplary method, one or more openings 121 in the third spacer 31 (as shown) and/or in the fourth spacer 32 (not shown) are formed. For instance, a first selective etch of the third spacer 31 and/or of the fourth spacer 32 may be performed to form the one or more openings 121. The one or more openings 121 may each expose the substrate 13. The one or more openings 121 may be referred to as via openings, as their purpose may be to form one or more first vias as described in the following.

FIG. 12 shows that in a further step of the first exemplary method, the openings 121 are extended into the substrate 13. For instance, a second selective etch of the substrate 13 may be carried out, in order to extend the one or more openings 121 into the substrate 13. The purpose may be to form one or more first vias into the substrate 13.

FIG. 13 shows that in a further step of the first exemplary method, the resist 101 is removed, and then a part of the third spacer 31 and/or of the fourth spacer 32 (both shown) is covered with a protective layer 131, in order to prevent the removal of this part of the third spacer 31 and/or the fourth spacer 32, respectively, in a subsequent next step. The current step may be referred to as block patterning.

FIG. 14 shows that in a further step of the first exemplary method, the plurality of first gaps 51 is formed by selectively removing the third spacer 31, the fourth spacer 32, the first structure 11, and the second structure 12. This step may be referred to as a spacer and core pull. Notably, the protective layer 131 prevents the part of the third spacer 31 and/or the second spacer 32 from being removed.

FIG. 15 shows that in a further step of the first exemplary method, the first metal material 61 is deposited into the first gaps 51. As can be seen, the depositing of the first metal material 61 into the first gaps 51 includes depositing the first metal material 61 into the openings 121 that extend into the substrate 13. This may form one or more first vias.

FIG. 16 shows that in a further step of the first exemplary method, the first metal material 61 (which has been deposited into the first gaps 51) may be recessed (in direction towards the substrate 13) . This step may thus be referred to as metal A recess.

FIG. 17 shows that in a further step of the first exemplary method 10, a first hard mask material 171 is deposited onto the recessed first metal material 61. This step may be referred to as hard mask A formation or hardmask A selective area deposition. Notably, the first hard mask material 171 may not be formed on, or may be removed from, the remaining part of the third spacer 31 or the fourth spacer 32.

FIG. 18 shows that in a further step of the first exemplary method, a plurality of second gaps 71 are formed by selectively removing the first spacer 21 and the second spacer 22, which is arranged between the first metal material 61 and hard mask material 171. This step may be referred to as a spacer pull step. Also the remaining part of the third spacer 31 and fourth spacer 32 may be removed in this step. The selective removal may be carried out by selective etching of the respective materials.

FIG. 19 shows that in a further step of the first exemplary method, the first dielectric material 81 is deposited into the second gaps 71. Further, the plurality of trenches 82 are formed in the first dielectric material 81 (which has been deposited into the second gaps 71) , for instance, by etching the first dielectric material 81.

FIG. 20 shows that in a further step of the first exemplary method, a filler material 201 is deposited into the plurality of trenches 82. This step may be referred to as filler and via B patterning. The patterning may comprise providing a mask material 202 onto one or more areas each above one of the trenches 82 (one is shown) . This may be used for patterning one or second vias as described in the following.

FIG. 21 shows that in a further step of the first exemplary method, lithographic patterning is performed. This lithographic patterning may include applying a resist 101 over the surface of the intermediate integrated device (which is not formed where the mask material 202 was arranged) , and removing the mask material 202 to expose the previously covered area via a mask opening, which particularly exposes one or more trenches 82. Further, a first selective etch of the filler material 201 may be performed in the exposed one or more trenches 82, in order to remove the filler material 201 from these one or more trenches 82.

FIG. 22 shows that in a further step of the first exemplary method, a second selective etch of the exposed and etched dielectric material 81 may be performed to extend the one or more trenches 82 through the dielectric material 81 and into the substrate 13. This may be referred to as via B etch.

FIG. 23 shows that in a further step of the first exemplary method, the resist 101 is removed and the filler material 201 is removed.

FIG. 24 shows that in a further step of the first exemplary method, the second metal material 91 is deposited into the trenches 82. Afterwards a planarization step may be performed. This may be referred to as metal B Fill followed by CMP. The second material 91 in the one or more trenches 82, which have been extended into the substrate 13, may form one or more second vias.

FIG. 25 shows that in a further step of the first exemplary method, lithographic patterning is performed to expose only a part 251 of the second metal material 91.

FIG. 26 shows that in a further step of the first exemplary method, the part 251 of the second metal material 91 that was exposed is selectively removed. This may be referred to as a self-aligned cut of metal B by direct metal etch (DME) . The dielectric material 81 under the removed second metal material 91 may be laid free.

FIG. 27 shows that in a further step of the first exemplary method, a second dielectric material 271 is deposited to where the second metal material 91 was selectively removed.

FIG. 28 shows that in a further step of the first exemplary method, the exposed second metal material 91 may be recessed in direction of the substrate 13. This may be referred to as metal B recess.

FIG. 29 shows that in a further step of the first exemplary method, a second hard mask material 291 is deposited onto the recessed second metal material 91. This may be referred to as hard mask B formation or hard mask B selective area deposition.

FIG. 30-49 show a second exemplary method for fabricating an integrated device according to this disclosure, in particular, show steps that happen after the steps of the method shown in FIG. 1-4. That, is the second exemplary method comprises the steps shown in FIG. 1-4 and the steps shown in FIG. 30-49. A repeated description of the former is omitted.

FIG. 30 shows that in a further step of the second exemplary method, the third spacer 31 and the fourth spacer 32, and the first structure 11 and the second structure 12 are selectively removed, respectively, wherein a plurality of first gaps 51 are formed above the substrate 13.

FIG. 31 shows that in a further step of the second exemplary method, a filler material 311 is deposited into the first gaps 51, particularly, between the first and

second spacer

21, 22. This may be followed by CMP.

FIG. 32 shows that in a further step of the second exemplary method, lithographic patterning is performed. The lithographic patterning may be referred to as via patterning, since it may be used for patterning one or more first vias. In particular, the intermediate integrated device is covered with a resist 101 or the like, which is then selectively developed and removed to open a certain area 321 of the underlying device for further processing. For instance, as shown, a part of the first spacer 21 and the filler material 311 (where the third spacer 31 was before) is exposed. It is also possible to expose another part of the filler material 311 (where the fourth spacer 32 may before) in a similar manner.

FIG. 33 shows that in a further step of the second exemplary method, one or more openings 121 are selectively formed in the filler material 311. For instance, a first selective etch of the filler material 311 may be performed, in order to form the one or more openings 121. These may be referred to as via openings, as their purpose may be fabricating the first vias.

FIG. 34 shows that in a further step of the second exemplary method, the openings 121 are extended into the substrate 13. For example, a second selective etch of the substrate 13 may be performed to extend the one or more openings 121 into the substrate 13. This may be referred to as via etch for the first vias.

FIG. 35 shows that in a further step of the second exemplary method, the resist 101 is removed and a part of the filler material 311 may be covered with a protective layer 131, in order to prevent the removal of this part of the filler material 311 in a subsequent step. The current step may be referred to as block patterning.

FIG. 36 shows that in a further step of the second exemplary method, the filler material 311 is removed to reopen the first gaps 51. For instance, the filler material 311 may be selectively etched. The protective layer 131 is then removed, and the previously covered filler material 311 remains.

FIG. 37 shows that in a further step of the second exemplary method, the first metal material 61 is deposited into the reopened first gaps 51. The depositing of the first metal material 61 into the reopened first gaps 51 includes depositing the first metal material 61 into the openings 121 that extend into the substrate 13, in order to form one or more first vias. Then, a planarization like CMP may be performed.

FIG. 38 shows that in a further step of the second exemplary method, the first metal material 61 in the first gaps 51 is recessed in direction of the substrate 13.

FIG. 39 shows that in a further step of the second exemplary method, the first hard mask material 171 is deposited onto the recessed first metal material 61.

FIG. 40 shows that in a further step of the second exemplary method, the plurality of second gaps 71 are formed by selectively removing the first spacer 21 and the second spacer 22. This may be referred to as spacer pull.

FIG. 41 shows that in a further step of the second exemplary method, the first dielectric material 81 is deposited into the second gaps 71. Further, the plurality of trenches 82 are formed in the first dielectric material 81 deposited into the second gaps 71. For instance, a selective etch of the dielectric material 81 may form the one or more trenches 82.

FIG. 42 shows that in a further step of the second exemplary method, a filler material 201 is deposited into the plurality of trenches 82. Further lithographic patterning is performed. This lithographic patterning may include applying a resist 101 over the surface of the intermediate integrated device and exposing, by forming a mask opening 42 in the resist 101, one or more of the trenches 82 that are filled with the filler material 201.

FIG. 43 shows that in a further step of the second exemplary method, a first selective etch of the filler material 201 in the one or more exposed trenches 82 may be performed, in order to remove the filler material 202 from these one or more trenches 82.

FIG. 44 shows that in a further step of the second exemplary method, a second selective etch of the dielectric material 81 in the exposed one or more trenches 82 may be performed to extend the one or more trenches 82 through the dielectric material 81 and into the substrate 13. This may be referred to as a via etch for the second vias.

FIG. 45 shows that in a further step of the second exemplary method, the resist 101 is removed and a third dielectric material 451 may be provided over a part of one or more the trenches 82 filled with filler material 201.

FIG. 46 shows that in a further step of the second exemplary method, the filler material 201 is removed. However, in the a part of one or more the trenches 82 filled with filler material 201 covered with the third dielectric material 451, the removal of the filler material 201 is prevented, and the filler material 201 remains after the third dielectric material 451 is removed.

FIG. 47 shows that in a further step of the second exemplary method, the second metal material 91 is deposited into the trenches 82. The deposition of the second metal material 91 into the part of the trenches 82 where the filler material 201 remains is prevented. The deposition of the second metal material 91 into the trenches 82 that are extended into the substrate 13 forms the second vias. Then, a CMP may be performed.

FIG. 48 shows that in a further step of the second exemplary method, the exposed second metal material 91 may be recessed in direction of the substrate 13.

FIG. 49 shows that in a further step of the second exemplary method, a second hard mask material 291 is deposited onto the recessed second metal material 91.

In all the above methods, which were described with respect to FIGs. 1-9, FIGs. 10-29, and FIGs. 30-49, respectively, a material of the first spacer 21 and the second spacer 22 on the one hand, and a material of the third spacer 31 and the fourth spacer 33 on the other hand, may be different materials. The first spacer 21 and the second spacer 22 are made of the same material. Also the third spacer 31 and the fourth spacer 32 may be made of the same material. The

spacers

21, 22, 31, 32 may, respectively, be made of an oxide (e.g., silicon oxide or titanium oxide) , or a nitride (e.g., silicon nitride) , or silicon germanium, or other suitable spacer material.

In all the above methods, which were described with respect to FIGs. 1-9, FIGs. 10-29, and FIGs. 30-49, respectively, the first metal material and the second metal material are different materials. For example, the first metal may comprise at least one of ruthenium, copper, molybdenum, cobalt, and tungsten. For example, the second metal material may comprise at least one of ruthenium, copper, molybdenum, cobalt, and tungsten

In all the above methods, which were described with respect to FIGs. 1-9, FIGs. 10-29, and FIGs. 30-49, respectively, the substrate 13 may comprise at least one of a MOL and a BEOL layer. Further, the first dielectric material 81 may comprise silicon nitride and/or may comprise a dielectric used in the MOL layer.

In all the above methods, which were described with respect to FIGs. 1-9, FIGs. 10-29, and FIGs. 30-49, respectively, the substrate 13 may comprise one or more integrated electrical circuits. Further, the first structure 11 and/or the second structure 12 may be a power rail of at least one of the integrated electrical circuits in the substrate 13.

The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

A method (10) of metal integration for fabricating an integrated device, the method (10) comprising

forming a first structure (11) and a second structure (12) from a common layer on a substrate (13) , wherein the first structure (11) and the second metal structure (12) are separated from each other along a first direction (x) and extend each into a second direction (z) ;

forming a first spacer (21) and a second spacer (22) on the substrate (13) , wherein the first spacer (21) and the second spacer (22) extend each into the second direction (z) , the first spacer (21) lining the first structure (11) on two sides of the first structure (11) , and the second spacer (22) lining the second structure (12) on two sides of the second structure (12) ;

forming a third spacer (31) and a fourth spacer (32) on the substrate (13) , wherein the third spacer (31) and the fourth spacer (32) extend each into the second direction (z) , the third spacer (31) lining the first spacer (21) on two sides of the first spacer (21) , and the fourth spacer (32) lining the second spacer (22) on two sides of the second spacer (22) ;

forming a fifth spacer (41) between the third spacer (31) and the fourth spacer (32) ;

forming a plurality of first gaps (51) by selectively removing the third spacer (31) , the fourth spacer (32) , the first structure (11) , and the second structure (12) ;

depositing a first metal material (61) into the first gaps (51) ;

forming a plurality of second gaps (71) by selectively removing the first spacer (21) and the second spacer (22) ;

depositing a first dielectric material (81) into the second gaps (71) ;

forming a plurality of trenches (82) in the first dielectric material (81) in the second gaps (7) ; and

depositing a second metal material (91) into the trenches (82) .
The method (10) according to claim 1, further comprising, after selectively removing the third spacer (31) , the fourth spacer (32) , the first structure (11) , and the second structure (12) :

depositing a first filler material (311) into the first gaps (51) ; and

removing the first filler material (311) to reopen the first gaps (51) ;

wherein the first metal material (61) is deposited into the reopened first gaps (51) .
The method (10) according to claim 1 or 2, further comprising, before selectively removing the first spacer (21) and the second spacer (22) :

selectively forming one or more openings (121) in the third spacer (31) , or in the fourth spacer (32) , or in the first filler material (311) , respectively; and

extending the openings (121) into the substrate (13) ;

wherein the depositing of the first metal material (61) into the first gaps (51) includes depositing the first metal material (61) into the openings (121) that extend into the substrate (13) , in order to form one or more first vias.
The method (10) according to one of the claims 1 to 3, further comprising, before depositing the second metal material (91) into the trenches (82) :

extending one or more of the trenches (82) through the first dielectric material (81) and into the substrate (13) ;

wherein the depositing of the second metal material (91) into the trenches (82) includes depositing the second metal material (91) into the trenches (82) that extend into the substrate (13) , in order to form one or more second vias.
The method (10) according to claim 3 or 4, wherein the one or more openings (121) are formed in the third spacer (31) , or in the fourth spacer (32) , or in the first filler material (311) by:

lithographic patterning;

a first selective etch of the third spacer (31) , or the fourth spacer (32) , or the first filler material (311) , to form the one or more openings (121) ; and

a second selective etch of the substrate (13) to extend the one or more openings (121) into the substrate (13) .
The method (10) according to one of the claims 2 to 5, further comprising, before selectively removing the third spacer (31) or the fourth spacer (32) , or before removing the first filler material (311) :

covering a part of the third spacer (31) , or of the fourth spacer (32) , or of the first filler material (311) with a protective layer (131) , in order to prevent the removal of this part of the third spacer (31) , or the fourth spacer (32) , or the first filler material (311) .
The method (10) according to one of the claims 1 to 6, further comprising, before selectively removing the first spacer (21) and the second spacer (22) :

recessing the first metal material (61) in the first gaps (51) ; and

depositing a first hard mask material (171) into the first gaps (51) onto the recessed first metal material (61) .
The method (10) according to one of the claims 4 to 7, wherein the one or more trenches (82) are extended into the substrate (13) by:

depositing a second filler material (201) into the plurality of trenches (82) ;

lithographic patterning;

a first selective etch of the second filler material (201) in the one or more trenches (82) ;

a second selective etch of the dielectric material (81) to extend the one or more trenches (82) through the dielectric material (81) and into the substrate (13) ; and

removing the second filler material (201) .
The method (10) according to one of the claims 1 to 8, further comprising, after depositing the second metal material (91) into the trenches (82) :

selectively removing a part of the second metal material (91) ; and

depositing a second dielectric material (271) to where the second metal material (91) was selectively removed.
The method (10) according to claim 9, wherein the selectively removing of the part of the second metal material (91) comprises:

lithographic patterning to expose only the part of the second metal material (91) ; and

a selective metal etch of the exposed second metal material (91) .
The method (10) according to one of the claims 1 to 8, comprising, before

depositing the second metal material (91) into the trenches (82) :

forming a third dielectric material (451) in a part of the trenches (82) , in order to prevent the deposition of the second metal material (91) into this part of the trenches (82) .
The method (10) according to one of the claims 9 or 11, further comprising:

recessing the exposed second metal material (91) ; and

depositing a second hard mask material (291) onto the recessed second metal material (91) .
The method (10) according to one of the claims 1 to 12, wherein:

a material of the first spacer (21) and the second spacer (22) on the one hand, and a material of the third spacer (31) and the fourth spacer (32) on the other hand, are different materials; and/or

the first metal material (61) and the second metal material (91) are different materials.
The method (10) according to one of the claims 1 to 13, wherein:

the first metal material (61) and/or the second metal material (91) comprises at least one of ruthenium, copper, molybdenum, cobalt, and tungsten.
The method (10) according to one of the claims 1 to 14, wherein:

the substrate (13) comprises at least one of a middle of line, MOL, and back end of line, BEOL, layer.
The method (10) according to one of the claims 1 to 15, wherein:

the first dielectric material (81) comprises silicon nitride and/or a dielectric used in the MOL layer.
The method (10) according to one of the claims 1 to 16, wherein:

the substrate (13) comprises one or more integrated electrical circuits; and

the first structure (11) and/or the second structure (12) is a power rail of at least one of the integrated electrical circuits in the substrate (13) .
An integrated device obtainable by the method (10) according to any one of the claims 1 to 17.