WO2023232251A1

WO2023232251A1 - Circuit for connecting two outputs of a differential amplifier to an input of a single-ended amplifier

Info

Publication number: WO2023232251A1
Application number: PCT/EP2022/065023
Authority: WO
Inventors: Federico VECCHI; Daniele MONTANARI; Filippo SCHEMBARI
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2022-06-02
Filing date: 2022-06-02
Publication date: 2023-12-07

Abstract

The present disclosure relates to a circuit (1) comprising a first terminal (T1) for a first output of a differential amplifier, a second terminal (T2) for a second output of the differential amplifier, a third terminal (T3) for an input of a single-ended amplifier, and three transistors each comprising a first terminal, a second terminal and a third terminal. The third terminal of a first transistor is connected to the first terminal of the circuit. The third terminal of a second transistor is connected to the second terminal of the circuit. The third terminal of a third transistor is electrically connected to the second terminal of the first transistor. The second terminal of the second transistor, the first terminal of the third transistor and the third terminal of the circuit are connected to a node. A transconductance of the second transistor equals a transconductance of the third transistor.

Description

CIRCUIT FOR CONNECTING TWO OUTPUTS OF A DIFFERENTIAE AMPUIFIER TO AN INPUT OF A SIN GEE-ENDED AMPLIFIER

TECHNICAL FIELD

The present disclosure relates to a circuit for connecting two outputs of a differential amplifier to an input of a single-ended amplifier, and relates to an amplifier circuit.

BACKGROUND

The present disclosure is in the field of electrically connecting outputs of a differential amplifier and an input of a single-ended amplifier with each other. For example, in some applications (e.g. PAM4 communications) it may be desired to provide a differential to single-ended conversion at some point of an amplifier chain, while maintaining high linearity.

SUMMARY

The following considerations are made by the inventors:

For electrically connecting an input of a single-ended amplifier to a differential amplifier, buffers may be inserted between outputs of the differential amplifier and the input of the single-ended amplifier. This may isolate the differential amplifier and the single-ended amplifier and may enhance bandwidth of the combination of the differential amplifier and single-ended amplifier. Such buffers may be implemented by bipolar junction transistors (BJTs) that may be connected to form an emitter follower or by fieldeffect transistors (FETs), such as metal-oxide-semiconductor FETs (MOSFETs), which may be connected to form a source follower. In this disclosure, the term “electrically connect” may be abbreviated by the term “connect”.

For example, the differential to single-ended conversion, i.e. connecting the input of the single-ended amplifier to the outputs of the differential amplifier, may be implemented by choosing one of the two outputs of the differential amplifier and connecting this output to the input of the single-ended amplifier, while leaving the other output of the two outputs of the differential amplifier floating.

The aforementioned strategy represents a simple way of performing a broadband differential to single- ended conversion. However, it results in a 6 dB gain loss, likely demanding additional amplifier(s) stage(s) and, thus, causing higher power consumption, lower bandwidth and/or linearity.

The aforementioned strategy is exemplarily shown in Figure 1, where one or more buffers 103a, 103b may be used for connecting one output of the two outputs of the differential amplifier 101 to the input of the single-ended amplifier (in Figure 1 the single-ended amplifier is not shown). In Figure 1 (A) both outputs of the differential amplifier 101 are connected to a buffer 103a respectively 103b, wherein the output of the differential amplifier 101 at the top of Figure 1 (A) may be connected via the buffer 103a to the input of the single-ended amplifier. The other output of the differential amplifier 101 at the bottom of Figure 1 (A) may be connected only to the buffer 103b. According to Figure 1 (A), the buffers 103a and 103b are implemented using BJTs. Alternatively, the buffers 103a and 103b may be implemented using MOSFETs, as exemplarily shown in Figure 1 (B). Alternatively, only the output of the differential amplifier 101 that is chosen to be connected to the input of the single-ended amplifier may be connected to a buffer 103a in order to be connected via the buffer 103a to the input of the single-ended amplifier. This is exemplarily shown in Figures 1 (C) and 1 (D), wherein according to Figure 1 (C) the buffer 103a is implemented using a BJT and according to Figure 1 (D) the buffer 103a is implemented using a MOSFET. In Figures 1 (A) to (D), an additional amplifier stage 102a is shown to be connected between the output of the differential amplifier 101 and the single-ended amplifier for compensating for the above-mentioned 6 dB gain loss. Alternatively, to the examples of Figures 1 (A) to (D), no buffers may be present and one output of the two outputs of the differential amplifier may be connected, optionally via the additional amplifier stage 102a, to the input of the single-ended amplifier, without a buffer being arranged between the output of the differential amplifier 101 and the input of the single-ended amplifier.

In the above-mentioned examples for achieving a differential to single-ended conversion, some imbalance may arise in the differential amplifier, due to uneven loading, and even-orders harmonics at the output of the differential amplifier may therefore worsen linearity.

Circuits for connecting the input of a single-ended amplifier to the outputs of a differential amplifier (i.e. circuit for differential to single-ended conversion) may be referred to as differential to single-ended converters or baluns (balance to unbalanced device). Such circuits may be divided into two main categories: passive circuits (may be referred to as passive differential to single-ended converters or passive baluns) and active circuit (may be referred to as active differential to single-ended converters or active baluns).

An example of a passive circuit for connecting the input of a single-ended amplifier to the two outputs of a differential amplifier may be or may comprise a transformer. For example, a simple 1 : 1 transformer with a coupling factor of one (K = 1) may act as a passive balun. The primary winding of the transformer may be differentially driven. That is, one of the two terminals of the primary winding may be connected to one of the two outputs of the differential amplifier and the other of the two terminals of the primary winding may be connected to the other of the two outputs of the differential amplifier. At the same time, the secondary winding of the transformer may have one of its terminals connected to the input of the single-ended amplifier and the other of its terminals connected to ground (e.g. radio frequency (RF) ground). That is, one of the two terminals of the secondary winding may be connected to the input of the single-ended amplifier and the other of the two terminals of the secondary winding may be connected to ground (e.g. radio frequency (RF) ground).

Passive circuits for connecting the input of a single-ended amplifier to a differential amplifier may be relatively narrowband. For example, in the case of the passive circuit being or comprising a transformer, in order to have a low frequency cutoff, the inductance LI of the primary winding and the inductance L2 of the secondary winding of the transformer need to be very large (i.e. JOJLU » output/input impedance of the previous/following amplifier (stage), for a given natural frequency co). On the other hand, to operate at high frequency, the inductance LI of the primary winding and the inductance L2 of the secondary winding of the transformer should be low (in order to maximize the self-resonance of the transformer). Therefore, it is not possible to achieve wideband operation when using a transformer (integrated transformer) for connecting the two outputs of the differential amplifier with the input of the single-ended amplifier, i.e. for differential to single-ended conversion.

Active circuits for connecting the input of a single-ended amplifier to the outputs of a differential amplifier are circuits comprising active devices (e.g. transistors) for achieving the function of differential to single-ended conversion, i.e. for connecting the input of a single-ended amplifier to the outputs of a differential amplifier. Active circuits for connecting the input of a single-ended amplifier to the outputs of a differential amplifier may achieve wide-bandwidth operation. However, with an active circuit it is not easy to achieve a high, wideband balanced input impedance. Further, linearity may be an issue. Moreover, biasing circuits may limit the low frequency cutoff and/or maximum operating frequency when using active circuits.

In view of the above, this disclosure aims to provide an improved circuit for connecting two outputs of a differential amplifier to an input of a single-ended amplifier. An objective of this disclosure may be providing a circuit for connecting two outputs of a differential amplifier to an input of a single-ended amplifier, wherein the circuit enables a wide bandwidth and/or a high linearity.

These and other objectives are achieved by the solution of this disclosure as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

A first aspect of this disclosure provides a circuit for connecting two outputs of a differential amplifier to an input of a single-ended amplifier. The circuit comprises a first terminal configured to be electrically connected to a first output of the two outputs of the differential amplifier, a second terminal configured to be electrically connected to a second output of the two outputs of the differential amplifier, a third terminal configured to be electrically connected to the input of the single-ended amplifier, and three transistors each comprising a first terminal, a second terminal and a third terminal. The third terminal of a first transistor of the three transistors is electrically connected to the first terminal of the circuit. The third terminal of a second transistor of the three transistors is electrically connected to the second terminal of the circuit. The third terminal of a third transistor of the three transistors is electrically connected to the second terminal of the first transistor. The second terminal of the second transistor, the first terminal of the third transistor and the third terminal of the circuit are electrically connected to a node. A transconductance of the second transistor equals a transconductance of the third transistor.

In other words, the first aspect provides a circuit comprising a first terminal for a first output of a differential amplifier, a second terminal for a second output of the differential amplifier, a third terminal for an input of a single-ended amplifier, and three transistors each comprising a first terminal, a second terminal and a third terminal. The third terminal of a first transistor is connected to the first terminal of the circuit. The third terminal of a second transistor is connected to the second terminal of the circuit. The third terminal of a third transistor is electrically connected to the second terminal of the first transistor. The second terminal of the second transistor, the first terminal of the third transistor and the third terminal of the circuit are connected to a node. A transconductance of the second transistor equals a transconductance of the third transistor.

The circuit according to the first aspect may provide a high input impedance for the previous stage, i.e. for the differential amplifier, and, thus, may enhance the overall radio frequency (RF) bandwidth (e.g. overall RF chain bandwidth) of an amplifier circuit comprising the differential amplifier and single- ended amplifier when the two outputs of the differential amplifier are connected to the input of the single-ended amplifier via the circuit according to the first aspect.

Due to its circuit configuration, the circuit according to the first aspect may reject common mode signals at the first terminal and the second terminal. As a result thereof, the circuit according to the first aspect may reject even order harmonic distortion (e.g. HD2, HD4 etc.) at the first terminal and the second terminal.

Thus, the first aspect proposes a wide bandwidth input impedance balanced active circuit for differential to single-ended conversion (i.e. active balun) with high linearity.

The circuit may be used in broadband trans-impedance amplifiers (TIAs) and/or drivers. In such amplifiers and/or drivers, signal bandwidth in the order of tens of GHz may be processed. Such amplifiers and/or drivers may be configured for high data-rate communications. The circuit may be part of such an amplifier or such a driver. The circuit may be used in fully-integrated high-frequency broadband amplifiers where high linearity, impedance-matched output and low AC cutoff frequency are desired; such as (but not limited to) broadband transimpedance amplifiers (TIAs) for optical communications, broadband drivers for optical communications, broadband amplifiers for wideband RF transceivers, etc.

The circuit may be referred to as “differential to single-ended converter” or “balun”. The circuit may have a 0 dB (differential to single-ended) gain. That is, the circuit may be a differential to single-ended converter with 0 dB (differential to single-ended) gain.

The third terminal of each transistor may be referred to as “control terminal”. If a transistor (e.g. of the three transistors) is a bipolar junction transistor (BJT), the third terminal is the base terminal of the BJT. If a transistor (e.g. of the three transistors) is a field-effect transistor (FET), such as a metal-oxide- semiconductor FET (MOSFET), the third terminal is the gate terminal of the FET (e.g. MOSFET).

The transconductance of the second transistor equaling to the transconductance of the third transistor may be achieved by equally dimensioning the second transistor and the third transistor. In other words, this may be achieved in that the size of the second transistor and the size of the third transistor are equal to each other. That is, the size of the second transistor and the size of the third transistor may be equal to each other so that the transconductance of the second transistor equals the transconductance of the third transistor. The transconductance of a transistor may be represented by the symbol “g_m”

If a transistor is a BJT, the size of the transistor may be the total emitter area (Ae, i.e. area of the emitter terminal), which is the product of emitter width (We, i.e. width of the emitter terminal), emitter length (Le, i.e. length of the emitter terminal) and the number (Ne) of emitter sub-terminals or emitter fingers forming the emitter terminal: Ae = We x Le x Ne. If a transistor is a FET (e.g. MOSFET), the size of the transistor may be the total gate area (Ag, i.e. area of the gate terminal) which is the product of the gate width (Wg, i.e. width of the gate terminal), gate length (Lg, i.e. length of the gate terminal) and the number (Nf) of gate sub-terminals or gate fingers forming the gate terminal: Ag = Wg x Lg x Nf.

Since the second terminal of the second transistor and the first terminal of the third transistor are connected to each other, the same current may flow through the second transistor and third transistor via the first terminals and second terminals. Due to the same current through the second and third transistor and the transconductance of the second transistor equaling to the transconductance of the third transistor, the third transistor may be configured to function or act as a unitary gain amplifier. Due to the connection (arrangement) of the first and second transistor in the circuit, the first and second transistor each may be configured to function or act as a unitary gain amplifier. In other words, the first, second and third transistor may be configured to act or function as a unitary gain amplifier. The second terminal of the third transistor may be connected to ground.

In an implementation form of the first aspect, each respective transistor of the three transistors is one of the following: a bipolar junction transistor (BJT), wherein the first terminal of the BJT is a collector terminal, the second terminal of the BJT is an emitter terminal and the third terminal of the BJT is a base terminal; and a field-effect transistor (FET), wherein the first terminal of the FET is a drain terminal, the second terminal of the FET is a source terminal and the third terminal of the FET is a gate terminal. For example, the FET may be a MOSFET. The three transistors may be differently implemented, e.g. by any other transistor type. The description of the three transistors may be valid for any other optional transistor of the circuit. That is, any other optional transistor of the circuit may be or may be implemented by a BJT, FET (e.g. MOSFET) or any other transistor type.

In an implementation form of the first aspect, the first terminal of the first transistor and the first terminal of the second transistor are each configured to be electrically connected to an electrical supply. For example, the electrical supply may be an electrical supply for the circuit (optionally being part of the circuit).

In an implementation form of the first aspect, the circuit comprises a biasing circuit for setting a current, and the second terminal of the first transistor is electrically connected to the biasing circuit.

The biasing circuit may be connected between the second terminal of the first transistor and ground. The biasing circuit may be provided for setting the current flow through the first transistor via the first terminal and second terminal of the first transistor.

In an implementation form of the first aspect, the biasing circuit comprises a current source or a resistor.

In an implementation form of the first aspect, the circuit comprises a first resistor and a second resistor having equal resistance. The second terminal of the second transistor may be electrically connected to the node via the first resistor, and the second resistor may be electrically connected to the second terminal of the third transistor.

If the parasitic (intrinsic) resistors of the second terminal of the second transistor and third transistor are negligible, the non-linearities of the transconductance of the second transistor and third transistor may cancel each other. For example, assuming that the second transistor and the third transistor are each a BJT, the following may be true: If the parasitic (intrinsic) emitter resistors of the second transistor and third transistor are negligible, the non-linearities of the transconductance of the second transistor and third transistor may cancel each other.

However, if the parasitic resistors of the second terminal of the second transistor and third transistor are not negligible, the linearity of the circuit may be improved by adding the first resistor and second resistor to the circuit, i.e. electrically connecting the first resistor to the second terminal of the second transistor and the second resistor to the second terminal of the third transistor.

The first resistor and second resistor may be referred to as “two degeneration resistors having equal resistance” or “two identical degeneration resistors”. The second resistor may be connected between the second terminal of the third transistor and ground. That is, the second terminal of the third transistor may be connected to ground via the second resistor.

In an implementation form of the first aspect, the circuit comprises an inductor. The inductor may be arranged such that the second terminal of the second transistor is electrically connected to the node via the inductor. Alternatively, the inductor may be arranged such that the first terminal of the third transistor is electrically connected to the node via the inductor. Alternatively, the inductor may be arranged such that the third terminal of the circuit is electrically connected to the node via the inductor.

The inductor allows extending the bandwidth of the circuit. Namely, arranging the inductor in the circuit creates a resonant network (e.g. some sort of resonant network). The inductor may extend the maximum operating frequency of the circuit

In an implementation form of the first aspect, the circuit comprises a first resistor and a second resistor having equal resistance, and an inductor. The second resistor may be electrically connected to the second terminal of the third transistor. The first resistor and the inductor may be arranged such that the second terminal of the second transistor is electrically connected to the node via the first resistor and the inductor. Alternatively, the first resistor and the inductor may be arranged such that the second terminal of the second transistor is electrically connected to the node via the first resistor, and the first terminal of the third transistor is electrically connected to the node via the inductor. Alternatively, the first resistor and the inductor may be arranged such that the second terminal of the second transistor is electrically connected to the node via the first resistor and the third terminal of the circuit is electrically connected to the node via the inductor. The first resistor and the inductor may be connected in series.

The inductor allows extending the bandwidth of the circuit. Namely, arranging the inductor in the circuit creates a resonant network (e.g. some sort of resonant network). The inductor may extend the maximum operating frequency of the circuit. This is advantageous when the circuit comprises the first resistor and second resistor for improving linearity of the circuit. Arranging the first resistor and second resistor in the circuit may lead to a bandwidth reduction. The part of the circuit comprising the second transistor may suffer from bandwidth reduction due to a low pass filter that may be formed by the first resistor and a load impedance that may be present at the third terminal of the circuit. The load impedance may be the input impedance of the single-ended amplifier when the single-ended amplifier and the third terminal of the circuit are connected to each other. The part of the circuit comprising the third transistor may suffer from a higher load impedance that may be formed by a series connection of the first resistor and the transconductance of the second transistor.

In an implementation form of the first aspect, the circuit comprises a first inductor and second inductor. The first inductor and the second inductor may be arranged such that the second terminal of the second transistor is electrically connected to the node via the first inductor, and the third terminal of the circuit is electrically connected to the node via the second inductor. Alternatively, the first inductor and the second inductor may be arranged such that the second terminal of the second transistor is electrically connected to the node via the first inductor, and the first terminal of the third transistor is electrically connected to the node via the second inductor. Alternatively, the first inductor and the second inductor may be arranged such that the first terminal of the third transistor is electrically connected to the node via the first inductor, and the third terminal of the circuit is electrically connected to the node via the second inductor.

The first inductor and second inductor allow extending the bandwidth of the circuit for the reasons outlined above with regard to the optional inductor of the circuit.

In an implementation form of the first aspect, the circuit comprises a first resistor and a second resistor having equal resistance, a first inductor and a second inductor. The second resistor may be electrically connected to the second terminal of the third transistor. The first resistor, the first inductor and the second inductor may be arranged such that the second terminal of the second transistor is electrically connected to the node via the first resistor and the first inductor, and the third terminal of the circuit is electrically connected to the node via the second inductor. Alternatively, the first resistor, the first inductor and the second inductor may be arranged such that the second terminal of the second transistor is electrically connected to the node via the first resistor and the first inductor, and the first terminal of the third transistor is electrically connected to the node via the second inductor. Alternatively, the first resistor, the first inductor and the second inductor may be arranged such that the second terminal of the second transistor is electrically connected to the node via the first resistor, the first terminal of the third transistor is electrically connected to the node via the first inductor, and the third terminal of the circuit is electrically connected to the node via the second inductor. The first resistor and the first inductor may be connected in series. The first inductor and second inductor allow extending the bandwidth of the circuit for the reasons outlined above with regard to the optional inductor of the circuit.

In an implementation form of the first aspect, the circuit comprising a first inductor, a second inductor and a third inductor. The second terminal of the second transistor may be electrically connected to the node via the first inductor. The first terminal of the third transistor may be electrically connected to the node via the second inductor. The third terminal of the circuit may be electrically connected to the node via the third inductor.

The first inductor, second inductor and third inductor allow extending the bandwidth of the circuit for the reasons outlined above with regard to the optional inductor of the circuit. These three inductors may form a triple resonant network.

In an implementation form of the first aspect, the circuit comprises a first resistor and a second resistor having equal resistance, a first inductor, a second inductor and a third inductor. The second resistor may be electrically connected to the second terminal of the third transistor. The second terminal of the second transistor may be electrically connected to the node via the first resistor and the first inductor. The first terminal of the third transistor may be electrically connected to the node via the second inductor. The third terminal of the circuit may be electrically connected to the node via the third inductor. The first resistor and the first inductor may be connected in series.

In an implementation form of the first aspect, the circuit comprises a level shifter circuit for shifting a level of a current and a current sense circuit. The third terminal of the first transistor may be electrically connected to the first terminal of the circuit via the level shifter circuit. The current sense circuit may be configured to sense a current flowing through the second transistor and the third transistor. The level shifter circuit may be configured to change a DC voltage at the third terminal of the first transistor by changing, depending on the current sensed by the current sense circuit, a current supplied from the first terminal of the circuit to the level shifter circuit.

The level shifter circuit may be configure to change the DC voltage at the third terminal of the first transistor by changing, depending on the current sensed by the current sense circuit, a current supplied from the first terminal of the circuit to a resistor of the level shifter circuit. The greater the current supplied from the first terminal of the circuit to the level shifter circuit (e.g. the resistor of the level shifter circuit), the greater the DC shift and, thus, the lower the DC voltage at the third terminal of the first transistor and vice versa. The level shifter circuit may be referred to as “DC level shifter circuit”. The terms “level shifter circuit” and “level shifter” may be used as synonyms. The level shifter circuit allows biasing the second transistor and third transistor. This allows DC coupling (i.e. a very low AC cutoff).

In an implementation form of the first aspect, the circuit comprises a level shifter circuit for shifting a level of a current and a current sense circuit. The third terminal of the third transistor may be electrically connected to the second terminal of the first transistor via the level shifter circuit. The current sense circuit may be configured to sense a current flowing through the second transistor and the third transistor. The level shifter circuit may be configured to change, depending on the current sensed by the current sense circuit, a current supplied from the second terminal of the first transistor to the third terminal of the third transistor. The level shifter circuit may be referred to as “DC level shifter circuit”. The level shifter circuit allows biasing the second transistor and third transistor. This allows DC coupling (i.e. a very low AC cutoff).

In the above two optional implementation forms, the current sense circuit may be or may comprise a sense resistor (e.g. a shunt resistor) for sensing the current flowing through the second transistor and the third transistor. The sense resistor may be connected to the first terminal of the second transistor. For example, the first terminal of the second transistor may be connected to an electrical supply via the sense resistor. For example, the electrical supply may be an electrical supply for the circuit (optionally being part of the circuit). Optionally, the current sense circuit may comprise a capacitor that may be electrically connected in parallel to the sense resistor. For example, if the first terminal of the second transistor may be connected to an electrical supply via the sense resistor, the capacitor may be electrically connected between the first terminal of the second transistor and the electrical supply. The capacitor may be provided to short-circuit the sense resistor at high frequencies, i.e. at frequencies greater than athreshold frequency.

The level shifter circuit may comprise a series connection of two resistors. In addition, the level shifter circuit may comprise a transistor connected to a node between the two resistors of the series connection of the two resistors. The circuit may be configured such that a control signal depending on the current sensed by the current sense circuit is provided to a control terminal of the transistor. Optionally, a capacitor may be electrically connected in parallel to the series connection of the two resistors. For example, the transistor may be a FET (e.g. a MOSFET), wherein the control terminal of the transistor is the gate terminal of the FET and the drain terminal of the FET may be connected to the node between the two resistors. The source terminal of the FET may be connected to ground. The transistor may be differently implemented, e.g. by any other transistor type.

If the level shifter circuit is configured to change a DC voltage at the third terminal of the first transistor by changing, depending on the current sensed by the current sense circuit, a current supplied from the first terminal of the circuit to the level shifter circuit, the series connection of the two resistors may be connected between the first terminal of the circuit and the third terminal of the first transistor. That is, the first terminal of the first transistor may be electrically connected to the first terminal of the circuit via the series connection of the two resistors of the level shifter circuit.

If the level shifter circuit is configured to change, depending on the current sensed by the current sense circuit, a current supplied from the second terminal of the first transistor to the third terminal of the third transistor, the series connection of the two resistors may be connected between the second terminal of the first transistor and the third terminal of the third transistor. That is, the third terminal of the third transistor may be electrically connected to the second terminal of the first transistor via the series connection of the two resistors of the level shifter circuit.

In an implementation form of the first aspect, the circuit comprises a second biasing circuit for setting a desired current and a comparator. The comparator may be configured to compare the current sensed by the current sense circuit with the desired current. The level shifter circuit may be configured to change, depending on a comparison result of the comparator, the current supplied from the first terminal of the circuit to the level shifter circuit respectively the current supplied from the second terminal of the first transistor to the third terminal of the third transistor.

The second biasing circuit may be a replica biasing circuit scaled by a factor Z for providing the desired current. The second biasing circuit may comprise a scaled resistor and a current source that are electrically connected in series to each other, wherein the second biasing circuit may be configured to provide the desired current at a node between the scaled resistor and the current source. The scaled resistor may have a resistance that is scaled up by the factor Z or greater by the factor Z than a resistance of the optional sense resistor. The desired current may be set or changed by the factor Z. Optionally, the current source may be configured to provide an adjustable current for adjusting or changing the desired current.

The current sensed by the current sense circuit, e.g. the sense resistor, may be provided via a further resistor to the comparator. The further resistor may be connected to the first terminal of the second transistor. The further resistor may be part of the current sense circuit. The comparator may comprise or be implemented by an operation amplifier. The current sense circuit (e.g. sense resistor) may be connected to an inverted input of the operation amplifier (optionally via the further resistor) for providing the sensed current to the comparator. The second biasing circuit (e.g. the node between the scaled resistor and the current source) may be connected to a non-inverted input of the operation amplifier for providing the desired current to the comparator.

In an implementation form of the first aspect, the circuit comprises a fourth transistor, a fifth transistor and a sixth transistor each comprising a first terminal, a second terminal and a third terminal, a first level shifter circuit, a second level shifter circuit and a fourth terminal. The third terminal of the second transistor may be electrically connected to the second terminal of the circuit via the fourth transistor, wherein the third terminal of the second transistor may be electrically connected to the second terminal of the fourth transistor and the third terminal of the fourth transistor may be electrically connected to the second terminal of the circuit. The third terminal of the fifth transistor may be electrically connected to the second terminal of the first transistor. The third terminal of the fifth transistor may be electrically connected to the third terminal of the third transistor via the first level shifter circuit. The second terminal of the fifth transistor, the first terminal of the sixth transistor and the fourth terminal of the circuit may be electrically connected to a second node. The third terminal of the second transistor may be electrically connected to the third terminal of the sixth transistor via the second level shifter circuit. A transconductance of the fifth transistor may equal a transconductance of the sixth transistor.

This allows using the circuit of the first aspect for connecting the two outputs of a differential amplifier to two inputs of another differential amplifier or for connecting the two outputs of a differential amplifier to an input of a single-ended amplifier circuit, depending on the functional configuration of the circuit. The functional configuration of the circuit may be controlled via the first level shifter circuit and the second level shifter circuit. In other words, the circuit may be configured to be configured or reconfigured from a differential push-pull amplifier configuration to a differential to single-ended converter (or balun) configuration. When the circuit is in the different push-pull amplifier configuration, it may be configured to provide 6 dB differential gain.

Optionally, the first terminal of the fourth transistor and the first terminal of the fifth transistor are each configured to be electrically connected to an electrical supply. For example, the electrical supply may be an electrical supply for the circuit (optionally being part of the circuit). Optionally, the circuit comprises a biasing circuit (e.g. second or third biasing circuit) for setting a current, and the second terminal of the fourth transistor may be electrically connected to the biasing circuit. The biasing circuit (e.g. second or third biasing circuit) may be connected between the second terminal of the fourth transistor and ground. The biasing circuit may be provided for setting the current flow through the fourth transistor via the first terminal and second terminal of the fourth transistor. For example, the biasing circuit comprises a current source or a resistor. In an implementation form of the first aspect, the second transistor, the third transistor, the fifth transistor and the sixth transistor have the same transconductance.

In an implementation form of the first aspect, the second level shifter circuit is configured to set the current flowing through the fifth transistor and sixth transistor to zero Amperes in case the single-ended amplifier is electrically connected to the third terminal of the circuit.

This allows turning-off a second branch of the circuit comprising the fifth transistor and sixth transistor. The second transistor and third transistor may form a first branch of the circuit that may be controlled (e.g. turned-off) by the first level shifter circuit. In other words, the second level shifter circuit may be configured to configure the circuit as a circuit for connecting two outputs of a differential amplifier to an input of a single-ended amplifier (differential to single-ended converter or balun) by setting the current flowing through the fifth transistor and sixth transistor to zero Amperes. The first level shifter circuit may be configured to set the current flowing through the second transistor and the third transistor to a current value greater than zero Amperes in case the second level shifter circuit sets the current flowing through the fifth transistor and sixth transistor to zero Amperes. This keeps the first branch of the circuit comprising the second transistor and third transistor tumed-on.

Optionally, the first level shifter circuit is configured to set the current flowing through the second transistor and third transistor to zero Amperes in case the single-ended amplifier is electrically connected to the fourth terminal of the circuit. This allows turning-off the first branch of the circuit comprising the second transistor and third transistor. In other words, the first level shifter circuit may be configured to configure the circuit as a circuit for connecting two outputs of a differential amplifier to an input of a single-ended amplifier (differential to single-ended converter or balun) by setting the current flowing through the second transistor and third transistor to zero Amperes. The second level shifter circuit may be configured to set the current flowing through the fifth transistor and the sixth transistor to a current value greater than zero Amperes in case the first level shifter circuit sets the current flowing through the second transistor and third transistor to zero Amperes. This keeps the second branch of the circuit comprising the fifth transistor and sixth transistor tumed-on.

In an implementation form of the first aspect, the second level shifter circuit is configured to set the current flowing through the fifth transistor and sixth transistor to a current value greater than zero Amperes in case a further differential amplifier is electrically connected to the third terminal and the fourth terminal of the circuit. In other words, the second level shifter circuit may be configured to configure the circuit as a circuit for connecting two outputs of a differential amplifier to two outputs of another differential amplifier (e.g. as a differential push-pull amplifier configuration) by setting the current flowing through the fifth transistor and sixth transistor to a current value greater than zero Amperes. The first level shifter circuit may be configured to set the current flowing through the second transistor and the third transistor to a current value greater than zero Amperes in case the further differential amplifier is electrically connected to the third terminal and the fourth terminal of the circuit.

Optionally, the circuit may comprise the second level shifter circuit without the first level shifter circuit (i.e. not comprising the first level shifter circuit). If the second level shifter circuit sets the current flowing through the fifth transistor and sixth transistor to a current value greater than zero Amperes for connecting the further differential amplifier to the third terminal and the fourth terminal of the circuit, the circuit may be configured to provide a 6 dB differential gain. This is correspondingly valid for the first level shifter circuit.

In an implementation form of the first aspect, the circuit comprises a third resistor and a fourth resistor having equal resistance. The second terminal of the fifth transistor may be electrically connected to the second node via the third resistor. The fourth resistor may be electrically connected to the second terminal of the sixth transistor.

The linearity of the circuit may be improved by adding the third resistor and fourth resistor to the circuit, i.e. electrically connecting the third resistor to the second terminal of the fifth transistor and the fourth resistor to the second terminal of the sixth transistor, for the same reasons outlined above with regard to the first resistor and second resistor. The fourth resistor may be connected between the second terminal of the sixth transistor and ground. That is, the second terminal of the sixth transistor may be connected to ground via the fourth resistor.

In an implementation form of the first aspect, the circuit comprises a second inductor. The second inductor may be arranged such that the second terminal of the fifth transistor is electrically connected to the second node via the second inductor. Alternatively, the second inductor may be arranged such that the first terminal of the sixth transistor is electrically connected to the second node via the second inductor. Alternatively, the second inductor may be arranged such that the fourth terminal of the circuit is electrically connected to the second node via the second inductor.

The second inductor allows extending the bandwidth of the circuit. Namely, arranging the second inductor in the circuit creates a resonant network (e.g. some sort of resonant network). The second inductor may extend the maximum operating frequency of the circuit. The aforementioned optional inductor connected to any one of the second transistor, third transistor and the third terminal of the circuit and the optional second inductor connected to any one of the fifth transistor, sixth transistor and fourth terminal of the circuit may be arranged in the circuit such that the arrangement is symmetrical.

In an implementation form of the first aspect, the circuit comprises a third resistor and a fourth resistor having equal resistance, and a second inductor. The fourth resistor may be electrically connected to the second terminal of the sixth transistor. The third resistor and the second inductor may be arranged such that the second terminal of the fifth transistor is electrically connected to the second node via the third resistor and the second inductor. Alternatively, the third resistor and the second inductor may be arranged such that the second terminal of the fifth transistor is electrically connected to the second node via the third resistor, and the first terminal of the sixth transistor is electrically connected to the second node via the second inductor. Alternatively, the third resistor and the second inductor may be arranged such that the second terminal of the fifth transistor is electrically connected to the second node via the third resistor, and the fourth terminal of the circuit is electrically connected to the second node via the second inductor. The third resistor and the second inductor may be connected in series.

The second inductor allows extending the bandwidth of the circuit. Namely, arranging the second inductor in the circuit creates a resonant network (e.g. some sort of resonant network). The second inductor may extend the maximum operating frequency of the circuit.

The first resistor and second resistor and the third resistor and fourth resistor may be arranged in the circuit such that the arrangement is symmetrical. The aforementioned optional inductor connected to any one of the second transistor, third transistor and the third terminal of the circuit and the optional second inductor connected to any one of the fifth transistor, sixth transistor and fourth terminal of the circuit may be arranged in the circuit such that the arrangement is symmetrical.

In an implementation form of the first aspect, the circuit comprises a third inductor and fourth inductor. The third inductor and the fourth inductor may be arranged such that the second terminal of the fifth transistor is electrically connected to the second node via the third inductor, and the fourth terminal of the circuit is electrically connected to the second node via the fourth inductor. Alternatively, the third inductor and the fourth inductor may be arranged such that the second terminal of the fifth transistor is electrically connected to the second node via the third inductor, and the first terminal of the sixth transistor is electrically connected to the second node via the fourth inductor. Alternatively, the third inductor and the fourth inductor may be arranged such that the first terminal of the sixth transistor is electrically connected to the second node via the third inductor, and the fourth terminal of the circuit is electrically connected to the second node via the fourth inductor.

The aforementioned optional first inductor and second inductor connected to any two of the second transistor, third transistor and the third terminal of the circuit and the optional third inductor and fourth inductor connected to any one of the fifth transistor, sixth transistor and fourth terminal of the circuit may be arranged in the circuit such that the arrangement is symmetrical. The third inductor and fourth inductor allow extending the bandwidth of the circuit for the reasons outlined above with regard to the aforementioned optional first inductor and second inductor connected to any two of the second transistor, third transistor and the third terminal of the circuit.

In an implementation form of the first aspect, the circuit comprises a third resistor and a fourth resistor having equal resistance, a third inductor and a fourth inductor. The fourth resistor may be electrically connected to the second terminal of the sixth transistor. The third resistor, the third inductor and the fourth inductor may be arranged such that the second terminal of the fifth transistor is electrically connected to the second node via the third resistor and the third inductor, and the fourth terminal of the circuit is electrically connected to the second node via the fourth inductor. Alternatively, the third resistor, the third inductor and the fourth inductor may be arranged such that the second terminal of the fifth transistor is electrically connected to the second node via the third resistor and the third inductor, and the first terminal of the sixth transistor is electrically connected to the second node via the fourth inductor. Alternatively, the third resistor, the third inductor and the fourth inductor may be arranged such that the second terminal of the fifth transistor is electrically connected to the second node via the third resistor, the first terminal of the sixth transistor is electrically connected to the second node via the third inductor, and the fourth terminal of the circuit is electrically connected to the second node via the fourth inductor. The third resistor and the third inductor may be connected in series.

The first resistor and second resistor and the third resistor and fourth resistor may be arranged in the circuit such that the arrangement is symmetrical. The aforementioned optional first inductor and second inductor connected to any two of the second transistor, third transistor and the third terminal of the circuit and the optional third inductor and fourth inductor connected to any one of the fifth transistor, sixth transistor and fourth terminal of the circuit may be arranged in the circuit such that the arrangement is symmetrical.

In an implementation form of the first aspect, the circuit comprises a fourth inductor, a fifth inductor and a sixth inductor. The second terminal of the fifth transistor may be electrically connected to the second node via the fourth inductor. The first terminal of the sixth transistor may be electrically connected to the second node via the fifth inductor. The fourth terminal of the circuit may be electrically connected to the second node via the sixth inductor. These three inductors may form a triple resonant network.

The aforementioned optional first inductor, second inductor and third inductor connected to the second transistor, third transistor and third terminal of the circuit, respectively, and the optional fourth inductor, fifth inductor and sixth inductor connected to the fifth transistor, sixth transistor and fourth terminal of the circuit, respectively, may be arranged in the circuit such that the arrangement is symmetrical. The fourth inductor, fifth inductor and sixth inductor allow extending the bandwidth of the circuit for the reasons outlined above with regard to the aforementioned optional first inductor, second inductor and third inductor connected to the second transistor, third transistor and the third terminal of the circuit, respectively.

In an implementation form of the first aspect, the circuit comprises a third resistor and a fourth resistor having equal resistance, a fourth inductor, a fifth inductor and a sixth inductor. The fourth resistor may be electrically connected to the second terminal of the sixth transistor. The second terminal of the fifth transistor may be electrically connected to the second node via the third resistor and the fourth inductor. The first terminal of the sixth transistor may be electrically connected to the second node via the fifth inductor. The fourth terminal of the circuit may be electrically connected to the second node via the sixth inductor. The third resistor and the fourth inductor may be connected in series.

The first resistor and second resistor and the third resistor and fourth resistor may be arranged in the circuit such that the arrangement is symmetrical. The aforementioned optional first inductor, second inductor and third inductor connected to the second transistor, third transistor and third terminal of the circuit, respectively, and the optional fourth inductor, fifth inductor and sixth inductor connected to the fifth transistor, sixth transistor and fourth terminal of the circuit, respectively, may be arranged in the circuit such that the arrangement is symmetrical.

In order to achieve the circuit according to the first aspect of this disclosure, some or all of the implementation forms and optional features of the first aspect, as described above, may be combined with each other.

A second aspect of this disclosure provides an amplifier circuit. The amplifier circuit comprises a differential amplifier with a first output and a second output, a single-ended amplifier with an input, and the circuit according to the first aspect of the disclosure, as described above. The first output of the differential amplifier is electrically connected to the first terminal of the circuit. The second output of the differential amplifier is electrically connected to the second terminal of the circuit. The input of the single-ended amplifier is electrically connected to the third terminal of the circuit. The amplifier circuit may be used in broadband trans-impedance amplifiers (TIAs) and/or drivers. In such amplifiers and/or drivers, signal bandwidth in the order of tens of GHz may be processed. Such amplifiers and/or drivers may be configured for high data-rate communications. The amplifier circuit may be or may be part of such an amplifier. The amplifier circuit may be or may be part of such a driver.

The amplifier circuit may be a fully-integrated high-frequency broadband amplifier, where high linearity, impedance-matched output and low AC cutoff frequency are desired. For example the amplifier circuit may be a broadband transimpedance amplifiers (TIAs) for optical communications; broadband drivers for optical communications; broadband amplifiers for wideband RF transceivers; etc.

The amplifier circuit may be a differential to single-ended wide-bandwidth amplifier circuit (may be referred to as differential to single-ended wide-bandwidth amplifier).

The differential amplifier may be or may be part of N differential amplifier stages of the amplifier circuit, wherein N is an integer number equal to or greater than one (N > 1). If N is equal to or greater than two (N > 2, i.e. the amplifier circuit comprises two or more differential amplifiers), the aforementioned differential amplifier is the differential amplifier stage of the two or more differential amplifiers that is to be connected to the single-ended amplifier. The two or more differential amplifiers (i.e. N > 2) may be connected with each other as a cascade, i.e. they may be cascade connected with each other. That is, the two or more differential amplifiers may form a N stage cascade differential amplifier. The N differential amplifier stages may implement or provide a desired differential signal gain (i.e. with a signal gain > 1) of the amplifier circuit. The N differential amplifier stages may form a differential amplifier chain.

The single-ended amplifier may be or may be part of M differential amplifier stages of the amplifier circuit, wherein M is an integer number equal to or greater than one (M > 1). If M is equal to or greater than two (M > 2, i.e. the amplifier circuit comprises two or more single-ended amplifiers), the aforementioned single-ended amplifier is the single-ended amplifier stage of the two or more single- ended amplifiers that is to be connected to the differential amplifier. The two or more single-ended amplifiers (i.e. M > 2) may be connected with each other as a cascade, i.e. they may be cascade connected with each other. That is, the two or more single-ended amplifiers may form an M stage cascade single-ended amplifier. The M single-ended amplifier stages may implement or provide a desired single-ended signal gain (i.e. with a signal gain > 1) of the amplifier circuit. The M single-ended amplifier stages may form a single-ended amplifier chain. The N differential amplifier stages, the circuit of the first aspect and the M single-ended amplifier stages may form an amplifier chain. The above description of the circuit according to the first aspect is correspondingly valid for the amplifier circuit according to the second aspect. The above description of the amplifier circuit according to the second aspect is correspondingly valid for the circuit according to the first aspect.

The amplifier circuit of the second aspect and its implementation forms and optional features achieve the same advantages as the circuit of the first aspect and its respective implementation forms and respective optional features.

In order to achieve the amplifier circuit according to the second aspect of the disclosure, some or all of the implementation forms and optional features of the second aspect, as described above, may be combined with each other.

All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

BRIEF DESCRIPTION OF DRAWINGS

The above described aspects and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

Figure 1 shows different examples of connecting a single-ended amplifier to a differential amplifier;

Figures 2 and 3 each show a circuit diagram of an example of a circuit according to an embodiment of this disclosure for connecting two outputs of a differential amplifier to an input of a single-ended amplifier;

Figure 4 shows a graph showing total harmonic distortion (THD) of the circuit of Figure

3 for different values of the first resistor and second resistor of the circuit of Figure 3;

Figure 5 shows a graph showing the relationship between output even order harmonic

(output HD2) and input even order harmonic (input HD2) of the circuit of Figure 3 for different values of the first resistor and second resistor of the circuit of Figure 3; Figure 6 shows a graph showing input capacitances over frequency for an example of a circuit corresponding to a part of the circuit of Figure 3;

Figure 7 shows a graph showing input capacitances over frequency for the first terminal and second terminal of the circuit of Figure 3;

Figure 8 shows a circuit diagram of an example of a circuit according to an embodiment of this disclosure for connecting two outputs of a differential amplifier to an input of a single-ended amplifier;

Figure 9 shows an example of an implementation form of the circuit of Figure 2 for biasing the second transistor and third transistor of the circuit of Figure 2;

Figure 10 shows a circuit diagram of an example of a circuit according to an embodiment of this disclosure for connecting two outputs of a differential amplifier to an input of a single-ended amplifier;

Figure 11 shows an example of an operation state of the circuit of Figure 10;

Figures 12 and 13 each show a circuit diagram of an example of a circuit according to an embodiment of this disclosure for connecting two outputs of a differential amplifier to an input of a single-ended amplifier; and

Figure 14 shows a block diagram of an example of an amplifier circuit according to an embodiment of this disclosure.

In the Figures corresponding elements are labelled by the same reference sign.

DETAILED DESCRIPTION OF EMBODIMENTS

Figures 2 and 3 each show a circuit diagram of an example of a circuit according to an embodiment of this disclosure for connecting two outputs of a differential amplifier to an input of a single-ended amplifier. The circuits of Figures 2 and 3 are examples of the circuit according to the first aspect of this disclosure. Therefore, the description of the circuit according to the first aspect of the disclosure is correspondingly valid for the circuits of Figures 2 and 3.

The circuit 1 of Figure 2 is a circuit for connecting two outputs of a differential amplifier (not shown in Figure 2) to an input of a single-ended amplifier (not shown in Figure 2). The circuit 1 comprises a first terminal T1 configured to be electrically connected to a first output of the two outputs of the differential amplifier, a second terminal T2 configured to be electrically connected to a second output of the two outputs of the differential amplifier, a third terminal T3 configured to be electrically connected to the input of the single-ended amplifier, and three transistors QI, Q2 and Q3 each comprising a first terminal 11, 21 respectively 31, a second terminal 12, 22 respectively 32, and a third terminal 13, 23 respectively 33. The third terminal 13 of a first transistor QI of the three transistors QI, Q2 and Q3 is electrically connected to the first terminal T1 of the circuit 1. The third terminal 23 of a second transistor Q2 of the three transistors Q 1 , Q2 and Q3 is electrically connected to the second terminal T2 of the circuit 1. The third terminal 33 of a third transistor Q3 of the three transistors QI, Q2 and Q3 is electrically connected to the second terminal 12 of the first transistor Q 1. The second terminal 22 of the second transistor Q2, the first terminal 31 of the third transistor Q3 and the third terminal T3 of the circuit 1 are electrically connected to a node 3. A transconductance of the second transistor Q2 equals a transconductance of the third transistor Q3.

According to the example of Figure 2, the transistors QI, Q2 and Q3 of the circuit 1 may each be a bipolar-junction transistor (BJT). In this case, the first terminal 11, 21 respectively 31 of the transistors QI, Q2 and Q3 is a collector terminal, the second terminal 12, 22 respectively 32 of the transistors QI, Q2 and Q3 is an emitter terminal, and the third terminal 13, 23 respectively 33 of the transistors QI, Q2 and Q3 is a base terminal. The present disclosure is not limited to the example that the transistors of the circuit are BJTs. Alternatively or additional, the circuit may comprise at least on other known transistor type. For example, the transistors QI, Q2 and Q3 of the circuit may each be a field-effect transistor (FET), such as a metal-oxide-semiconductor FET (MOSFET). In this case the first terminal 11, 21 respectively 31 of the transistors QI, Q2 and Q3 is a drain terminal, the second terminal 12, 22 respectively 32 of the transistors QI, Q2 and Q3 is a source terminal, and the third terminal 13, 23 respectively 33 of the transistors QI, Q2 and Q3 is a gate terminal.

For the following description of the Figures it is assumed that BJTs are used for implementing transistors of the circuit 1. As outlined above, this is only by way of example and not limiting the present disclosure. The description with regard to the circuit 1 comprising BJTs as transistors is correspondingly valid for the case that alternatively or additionally at least one other transistor type is used for implementing the transistors of the circuit 1.

The first terminal 11 of the first transistor Q 1 and the first terminal 21 of the second transistor Q2 may each be configured to be electrically connected to an electrical supply (not shown in Figure 2). For example, the electrical supply may be an electrical supply for the circuit 1 (optionally being part of the circuit 1). The circuit 1 may comprise a biasing circuit 2 for setting a current, and the second terminal 12 of the first transistor QI may be electrically connected to the biasing circuit 2. The optional biasing circuit 2 may comprise a current source 2a (as shown in Figure 2) or a resistor (not shown). As shown in Figure 2, the optional biasing circuit 2 may be connected between the second terminal 12 of the first transistor Q 1 and ground. The second terminal 32 of the third transistor Q3 may be electrically connected to ground.

As shown in Figure 2, the circuit 1 comprises a pair of emitter follower stages (i.e. a differential emitter follower stage). The pair of emitter follower stages is implemented or provided by the first transistor QI and second transistor Q2 of the circuit 1. The circuit 1 comprises a common emitter amplifier in the form of the third transistor Q3 with the same transconductance as the second transistor Q2. The transconductance of the second transistor Q2 equaling to the transconductance of the third transistor Q3 may be achieved by equally dimensioning the second transistor Q2 and the third transistor Q3. The second transistor Q2 and the third transistor Q3 share the same DC current. An example of an optional biasing circuit (second biasing circuit) for setting the DC current (i.e. providing DC biasing of the second transistor Q2 and third transistor Q3) is described with regard to Figure 9.

According to the example of Figure 2, the AC gain from the first terminal T1 of the circuit 1 to the third terminal T3 of the circuit 1 (assuming that no signal is applied to the second terminal T2 of the circuit 1) is one (AC gain = 1), because the first transistor QI is an emitter follower, and the load impedance of the third transistor Q3 is equal to l/g_m (where g_m is the transconductance of the second transistor Q2, which is equal to the transconductance of the third transistor Q3). The second transistor Q2 and the third transistors Q3 may be two transistor biased at the same current.

According to the example of Figure 2, the AC gain from the second terminal T2 of the circuit 1 to the third terminal T3 of the circuit 1 (assuming that no signal is applied to the first terminal T1 of the circuit 1) is also one (AC gain = 1), because the second transistor Q2 acts as an emitter follower. Moreover, the first transistor QI acts as a buffer for the third transistor Q3, providing a high input impedance for the previous stage (e.g. the differential amplifier to be connected to the first terminal T1 and second terminal T2). This enhances an overall radio frequency (RF) chain bandwidth, when the circuit is part of an amplifier chain connecting a differential amplifier of the amplifier chain to a single-ended amplifier of the amplifier chain.

Further, the circuit 1, i.e. differential to single-ended converter, of Figure 2 may reject common mode signals at the first terminal T1 and the second terminal T2 of the circuit 1 (i.e. at its input). Due to this, the circuit 1 of Figure 2 may also reject even order harmonic distortion (HD2, HD4 etc.). Moreover, if the parasitic (intrinsic) emitter resistors of the second transistor Q2 and the third transistor Q3 are negligible, the non-linearity of their transconductance g_m cancel each other.

If the parasitic emitter resistors of the second transistor Q2 and the third transistor Q3 are not negligible, linearity may optionally be improved by adding two resistors having equal resistance (i.e. two identical resistors) to the second transistor Q2 and the third transistor Q3, as is described with regard to Figure 3.

As exemplarily shown in Figure 2, the circuit 1 may be implemented by combining a differential emitter follower stage (implemented or provided by the first transistor Q 1 and the second transistor Q2) with a degenerated common emitter amplifier (implemented or provided by the third transistor Q3). The circuit 1 of Figure 2 realizes a wide bandwidth, input impedance balanced differential to single-ended converter (balun) with high linearity. Since the circuit 1 of Figure 2 comprises transistors, it is an active differential to single-ended converter (active balun).

The circuit of Figure 3 corresponds to the circuit of Figure 2 comprising additional optional features. Thus, the description of Figure 2 is correspondingly valid for the circuit of Figure 3 and in the following mainly the additional optional features are described.

As shown in Figure 3, the circuit 1 comprises a first resistor R1 and a second resistor R2 having equal resistance. That is, they have the same resistance. The second terminal 22 of the second transistor Q2 is electrically connected to the node 3 via the first resistor Rl, and the second resistor R2 is electrically connected to the second terminal 32 of the third transistor Q3. As outlined above, the two resistors Rl and R2 improve the linearity of the circuit 1. In the following, characteristics of the circuit 1 of Figure 3 are exemplarily described with regard to Figures 4 to 7, which is also valid for the circuits of Figures

2 and 8 to 13.

Figure 4 shows a graph showing total harmonic distortion (THD) of the circuit of Figure 3 for different values of the first resistor and second resistor of the circuit of Figure 3.

The y-axis of the graph of Figure 4 shows the total harmonic distortion (THD) as a percentage (%), wherein the greater the THD is, the lower the linearity of the circuit is and vice versa. The x-axis of the graph of Figure 4 show different values of the second resistor R2 between 0 Q (i.e. no second resistor R2 is present) and 5 Q. In the following table, the different values of the first resistor Rl for the different curves SO to S5 are shown:

In the graph of Figure 4, the dashed circle of the curve SO show the case of the circuit of Figure 2, because at the dashed circle of the curve SO the value of the first resistor Rl and the second resistor R2 equals to 0 Q. In other words, the dashed circle of the curve SO shows the case, in which the first resitor R1 and the second resistor R2 are not part of the circuit, as shown in Figure 2. The dashed circles of the curves SI to S5 show the case of the circuit of Figure 3, because at the dashed circles of the curves SI to S5 the first resistor R1 and the second resistor R2 have equal resistance (i.e. they have the same resistance).

As may be derived from Figure 4, linearity of the circuit of Figure 2 (i.e. having no first resistor R1 and second resistor R2 connected to the second transistor Q2 and third transistor Q3 of the circuit 1) is better compared to the case of adding only the first resistor R1 to the circuit of Figure 2 (i.e. the second resistor R2 equals to 0 Q). Further, Figure 4 shows that the linearity of the circuit of Figure 3 is greater or better compared to the circuit of Figure 2. In other words, the linearity of Figure 2 may be improved by adding the first resistor R1 and the second resistor R2 having equal resistance to the circuit of Figure 2 which leads to the circuit of Figure 3. Moreover, the greater the same resistance of the first resistor R1 and second resistor R2 of the circuit 1 of Figure 3 is, the smaller the THD and, thus, the greater or better the linearity of the circuit 1 of Figure 3 is.

Figure 5 shows a graph showing the relationship between output even order harmonic (output HD2) and input even order harmonic (input HD2) of the circuit of Figure 3 for different values of the first resistor and second resistor of the circuit of Figure 3.

The y-axis of the graph of Figure 5 shows an output even order harmonic, such as the output second harmonic distortion (HD2), in mV. The x-axis of the graph of Figure 5 shows an input even order harmonic, such as the input second harmonic distortion (HD2), in mV. In the following table, the different values of the first resistor R1 and second resistor R2 for the different curves S6 to S9 are shown:

As may be derived from Figure 5, the curve S7 shows the case of the circuit of Figure 2, because for the curve S7 the value of the first resistor R1 and the second resistor R2 equals to 0 Q. In other words, the curve S7 shows the case, in which the first resitor R1 and the second resistor R2 are not part of the circuit, as shown in Figure 2. The curve S6 show the case of the circuit of Figure 3, because for the curve S6 the first resistor R1 and the second resistor R2 have equal resistance (i.e. they have the same resistance) of 5 Q.

As may be derived from Figure 5, the circuit of Figure 2 (cf. curve S7) and the circuit of Figure 3 (cf. curve S6) have a better even order harmonic(s) rejection (e.g. HD2 rejection) compared to the case that the circuit of Figure 2 comprises only the first resistor R1 (cf. curve S9) having a resistance of 5 Q or the second resistor R2 (cf. curve S8) having a resistance of 5 Q. The even order harmonic(s) rejection (e.g. HD2 rejection) of the circuit of Figure 3 (i.e. the first resistor R1 and second resistor R2 having equal resistance are present) is better compared to the even order harmonic(s) rejection (e.g. HD2 rejection) of the circuit of Figure 2 (i.e. the first resistor R1 and second resistor R2 are not present). The greater the equal resistance of the first resistor R1 and the second resistor R2 of the circuit of Figure 3 is, the better the even order harmonic(s) rejection (e.g. HD2 rejection) of the circuit of Figure 3 is (not shown in Figure 5).

Figure 6 shows a graph showing input capacitances over frequency for an example of a circuit corresponding to a part of the circuit of Figure 3.

The circuit, for which Figure 6 shows input capacitances over frequency, corresponds to the circuit of Figure 3 without the left branch comprising the first transistor QI and the optional biasing circuit 2. Thus, in this example of circuit, the third terminal 33 of the third transistor Q3 is connected to the first terminal T1 of the circuit. The first resistor R1 and second resistor R2 of this example of circuit have equal resistance. In other words, Figure 6 shows the input capacitances over frequency for the case in which the input emitter follower formed by the first transistor Q 1 for driving the common emitter stage formed by the third transistor Q3 is removed from the circuit 1 of Figure 3. This example of circuit is indicated on the right side of Figure 6. The y-axis of the graph of Figure 6 shows input capacitance in fF. The x-axis of the graph of Figure 6 shows frequency in GHz. The curve S10 shows the input capacitance of the second terminal T2 of the circuit indicated on the right side of Figure 6 over frequency and the curve Si l shows the input capacitance of the first terminal T1 of the circuit indicated on the right side of Figure 6 over frequency.

As may be derived from the curves S10 and Si l of Figure 6, the input capacitance of the two terminals T1 and T2 of the circuit of Figure 6, to which the two outputs of a differential amplifier may be connected, differs from each other. The smaller the frequency is, the greater the difference between these two input capacitances. In other words, the two input impedances (i.e. input capacitances) of the circuit of Figure 6 are unbalanced. In contrast thereto, the circuit of Figure 3 allows a balance between the two input impedances (i.e. input capacitances) up to very high frequencies, as is shown in Figure 7. This is correspondingly valid for the circuit of Figures 2 and 8 to 13. Figure 7 shows a graph showing input capacitances over frequency for the first terminal and second terminal of the circuit of Figure 3.

The y-axis of the graph of Figure 7 shows input capacitance in fF. The x-axis of the graph of Figure 7 shows frequency in GHz. The curve S12 shows the input capacitance of the first terminal T1 of the circuit 1 of Figure 3 over frequency and the curve S13 shows the input capacitance of the second terminal T2 of circuit 1 of Figure 3 over frequency. Due to the emitter follower in the form of the first transistor QI driving the common emitter stage in the form of the third transistor Q3 being present in the circuit of Figure 3, a good balance (almost perfect balance) between the two input impedances (i.e. input capacitances) up to very high frequency may be achieved. This is correspondingly valid for the circuit of Figures 2 and 8 to 13.

Figure 8 shows a circuit diagram of an example of a circuit according to an embodiment of this disclosure for connecting two outputs of a differential amplifier to an input of a single-ended amplifier.

The circuit of Figure 8 corresponds to the circuit of Figure 3 comprising additional optional features. Thus, the description of Figures 2 to 7 is correspondingly valid for the circuit of Figure 8 and in the following mainly the additional optional features are described.

As shown in Figure 8, the circuit 1 may comprise three inductors, i.e. a first inductor LI, a second inductor L2 and a third inductor L3. The second terminal 22 of the second transistor Q2 may be electrically connected to the node 3 via the optional first resistor R1 and the first inductor LI. The first resistor R1 and the first inductor LI may be electrically connected in series. The first terminal 31 of the third transistor Q3 may be electrically connected to the node 3 via the second inductor L2. The third terminal T3 of the circuit 1 may be electrically connected to the node 3 via the third inductor L3. The three inductors LI, L2 and L3 may be present in the circuit 1 without the optional first resistor R1 and optional second resistor R2 being present in the circuit 1. In this case the second terminal 22 of the second transistor Q2 may be electrically connected to the node 3 via the first inductor LI . This optional case (without the resistors R1 and R2) corresponds to the circuit of Figure 2 comprising the optional three inductors LI, L2 and L3 of Figure 8.

The inductors LI, L2 and L3 allow extending the bandwidth of the circuit 1. Namely, arranging the inductors LI, L2 and L3 in the circuit 1 creates a resonant network (e.g. some sort of resonant network). The inductors LI, L2 and L3 may extend the maximum operating frequency of the circuit 1. The circuit 1 is not limited to the number of inductors shown in Figure 8. According to an optional alternative (not shown in Figure 8), the circuit 1 of Figure 8 may comprise only two inductors, for example the first inductor LI and the second inductor L2 of Figure 8; or the first inductor LI and the third inductor L3 of Figure 8; or the second inductor L2 and third inductor L3 of Figure 8. The respective aforementioned two inductors may be arranged or connected as shown in Figure 8. In the aforementioned optional case of only two inductors, the circuit 1 of Figure 8 may comprise the first resistor R1 and second resistor R2 or not. According to a further optional alternative (not shown in Figure 8), the circuit of Figure 8 may comprise only one inductor, for example the first inductor LI of Figure 8; or the second inductor L2 of Figure 8; or the third inductor L3 of Figure 8. The respective aforementioned inductor may be arranged or connected as shown in Figure 8. In the aforementioned further optional case of only one inductor, the circuit of Figure 8 may comprise the first resistor R1 and second resistor R2 or not.

Figure 9 shows an example of an implementation form of the circuit of Figure 2 for biasing the second transistor and third transistor of the circuit of Figure 2. The above description of Figure 2 is correspondingly valid for the circuit of Figure 9. In the following mainly the additional optional features of Figure 9 that may be added to the circuit of Figure 2 for implementing an example of biasing the second transistor Q2 and third transistor Q3 of the circuit 1 of Figure 2 is described. The description of Figure 9 is correspondingly valid for describing an example of biasing the second transistor Q2 and third transistor Q3 of the circuits of Figures 3 and 8.

The circuit 1 of Figure 9 comprises a current sense circuit 5 and a level shifter circuit 4 for shifting a level of a current. The third terminal 13 of the first transistor QI is connected to the first terminal T1 of the circuit 1 via the level shifter circuit 4. The current sense circuit 5 is configured to sense a current flowing through the second transistor Q2 and the third transistor Q3. The level shifter circuit 4 is configured to change a DC voltage at the third terminal 13 of the first transistor QI by changing, depending on the current sensed by the current sense circuit 5, a current supplied from the first terminal T1 of the circuit 1 to the level shifter circuit 4.

As shown in Figure 9, the level shifter circuit 4 may comprise a series connection of two resistors R5 and R6. The optional series connection of the two resistors R5 and R6 may be connected between the first terminal T1 of the circuit 1 and the third terminal 13 of the first transistor QI. That is, the first terminal 11 of the first transistor QI may be electrically connected to the first terminal T1 of the circuit 1 via the series connection of the two resistors R5 and R6 of the level shifter circuit 4. In addition, the level shifter circuit 4 may comprise a transistor Q7 connected to a node between the two resistors R5 and R6 of the series connection of the two resistors R5 and R6. The circuit 1 may be configured such that a control signal depending on the current sensed by the current sense circuit 5 is provided to a control terminal 73 of the transistor Q7. Optionally, a capacitor Cl may be electrically connected in parallel to the series connection of the two resistors R5 and R6. As shown in Figure 9, the transistor 7 may be a FET (e.g. a MOSFET), wherein the control terminal 73 of the transistor is the gate terminal of the FET and the drain terminal of the FET may be connected to the node between the two resistors R5 and R6. The transistor 7 may be differently implemented, e.g. by any other transistor type.

As shown in Figure 9, the current sense circuit 5 may comprise a sense resistor R7 (e.g. a shunt resistor) for sensing the current flowing through the second transistor Q2 and the third transistor Q3. The sense resistor R7 is connected to the first terminal 21 of the second transistor Q2. For example, the first terminal 21 of the second transistor Q2 may be connected to an electrical supply via the sense resistor R7. For example, the electrical supply may be an electrical supply for the circuit (optionally being part of the circuit). Optionally, the current sense circuit 5 may comprise a capacitor C2 that is electrically connected in parallel to the sense resistor R7 as shown in Figure 9. The capacitor C2 may be provided to short-circuit the sense resistor R7 at high frequencies, i.e. at frequencies greater than a threshold frequency.

As shown in Figure 9, the circuit 1 may comprise a comparator 7 and a second biasing circuit 6 for setting a desired current. The comparator 7 may be configured to compare the current sensed by the current sense circuit 5 with the desired current. The level shifter circuit 4 may be configured to change, depending on a comparison result of the comparator 7, the current supplied from the first terminal T1 of the circuit 1 to the level shifter circuit 4.

The second biasing circuit 6 may be a replica biasing circuit scaled by a factor Z for providing the desired current. The second biasing circuit 6 may comprise a scaled resistor R9 and a current source 6a that are electrically connected in series to each other, wherein the second biasing circuit 6 may be configured to provide the desired current at a node between the scaled resistor R9 and the current source 6a. The scaled resistor R9 may have a resistance that is scaled up by the factor Z or greater by the factor Z than a resistance of the sense resistor R7 of the current sense circuit 5 (R9 = Z * R7). The desired current may be set or changed by the factor Z. Optionally, the current source 6a may be configured to provide an adjustable current for adjusting or changing the desired current.

As shown in Figure 9, the current sensed by the current sense circuit 5, e.g. the sense resistor R7, may be provided via a further resistor R8 to the comparator 7. The further resistor R8 may be connected to the first terminal 21 of the second transistor Q2. The further resistor R8 may optionally be part of the current sense circuit 5, as indicated in Figure 9. The comparator 7 may comprise or be implemented by an operation amplifier, as shown in Figure 9. The current sense circuit 5 (e.g. sense resistor R7) may be connected to an inverted input of the operation amplifier (optionally via the further resistor R8) for providing the sensed current to the comparator 7. The second biasing circuit 6 (e.g. the node between the scaled resistor R9 and the current source 6a) may be connected to a non-inverted input of the operation amplifier for providing the desired current to the comparator 7.

Optionally, the level shifter circuit 4 may be differently arranged than shown in Figure 8. For example, the third terminal 33 of the third transistor Q3 may be electrically connected to the second terminal 12 of the first transistor QI via the level shifter circuit 4 (not shown in Figure 9). In this case, the level shifter circuit 4 may be configured to change, depending on the current sensed by the current sense circuit 5, a current supplied from the second terminal 12 of the first transistor QI to the third terminal 33 of the third transistor Q3. For this, the optional series connection of the two resistors R5 and R6 of the level shifter circuit 4 may be connected between the second terminal 12 of the first transistor QI and the third terminal 33 of the third transistor Q3. That is, the third terminal 33 of the third transistor Q3 maybe electrically connected to the second terminal 12 of the first transistor QI via the series connection of the two resistors R5 and R6 of the level shifter circuit 4. In the aforementioned optional case, the level shifter circuit 4 may be configured to change, depending on a comparison result of the optional comparator 7, the current supplied from the second terminal 12 of the first transistor QI to the third terminal 33 of the third transistor Q3.

The level shifter circuit 4 (irrespective whether it is arranged as shown in Figure 9 or described according to the aforementioned different example of arranging the level shifter circuit in the circuit of Figure 9) allows biasing the second transistor Q2 and third transistor Q3. This allows DC coupling (i.e. a very low AC cutoff).

Figure 10 shows a circuit diagram of an example of a circuit according to an embodiment of this disclosure for connecting two outputs of a differential amplifier to an input of a single-ended amplifier.

The circuit of Figure 10 corresponds to the circuit of Figure 2 comprising additional optional features. Thus, the description of Figures 2 to 9 is correspondingly valid for the circuit of Figure 10 and in the following mainly the additional optional features are described.

As shown in Figure 10, in addition to the components of the circuit 1 of Figure 2, the circuit 1 of Figure

10 comprises a fourth transistor Q4, a fifth transistor Q5 and a sixth transistor Q6 each comprising a first terminal 41, 51 respectively 61, a second terminal 42, 52 respectively 62 and a third terminal 43, 53 respectively 63. The circuit 1 comprises a first level shifter circuit 10, a second level shifter circuit

11 and a fourth terminal T4. The third terminal 23 of the second transistor Q2 is electrically connected to the second terminal T2 of the circuit 1 via the fourth transistor Q4, wherein the third terminal 23 of the second transistor Q2 is electrically connected to the second terminal 42 of the fourth transistor Q4 and the third terminal 43 of the fourth transistor Q4 is electrically connected to the second terminal T2 of the circuit 1. The third terminal 53 of the fifth transistor Q5 is electrically connected to the second terminal 12 of the first transistor QI. The third terminal 53 of the fifth transistor Q5 is electrically connected to the third terminal 33 of the third transistor Q3 via the first level shifter circuit 10. That is, the third terminal 33 of the third transistor Q3 is connected to the second terminal 12 of the first transistor QI via the first level shifter circuit 10. The second terminal 52 of the fifth transistor Q5, the first terminal 61 of the sixth transistor Q6 and the fourth terminal T4 of the circuit 1 are electrically connected to a second node 8. The third terminal 23 of the second transistor Q2 is electrically connected to the third terminal 63 of the sixth transistor Q3 via the second level shifter circuit 11. That is, the third terminal 63 of the sixth transistor Q6 is connected to the second terminal 42 of the fourth transistor Q2 via the second level shifter circuit 11. The transconductance of the fifth transistor Q5 equals a transconductance of the sixth transistor Q6.

The circuit 1 of Figure 10 may be used for connecting the two outputs of a differential amplifier to two inputs of another differential amplifier or for connecting the two outputs of a differential amplifier to an input of a single-ended amplifier circuit, depending on the functional configuration of the circuit 1. The functional configuration of the circuit 1 may be controlled via the first level shifter circuit 10 and the second level shifter circuit 11. In other words, the circuit may be configured to be configured or reconfigured from a differential push-pull amplifier configuration (as shown in Figure 10) to a differential to single-ended converter (or balun) configuration (as exemplarily shown in Figure 11).

In the circuit 1 of Figure 10 (i.e. in a configuration of a differential push-pull amplifier) the second transistor Q2 and the fifth transistor Q5 may act as a differential emitter follower while the third transistor Q3 and the sixth transistor Q6 (connected to the first level shifter circuit 10 and second level shifter circuit 11, respectively) may act as a differential degenerated common emitter amplifier. When the circuit 1 is in the different push-pull amplifier configuration, it may be configured to provide 6 dB differential gain.

As shown in Figure 10, optionally, the first terminal 41 of the fourth transistor Q4 and the first terminal 51 of the fifth transistor Q5 are each configured to be electrically connected to an electrical supply (not shown in Figure 10). For example, the electrical supply may be an electrical supply for the circuit 1 (optionally being part of the circuit 1). Optionally, the circuit 1 comprises a biasing circuit 9 (e.g. second or third biasing circuit) for setting a current, and the second terminal 42 of the fourth transistor Q4 may be electrically connected to the biasing circuit 9. The biasing circuit 9 may be provided for setting the current flow through the fourth transistor Q4 via the first terminal 41 and second terminal 42 of the fourth transistor Q4. The optional biasing circuit 9 may comprise a current source (as shown in Figure 10) or a resistor (not shown). As shown in Figure 10, the optional biasing circuit 9 may be connected between the second terminal 42 of the fourth transistor Q4 and ground. The second terminal 62 of the sixth transistor Q6 may be electrically connected to ground.

Optionally, the second transistor Q2, the third transistor Q3, the fifth transistor Q5 and the sixth transistor Q6 have the same transconductance.

The second level shifter circuit 11 may be configured to set the current flowing through the fifth transistor Q5 and sixth transistor Q6 to zero Amperes in case a single-ended amplifier is to be electrically connected to the third terminal T3 of the circuit 1. This state is exemplarily shown in Figure 11. For this the first level shifter circuit 10 may be configured to set the current flowing through the second transistor Q2 and the third transistor Q3 to a current value greater than zero Amperes. In the aforementioned example, the operation of the second level shifter circuit 11 and the first level shifter circuit 10 may be switched in case the single-ended amplifier is to be electrically connected to the fourth terminal T4 of the circuit 1.

The second level shifter circuit 11 may be configured to set the current flowing through the fifth transistor Q5 and sixth transistor Q6 to a current value greater than zero Amperes in case a further differential amplifier is electrically connected to the third terminal T3 and the fourth terminal T4 of the circuit 1. For this, the first level shifter circuit 11 may be configured to set the current flowing through the second transistor Q2 and third transistor Q3 to a current value greater than zero Amperes.

Thus, the first level shifter circuit 10 may be configured to turn-off a first branch of the circuit 1 comprising the second transistor Q2 and third transistor Q3 by setting the current flowing through the second transistor Q2 and third transistor Q3 to zero Amperes. Accordingly, the first level shifter circuit 10 may be configured to turn-on the first branch of the circuit 1 comprising the second transistor Q2 and third transistor Q3 by setting the current flowing through the second transistor Q2 and third transistor Q3 to a current value greater than zero Amperes. The second level shifter circuit 11 may be configured to turn-off a second branch of the circuit 1 comprising the fifth transistor Q5 and sixth transistor Q6 by setting the current flowing through the fifth transistor Q5 and sixth transistor Q6 to zero Amperes. Accordingly, the second level shifter circuit 11 may be configured to turn-on the second branch of the circuit 1 comprising the fifth transistor Q5 and sixth transistor Q6 by setting the current flowing through the fifth transistor Q5 and sixth transistor Q6 to a current value greater than zero Amperes.

Figure 11 shows an example of an operation state of the circuit of Figure 10. In the operation state of Figure 11, the second level shifter circuit 11 has turned off the second branch of the circuit 1 comprising the fifth transistor Q5 and sixth transistor Q6 by setting the current flowing through the fifth transistor Q5 and sixth transistor Q6 to zero Amperes. As a result, with regard to its function the circuit 1 of Figure 11 corresponds to the circuit 1 of Figure 2, because the circuit 1 of Figure 11 allows a differential to single-ended conversion (i.e. two outputs of a differential amplifier may be connected to the first terminal T1 and second terminal T2 of the circuit 1 and a input of a single-ended amplifier may be connected to the third terminal T3 of the circuit 1).

Figures 12 and 13 each show a circuit diagram of an example of a circuit according to an embodiment of this disclosure for connecting two outputs of a differential amplifier to an input of a single-ended amplifier.

The circuit of Figure 12 corresponds to the circuit of Figure 10 comprising in addition to the optional features of the first resistor R1 and second resistor R2 of the circuit of Figure 3 additional optional features. Thus, the description of Figures 2 to 11 is correspondingly valid for the circuit of Figure 12 and in the following mainly the additional optional features are described.

As shown in Figure 12 the circuit 1 may comprise a third resistor R3 and a fourth resistor R4 having equal resistance. The second terminal 52 of the fifth transistor Q5 may be electrically connected to the second node 8 via the third resistor R3. The fourth resistor R4 may be electrically connected to the second terminal 62 of the sixth transistor Q6. The linearity of the circuit 1 may be improved by adding the optional first resistor Rl, second resistor R2, third resistor R3 and fourth resistor R4 to the circuit 1.

The circuit of Figure 13 corresponds to the circuit of Figure 12 comprising in addition to the optional features of the first inductor LI, second inductor L2 and third inductor L3 of the circuit of Figure 8 additional optional features. Thus, the description of Figures 2 to 12 is correspondingly valid for the circuit of Figure 13 and in the following mainly the additional optional features are described.

As shown in Figure 13, the circuit 1 may comprise three additional inductors, i.e. a fourth inductor L4, a fifth inductor L5 and a sixth inductor L6. The second terminal 52 of the fifth transistor Q5 may be electrically connected to the second node 8 via the third resistor R3 and the fourth inductor L4. The third resistor R3 and the fourth inductor L4 may be electrically connected in series. The first terminal 61 of the sixth transistor Q6 may be electrically connected to the second node 8 via the fifth inductor L5. The fourth terminal T4 of the circuit 1 may be electrically connected to the second node 8 via the sixth inductor L6. The three inductors L4, L5 and L6 may be present in the circuit 1 without the optional third resistor R3 and optional fourth resistor R4 being present in the circuit 1. In this case the second terminal 52 of the fifth transistor Q5 may be electrically connected to the second node 8 via the fourth inductor L4. In this case, the optional first resistor Rl and second resistor R2 may not be part of the circuit. This optional case (without the resistors Rl, R2, R3 and R4) corresponds to the circuit of Figure 10 comprising the optional three inductors LI, L2 and L3 of Figure 8 or 13 and the optional three inductors L4, L5 and L6 of Figure 13.

The inductors L4, L5 and L6 allow extending the bandwidth of the circuit 1. Namely, arranging the inductors L4, L5 and L6 in the circuit creates a resonant network (e.g. some sort of resonant network). The inductors L4, L5 and L6 may extend the maximum operating frequency of the circuit 1.

The circuit 1 is not limited to the number of inductors shown in Figure 13. According to an optional alternative, the circuit of Figure 13 may comprise only four inductors, for example the first inductor LI, the second inductor L2, the fourth inductor L4 and the fifth inductor L5 of Figure 13; or the first inductor LI, the third inductor L3, the fourth inductor L4 and the sixth inductor L6 of Figure 13; or the second inductor L2, third inductor L3, fifth inductor L5 and sixth inductor L6 of Figure 13. In other words, the circuit of Figure 13 may comprise only four inductors of the inductors LI, L2, L3, L4, L5 and L6 such that these four inductors are symmetrically arranged. The respective aforementioned four inductors may be arranged or connected as shown in Figure 13. In the aforementioned optional case of only four inductors, the circuit of Figure 13 may comprise the first resistor Rl, second resistor R2, third resistor R3 and fourth resistor R4 or not.

According to a further optional alternative, the circuit of Figure 13 may comprise only two inductors, for example the first inductor LI and fourth inductor L4 of Figure 13; or the second inductor L2 and fifth inductor L5 of Figure 13; or the third inductor L3 and sixth inductor L6 of Figure 13. In other words, the circuit of Figure 13 may comprise only two inductors of the inductors LI, L2, L3, L4, L5 and L6 such that these two inductors are symmetrically arranged. The respective aforementioned inductors may be arranged or connected as shown in Figure 13. In the aforementioned further optional case of only two inductors, the circuit of Figure 13 may comprise the first resistor Rl, second resistor R2, third resistor R3 and fourth resistor R4 or not.

For further details on the circuits of Figures 2, 3 and 8 to 13 reference is made to the description of the circuit according to the first aspect of this disclosure.

Figure 14 shows a block diagram of an example of an amplifier circuit according to an embodiment of this disclosure. The amplifier circuit of Figure 14 is an example of the amplifier circuit according to the second aspect of this disclosure. Therefore, the description of the amplifier circuit according to the second aspect of the disclosure is correspondingly valid for the amplifier circuit of Figure 14.

The amplifier circuit 100 of Figure 14 comprises a differential amplifier 101 with a first output OUT1 and a second output OUT2, a single-ended amplifier 102 with an input IN3, and a circuit 1 according to the first aspect of this disclosure. The circuit 1 may be the circuit of any one of Figures 2, 3 and 8 to 13. Therefore, for further information on the circuit 1 of the amplifier circuit 100 reference is made to the description of the circuit according to the first aspect and the description of Figures 2 to 13. As shown in Figure 14, the first output OUT1 of the differential amplifier 101 may be electrically connected to the first terminal T1 of the circuit 1. The second output OUT2 of the differential amplifier 101 may be electrically connected to the second T2 terminal of the circuit 1. The input IN3 of the single-ended amplifier 102 may be electrically connected to the third terminal T3 of the circuit 1. Thus, in the amplifier circuit 100 the circuit 1 allows a differential to single-ended conversion, i.e. connecting two outputs OUT1, OUT2 of a differential amplifier 101 to an input IN3 of a single-ended amplifier 102. This connections is provided via the circuit 1.

Optionally, the two inputs INI, IN2 of the differential amplifier 101 may be electrically connected to two outputs of another differential amplifier (not shown in Figure 14). That is, the amplifier circuit 100 may optionally comprise two or more differential amplifier stages (e.g. the differential amplifier 101 and the aforementioned other differential amplifier) that may be connected with each other as a cascade, i.e. they may be cascade connected with each other. The differential amplifier 101 or the aforementioned optional two or more differential amplifier stages may implement or provide a desired differential signal gain (i.e. with a signal gain > 1) of the amplifier circuit 100.

Optionally, the output OUT3 of the single-ended amplifier 102 may be electrically connected to an input of another single-ended amplifier (not shown in Figure 14). That is, the amplifier circuit 100 may optionally comprise two or more single-ended amplifier stages (e.g. the single-ended amplifier 102 and the aforementioned other single-ended amplifier) that may be connected with each other as a cascade, i.e. they may be cascade connected with each other. The single-ended amplifier 102 or the aforementioned optional two or more single-ended amplifier stages may implement or provide a desired single-ended signal gain (i.e. with a signal gain > 1) of the amplifier circuit 100.

The present invention has been described in conjunction with various embodiments. However, other variations of the invention can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of this disclosure. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A circuit (1) for connecting two outputs (0UT1, 0UT2) of a differential amplifier (101) to an input (IN3) of a single-ended amplifier (102), wherein the circuit (1) comprises a first terminal (Tl) configured to be electrically connected to a first output (OUT1) of the two outputs (OUT1, OUT2) of the differential amplifier (101), a second terminal (T2) configured to be electrically connected to a second output (OUT2) of the two outputs (OUT1, OUT2) of the differential amplifier (101), a third terminal (T3) configured to be electrically connected to the input (IN3) of the single- ended amplifier (102), and three transistors (QI, Q2, Q3) each comprising a first terminal (11; 21; 31), a second terminal (12; 22; 32) and a third terminal (13; 23; 33); wherein the third terminal (13) ofa first transistor (QI) of the three transistors (QI, Q2, Q3) is electrically connected to the first terminal (Tl) of the circuit (1), the third terminal (23) of a second transistor (Q2) of the three transistors (QI, Q2, Q3) is electrically connected to the second terminal (T2) of the circuit (1), the third terminal (33) of a third transistor (Q3) of the three transistors (QI, Q2, Q3) is electrically connected to the second terminal (12) of the first transistor (QI), the second terminal (22) of the second transistor (Q2), the first terminal (31) of the third transistor (Q3) and the third terminal (T3) of the circuit (1) are electrically connected to a node (3), and a transconductance of the second transistor (Q2) equals a transconductance of the third transistor (Q3).

2. The circuit (1) according to claim 1, wherein each respective transistor of the three transistors (QI, Q2, Q3) is one of the following: a bipolar junction transistor, BJT, wherein the first terminal of the BJT is a collector terminal, the second terminal of the BJT is an emitter terminal and the third terminal of the BJT is a base terminal; a field-effect transistor, FET, wherein the first terminal of the FET is a drain terminal, the second terminal of the FET is a source terminal and the third terminal of the FET is a gate terminal.

3. The circuit (1) according to claim 1 or 2, wherein the first terminal (11) of the first transistor (QI) and the first terminal (21) of the second transistor (Q2) are each configured to be electrically connected to an electrical supply. The circuit (1) according to any one of the previous claims, wherein the circuit (1) comprises a biasing circuit (2) for setting a current, and the second terminal (12) of the first transistor (QI) is electrically connected to the biasing circuit (2). The circuit (1) according to claim 4, wherein the biasing circuit (2) comprises a current source (2a) or a resistor. The circuit (1) according to any one of the previous claims, wherein the circuit (1) comprises a first resistor (Rl) and a second resistor (R2) having equal resistance, the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor (Rl), and the second resistor (R2) is electrically connected to the second terminal (32) of the third transistor (Q3). The circuit (1) according to any one of claims 1 to 5, the circuit (1) comprising an inductor, wherein the inductor is arranged such that one of the following is true: the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the inductor, the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the inductor, and the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the inductor. The circuit (1) according to any one of claims 1 to 5, wherein the circuit (1) comprises a first resistor and a second resistor having equal resistance, and an inductor, the second resistor is electrically connected to the second terminal (32) of the third transistor (Q3), and the first resistor and the inductor are arranged such that one of the following is true: the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor and the inductor; the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor, and the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the inductor; and the second terminal (22) of the second transistor is electrically connected to the node (3) via the first resistor, and the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the inductor. The circuit (1) according to any one of claims 1 to 5, the circuit comprising a first inductor and second inductor, wherein the first inductor and the second inductor are arranged such that one of the following is true: the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first inductor, and the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the second inductor; the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first inductor, and the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the second inductor; and the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the first inductor, and the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the second inductor. The circuit (1) according to any one of claims 1 to 5, wherein the circuit (1) comprises a first resistor and a second resistor having equal resistance, an first inductor and a second inductor, the second resistor is electrically connected to the second terminal (32) of the third transistor (Q3), and the first resistor, the first inductor and the second inductor are arranged such that one of the following is true: the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor and the first inductor, and the third terminal (T3) of the circuit is electrically connected to the node (3) via the second inductor; the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor and the first inductor, and the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the second inductor; and the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor, the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the first inductor, and the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the second inductor. The circuit (1) according to any one of claims 1 to 5, the circuit (1) comprising a first inductor, a second inductor and a third inductor, wherein the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first inductor, the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the second inductor, and the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the third inductor. The circuit (1) according to any one of claims 1 to 5, wherein the circuit (1) comprises a first resistor (Rl) and a second resistor (R2) having equal resistance, an first inductor (LI), a second inductor (L2) and a third inductor (L3), the second resistor (R2) is electrically connected to the second terminal (32) of the third transistor (Q3), the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor (Rl) and the first inductor (LI), the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the second inductor (L2), and the third terminal (T3) of the circuit is electrically connected to the node (3) via the third inductor (L3). The circuit (1) according to any one of the previous claims, wherein the circuit (1) comprises a level shifter circuit (4) for shifting a level of a current and a current sense circuit (5), the third terminal (13) of the first transistor (QI) is electrically connected to the first terminal (Tl) of the circuit (1) via the level shifter circuit (4), the current sense circuit (5) is configured to sense a current flowing through the second transistor (Q2) and the third transistor (Q3), and the level shifter circuit (4) is configured to change a DC voltage at the third terminal (13) of the first transistor (QI) by changing, depending on the current sensed by the current sense circuit (5), a current supplied from the first terminal (Tl) of the circuit (1) to the level shifter circuit (4). The circuit (1) according to any one of claims 1 to 12, wherein the circuit comprises a level shifter circuit (4) for shifting a level of a current and a current sense circuit (5), the third terminal (33) of the third transistor (Q3) is electrically connected to the second terminal (12) of the first transistor (QI) via the level shifter circuit (4), the current sense circuit (5) is configured to sense a current flowing through the second transistor (Q2) and the third transistor (Q3), and the level shifter circuit (4) is configured to change, depending on the current sensed by the current sense circuit (5), a current supplied from the second terminal (12) of the first transistor (QI) to the third terminal (33) of the third transistor (Q3).

15. The circuit (1) according to claim 13 or 14, wherein the circuit (1) comprises a second biasing circuit (6) for setting a desired current and a comparator (7), the comparator (7) is configured to compare the current sensed by the current sense circuit (5) with the desired current, and the level shifter circuit (4) is configured to change, depending on a comparison result of the comparator (7), the current supplied from the first terminal (Tl) of the circuit (1) to the level shifter circuit (4) respectively the current supplied from the second terminal (12) of the first transistor (QI) to the third terminal (33) of the third transistor (Q3).

16. The circuit (1) according to any one of claims 1 to 12, wherein the circuit comprises a fourth transistor (Q4), a fifth transistor (Q5) and a sixth transistor (Q6) each comprising a first terminal (41 ; 51 ; 61), a second terminal (42; 52; 62) and a third terminal (43; 53; 63), a first level shifter circuit (10), a second level shifter circuit (11) and a fourth terminal (8); the third terminal (23) of the second transistor (Q2) is electrically connected to the second terminal (T2) of the circuit (1) via the fourth transistor (Q4), wherein the third terminal (23) of the second transistor (Q2) is electrically connected to the second terminal (42) of the fourth transistor (Q4) and the third terminal (43) of the fourth transistor (Q4) is electrically connected to the second terminal (T2) of the circuit (1); the third terminal (53) of the fifth transistor (Q5) is electrically connected to the second terminal (12) of the first transistor (QI); the third terminal (53) of the fifth transistor (Q5) is electrically connected to the third terminal (33) of the third transistor (Q3) via the first level shifter circuit (10); the second terminal (52) of the fifth transistor (Q5), the first terminal (61) of the sixth transistor (Q6) and the fourth terminal (T4) of the circuit (1) are electrically connected to a second node (8); the third terminal (23) of the second transistor (Q2) is electrically connected to the third terminal (63) of the sixth transistor (Q6) via the second level shifter circuit (11); and a transconductance of the fifth transistor (Q5) equals a transconductance of the sixth transistor (Q6). The circuit (1) according to claim 16, wherein the second transistor (Q2), the third transistor (Q3), the fifth transistor (Q5) and the sixth transistor (Q6) have the same transconductance. The circuit (1) according to claim 16 or 17, wherein the second level shifter circuit (11) is configured to set the current flowing through the fifth transistor (Q5) and sixth transistor (Q6) to zero Amperes in case the single-ended amplifier is electrically connected to the third terminal (T3) of the circuit (1). The circuit (1) according to any one of claims 16 to 18, wherein the second level shifter circuit (11) is configured to set the current flowing through the fifth transistor (Q5) and sixth transistor (Q6) to a current value greater than zero Amperes in case a further differential amplifier is electrically connected to the third terminal (T3) and the fourth terminal (T4) of the circuit (1). The circuit (1) according to any one of claims 16 to 19 when depending on claim 6, wherein the circuit (1) comprises a third resistor (R3) and a fourth resistor (R4) having equal resistance, the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor (R3), and the fourth resistor (R4) is electrically connected to the second terminal (62) of the sixth transistor (Q6). The circuit (1) according to any one of claims 16 to 19 when depending on claim 7, the circuit (1) comprising a second inductor, wherein the second inductor is arranged such that one of the following is true: the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the second inductor, the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the second inductor, and the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) via the second inductor. The circuit (1) according to any one of claims 16 to 19 when depending on claim 8, wherein the circuit (1) comprises a third resistor and a fourth resistor having equal resistance, and a second inductor, the fourth resistor is electrically connected to the second terminal (62) of the sixth transistor (Q6), and the third resistor and the second inductor are arranged such that one of the following is true: the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor and the second inductor; the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor, and the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the second inductor; and the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor, and the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) via the second inductor.

23. The circuit (1) according to any one of claims 16 to 19 when depending on claim 9, the circuit (1) comprising a third inductor and fourth inductor, wherein the third inductor and the fourth inductor are arranged such that one of the following is true: the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third inductor, and the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) via the fourth inductor; the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third inductor, and the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the fourth inductor; and the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the third inductor, and the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) via the fourth inductor.

24. The circuit (1) according to any one of claims 16 to 19 when depending on claim 10, wherein the circuit (1) comprises a third resistor and a fourth resistor having equal resistance, an third inductor and a fourth inductor, the fourth resistor is electrically connected to the second terminal (62) of the sixth transistor (Q6), and the third resistor, the third inductor and the fourth inductor are arranged such that one of the following is true: the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor and the third inductor, and the fourth terminal (T4) of the circuit is electrically connected to the second node (8) via the fourth inductor; the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor and the third inductor, and the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the fourth inductor; and the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor, the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the third inductor, and the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) via the fourth inductor. The circuit (1) according to any one of claims 16 to 19 when depending on claim 11, the circuit (1) comprising a fourth inductor, a fifth inductor and a sixth inductor, wherein the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the fourth inductor, the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the fifth inductor, and the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) via the sixth inductor. The circuit (1) according to any one of claims 16 to 19 when depending on claim 12, wherein the circuit (1) comprises a third resistor (R3) and a fourth resistor (R4) having equal resistance, an fourth inductor (L4), a fifth inductor (L5) and a sixth inductor (L6), the fourth resistor (R4) is electrically connected to the second terminal (62) of the sixth transistor (Q6), the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor (R3) and the fourth inductor (L4), the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the fifth inductor (L5), and the fourth terminal (T4) of the circuit is electrically connected to the second node (8) via the sixth inductor (L6). An amplifier circuit (100) comprising a differential amplifier (101) with a first output (OUT1) and a second output (OUT2), a single-ended amplifier (102) with an input (IN3), and the circuit (1) according to any one of the previous claims, wherein the first output (OUT1) of the differential amplifier (101) is electrically connected to the first terminal (Tl) of the circuit (1), the second output (OUT2) of the differential amplifier (101) is electrically connected to the second terminal (T2) of the circuit (1), and the input (IN3) of the single-ended amplifier (102) is electrically connected to the third terminal (T3) of the circuit (1).