WO2023230903A1 - 显示控制器、显示设备、显示系统以及控制方法 - Google Patents

显示控制器、显示设备、显示系统以及控制方法 Download PDF

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Publication number
WO2023230903A1
WO2023230903A1 PCT/CN2022/096429 CN2022096429W WO2023230903A1 WO 2023230903 A1 WO2023230903 A1 WO 2023230903A1 CN 2022096429 W CN2022096429 W CN 2022096429W WO 2023230903 A1 WO2023230903 A1 WO 2023230903A1
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WIPO (PCT)
Prior art keywords
display
frequency
image data
signal
circuit
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PCT/CN2022/096429
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English (en)
French (fr)
Inventor
吴宝云
于洋
朱元章
田雪松
韩新斌
史世明
赵辉
杨华玲
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/096429 priority Critical patent/WO2023230903A1/zh
Priority to CN202280001563.5A priority patent/CN117501336A/zh
Publication of WO2023230903A1 publication Critical patent/WO2023230903A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, and more specifically, to a display controller, a display device, a display system and a control method.
  • Display technology based on Organic Electroluminescence Display (OLED) has the characteristics of self-illumination, wide viewing angle, fast response, bendability and flexibility. It is an important breakthrough in the field of display technology and improves visual effects.
  • OLED Organic Electroluminescence Display
  • the display frequency of the display module can not only achieve high display frequencies, but also move to ultra-low display frequencies. As a result, the display module needs to support more and more display frequencies.
  • the present disclosure provides a display controller, a display device, a display system and a control method.
  • One aspect of the present disclosure provides a display controller including:
  • a flag signal circuit configured to send a flag signal to the application processor
  • the image processing circuit is configured to obtain second current image data in response to receiving the first current image data from the above-mentioned application processor, wherein the above-mentioned first current image data is the above-mentioned application processor in response to receiving the above-mentioned flag bit from the above-mentioned flag bit.
  • the flag bit signal sent by the signaling circuit is sent;
  • a driving circuit configured to generate a first driving control signal in response to receiving second current image data from the image processing circuit.
  • the above-mentioned flag signal circuit is configured to send a flag signal loaded with a first pulse signal to the above-mentioned application processor, wherein the flag signal loaded with the above-mentioned first pulse signal is used to indicate that the above-mentioned application processor is allowed to the above-mentioned image processing
  • the circuit sends the above-mentioned first current image data
  • the above-mentioned image processing circuit is configured to, in response to receiving the first current image data from the above-mentioned application processor, obtain the above-mentioned second current image data based on the above-mentioned first current image data, wherein the above-mentioned first current image data is the above-mentioned application processor.
  • the processor sends the flag signal loaded with the first pulse signal in response to receiving the flag signal sent from the flag signal circuit.
  • the above-mentioned first drive control signal includes a scan start signal loaded with a second pulse signal
  • the above-mentioned driving circuit is configured to generate a scan start signal loaded with the above-mentioned second pulse signal in response to detecting that the previous image data from the above-mentioned application processor is processed;
  • the flag signal circuit is configured to generate a flag signal loaded with the first pulse signal in response to receiving a scan start signal loaded with the second pulse signal from the driving circuit.
  • the changing frequency of the flag signal loaded with the above-mentioned first pulse signal is consistent with the changing frequency of the above-mentioned scanning start signal
  • the response speed of the above-mentioned display module is consistent with the changing frequency of the above-mentioned scanning start signal.
  • the driving circuit is configured to adjust the changing frequency of the first driving control signal according to the image data transmission frequency of the application processor to obtain a second driving control signal, wherein the second driving control signal is used to drive the sub-unit.
  • the pixel circuit displays the display data, and the changing frequency of the second driving control signal matches the image data sending frequency.
  • the driving circuit is configured to, when it is determined that the current display frequency does not match the image data transmission frequency, adjust the changing frequency of the first drive control signal according to the image data transmission frequency to obtain the second drive control. Signal.
  • the driving circuit is configured to, when it is determined that the current display frequency is less than the image data transmission frequency, increase the change frequency of the first drive control signal according to the image data transmission frequency to obtain the second drive control signal.
  • the above-mentioned driving circuit is configured to reduce the change frequency of the above-mentioned first drive control signal according to the above-mentioned image data transmission frequency to obtain the above-mentioned second drive control signal when it is determined that the current display frequency is greater than the image data transmission frequency.
  • the above-mentioned driving circuit is configured to determine the display frequency adjustment information in response to receiving the first display frequency adjustment request from the above-mentioned application processor, and adjust the change frequency of the above-mentioned first drive control signal according to the above-mentioned display frequency adjustment information, to obtain A third drive control signal, wherein the third drive control signal is used to drive the sub-pixel circuit to display display data.
  • the display frequency adjustment information includes a first display frequency range corresponding to the current application program, and the first display frequency range is determined by the application processor based on the attribute information of the current application program.
  • the above display frequency adjustment information includes a preset second display frequency range.
  • the above-mentioned first drive control signal is used to drive the sub-pixel circuit included in the display module to display display data, wherein the above-mentioned display data is determined based on the above-mentioned second current image data, and the current response speed of the above-mentioned display module is the above-mentioned N times the current display frequency of the display module, N is an integer greater than or equal to 1
  • a display device including:
  • the display module is connected to the above-mentioned display controller and configured to display display data according to the drive control signal provided by the above-mentioned display controller, wherein the above-mentioned display data is determined based on the above-mentioned second current image data.
  • the above display modules include:
  • a gate drive circuit connected to the above-mentioned display controller and the above-mentioned sub-pixel circuit, configured to provide a scan start signal, a gate drive signal and a reset signal to the above-mentioned sub-pixel circuit according to the first drive control signal sent by the above-mentioned display controller; as well as
  • the source driving circuit is connected to the above-mentioned display controller and the above-mentioned sub-pixel circuit, and is configured to provide a data signal to the above-mentioned sub-pixel circuit according to the first drive control signal sent by the above-mentioned display controller, wherein the above-mentioned gate drive signal, the above-mentioned reset The signal and the above-mentioned data signal are used to drive the above-mentioned sub-pixel circuit to display the above-mentioned display data.
  • the changing frequency of the scan start signal is used as the anode reset frequency of the sub-pixel circuit.
  • a display system including:
  • the application processor is configured to send the first current image data to the image processing circuit in response to receiving the flag signal from the flag signal circuit.
  • the above-mentioned application processor is configured to send a display frequency adjustment request to the above-mentioned driving circuit, so that the above-mentioned driving circuit responds to receiving the display frequency adjustment request from the above-mentioned application processor and determines the display frequency adjustment information according to the above-mentioned display frequency adjustment information. , adjust the change frequency of the first drive control signal to obtain a third drive control signal, wherein the third drive control signal is used to drive the sub-pixel circuit to display display data.
  • the display frequency adjustment information includes a first display frequency range corresponding to the current application program, and the first display frequency range is determined by the application processor based on the attribute information of the current application program.
  • the above display frequency adjustment information includes a preset second display frequency range.
  • Another aspect of the present disclosure provides a control method applied to the above-mentioned display controller of the present disclosure, including:
  • the flag signal circuit sends the flag signal to the application processor
  • the image processing circuit obtains second current image data in response to receiving the first current image data from the above-mentioned application processor, wherein the above-mentioned first current image data is sent by the above-mentioned application processor in response to receiving the above-mentioned flag signal circuit.
  • the flag bit signal is sent;
  • the driving circuit generates a first driving control signal in response to receiving the second current image data from the above-mentioned image processing circuit.
  • FIG. 1A schematically illustrates a block diagram of a display controller according to an embodiment of the present disclosure
  • FIG. 1B schematically illustrates an example schematic diagram of first current image data and second current image data according to an embodiment of the present disclosure
  • FIG. 2A schematically shows an example schematic diagram of the working process of the flag signal according to an embodiment of the present disclosure
  • FIG. 2B schematically shows an example schematic diagram of the working process of the flag signal according to another embodiment of the present disclosure
  • FIG. 3A schematically shows an example diagram of determining the current display frequency according to the image data transmission frequency according to an embodiment of the present disclosure
  • 3B schematically illustrates an example diagram of determining the current display frequency according to the image data transmission frequency according to another embodiment of the present disclosure
  • FIG. 4 schematically illustrates a block diagram of a display device according to an embodiment of the present disclosure
  • Figure 5 schematically shows a block diagram of a display device according to another embodiment of the present disclosure.
  • FIG. 6A schematically shows a schematic circuit structure diagram of a sub-pixel circuit according to an embodiment of the present disclosure
  • FIG. 6B schematically shows a circuit structure diagram of a sub-pixel circuit according to another embodiment of the present disclosure
  • FIG. 6C schematically shows a schematic circuit structure diagram of a sub-pixel circuit according to another embodiment of the present disclosure
  • Figure 7 schematically shows a signal timing diagram of a display device according to an embodiment of the present disclosure
  • Figure 8 schematically shows a block diagram of a display system according to an embodiment of the present disclosure
  • Figure 9 schematically shows a block diagram of a display system according to another embodiment of the present disclosure.
  • FIG. 10 schematically shows a flowchart of a control method of a display controller according to an embodiment of the present disclosure.
  • FIG. 1A schematically illustrates a block diagram of a display controller according to an embodiment of the present disclosure.
  • a display controller (Display Driver Integrated Circuit, DDIC) 100 may include a flag signal circuit 101 , an image processing circuit 102 and a driving circuit 103 .
  • the driving circuit 103 can be connected with the flag signal circuit 101 and the image processing circuit 102.
  • the flag signal circuit 101 can send a flag signal to an application processor (Application Processor, AP).
  • application processor Application Processor
  • the image processing circuit 102 may obtain second current image data in response to receiving the first current image data from the application processor.
  • the first current image data may be sent by the application processor in response to receiving a flag signal sent from the flag signal circuit 101 .
  • the driving circuit 103 may generate the first driving control signal in response to receiving the second current image data from the image processing circuit 102 .
  • the flag signal may be used to indicate the data processing stage of the display controller.
  • the data processing phase may include at least one of the following: a processing phase and a data retention phase.
  • the processing stage may refer to the stage from which the display controller receives the first current image data from the application processor to generating the first driving control signal.
  • the data holding phase may refer to a phase in which the first current image data is maintained.
  • the flag signal may be a variable frequency flag signal.
  • the variable frequency flag signal can mean that each data processing stage has its own corresponding changing frequency. For example, when the data processing stage is a processing stage, the changing frequency of the flag signal may be 120 Hz. During the data retention phase, the change frequency of the flag signal can be 240Hz.
  • the first current image data may be image data currently received by the display controller from the application processor.
  • the second current image data may be image data obtained by processing the first current image data by the image processing circuit.
  • the first drive control signal can be used to drive the sub-pixel circuit included in the display module to display display data.
  • the display data may be determined based on the second current image data.
  • the first drive control signal may include at least one of the following: scan start (Scan Start Vertical, Scan STV) signal, gate drive (ie Gate STV) signal, reset (ie Reset STV) signal, light emitting (ie EM STV) signal and data signals.
  • the scan start signal can be used to drive the Scan GOA (Gate driver On Array) in the sub-pixel circuit.
  • the gate drive signal can be used to drive the Gate GOA in the sub-pixel circuit.
  • the reset signal can be used to drive the Reset GOA in the sub-pixel circuit.
  • the luminescence signal can be used to drive the EM GOA in the sub-
  • the image processing circuit may include at least one of the following: a decoder, a memory, a rendering circuit, and a compensation circuit.
  • the memory may include multiple memories.
  • the multiple memories may include a frame buffer (ie, Frame Buffer) and other memories.
  • the decoder can be connected to the frame buffer and rendering circuit separately.
  • the compensation circuit can be connected to the rendering circuit and other memories respectively.
  • the frame buffer may be configured to store third current image data.
  • the third current image data may refer to the encoded first current image data.
  • the decoder may be configured to decode the received third current image data to obtain fourth current image data.
  • the fourth current image data may refer to the decoded third current image data.
  • the rendering circuit may be configured to render the received fourth current image data to obtain fifth current image data.
  • Other memory can be configured to store compensation data.
  • the compensation circuit may be configured to compensate the fifth current image data based on compensation data in other memories to obtain the second current image data.
  • the application processor may send the first current image data to the image processing circuit in response to receiving the flag signal sent from the flag signal circuit.
  • the image processing circuit can process the first current image data to obtain the second current image data.
  • the image processing circuit sends the second current image data to the driving circuit.
  • the driving circuit may generate the first driving control signal according to the second current image data.
  • the first drive control signal can be used to drive the sub-pixel circuit in the display module to display display data.
  • the display data may be obtained according to the second current image data.
  • FIG. 1B schematically illustrates an example diagram of first current image data and second current image data according to an embodiment of the present disclosure.
  • the size of the first current image data may be 9 ⁇ 3.
  • the size of the second current image data may be 6 ⁇ 3.
  • the pixel values of the first current image data and the pixel values of the second current image data are different from each other.
  • R in Figure 1B represents Red (i.e. red).
  • G represents Green.
  • B represents Blue (i.e. blue).
  • a flag signal is sent to the application processor through the flag signal circuit.
  • the flag signal is used to indicate that the application processor is allowed to send the first current image data to the image processing circuit, which improves the response speed of the application processor.
  • the first driving control signal may be used to drive a sub-pixel circuit included in the display module to display display data.
  • the display data may be determined based on the second current image data.
  • the current response speed of the display module is N times the current display frequency of the display module. N can be an integer greater than or equal to 1.
  • determining the display data according to the second current image data may include: determining the second current image data as the display data.
  • the second current image data may be processed to obtain display data.
  • the response speed of the display module may refer to the speed at which the display module refreshes the display interface in response to user operations.
  • the display frequency of the display module can refer to the refresh rate of the display module, that is, the number of times the display module refreshes the display interface per second.
  • the response speed of the display module can be independent of the display frequency of the display module.
  • the response speed of the display module may be determined based on the changing frequency of the scan start signal. Since the changing frequency of the scan start signal may be N times the display frequency of the display module, the response speed of the display module may be N times the display frequency of the display module. Regarding the current response speed and the current display frequency, the current response speed of the display module may be N times the current display frequency of the display module.
  • N can be an integer greater than or equal to 1.
  • the current response speed of the display module may be 240Hz.
  • the current display frequency of the display module can be 240/N Hz.
  • the current response speed of the display module may be 360Hz.
  • the current display frequency of the display module can be 360/N Hz.
  • the value of N can be configured according to actual business needs and is not limited here. For example, N can be one of the following: 1, 2, 3, 4, ....
  • the current response speed of the display module is N times the current display frequency of the display module, and the current response speed is no longer limited by the current display frequency, as This improves the current response speed. Due to the improvement of the current response speed, the frequency change granularity of the display frequency has been refined, allowing the display module to share a set of gamma values (i.e. Gamma) at multiple current display frequencies, thus reducing the Cost of production. In addition, since the application processor no longer needs to adapt to multiple display modules with current display frequencies, the adaptation difficulty of the application processor is reduced. Frequency change granularity can refer to the maximum interval between various display frequencies that the display module can support.
  • the flag signal circuit 101 may send the flag signal loaded with the first pulse signal to the application processor.
  • the flag signal loaded with the first pulse signal may be used to indicate that the application processor is allowed to send the first current image data to the image processing circuit 102 .
  • the image processing circuit 102 may obtain second current image data based on the first current image data in response to receiving the first current image data from the application processor.
  • the first current image data may be sent by the application processor in response to receiving a flag signal loaded with a first pulse signal sent from the flag signal circuit 101 .
  • the flag signal loaded with the first pulse signal may be used to indicate that the application processor is allowed to send the first current image data to the image processing circuit 102 . That is, when the application processor receives the flag signal loaded with the first pulse signal from the flag signal circuit 101, if the application processor needs to send the first current image data to the image processing circuit 102, the application processor can be allowed to Send the first current image data. When the application processor receives the flag signal from the flag signal circuit 101 that is not loaded with the first pulse signal, if the application processor needs to send the first current image data to the image processing circuit 102, it may not allow the application. The processor sends first current image data.
  • the form of the first pulse signal can be configured according to actual business requirements, and is not limited here.
  • the first pulse signal may be a positive pulse signal.
  • FIG. 2A schematically shows an example schematic diagram of a working process of a flag signal according to an embodiment of the present disclosure.
  • the flag signal is a variable frequency flag signal.
  • the changing frequency of the flag signal is 120Hz.
  • the change frequency of the flag signal is 240Hz.
  • the flag signal loaded with the first pulse signal may be used to indicate that the application processor is allowed to send image data to the image processing circuit.
  • the application processor When the application processor receives the flag signal loaded with the first pulse signal from the flag signal circuit, if the application processor needs to send the previous image data to the image processing circuit, the application processor is allowed to send the previous image data. .
  • the application processor receives a flag signal sent from the flag signal circuit that is not loaded with the first pulse signal, if the application processor needs to send the first current image data to the image processing circuit, the application processor is not allowed to send The first current image data, until the application processor receives the flag signal loaded with the first pulse signal sent from the flag circuit, can then send the first current image data to the image processing circuit.
  • a flag signal loaded with the first pulse signal is sent to the application processor through the flag signal circuit, and the flag signal loaded with the first pulse signal is used to indicate that the application processor is allowed to send the first pulse signal to the image processing circuit.
  • Current image data improves the response speed of the application processor.
  • the separation of the processing stage and the data maintenance stage allows the application processor to update the image data in time according to the instructions of the flag signal during the data maintenance stage.
  • the first drive control signal may include a scan start signal loaded with a second pulse signal.
  • the driving circuit 103 may generate a scan start signal loaded with the second pulse signal in response to detecting that the previous image data from the application processor is processed.
  • the flag signal circuit 101 may generate a flag signal loaded with the first pulse signal in response to receiving the scan start signal loaded with the second pulse signal from the driving circuit 103 .
  • the possible form of the second pulse signal can be configured according to actual business requirements, and is not limited here.
  • the form of the second pulse signal may be different from the form of the first pulse signal.
  • the second pulse signal may be a negative pulse signal.
  • the first pulse signal may be a positive pulse signal.
  • the pulse width of the second pulse signal is different from the pulse width of the first pulse signal.
  • the scan start signal may be used to drive the Scan GOA in the sub-pixel circuit.
  • the driving circuit 103 may, in response to receiving the previous image data from the application processor, determine whether the previous image data has been processed, and if it is determined that the previous image data has been processed, may generate a scan start loaded with the second pulse signal. Signal. Whether the previous image data is processed may include one of the following: whether the previous image data is being processed and has not been processed, and whether the previous image data has been processed. For example, the driving circuit 103 may generate a scan start signal loaded with the second pulse signal when it is determined that the previous image data has been processed.
  • the driving circuit 103 may send the scan start signal loaded with the second pulse signal to the flag signal circuit 101.
  • the flag signal circuit 101 may generate a flag signal loaded with the first pulse signal in response to receiving the scan start signal loaded with the second pulse signal.
  • the changing frequency of the flag signal loaded with the first pulse signal may be consistent with the changing frequency of the scan start signal.
  • the current response speed of the display module can be consistent with the changing frequency of the scan start signal.
  • the changing frequency of the scan start signal may be 240 Hz.
  • the changing frequency of the flag signal loaded with the first pulse signal may be 240 Hz, that is, the flag signal loaded with the first pulse signal may be generated every 240 Hz.
  • the current response speed of the display module can also be 240Hz. If the changing frequency of the scan start signal is increased to 360 Hz, the changing frequency of the flag signal loaded with the first pulse signal and the current response speed of the display module can also reach 360 Hz.
  • FIG. 2B schematically shows an example schematic diagram of a working process of a flag signal according to another embodiment of the present disclosure.
  • the changing frequency of the scan start signal is 240Hz.
  • the changing frequency of the flag signal loaded with the first pulse signal is consistent with the changing frequency of the scanning start signal.
  • the driving circuit may respond to receiving the previous image data from the application processor and, if it is determined that the previous image data has been processed, may generate a scan start signal loaded with the second pulse signal.
  • the flag signal circuit may generate a flag signal loaded with the first pulse signal in response to receiving the scan start signal loaded with the second pulse signal from the driving circuit.
  • the application processor When the application processor receives the flag signal loaded with the first pulse signal from the flag signal circuit, if the application processor needs to send the previous image data to the image processing circuit, the application processor is allowed to send the previous image data. .
  • the application processor receives a flag signal sent from the flag signal circuit that is not loaded with the first pulse signal, if the application processor needs to send the first current image data to the image processing circuit, the application processor is not allowed to send The first current image data, until the application processor receives the flag signal loaded with the first pulse signal sent from the flag circuit, can then send the first current image data to the image processing circuit.
  • the current response speed of the display module can be N times the current display frequency, thereby improving the current response speed, thereby achieving a display frequency of
  • the refinement of the change granularity allows the display module to share a set of gamma at multiple current display frequencies, thereby reducing production costs.
  • the adaptation difficulty of the application processor is reduced.
  • the driving circuit 103 can adjust the changing frequency of the first driving control signal according to the image data transmission frequency to obtain the second driving control signal.
  • the second drive control signal may be used to drive the sub-pixel circuit to display display data.
  • the changing frequency of the second drive control signal may match the image data transmission frequency.
  • the display controller 100 may adjust the display frequency of the sub-pixel circuit according to the image transmission frequency of the application processor.
  • the image transmission frequency may be determined based on the reception time interval between adjacent predetermined numbers of image data.
  • the predetermined number may be two.
  • the two adjacent image data may include the first current image data and the previous image data.
  • the driving circuit 103 may determine the reception time interval between the first current image data and the previous image data based on the reception time of the first current image data and the reception time of the previous image data.
  • the image transmission frequency is determined based on the reception time interval between the first current image data and the previous image data. It should be noted that the first current image data and the previous image data may change with time.
  • the change frequency of the second drive control signal matching the image data transmission frequency may mean that the change frequency of the second drive control signal may be greater than or equal to the image data transmission frequency.
  • the change frequency of the second drive control signal may be the minimum absolute value of the difference between the candidate change frequency set and the image data transmission frequency.
  • the frequency of target candidate changes.
  • the candidate change frequency set may be determined based on the change frequency of the scan start signal.
  • the driving circuit 103 may determine the target candidate change frequency according to the image data transmission frequency of the application processor.
  • the change frequency of the first drive control signal is adjusted according to the target candidate change frequency to obtain the second drive control signal.
  • the second drive control signal can be used to drive the sub-pixel circuit to display the display data, so that the current display frequency of the display module can match the image data transmission frequency. That is, the driving circuit 103 can obtain the second driving control signal whose changing frequency matches the image data transmission frequency by adjusting the changing frequency of the first driving control signal according to the target candidate changing frequency, because the second driving control signal can be used to drive the display module.
  • a set of sub-pixel circuits is used to display display data. The changing frequency of the second drive control signal can match the display frequency of the current display module. Therefore, the current display frequency of the display module can be matched with the image transmission frequency.
  • the drive circuit 103 may determine that the current display frequency does not match the image data transmission frequency, and adjust the change frequency of the first drive control signal according to the image data transmission frequency to obtain the second drive control signal.
  • the driving circuit 103 may determine whether the current display frequency matches the image data sending frequency. In the case where it is determined that the current display frequency does not match the image data sending frequency, the driving circuit 103 may determine whether the current display frequency matches the image data sending frequency according to the image data sending frequency of the application processor. , adjust the changing frequency of the first drive control signal to obtain the second drive control signal. When it is determined that the current display frequency matches the image data transmission frequency, the operation of adjusting the change frequency of the first drive control signal to obtain the second drive control signal according to the image data transmission frequency of the application processor may no longer be performed.
  • the changing frequency of the first driving control signal that needs to be adjusted may include at least one of the changing frequency of the gate driving signal and the changing frequency of the reset signal.
  • the current display frequency is adjusted according to the image data transmission frequency, thereby achieving the effect that the current display frequency automatically changes with the rendering speed of the application processor.
  • the driving circuit 103 may increase the change frequency of the first driving control signal according to the image data transmission frequency to obtain the second driving control signal.
  • the driving circuit 103 may reduce the change frequency of the first driving control signal according to the image data transmission frequency to obtain the second driving control signal.
  • the image data transmission frequency is 90Hz.
  • the current display frequency is 80Hz.
  • the current response speed is 240Hz.
  • the display frequency is 240/N Hz. N ⁇ 1, 2, 3,... ⁇ , that is, the display frequency can be one of the following: 240Hz, 120Hz, 80Hz, 60Hz, 48Hz, 40Hz, 30Hz, 24Hz,....
  • the above display frequencies can be used as candidate display frequencies.
  • the driving circuit 103 may determine based on the image data transmission frequency and the current display frequency that the current display frequency is smaller than the image data transmission frequency. Therefore, the current display frequency needs to be increased, that is, the change frequency of the first drive control signal needs to be increased. Since there is no candidate display frequency equal to the image data transmission frequency in the at least one candidate display frequency, an absolute value that is greater than the image data transmission frequency and a difference between the image data transmission frequency and the image data transmission frequency can be determined from the at least one candidate display frequency. The minimum target candidate display frequency, therefore, it is determined that the target candidate display frequency is 120 Hz. The driving circuit 103 can increase the changing frequency of the first driving control signal according to the target candidate display frequency to obtain the second driving control signal.
  • the image data transmission frequency is 90Hz.
  • the current display frequency is 80Hz.
  • the current response speed is 360Hz.
  • the display frequency is 360/N Hz. N ⁇ 1, 2, 3,... ⁇ , that is, the display frequency can be one of the following: 360Hz, 180Hz, 120Hz, 90Hz, 72Hz, 60Hz, 45Hz, 40Hz, 36Hz, 30Hz, 24Hz, 20Hz, 18Hz,....
  • the above display frequencies can be used as candidate display frequencies.
  • the driving circuit 103 may determine based on the image data transmission frequency and the current display frequency that the current display frequency is smaller than the image data transmission frequency. Therefore, the current display frequency needs to be increased, that is, the change frequency of the first drive control signal needs to be increased. Since there is a candidate display frequency equal to the image data transmission frequency in at least one candidate display frequency, a target candidate display frequency equal to the image data transmission frequency can be determined from the at least one candidate display frequency, thereby determining the target candidate display frequency It's 90Hz. The driving circuit 103 can increase the changing frequency of the first driving control signal according to the target candidate display frequency to obtain the second driving control signal.
  • the image data transmission frequency is 80Hz.
  • the current display frequency is 90Hz.
  • the current response speed is 360Hz.
  • the display frequency is 360/N Hz. N ⁇ 1, 2, 3,... ⁇ , that is, the display frequency can be one of the following: 360Hz, 180Hz, 120Hz, 90Hz, 72Hz, 60Hz, 45Hz, 40Hz, 36Hz, 30Hz, 24Hz, 20Hz, 18Hz,....
  • the above display frequencies can be used as candidate display frequencies.
  • the driving circuit 103 may determine based on the image data transmission frequency and the current display frequency that the current display frequency is greater than the image data transmission frequency. Therefore, the current display frequency needs to be reduced, that is, the change frequency of the first drive control signal needs to be reduced. Since there is no candidate display frequency equal to the image data transmission frequency in the at least one candidate display frequency, an absolute value that is greater than the image data transmission frequency and a difference between the image data transmission frequency and the image data transmission frequency can be determined from the at least one candidate display frequency. The minimum target candidate display frequency, therefore, it is determined that the target candidate display frequency is 90 Hz. Since the current display frequency is 90 Hz, the current display frequency is equal to the target candidate display frequency. Therefore, the driving circuit 103 can no longer perform the adjustment of the changing frequency of the first driving control signal according to the image data sending frequency of the application processor to obtain the second driving. Control the operation of signals.
  • the image data transmission frequency is 80Hz.
  • the current display frequency is 90Hz.
  • the current response speed is 240Hz.
  • the display frequency is 240/N Hz. N ⁇ 1, 2, 3,... ⁇ , that is, the display frequency can be one of the following: 240Hz, 120Hz, 80Hz, 60Hz, 48Hz, 40Hz, 30Hz, 24Hz,....
  • the above display frequencies can be used as candidate display frequencies.
  • the driving circuit 103 may determine based on the image data transmission frequency and the current display frequency that the current display frequency is greater than the image data transmission frequency. Therefore, the current display frequency needs to be reduced, that is, the change frequency of the first drive control signal needs to be reduced. Since there is a candidate display frequency equal to the image data transmission frequency in at least one candidate display frequency, a target candidate display frequency equal to the image data transmission frequency can be determined from the at least one candidate display frequency, thereby determining the target candidate display frequency It's 80Hz. The driving circuit 103 can reduce the changing frequency of the first driving control signal according to the target candidate display frequency to obtain the second driving control signal.
  • FIG. 3A schematically shows an example diagram of determining the current display frequency according to the image data transmission frequency according to an embodiment of the present disclosure.
  • the image data transmission frequency B is greater than the image data transmission frequency C and less than the image data transmission frequency A. If the image data transmission frequency is the image data transmission frequency A, the current display frequency A that matches the image data transmission frequency A can be determined based on the image data transmission frequency A. If the image data transmission frequency is the image data transmission frequency B, the current display frequency B matching the image data transmission frequency B can be determined based on the image data transmission frequency B. If the image data transmission frequency is the image data transmission frequency C, the current display frequency C that matches the image data transmission frequency C can be determined based on the image data transmission frequency C.
  • FIG. 3B schematically shows an example diagram of determining the current display frequency according to the image data transmission frequency according to another embodiment of the present disclosure.
  • the "dashed line” part may indicate that it is determined that the current display frequency needs to be reduced based on the image data transmission frequency and the current display frequency.
  • the “solid line” part may indicate that the current display frequency needs to be increased based on the image data transmission frequency and the current display frequency.
  • the current display frequency 1 For example, based on the image data transmission frequency 1 and the current display frequency, it is determined that the current display frequency needs to be increased, and the current display frequency 1 is obtained. According to the image data sending frequency 2 and the current display frequency 1, it is determined that the current display frequency 1 needs to be reduced, and the current display frequency 2 is obtained. .
  • According to the image data transmission frequency M and the current display frequency M-1 it is determined that the current display frequency M-1 needs to be increased, and the current display frequency M is obtained.
  • M can be a number greater than 0.
  • the driving circuit 103 may determine the display frequency adjustment information in response to receiving a display frequency adjustment request from the application processor, and adjust the changing frequency of the first driving control signal according to the display frequency adjustment information to obtain a third drive control signal.
  • the third drive control signal may be used to drive the sub-pixel circuit to display display data.
  • the display frequency adjustment request may refer to a request for adjusting the display frequency.
  • the display frequency adjustment request may include display frequency adjustment information.
  • the display frequency adjustment information may include a display frequency range.
  • the display frequency range may be obtained in one of the following ways: the display frequency range may be preset.
  • the display frequency range may be determined by the application processor based on attribute information of the current application.
  • the application processor may generate a display frequency adjustment request according to the display frequency adjustment information.
  • the application processor may send a display frequency adjustment request to the driving circuit 103 .
  • the driving circuit 103 may respond to receiving the display frequency adjustment request from the application processor, analyze the display frequency adjustment request, and obtain the display frequency adjustment information.
  • the driving circuit 103 may adjust the changing frequency of the first driving control signal according to the display frequency adjustment information to obtain a third driving control signal.
  • the display frequency adjustment information may include a first display frequency range corresponding to the current application.
  • the first display frequency range may be determined by the application processor based on attribute information of the current application program.
  • the attribute information may include an application type.
  • the application type can refer to the type of the application itself.
  • the type of the application itself can be determined based on the application's application ID.
  • the application type can also refer to the type determined based on the functions provided by the application.
  • the functions provided by the application may include at least one of the following: games, social, shopping, video, audio, and text.
  • the application type may include at least one of the following: game type, social type, shopping type, video type, audio type and text type.
  • an application program may have a display frequency range corresponding to the application program.
  • the application processor may determine the first display frequency range of the current application program according to the attribute information of the current application program.
  • the first display frequency range may be determined based on the first display frequency and the second display frequency.
  • the first display frequency may be greater than the second display frequency.
  • the first display frequency may be the highest display frequency in the first display frequency range.
  • the second display frequency may be the lowest display frequency in the first display frequency range.
  • the display frequency may have a display frequency level corresponding to the display frequency.
  • the current application is "XX".
  • " ⁇ " can represent the application identifier.
  • the functionality provided by the current application is gaming. According to the application identification, it can be determined that the application type of the current application can be "XX”. Alternatively, since the function provided by the current application is a game, it may be determined that the application type of the current application may be a game class.
  • the first display frequency range corresponding to the current application "XX” may be greater than or equal to 120 Hz and less than or equal to 240 Hz.
  • the current application is "**".
  • "**" can represent application identification.
  • the functionality provided by the current application is social. Based on the application identification, it can be determined that the application type of the current application can be "**".
  • the function provided by the current application is social, it may be determined that the application type of the current application may be a social type.
  • the first display frequency range corresponding to the current application "**" may be greater than or equal to 80 Hz and less than or equal to 120 Hz.
  • the application processor may determine the first display frequency range corresponding to the current application program according to the attribute information of the current application program, the application processor sends the first display frequency range to the driving circuit, and the driving circuit determines the first display frequency range corresponding to the current application program according to the first display frequency range.
  • the display frequency range is used to adjust the current display frequency of the display module so that the current display frequency of the display module matches the display frequency required by the current application, thus reducing the power consumption of the display module.
  • the display frequency adjustment information may include a preset second display frequency range.
  • the second display frequency range may be preset. Different from the first display frequency range, current applications may not be distinguished, and each current application program has the same second display frequency range.
  • FIG. 4 schematically shows a block diagram of a display device according to an embodiment of the present disclosure.
  • the display device 400 may include a display controller 401 and a display module 402 .
  • the display controller 401 can be connected with the display module 402.
  • the display controller 401 may be the display controller 100 according to embodiments of the present disclosure.
  • the display module 402 may be configured to display display data according to the driving control signal provided by the display controller 401 .
  • the display data may be determined based on the second current image data.
  • FIG. 5 schematically shows a block diagram of a display device according to another embodiment of the present disclosure.
  • the display device 500 may include a display controller 501 and a display module 502 .
  • the display controller 501 may include a flag signal circuit 501_1, an image processing circuit 501_2 and a driving circuit 501_3.
  • the driving circuit 501_3 may be connected with the flag signal circuit 501_1 and the image processing circuit 501_2.
  • the display module 502 may include a sub-pixel circuit 502_1, a gate driving circuit 502_2 and a source driving circuit 502_3.
  • the gate driving circuit 502_2 may be connected with the sub-pixel circuit 502_1 and the display controller 501.
  • the source driving circuit 502_3 may be connected with the sub-pixel circuit 502_1 and the display controller 501.
  • the gate driving circuit 502_2 may provide the scan start signal, the gate driving signal and the reset signal to the sub-pixel circuit 502_1 according to the first driving control signal sent by the display controller 501.
  • the source driving circuit 502_3 may provide a data signal to the sub-pixel circuit 502_1 according to the first driving control signal sent by the display controller 501.
  • the scan start signal, gate drive signal, reset signal and data signal can be used to drive the sub-pixel circuit 502_1 to display display data.
  • the drive control signal may include a scan start signal, a gate drive signal, a reset signal, and a data signal.
  • the driving control signal may also include a light emitting signal.
  • the subpixel circuit 502_1 may include R ⁇ S subpixels. R ⁇ S sub-pixels are arranged in an R ⁇ S array. R and S can be integers greater than 1.
  • the changing frequency of the scan start signal may be used as the anode reset frequency of the sub-pixel circuit.
  • the reset signal of the T7 tube in the sub-pixel circuit 502_1 can be independently driven by the scan start signal and is not affected by the display frequency. Therefore, the changing frequency of the scan start signal can be used as The anode reset frequency of the subpixel circuit.
  • the type of sub-pixel circuit 502_1 may include one of the following: 7T1C, 8T1C, and 9T1C.
  • the type of the sub-pixel circuit 502_1 can also be other types, which is not limited here.
  • FIG. 6A schematically shows a circuit structure diagram of a sub-pixel circuit according to an embodiment of the present disclosure.
  • the sub-pixel circuit 600A can separate the reset signal of the T7 tube in the 7T1C and drive it solely by the scan start signal.
  • Other structures are the same as those of 7T1C and will not be described again here.
  • FIG. 6B schematically shows a schematic circuit structure diagram of a sub-pixel circuit according to another embodiment of the present disclosure.
  • the sub-pixel circuit 600B can separate the reset signal of the T7 tube in the 8T1C and drive it solely by the scan start signal.
  • the scan start signal can also be shared with the reset signal of the T8 tube.
  • the changing frequency of the reset signal of the T8 tube can change with the changing frequency of the scan start signal.
  • Other structures are the same as those of 8T1C and will not be described again here.
  • FIG. 6C schematically shows a circuit structure diagram of a sub-pixel circuit according to another embodiment of the present disclosure.
  • the sub-pixel circuit 600C can separate the reset signal of the T7 tube in 9T1C and drive it solely by the scan start signal.
  • the scan start signal can also be shared with the reset signals of the T8 tube and T9 tube.
  • the changing frequency of the reset signal of the T8 tube and the T9 tube can change with the changing frequency of the scan start signal.
  • Other structures are the same as those of 9T1C and will not be described again here.
  • FIG. 7 schematically shows a signal timing diagram of a display device according to an embodiment of the present disclosure.
  • the P_gate/reset signal may refer to the gate drive signal and the reset signal of the P pole.
  • the N_gate/reset signal can refer to the N-pole gate drive signal and reset signal.
  • the changing frequency of the luminous signal is 480Hz.
  • the changing frequency of the scan start signal is 240Hz.
  • the changing frequency of the flag signal is 120Hz.
  • the changing frequency of the flag signal is 240Hz.
  • the current response speed of the display module is consistent with the changing frequency of the scan start signal, that is, the current response speed of the display module is 240Hz.
  • the current display frequency of the display module is consistent with the changing frequency of the P_gate/reset signal and N_gate/reset signal, that is, the current display frequency of the display module is 120Hz. It should be noted that the luminescence signal and the scan start signal are displayed at a constant predetermined frequency, and the P-gate/reset signal and N-gate/reset signal are consistent with the current display frequency of the display module.
  • N can be an integer greater than or equal to 1.
  • Figure 8 schematically shows a block diagram of a display system according to an embodiment of the present disclosure.
  • display system 800 may include a display device 801 and an application processor 802 .
  • Display device 801 may be connected to application processor 802.
  • the display device 801 may be a display device according to embodiments of the present disclosure.
  • the application processor 802 may send the first current image data to the image processing circuit in response to receiving the flag signal from the flag signal circuit.
  • the application processor 802 may send a display frequency adjustment request to the driving circuit, so that the driving circuit determines the display frequency adjustment information in response to receiving the display frequency adjustment request from the application processor 802, according to the display frequency adjustment information , adjust the changing frequency of the first drive control signal to obtain the third drive control signal.
  • the third drive control signal may be used to drive the sub-pixel circuit to display display data.
  • the application processor 802 may send a display frequency adjustment request to the driving circuit, so that the driving circuit determines the display frequency adjustment information in response to receiving the display frequency adjustment request from the application processor 802, according to the display frequency adjustment information , adjust the changing frequency of the first drive control signal to obtain the third drive control signal.
  • the third drive control signal may be used to drive the sub-pixel circuit to display display data.
  • the display frequency adjustment information may include a first display frequency range corresponding to the current application.
  • the first display frequency range may be determined by the application processor 802 according to the attribute information of the current application program.
  • the display frequency adjustment information may include a preset second display frequency range.
  • Figure 9 schematically shows a block diagram of a display system according to another embodiment of the present disclosure.
  • display system 900 may include a display device 901 and an application processor 902 .
  • the display device 900 may include a display controller 901_1 and a display module 901_2.
  • the display controller 901_1 may send a flag signal to the application processor 902, and in response to receiving the first current image data from the application processor 902, obtain the second current image data according to the first current image data.
  • the first current image data is sent by the application processor 902 in response to receiving the flag signal sent from the display controller 901_1.
  • the display controller 901_1 may generate the first drive control signal in response to the second current image data.
  • the first drive control signal can be used to drive the sub-pixel circuit included in the display module 901_2 to display display data.
  • FIG. 10 schematically shows a flowchart of a control method of a display controller according to an embodiment of the present disclosure.
  • the method 1000 includes operations S1010 to S1030.
  • the flag signal circuit sends a flag signal to the application processor.
  • the image processing circuit obtains second current image data in response to receiving the first current image data from the application processor.
  • the first current image data is sent by the application processor in response to receiving the flag signal sent from the flag signal circuit.
  • the driving circuit In operation S1030, the driving circuit generates a first driving control signal in response to receiving the second current image data from the image processing circuit.

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Abstract

一种显示控制器（100、401、501、901_1）、显示设备（400、500，801、901）、显示系统（800、900）以及控制方法。显示控制器（100、401、501、901_1）包括：标志位信号电路（101、501_1），配置为向应用处理器（802、902）发送标志位信号；图像处理电路（102、501_2），配置为响应于接收到来自应用处理器（802、902）的第一当前图像数据，得到第二当前图像数据。其中，第一当前图像数据是应用处理器（802、902）响应于接收到来自标志位信号电路（102、501_2）发送的标志位信号发送的；驱动电路（103），配置为响应于接收到来自图像处理电路（102、501_2）的第二当前图像数据生成第一驱动控制信号。

Description

显示控制器、显示设备、显示系统以及控制方法 技术领域
本公开涉及显示技术领域，更具体地，涉及一种显示控制器、显示设备、显示系统以及控制方法。
背景技术
随着信息科学技术的发展，显示技术也得到了发展。基于有机发光二极管(Organic Electroluminescence Display，OLED)的显示技术具有自发光、视角广、响应快、可弯曲和柔性化等特点，是显示技术领域的较为重要的突破，提高了视觉效果。
随着LTPO(Low-Temperature Polycrystalline Oxide，低温多晶氧化物)技术基于在OLED的显示技术的应用，使得显示模组的显示频率能够在实现高显示频率的同时，也可以向超低显示频率进行延伸，由此，使得显示模组所需要支持的显示频率越来越多。
发明内容
有鉴于此，本公开提供了一种显示控制器、显示设备、显示系统以及控制方法。
本公开的一个方面提供了一种显示控制器，包括：
标志位信号电路，配置为向应用处理器发送标志位信号；
图像处理电路，配置为响应于接收到来自上述应用处理器的第一当前图像数据，得到第二当前图像数据，其中，上述第一当前图像数据是上述应用处理器响应于接收到来自上述标志位信号电路发送的标志位信号发送的；以及
驱动电路，配置为响应于接收到来自上述图像处理电路的第二当前图像数据生成第一驱动控制信号。
例如，上述标志位信号电路，配置为向上述应用处理器发送加载第一脉冲信号的标志位信号，其中，加载上述第一脉冲信号的标志位信号用于指示允许上述应用处理器向上述图像处理电路发送上述第一当前图像数据；以及
上述图像处理电路，配置为响应于接收到来自上述应用处理器的第一当前图像 数据，根据上述第一当前图像数据，得到上述第二当前图像数据，其中，上述第一当前图像数据是上述应用处理器响应于接收到来自上述标志位信号电路发送的加载上述第一脉冲信号的标志位信号发送的。
例如，上述第一驱动控制信号包括加载第二脉冲信号的扫描起始信号；
上述驱动电路，配置为响应于检测到来自上述应用处理器的上一图像数据被处理，生成加载上述第二脉冲信号的扫描起始信号；以及
上述标志位信号电路，配置为响应于接收到来自上述驱动电路的加载上述第二脉冲信号的扫描起始信号，生成加载上述第一脉冲信号的标志位信号。
例如，加载上述第一脉冲信号的标志位信号的变化频率与上述扫描起始信号的变化频率一致；
上述显示模组的响应速度与上述扫描起始信号的变化频率一致。
例如，上述驱动电路，配置为根据上述应用处理器的图像数据发送频率，调整上述第一驱动控制信号的变化频率，得到第二驱动控制信号，其中，上述第二驱动控制信号用于驱动上述子像素电路来显示显示数据，上述第二驱动控制信号的变化频率与上述图像数据发送频率相匹配。
例如，上述驱动电路，配置为在确定上述当前显示频率与上述图像数据发送频率不匹配的情况下，根据上述图像数据发送频率，调整上述第一驱动控制信号的变化频率，得到上述第二驱动控制信号。
例如，上述驱动电路，配置为在确定上述当前显示频率小于上述图像数据发送频率的情况下，根据上述图像数据发送频率，增加上述第一驱动控制信号的变化频率，得到上述第二驱动控制信号。
例如，上述驱动电路，配置为在确定上述当前显示频率大于上述图像数据发送频率的情况下，根据上述图像数据发送频率，减小上述第一驱动控制信号的变化频率，得到上述第二驱动控制信号。
例如，上述驱动电路，配置为响应于接收到来自上述应用处理器的第一显示频率调整请求，确定显示频率调整信息，根据上述显示频率调整信息，调整上述第一驱动控制信号的变化频率，得到第三驱动控制信号，其中，上述第三驱动控制信号用于驱动上述子像素电路来显示显示数据。
例如，上述显示频率调整信息包括与当前应用程序对应的第一显示频率范围， 上述第一显示频率范围是上述应用处理器根据上述当前应用程序的属性信息确定的。
例如，上述显示频率调整信息包括预先设置的第二显示频率范围。
例如，上述第一驱动控制信号用于驱动显示模组包括的子像素电路来显示显示数据，其中，上述显示数据是根据上述第二当前图像数据确定的，上述显示模组的当前响应速度是上述显示模组的当前显示频率的N倍，N是大于或等于1的整数
本公开的另一方面，提供了一种显示设备，包括：
根据本公开上述的显示控制器；以及
显示模组，与上述显示控制器连接，配置为根据上述显示控制器提供的驱动控制信号来显示显示数据，其中，上述显示数据是根据上述第二当前图像数据确定的。
例如，上述显示模组，包括：
子像素电路；
栅极驱动电路，与上述显示控制器和上述子像素电路连接，配置为根据上述显示控制器发送的第一驱动控制信号向上述子像素电路提供扫描起始信号、栅极驱动信号和复位信号；以及
源极驱动电路，与上述显示控制器和上述子像素电路连接，配置为根据上述显示控制器发送的第一驱动控制信号向上述子像素电路提供数据信号，其中，上述栅极驱动信号、上述复位信号和上述数据信号用于驱动上述子像素电路来显示上述显示数据。
例如，上述扫描起始信号的变化频率用于作为上述子像素电路的阳极复位频率。
本公开的另一方面，提供了一种显示系统，包括：
根据本公开上述的显示设备；以及
应用处理器，配置为响应于接收到来自标志位信号电路的标志位信号，向上述图像处理电路发送上述第一当前图像数据。
例如，上述应用处理器，配置为向上述驱动电路发送显示频率调整请求，以便上述驱动电路响应于接收到来自上述应用处理器的显示频率调整请求，确定显示频率调整信息，根据上述显示频率调整信息，调整上述第一驱动控制信号的变化频率，得到第三驱动控制信号，其中，上述第三驱动控制信号用于驱动上述子像素电路来显示显示数据。
例如，上述显示频率调整信息包括与当前应用程序对应的第一显示频率范围， 上述第一显示频率范围是上述应用处理器根据上述当前应用程序的属性信息确定的。
例如，上述显示频率调整信息包括预先设置的第二显示频率范围。
本公开的另一方面，提供了一种应用于本公开上述的显示控制器的控制方法，包括：
标志位信号电路向应用处理器发送标志位信号；
图像处理电路响应于接收到来自上述应用处理器的第一当前图像数据，得到第二当前图像数据，其中，上述第一当前图像数据是上述应用处理器响应于接收到来自上述标志位信号电路发送的标志位信号发送的；以及
驱动电路响应于接收到来自上述图像处理电路的第二当前图像数据生成第一驱动控制信号。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1A示意性示出了根据本公开实施例的显示控制器的框图；
图1B示意性示出了根据本公开实施例的第一当前图像数据和第二当前图像数据的示例示意图；
图2A示意性示出了根据本公开实施例的标志位信号的工作过程的示例示意图；
图2B示意性示出了根据本公开另一实施例的标志位信号的工作过程的示例示意图；
图3A示意性示出了根据本公开实施例的根据图像数据发送频率，确定当前显示频率的示例示意图；
图3B示意性示出了根据本公开另一实施例的根据图像数据发送频率，确定当前显示频率的示例示意图；
图4示意性示出了根据本公开实施例的显示设备的框图；
图5示意性示出了根据本公开另一实施例的显示设备的框图；
图6A示意性示出了根据本公开实施例的子像素电路的电路结构示意图；
图6B示意性示出了根据本公开另一实施例的子像素电路的电路结构示意图；
图6C示意性示出了根据本公开另一实施例的子像素电路的电路结构示意图；
图7示意性示出了根据本公开实施例的显示设备的信号时序图；
图8示意性示出了根据本公开实施例的显示系统的框图；
图9示意性示出了根据本公开另一实施例的显示系统的框图；以及
图10示意性示出了根据本公开实施例的显示控制器的控制方法的流程图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本公开实施例的全面理解。然而，明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在此使用的术语仅仅是为了描述具体实施例，而并非意在限制本公开。在此使用的术语“包括”、“包含”等表明了所述特征、步骤、操作和/或部件的存在，但是并不排除存在或添加一个或多个其他特征、步骤、操作或部件。
在此使用的所有术语(包括技术和科学术语)具有本领域技术人员通常所理解的含义，除非另外定义。应注意，这里使用的术语应解释为具有与本说明书的上下文相一致的含义，而不应以理想化或过于刻板的方式来解释。
在使用类似于“A、B和C等中至少一个”这样的表述的情况下，一般来说应该按照本领域技术人员通常理解该表述的含义来予以解释(例如，“具有A、B和C中至少一个的系统”应包括但不限于单独具有A、单独具有B、单独具有C、具有A和B、具有A和C、具有B和C、和/或具有A、B、C的系统等)。在使用类似于“A、B或C等中至少一个”这样的表述的情况下，一般来说应该按照本领域技术人员通常理解该表述的含义来予以解释(例如，“具有A、B或C中至少一个的系统”应包括但不限于单独具有A、单独具有B、单独具有C、具有A和B、具有A和C、具有B和C、和/或具有A、B、C的系统等)。
图1A示意性示出了根据本公开实施例的显示控制器的框图。
如图1A所示，在100A中，显示控制器(Display Driver Integrated Circuit，DDIC)100可以包括标志位信号电路101、图像处理电路102和驱动电路103。驱动电路103可以与标志位信号电路101和图像处理电路102连接。
标志位信号电路101可以向应用处理器(Application Processor，AP)发送标志位信号。
图像处理电路102可以响应于接收到来自应用处理器的第一当前图像数据，得到第二当前图像数据。第一当前图像数据可以是应用处理器响应于接收到来自标志位信号电路101发送的标志位信号发送的。
驱动电路103可以响应于接收到来自图像处理电路102的第二当前图像数据生成第一驱动控制信号。
根据本公开的实施例，标志位信号可以用于指示显示控制器的数据处理阶段。数据处理阶段可以包括以下至少之一：正在处理阶段和数据保持阶段。正在处理阶段可以指显示控制器从接收到来自应用处理器的第一当前图像数据到生成第一驱动控制信号的阶段。数据保持阶段可以指维持第一当前图像数据的阶段。标志位信号可以是频率可变的标志位信号。频率可变的标志位信号可以指各个数据处理阶段具有各自对应的变化频率。例如，在数据处理阶段是正在处理阶段的情况下，标志位信号的变化频率可以是120Hz。在数据保持阶段，标志位信号的变化频率可以是240Hz。
根据本公开的实施例，第一当前图像数据可以是显示控制器当前接收到的来自应用处理器的图像数据。第二当前图像数据可以是图像处理电路对第一当前图像数据进行处理得到的图像数据。第一驱动控制信号可以用于驱动显示模组包括的子像素电路来显示显示数据。显示数据可以是根据第二当前图像数据确定的。第一驱动控制信号可以包括以下至少之一：扫描起始(Scan Start Vertical，Scan STV)信号、栅极驱动(即Gate STV)信号、复位(即Reset STV)信号、发光(即EM STV)信号和数据信号。扫描起始信号可以用于驱动子像素电路中的Scan GOA(Gate driver On Array，栅极驱动器阵列)。栅极驱动信号可以用于驱动子像素电路中的Gate GOA。复位信号可以用于驱动子像素电路中的Reset GOA。发光信号可以用于驱动子像素电路中的EM GOA。
根据本公开的实施例，图像处理电路可以包括以下至少之一：解码器、存储器、渲染电路和补偿电路。存储器可以包括多个，例如，多个存储器可以包括帧缓存(即Frame Buffer)和其他存储器。解码器可以分别与帧缓存和渲染电路连接。补偿电路可以分别与渲染电路和其他存储器连接。帧缓存可以配置为存储第三当前图像数据。 第三当前图像数据可以指编码后的第一当前图像数据。解码器可以配置为对接收到的第三当前图像数据进行解码，得到第四当前图像数据。第四当前图像数据可以指解码后的第三当前图像数据。渲染电路可以配置为对接收到的第四当前图像数据进行渲染，得到第五当前图像数据。其他存储器可以配置为存储补偿数据。补偿电路可以配置为基于其他存储器中的补偿数据对第五当前图像数据进行补偿，得到第二当前图像数据。
根据本公开的实施例，应用处理器可以响应于接收到来自标志位信号电路发送的向标志位信号，向图像处理电路发送第一当前图像数据。图像处理电路可以对第一当前图像数据进行处理，得到第二当前图像数据。图像处理电路向驱动电路发送第二当前图像数据。驱动电路可以根据第二当前图像数据来生成第一驱动控制信号。第一驱动控制信号可以用于驱动显示模组中的子像素电路显示显示数据。显示数据可以是根据第二当前图像数据得到的。
图1B示意性示出了根据本公开实施例的第一当前图像数据和第二当前图像数据的示例示意图。
如图1B所示，在100B中，第一当前图像数据的尺寸可以是9×3。第二当前图像数据的尺寸可以是6×3。此外，第一当前图像数据的像素值与第二当前图像数据的像素值各不相同。图1B中R表征Red(即红色)。G表征Green(即绿色)。B表征Blue(即蓝色)。
根据本公开的实施例，通过标志位信号电路向应用处理器发送标志位信号，标志位信号用于指示允许应用处理器向图像处理电路发送第一当前图像数据，提高了应用处理器的反应速度。
根据本公开的实施例，第一驱动控制信号可以用于驱动显示模组包括的子像素电路来显示显示数据。显示数据可以是根据第二当前图像数据确定的。显示模组的当前响应速度是显示模组的当前显示频率的N倍。N可以是大于或等于1的整数。
根据本公开的实施例，根据第二当前图像数据，确定显示数据，可以包括：将第二当前图像数据确定为显示数据。备选地，可以对第二当前图像数据进行处理，得到显示数据。
根据本公开的实施例，显示模组的响应速度可以指显示模组响应用户操作来刷新显示界面的速度。显示模组的显示频率可以指显示模组的刷新率，即每秒显示模 组刷新显示界面的次数。显示模组的响应速度可以与显示模组的显示频率独立。显示模组的响应速度可以是根据扫描起始信号的变化频率确定的。由于扫描起始信号的变化频率可以是显示模组的显示频率N倍，因此，显示模组的响应速度可以是显示模组的显示频率的N倍。针对当前响应速度和当前显示频率，显示模组的当前响应速度可以是显示模组的当前显示频率的N倍。N可以是大于或等于1的整数。例如，显示模组的当前响应速度可以是240Hz。显示模组的当前显示频率可以是240/N Hz。备选地，显示模组的当前响应速度可以是360Hz。显示模组的当前显示频率可以是360/N Hz。N的数值可以根据实际业务需求进行配置，在此不作限定。例如，N可以是以下之一：1、2、3、4、......。
根据本公开的实施例，通过显示控制器的内部数据处理方式，使得显示模组的当前响应速度是显示模组的当前显示频率的N倍，当前响应速度不再受限于当前显示频率，由此，提高了当前响应速度。由于当前响应速度的提高，因此，实现了显示频率的频率变化颗粒度的精细化，使得显示模组能够在多个当前显示频率下共用一组伽马值(即Gamma)，由此，降低了生产成本。此外，由于应用处理器无需再对多个当前显示频率的显示模组进行适配，因此，降低了应用处理器的适配难度。频率变化颗粒度可以指显示模组可以支持的各个显示频率之间的最大间隔。
根据本公开的实施例，标志位信号电路101可以向应用处理器发送加载第一脉冲信号的标志位信号。加载第一脉冲信号的标志位信号可以用于指示允许应用处理器向图像处理电路102发送第一当前图像数据。
图像处理电路102可以响应于接收到来自应用处理器的第一当前图像数据，根据第一当前图像数据，得到第二当前图像数据。第一当前图像数据可以是应用处理器响应于接收到来自标志位信号电路101发送的加载第一脉冲信号的标志位信号发送的。
根据本公开的实施例，加载第一脉冲信号的标志位信号可以用于指示允许应用处理器向图像处理电路102发送第一当前图像数据。即应用处理器在接收到来自标志位信号电路101的加载第一脉冲信号的标志位信号的情况下，应用处理器如果需要向图像处理电路102发送第一当前图像数据，则可以允许应用处理器发送第一当前图像数据。应用处理器在接收到来自标志位信号电路101发送的未加载第一脉冲信号的标志位信号的情况下，应用处理器如果需要向图像处理电路102发送第一当前图像数据， 则可以不允许应用处理器发送第一当前图像数据。
根据本公开的实施例，第一脉冲信号的形式可以根据实际业务需求进行配置，在此不作限定。例如，第一脉冲信号可以是正脉冲信号。
图2A示意性示出了根据本公开实施例的标志位信号的工作过程的示例示意图。
如图2A所示，在200A中，标志位信号是频率可变的标志位信号。在数据处理阶段是正在处理阶段的情况下，标志位信号的变化频率是120Hz。在数据保持阶段，标志位信号的变化频率是240Hz。加载第一脉冲信号的标志位信号可以用于指示允许应用处理器向图像处理电路发送图像数据。
应用处理器在接收到来自标志位信号电路的加载第一脉冲信号的标志位信号的情况下，应用处理器如果需要向图像处理电路发送上一图像数据，则允许应用处理器发送上一图像数据。应用处理器在接收到来自标志位信号电路发送的未加载第一脉冲信号的标志位信号的情况下，应用处理器如果需要向图像处理电路发送第一当前图像数据，则不允许应用处理器发送第一当前图像数据，直至应用处理器接收到来自标志位电路发送的加载第一脉冲信号的标志位信号，则可以向图像处理电路发送第一当前图像数据。
根据本公开的实施例，通过标志位信号电路向应用处理器发送加载第一脉冲信号的标志位信号，加载第一脉冲信号的标志位信号用于指示允许应用处理器向图像处理电路发送第一当前图像数据，提高了应用处理器的反应速度。此外，将正在处理阶段和数据维持阶段分离，允许应用处理器在数据维持阶段，根据标志位信号的指示及时更新图像数据。
根据本公开的实施例，第一驱动控制信号可以包括加载第二脉冲信号的扫描起始信号。
驱动电路103可以响应于检测到来自应用处理器的上一图像数据被处理，生成加载第二脉冲信号的扫描起始信号。
标志位信号电路101可以响应于接收到来自驱动电路103的加载第二脉冲信号的扫描起始信号，生成加载第一脉冲信号的标志位信号。
根据本公开的实施例，第二脉冲信号可以的形式可以根据实际业务需求进行配置，在此不作限定。第二脉冲信号的形式可以与第一脉冲信号的形式不同。例如，第二脉冲信号可以是负脉冲信号。第一脉冲信号可以是正脉冲信号。第二脉冲信号 的脉宽与第一脉冲信号的脉宽不同。
根据本公开的实施例，扫描起始信号可以用于驱动子像素电路中的Scan GOA。驱动电路103可以响应于接收到来自应用处理器的上一图像数据，确定上一图像数据是否被处理，在确定上一图像数据被处理的情况下，可以生成加载第二脉冲信号的扫描起始信号。上一图像数据是否被处理可以包括以下之一：上一图像数据是否被正在处理且未被处理完毕和上一图像数据是否被处理完毕。例如，驱动电路103可以在确定上一图像数据被处理完毕的情况下，生成加载第二脉冲信号的扫描起始信号。
根据本公开的实施例，驱动电路103可以向标志位信号电路101发送加载第二脉冲信号的扫描起始信号。标志位信号电路101可以可以响应于接收到加载第二脉冲信号的扫描起始信号，生成加载第一脉冲信号的标志位信号。
根据本公开的实施例，加载第一脉冲信号的标志位信号的变化频率可以与扫描起始信号的变化频率一致。显示模组的当前响应速度可以与扫描起始信号的变化频率一致。
根据本公开的实施例，例如，扫描起始信号的变化频率可以是240Hz。加载第一脉冲信号的标志位信号的变化频率可以是240Hz，即可以每隔240Hz生成加载第一脉冲信号的标志位信号。显示模组的当前响应速度也可以是240Hz。如果将扫描起始信号的变化频率提高到360Hz，则加载第一脉冲信号的标志位信号的变化频率和显示模组的当前响应速度也可以达到360Hz。
图2B示意性示出了根据本公开另一实施例的标志位信号的工作过程的示例示意图。
如图2B所示，在200B中，扫描起始信号的变化频率是240Hz。加载第一脉冲信号的标志位信号的变化频率与扫描起始信号的变化频率一致。
驱动电路可以响应于接收到来自应用处理器的上一图像数据，在确定上一图像数据被处理完毕的情况下，可以生成加载第二脉冲信号的扫描起始信号。标志位信号电路可以响应于接收到来自驱动电路的加载第二脉冲信号的扫描起始信号，生成加载第一脉冲信号的标志位信号。
应用处理器在接收到来自标志位信号电路的加载第一脉冲信号的标志位信号的情况下，应用处理器如果需要向图像处理电路发送上一图像数据，则允许应用处理器发送上一图像数据。应用处理器在接收到来自标志位信号电路发送的未加载第一 脉冲信号的标志位信号的情况下，应用处理器如果需要向图像处理电路发送第一当前图像数据，则不允许应用处理器发送第一当前图像数据，直至应用处理器接收到来自标志位电路发送的加载第一脉冲信号的标志位信号，则可以向图像处理电路发送第一当前图像数据。
根据本公开的实施例，通过将显示模组的当前响应速度与当前显示频率彼此独立，当前响应速度可以是当前显示频率的N倍，提高了当前响应速度，由此，实现了显示频率的频率变化颗粒度的精细化，使得显示模组能够在多个当前显示频率下共用一组Gamma，进而降低了生产成本。此外，由于应用处理器无需再对多个当前显示频率的显示模组进行适配，因此，降低了应用处理器的适配难度。
根据本公开的实施例，驱动电路103可以根据图像数据发送频率，调整第一驱动控制信号的变化频率，得到第二驱动控制信号。第二驱动控制信号可以用于驱动子像素电路来显示显示数据。第二驱动控制信号的变化频率可以与图像数据发送频率相匹配。
根据本公开的实施例，显示控制器100可以根据应用处理器的图像发送频率来调整子像素电路的显示频率。图像发送频率可以是根据相邻预定数目的图像数据之间的接收时间间隔来确定的。例如，预定数目可以是两个。相邻两个图像数据可以包括第一当前图像数据和上一图像数据。驱动电路103可以根据第一当前图像数据的接收时刻和上一图像数据的接收时刻，确定第一当前图像数据和上一图像数据时间的接收时间间隔。根据第一当前图像数据和上一图像数据的接收时间间隔，确定图像发送频率。需要说明的是，第一当前图像数据和上一图像数据可以是随着时间的变化而变化的。
根据本公开的实施例，第二驱动控制信号的变化频率与图像数据发送频率相匹配可以指第二驱动控制信号的变化频率可以大于或等于图像数据发送频率。在此情况下，如果第二驱动控制信号的变化频率大于图像数据发送频率，则第二驱动控制信号的变化频率可以是候选变化频率集合中与图像数据发送频率之间的差值的绝对值最小的目标候选变化频率。候选变化频率集合可以是根据扫描起始信号的变化频率确定的。
根据本公开的实施例，驱动电路103可以根据应用处理器的图像数据发送频率，确定目标候选变化频率。根据目标候选变化频率来调整第一驱动控制信号的变化频 率，得到第二驱动控制信号。第二驱动控制信号可以用于驱动子像素电路来显示显示数据，由此，使得显示模组的当前显示频率可以与图像数据发送频率相匹配。即驱动电路103可以通过根据目标候选变化频率调整第一驱动控制信号的变化频率来得到变化频率与图像数据发送频率相匹配的第二驱动控制信号，由于第二驱动控制信号可以用于驱动显示模组的子像素电路来显示显示数据，第二驱动控制信号的变化频率可以与当前显示模组的显示频率相匹配，因此，可以实现显示模组的当前显示频率与图像发送频率相匹配。
根据本公开的实施例，驱动电路103可以确定当前显示频率与图像数据发送频率不匹配的情况下，根据图像数据发送频率，调整第一驱动控制信号的变化频率，得到第二驱动控制信号。
根据本公开的实施例，驱动电路103可以确定当前显示频率是否与图像数据发送频率相匹配，在确定当前显示频率与图像数据发送频率不匹配的情况下，可以根据应用处理器的图像数据发送频率，调整第一驱动控制信号的变化频率，得到第二驱动控制信号。在确定当前显示频率与图像数据发送频率匹配的情况下，可以不再执行根据应用处理器的图像数据发送频率，调整第一驱动控制信号的变化频率来得到第二驱动控制信号的操作。需要调整的第一驱动控制信号的变化频率可以包括栅极驱动信号的变化频率和复位信号的变化频率中的至少之一。
根据本公开的实施例，根据图像数据发送频率来调整当前显示频率，实现了当前显示频率随应用处理器的渲染速度自动变化的效果。
根据本公开的实施例，驱动电路103可以在确定当前显示频率小于图像数据发送频率的情况下，根据图像数据发送频率，增加第一驱动控制信号的变化频率，得到第二驱动控制信号。
根据本公开的实施例，驱动电路103可以在确定当前显示频率大于图像数据发送频率的情况下，根据图像数据发送频率，减小第一驱动控制信号的变化频率，得到第二驱动控制信号。
例如，图像数据发送频率是90Hz。当前显示频率是80Hz。当前响应速度是240Hz。显示频率是240/N Hz。N∈{1，2，3，......}，即显示频率可以是以下之一：240Hz、120Hz、80Hz、60Hz、48Hz、40Hz、30Hz、24Hz、......。上述显示频率可以作为候选显示频率。
驱动电路103可以根据图像数据发送频率和当前显示频率，确定当前显示频率小于图像数据发送频率，因此，需要增加当前显示频率，即需要增加第一驱动控制信号的变化频率。由于至少一个候选显示频率中不存在与图像数据发送频率相等的候选显示频率，因此，可以从至少一个候选显示频率中确定大于图像数据发送频率且与图像数据发送频率之间的差值的绝对值最小的目标候选显示频率，由此，确定目标候选显示频率是120Hz。驱动电路103可以根据目标候选显示频率，增加第一驱动控制信号的变化频率，得到第二驱动控制信号。
例如，图像数据发送频率是90Hz。当前显示频率是80Hz。当前响应速度是360Hz。显示频率是360/N Hz。N∈{1，2，3，......}，即显示频率可以是以下之一：360Hz、180Hz、120Hz、90Hz、72Hz、60Hz、45Hz、40Hz、36Hz、30Hz、24Hz、20Hz、18Hz、.....。上述显示频率可以作为候选显示频率。
驱动电路103可以根据图像数据发送频率和当前显示频率，确定当前显示频率小于图像数据发送频率，因此，需要增加当前显示频率，即需要增加第一驱动控制信号的变化频率。由于至少一个候选显示频率中存在与图像数据发送频率相等的候选显示频率，因此，可以从至少一个候选显示频率中确定与图像数据发送频率相等的目标候选显示频率，由此，确定目标候选显示频率是90Hz。驱动电路103可以根据目标候选显示频率，增加第一驱动控制信号的变化频率，得到第二驱动控制信号。
例如，图像数据发送频率是80Hz。当前显示频率是90Hz。当前响应速度是360Hz。显示频率是360/N Hz。N∈{1，2，3，......}，即显示频率可以是以下之一：360Hz、180Hz、120Hz、90Hz、72Hz、60Hz、45Hz、40Hz、36Hz、30Hz、24Hz、20Hz、18Hz、.....。上述显示频率可以作为候选显示频率。
驱动电路103可以根据图像数据发送频率和当前显示频率，确定当前显示频率大于图像数据发送频率，因此，需要减小当前显示频率，即需要减小第一驱动控制信号的变化频率。由于至少一个候选显示频率中不存在与图像数据发送频率相等的候选显示频率，因此，可以从至少一个候选显示频率中确定大于图像数据发送频率且与图像数据发送频率之间的差值的绝对值最小的目标候选显示频率，由此，确定目标候选显示频率是90Hz。由于当前显示频率是90Hz，当前显示频率与目标候选显示频率相等，因此，驱动电路103可以不再执行根据应用处理器的图像数据发送频率，调整第一驱动控制信号的变化频率来得到第二驱动控制信号的操作。
例如，图像数据发送频率是80Hz。当前显示频率是90Hz。当前响应速度是240Hz。显示频率是240/N Hz。N∈{1，2，3，......}，即显示频率可以是以下之一：240Hz、120Hz、80Hz、60Hz、48Hz、40Hz、30Hz、24Hz、......。上述显示频率可以作为候选显示频率。
驱动电路103可以根据图像数据发送频率和当前显示频率，确定当前显示频率大于图像数据发送频率，因此，需要减小当前显示频率，即需要减小第一驱动控制信号的变化频率。由于至少一个候选显示频率中存在与图像数据发送频率相等的候选显示频率，因此，可以从至少一个候选显示频率中确定与图像数据发送频率相等的目标候选显示频率，由此，确定目标候选显示频率是80Hz。驱动电路103可以根据目标候选显示频率，减小第一驱动控制信号的变化频率，得到第二驱动控制信号。
图3A示意性示出了根据本公开实施例的根据图像数据发送频率，确定当前显示频率的示例示意图。
如图3A所示，在300A中，图像数据发送频率B大于图像数据发送频率C且小于图像数据发送频率A。如果图像数据发送频率是图像数据发送频率A，则可以根据图像数据发送频率A确定与图像数据发送频率A相匹配的当前显示频率A。如果图像数据发送频率是图像数据发送频率B，则可以根据图像数据发送频率B确定与图像数据发送频率B相匹配的当前显示频率B。如果图像数据发送频率是图像数据发送频率C，则可以根据图像数据发送频率C确定与图像数据发送频率C相匹配的当前显示频率C。
图3B示意性示出了根据本公开另一实施例的根据图像数据发送频率，确定当前显示频率的示例示意图。
如图3B所示，在300B中，“虚线”部分可以指示根据图像数据发送频率和当前显示频率，确定需要减小当前显示频率。“实线”部分可以指示根据图像数据发送频率和当前显示频率，需要增大当前显示频率。
例如，根据图像数据发送频率1和当前显示频率，确定需要增加当前显示频率，得到当前显示频率1。根据图像数据发送频率2和当前显示频率1，确定需要减小当前显示频率1，得到当前显示频率2。......。根据图像数据发送频率M和当前显示频率M-1，确定需要增加当前显示频率M-1，得到当前显示频率M。M可以是大于0的数。
根据本公开的实施例，驱动电路103可以响应于接收到来自应用处理器的显示频率调整请求，确定显示频率调整信息，根据显示频率调整信息，调整第一驱动控制 信号的变化频率，得到第三驱动控制信号。第三驱动控制信号可以用于驱动子像素电路来显示显示数据。
根据本公开的实施例，显示频率调整请求可以指用于调整显示频率的请求。显示频率调整请求可以包括显示频率调整信息。显示频率调整信息可以包括显示频率范围。显示频率范围可以是通过以下方式之一得到的：显示频率范围可以是预先设置的。显示频率范围可以是应用处理器根据当前应用程序的属性信息确定的。
根据本公开的实施例，应用处理器可以根据显示频率调整信息生成显示频率调整请求。应用处理器可以向驱动电路103发送显示频率调整请求。驱动电路103可以响应于接收到来自应用处理器的显示频率调整请求，对显示频率调整请求进行解析，得到显示频率调整信息。
根据本公开的实施例，驱动电路103在获得显示频率调整信息之后，可以根据显示频率调整信息，调整第一驱动控制信号的变化频率，得到第三驱动控制信号。
根据本公开的实施例，显示频率调整信息可以包括与当前应用程序对应的第一显示频率范围。第一显示频率范围可以是应用处理器根据当前应用程序的属性信息确定的。
根据本公开的实施例，属性信息可以包括应用程序类型。应用程序类型可以指应用程序自身的类型。应用程序自身的类型可以根据应用程序的应用程序标识确定。此外，应用程序类型也可以指根据应用程序所提供的功能所确定的类型。应用程序所提供的功能可以包括以下至少之一：游戏、社交、购物、视频、音频和文本。应用程序类型可以包括以下至少之一：游戏类、社交类、购物类、视频类、音频类和文本类。
根据本公开的实施例，应用程序可以具有与该应用程序对应的显示频率范围。例如，针对当前应用程序，应用处理器可以根据当前应用程序的属性信息，确定当前应用程序的第一显示频率范围。第一显示频率范围可以是根据第一显示频率和第二显示频率确定的。第一显示频率可以大于第二显示频率。第一显示频率可以是第一显示频率范围中的最高显示频率。第二显示频率可以是第一显示频率范围中的最低显示频率。此外，显示频率可以具有与该显示频率对应的显示频率等级。
例如，当前应用程序是“××”。“××”可以表征应用程序标识。当前应用程序所提供的功能是游戏。根据应用程序标识，可以确定当前应用程序的应用程序 类型可以是“××”。备选地，由于当前应用程序所提供的功能是游戏，因此，可以确定当前应用程序的应用程序类型可以是游戏类。与当前应用程序“××”对应的第一显示频率范围可以是大于或等于120Hz且小于或等于240Hz。
例如，当前应用程序是“**”。“**”可以表征应用程序标识。当前应用程序所提供的功能是社交。根据应用程序标识，可以确定当前应用程序的应用程序类型可以是“**”。备选地，由于当前应用程序所提供的功能是社交，因此，可以确定当前应用程序的应用程序类型可以是社交类。与当前应用程序“**”对应的第一显示频率范围可以是大于或等于80Hz且小于或等于120Hz。
根据本公开的实施例，应用处理器可以根据当前应用程序的属性信息来确定与当前应用程序对应的第一显示频率范围，应用处理器向驱动电路发送第一显示频率范围，驱动电路根据第一显示频率范围来调整显示模组的当前显示频率，使得显示模组的当前显示频率与当前应用程序的需求显示频率相匹配，由此，降低了显示模组的功耗。
根据本公开的实施例，显示频率调整信息可以包括预先设置的第二显示频率范围。
根据本公开的实施例，第二显示频率范围可以是预先设置的。与第一显示频率范围不同的是，可以不区分当前应用程序，各个当前应用程序具有相同的第二显示频率范围。
图4示意性示出了根据本公开实施例的显示设备的框图。
如图4所示，显示设备400可以包括显示控制器401和显示模组402。显示控制器401可以与显示模组402连接。
显示控制器401可以是根据本公开实施例所述的显示控制器100。
显示模组402可以配置为根据显示控制器401提供的驱动控制信号来显示显示数据。显示数据可以是根据第二当前图像数据确定的。
下面参考图5，结合具体实施例对根据本公开实施例所述的显示设备做进一步说明。
图5示意性示出了根据本公开另一实施例的显示设备的框图。
如图5所示，显示设备500可以包括显示控制器501和显示模组502。
显示控制器501可以包括标志位信号电路501_1、图像处理电路501_2和驱动电路 501_3。驱动电路501_3可以与标志位信号电路501_1和图像处理电路501_2连接。
显示模组502可以包括子像素电路502_1、栅极驱动电路502_2和源极驱动电路502_3。栅极驱动电路502_2可以与子像素电路502_1和显示控制器501连接。源极驱动电路502_3可以与子像素电路502_1和显示控制器501连接。
子像素电路502_1。
栅极驱动电路502_2可以根据显示控制器501发送的第一驱动控制信号向子像素电路502_1提供扫描起始信号、栅极驱动信号和复位信号。
源极驱动电路502_3可以根据显示控制器501发送的第一驱动控制信号向子像素电路502_1提供数据信号。扫描起始信号、栅极驱动信号、复位信号和数据信号可以用于驱动子像素电路502_1来显示显示数据。
根据本公开的实施例，驱动控制信号可以包括扫描起始信号、栅极驱动信号、复位信号和数据信号。此外，驱动控制信号还可以包括发光信号。子像素电路502_1可以包括R×S个子像素。R×S个子像素布置成R×S阵列。R和S可以为大于1的整数。
根据本公开的实施例，扫描起始信号的变化频率可以用于作为子像素电路的阳极复位频率。
根据本公开的实施例，可以将子像素电路502_1中T7管的复位信号独立出来，由扫描起始信号单独驱动，不受显示频率影响，由此，扫描起始信号的变化频率可以用于作为子像素电路的阳极复位频率。子像素电路502_1的类型可以包括以下之一：7T1C、8T1C和9T1C。此外，子像素电路502_1的类型还可以是其他类型，在此不作限定。
图6A示意性示出了根据本公开实施例的子像素电路的电路结构示意图。
如图6A所示，子像素电路600A可以是将7T1C中T7管的复位信号独立出来，由扫描起始信号单独驱动。其他结构与7T1C的结构相同，在此不再赘述。
图6B示意性示出了根据本公开另一实施例的子像素电路的电路结构示意图。
如图6B所示，子像素电路600B可以是将8T1C中T7管的复位信号独立出来，由扫描起始信号单独驱动。此外，扫描起始信号还可以与T8管的复位信号共用。T8管的复位信号的变化频率可以随着扫描起始信号的变化频率而变化。其他结构与8T1C的结构相同，在此不再赘述。
图6C示意性示出了根据本公开另一实施例的子像素电路的电路结构示意图。
如图6C所示，子像素电路600C可以是将9T1C中T7管的复位信号独立出来，由扫描起始信号单独驱动。此外，扫描起始信号还可以与T8管和T9管的复位信号共用。T8管和T9管的复位信号的变化频率可以随着扫描起始信号的变化频率而变化。其他结构与9T1C的结构相同，在此不再赘述。
图7示意性示出了根据本公开实施例的显示设备的信号时序图。
如图7所示，在700中，P_gate/reset信号可以指P极的栅极驱动信号和复位信号。N_gate/reset信号可以指N极的栅极驱动信号和复位信号。
发光信号的变化频率是480Hz。扫描起始信号的变化频率是240Hz。在数据处理阶段是正在处理阶段的情况下，标志位信号的变化频率是120Hz。在数据处理阶段是数据维持阶段的情况下，标志位信号的变化频率是240Hz。
显示模组的当前响应速度与扫描起始信号的变化频率一致，即显示模组的当前响应速度是240Hz。显示模组的当前显示频率与P_gate/reset信号和N_gate/reset信号的变化频率一致，即显示模组的当前显示频率是120Hz。需要说明的是，发光信号和扫描起始信号保持恒定的预定频率进行显示，P-gate/reset信号和N-gate/reset信号与显示模组的当前显示频率保持一致。
如果需要调整显示模组的当前显示频率，则可以共用同一套Gamma的显示频率是240/N Hz。如果将扫描起始信号的变化频率提高到360Hz，则可以共用同一套Gamma的显示频率为360/N Hz。频率调整颗粒度进一步精细化，显示模组的当前响应速度也可以达到360Hz。N可以是大于或等于1的整数。
图8示意性示出了根据本公开实施例的显示系统的框图。
如图8所示，显示系统800可以包括显示设备801和应用处理器802。显示设备801可以与应用处理器802连接。
显示设备801可以是根据本公开实施例所述的显示设备。
应用处理器802可以响应于接收到来自标志位信号电路的标志位信号，向图像处理电路发送第一当前图像数据。
根据本公开的实施例，应用处理器802可以向驱动电路发送显示频率调整请求，以便驱动电路响应于接收到来自应用处理器802的显示频率调整请求，确定显示频率调整信息，根据显示频率调整信息，调整第一驱动控制信号的变化频率，得到第三驱动控制信号。第三驱动控制信号可以用于驱动子像素电路来显示显示数据。
根据本公开的实施例，应用处理器802可以向驱动电路发送显示频率调整请求，以便驱动电路响应于接收到来自应用处理器802的显示频率调整请求，确定显示频率调整信息，根据显示频率调整信息，调整第一驱动控制信号的变化频率，得到第三驱动控制信号。第三驱动控制信号可以用于驱动子像素电路来显示显示数据。
根据本公开的实施例，显示频率调整信息可以包括与当前应用程序对应的第一显示频率范围。第一显示频率范围可以是应用处理器802根据当前应用程序的属性信息确定的。
根据本公开的实施例，显示频率调整信息可以包括预先设置的第二显示频率范围。
图9示意性示出了根据本公开另一实施例的显示系统的框图。
如图9所示，显示系统900可以包括显示设备901和应用处理器902。显示设备900可以包括显示控制器901_1和显示模组901_2。
显示控制器901_1可以向应用处理器902发送标志位信号，响应于接收到来自应用处理器902的第一当前图像数据，根据第一当前图像数据，得到第二当前图像数据。第一当前图像数据是应用处理器902响应于接收到来自显示控制器901_1发送的标志位信号发送的。显示控制器901_1可以响应于根据第二当前图像数据生成第一驱动控制信号。第一驱动控制信号可以用于驱动显示模组901_2包括的子像素电路来显示显示数据。
图10示意性示出了根据本公开实施例的显示控制器的控制方法的流程图。
如图10所示，该方法1000包括操作S1010～S1030。
在操作S1010，标志位信号电路向应用处理器发送标志位信号。
在操作S1020，图像处理电路响应于接收到来自应用处理器的第一当前图像数据，得到第二当前图像数据。第一当前图像数据是应用处理器响应于接收到来自标志位信号电路发送的标志位信号发送的。
在操作S1030，驱动电路响应于接收到来自图像处理电路的第二当前图像数据生成第一驱动控制信号。
本领域技术人员可以理解，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合，即使这样的组合或结合没有明确记载于本公开中。特别地，在不脱离本公开精神和教导的情况下，本公开的各个实施例和/或权利要求中记 载的特征可以进行多种组合和/或结合。所有这些组合和/或结合均落入本公开的范围。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。本公开的范围由所附权利要求及其等同物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (20)

  1. 一种显示控制器，包括：
    标志位信号电路，配置为向应用处理器发送标志位信号；
    图像处理电路，配置为响应于接收到来自所述应用处理器的第一当前图像数据，得到第二当前图像数据，其中，所述第一当前图像数据是所述应用处理器响应于接收到来自所述标志位信号电路发送的标志位信号发送的；以及
    驱动电路，配置为响应于接收到来自所述图像处理电路的第二当前图像数据生成第一驱动控制信号。
  2. 根据权利要求1所述的显示控制器，其中，
    所述标志位信号电路，配置为向所述应用处理器发送加载第一脉冲信号的标志位信号，其中，加载所述第一脉冲信号的标志位信号用于指示允许所述应用处理器向所述图像处理电路发送所述第一当前图像数据；以及
    所述图像处理电路，配置为响应于接收到来自所述应用处理器的第一当前图像数据，根据所述第一当前图像数据，得到所述第二当前图像数据，其中，所述第一当前图像数据是所述应用处理器响应于接收到来自所述标志位信号电路发送的加载所述第一脉冲信号的标志位信号发送的。
  3. 根据权利要求2所述的显示控制器，其中，所述第一驱动控制信号包括加载第二脉冲信号的扫描起始信号；
    所述驱动电路，配置为响应于检测到来自所述应用处理器的上一图像数据被处理，生成加载所述第二脉冲信号的扫描起始信号；以及
    所述标志位信号电路，配置为响应于接收到来自所述驱动电路的加载所述第二脉冲信号的扫描起始信号，生成加载所述第一脉冲信号的标志位信号。
  4. 根据权利要求3所述的显示控制器，其中，加载所述第一脉冲信号的标志位信号的变化频率与所述扫描起始信号的变化频率一致；
    所述显示模组的当前响应速度与所述扫描起始信号的变化频率一致。
  5. 根据权利要求1或2所述的显示控制器，其中，
    所述驱动电路，配置为根据所述应用处理器的图像数据发送频率，调整所述第一驱动控制信号的变化频率，得到第二驱动控制信号，其中，所述第二驱动控制信 号用于驱动显示模组包括的子像素电路来显示显示数据，所述第二驱动控制信号的变化频率与所述图像数据发送频率相匹配。
  6. 根据权利要求5所述的显示控制器，其中，
    所述驱动电路，配置为在确定所述当前显示频率与所述图像数据发送频率不匹配的情况下，根据所述图像数据发送频率，调整所述第一驱动控制信号的变化频率，得到所述第二驱动控制信号。
  7. 根据权利要求6所述的显示控制器，其中，
    所述驱动电路，配置为在确定所述当前显示频率小于所述图像数据发送频率的情况下，根据所述图像数据发送频率，增加所述第一驱动控制信号的变化频率，得到所述第二驱动控制信号。
  8. 根据权利要求6所述的显示控制器，其中，
    所述驱动电路，配置为在确定所述当前显示频率大于所述图像数据发送频率的情况下，根据所述图像数据发送频率，减小所述第一驱动控制信号的变化频率，得到所述第二驱动控制信号。
  9. 根据权利要求1或2所述的显示控制器，其中，
    所述驱动电路，配置为响应于接收到来自所述应用处理器的第一显示频率调整请求，确定显示频率调整信息，根据所述显示频率调整信息，调整所述第一驱动控制信号的变化频率，得到第三驱动控制信号，其中，所述第三驱动控制信号用于驱动显示模组包括的子像素电路来显示显示数据。
  10. 根据权利要求9所述的显示控制器，其中，所述显示频率调整信息包括与当前应用程序对应的第一显示频率范围，所述第一显示频率范围是所述应用处理器根据所述当前应用程序的属性信息确定的。
  11. 根据权利要求9所述的显示控制器，其中，所述显示频率调整信息包括预先设置的第二显示频率范围。
  12. 根据权利要求1～11中任一项所述的显示控制器，其中，所述第一驱动控制信号用于驱动显示模组包括的子像素电路来显示显示数据，其中，所述显示数据是根据所述第二当前图像数据确定的，所述显示模组的当前响应速度是所述显示模组的当前显示频率的N倍，N是大于或等于1的整数。
  13. 一种显示设备，包括：
    根据权利要求1～12中任一项所述的显示控制器；以及
    显示模组，与所述显示控制器连接，配置为根据所述显示控制器提供的驱动控制信号来显示显示数据，其中，所述显示数据是根据所述第二当前图像数据确定的。
  14. 根据权利要求13所述的显示设备，其中，所述显示模组，包括：
    子像素电路；
    栅极驱动电路，与所述显示控制器和所述子像素电路连接，配置为根据所述显示控制器发送的第一驱动控制信号向所述子像素电路提供扫描起始信号、栅极驱动信号和复位信号；以及
    源极驱动电路，与所述显示控制器和所述子像素电路连接，配置为根据所述显示控制器发送的第一驱动控制信号向所述子像素电路提供数据信号，其中，所述栅极驱动信号、所述复位信号和所述数据信号用于驱动所述子像素电路来显示所述显示数据。
  15. 根据权利要求14所述的显示设备，其中，所述扫描起始信号的变化频率用于作为所述子像素电路的阳极复位频率。
  16. 一种显示系统，包括：
    根据权利要求13～15中任一项所述的显示设备；以及
    应用处理器，配置为响应于接收到来自标志位信号电路的标志位信号，向所述图像处理电路发送所述第一当前图像数据。
  17. 根据权利要求16所述的显示系统，其中，
    所述应用处理器，配置为向所述驱动电路发送显示频率调整请求，以便所述驱动电路响应于接收到来自所述应用处理器的显示频率调整请求，确定显示频率调整信息，根据所述显示频率调整信息，调整所述第一驱动控制信号的变化频率，得到第三驱动控制信号，其中，所述第三驱动控制信号用于驱动所述子像素电路来显示显示数据。
  18. 根据权利要求17所述的显示系统，其中，所述显示频率调整信息包括与当前应用程序对应的第一显示频率范围，所述第一显示频率范围是所述应用处理器根据所述当前应用程序的属性信息确定的。
  19. 根据权利要求17所述的显示系统，其中，所述显示频率调整信息包括预先设置的第二显示频率范围。
  20. 一种应用于权利要求1～12中任一项所述的显示控制器的控制方法，包括：
    标志位信号电路向应用处理器发送标志位信号；
    图像处理电路响应于接收到来自所述应用处理器的第一当前图像数据，得到第二当前图像数据，其中，所述第一当前图像数据是所述应用处理器响应于接收到来自所述标志位信号电路发送的标志位信号发送的；以及
    驱动电路响应于接收到来自所述图像处理电路的第二当前图像数据生成第一驱动控制信号。
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