WO2023226275A1

WO2023226275A1 - Power switching circuit and memory

Info

Publication number: WO2023226275A1
Application number: PCT/CN2022/124357
Authority: WO
Inventors: 范玉鹏
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-05-25
Filing date: 2022-10-10
Publication date: 2023-11-30
Also published as: CN117175768A; TW202347938A

Abstract

Embodiments of the present disclosure provide a power switching circuit. The first control signal is jointly generated by means of the first input signal and the first driving signal having a phase opposite to that of the second control signal, and the second control signal is jointly generated by means of the second input signal and the second driving signal having a phase opposite to that of the first control signal, so that the time, i.e., overlap time, for a first output unit and a second output unit to be turned on or turned off at the same time is greatly reduced or even eliminated, thereby realizing effective output of an output node, and improving the reliability of a device; moreover, compared with eliminating the overlap time by means of delay, eliminating the overlap time by means of the power switching circuit of the present disclosure has simple and reliable control logic, and is not sensitive to a process, thereby improving the reliability of the device.

Description

Power switching circuit and memory

Related application citations

This application claims priority to the Chinese patent application number 202210577063.8, titled "Power Switching Circuit and Memory" submitted on May 25, 2022, the entire content of which is appended hereto by reference.

Technical field

The present disclosure relates to the field of integrated circuits, and in particular, to a power switching circuit and a memory.

Background technique

In integrated circuit chips, power switching circuits are used to provide power to circuits in memory based on the timing of input signals. Existing power switching circuits usually use independent control logic to control clock overlap, or use standard non-overlap control logic to control clock overlap. However, these two methods have complex control logic and low reliability. And it is sensitive to the process and cannot meet the demand.

Contents of the invention

The technical problem to be solved by this disclosure is to provide a power switching circuit and a memory.

In order to solve the above problem, an embodiment of the present disclosure provides a power switching circuit, which includes: a first output unit for providing a first power voltage signal to an output node in response to a first control signal; a first control unit coupled to The first output unit is used to generate the first control signal in response to the first driving signal and the first input signal; the second output unit is used to provide a second power supply voltage signal to the output node in response to the second control signal. ; The second control unit, coupled to the second output unit, is used to generate the second control signal in response to the second drive signal and the second input signal; wherein the first input signal and the second input signal The phases of the first drive signal and the second control signal are opposite, and the phases of the second drive signal and the first control signal are opposite.

In an embodiment of the present disclosure, it further includes: a first inverting unit, coupled between the output terminal of the second control unit and an input terminal of the first output unit, for responding to the second control signal to generate the first driving signal; a second inverting unit, coupled between the output end of the first control unit and an input end of the second output unit, for responding to the first control signal to generate the second driving signal.

In an embodiment of the present disclosure, the first inverter unit includes an odd number of first inverters connected in series.

In an embodiment of the present disclosure, the first inverter includes a PMOS transistor and an NMOS transistor, wherein the size of the NMOS transistor of at least one first inverter is larger than the size of the PMOS transistor.

In an embodiment of the present disclosure, the second inverter unit includes an odd number of second inverters connected in series.

In an embodiment of the present disclosure, the second inverter includes a PMOS transistor and an NMOS transistor, wherein the size of the NMOS transistor of at least one second inverter is larger than the size of the PMOS transistor.

In an embodiment of the present disclosure, the number of first inverters included in the first inverting unit is the same as the number of second inverters included in the second inverting unit.

In an embodiment of the present disclosure, the first output unit includes a first NMOS transistor, a gate of the first NMOS transistor receives the first control signal, and a first electrode of the first NMOS transistor receives the The first power supply voltage signal, the second electrode of the first NMOS transistor is connected to the output node; the second output unit includes a second NMOS transistor, the gate of the second NMOS transistor receives the second control signal , the first pole of the second NMOS transistor receives the second power supply voltage signal, and the second pole of the second NMOS transistor is connected to the output node.

In an embodiment of the present disclosure, the first control unit includes a first logic gate circuit, and the first logic gate circuit is used to perform a logical AND operation on the first input signal and the first driving signal.

In an embodiment of the present disclosure, the first logic gate circuit includes a first AND gate, a first input terminal of the first AND gate receives the first input signal, and a second input of the first AND gate The terminal receives the first driving signal, and the output terminal of the first AND gate outputs the first control signal.

In an embodiment of the present disclosure, a first delay unit is further included, and the first delay unit is coupled between the first control unit and the first output unit.

In an embodiment of the present disclosure, the first logic gate circuit includes a first NAND gate circuit and a first NOT gate circuit connected in series.

In an embodiment of the present disclosure, a second delay unit is further included, and the second delay unit is coupled between the first NAND gate circuit and the first NOT gate circuit.

In an embodiment of the present disclosure, the second control unit includes a second logic gate circuit, and the second logic gate circuit is used to perform a logical AND operation on the second input signal and the second driving signal.

In an embodiment of the present disclosure, the second logic gate circuit includes a third inverting unit and a second AND gate, an input terminal of the third inverting unit receives the first input signal, and the third inverting unit The output terminal of the phase unit outputs the second input signal, the first input terminal of the second AND gate receives the second input signal, and the second input terminal of the second AND gate receives the second drive signal. , the output terminal of the second AND gate outputs the second control signal.

In an embodiment of the present disclosure, a third delay unit is further included, and the third delay unit is coupled between the second control unit and the second output unit.

In an embodiment of the present disclosure, the second logic gate circuit includes a second NAND gate circuit and a second NOT gate circuit connected in series.

In an embodiment of the present disclosure, a fourth delay unit is further included, and the fourth delay unit is coupled between the second NAND gate circuit and the second NOT gate circuit.

In an embodiment of the present disclosure, the first power supply voltage signal is a device operating voltage signal, and the second power supply voltage signal is a ground terminal voltage signal.

An embodiment of the present disclosure also provides a memory, which includes the power switching circuit as described above.

The power switching circuit provided by the embodiment of the present disclosure uses the first input signal and the first driving signal with an opposite phase to the second control signal to jointly generate the first control signal, and uses the second input signal and The second drive signal with the opposite phase to the first control signal jointly generates the second control signal, which greatly reduces or even eliminates the time when the first output unit and the second output unit are turned on or off at the same time, that is, overlap. (overlap) time to achieve effective output of the output node and improve the reliability of the device. Moreover, using the power switching circuit of the present disclosure to eliminate the overlap time has a simple and reliable control logic compared to using a delay to eliminate the overlap time. The process is not sensitive, further improving the reliability of the device.

Description of the drawings

Figure 1 is a circuit schematic diagram of a power switching circuit provided by the first embodiment of the present disclosure;

Figure 2 is a timing diagram of the circuit schematic shown in Figure 1;

Figure 3 is a circuit schematic diagram of a power switching circuit provided by a second embodiment of the present disclosure;

Figure 4 is a circuit schematic diagram of a power switching circuit provided by a third embodiment of the present disclosure;

Figure 5 is a schematic circuit diagram of a first inverter provided by a third embodiment of the present disclosure;

Figure 6 is a timing diagram of a power switching circuit provided by a second embodiment of the present disclosure;

Figure 7 is a circuit schematic diagram of a power switching circuit provided by a fourth embodiment of the present disclosure;

FIG. 8 is a circuit schematic diagram of a power switching circuit provided by the fifth embodiment of the present disclosure.

Detailed ways

Embodiments of the power switching circuit and memory provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a circuit schematic diagram of a traditional power switching circuit provided by the first embodiment of the present disclosure. Referring to FIG. 1 , the power switching circuit includes a first output unit and a second output unit. In this embodiment, the first output unit is a first NMOS transistor MN1, and the second output unit is a second NMOS transistor MN2. The first output unit provides the first power supply voltage signal Vddh to the output node Q in response to the first control signal Selh, and the second output unit provides the second power supply voltage signal Vddl to the output node Q in response to the second control signal Sell.

The power switching circuit provided in this embodiment is affected by the timing of the first control signal Selh and the second control signal Sell. The first NMOS transistor MN1 (ie, the first output unit) and the second NMOS transistor MN2 (ie, the second output unit) exist. Simultaneous opening or simultaneous closing affects the effective output of output node Q. For example, FIG. 2 is a timing diagram of the first control signal Selh and the second control signal Sell in the circuit schematic diagram shown in FIG. 1 . Please refer to Figure 2. There is a situation where the first control signal Selh and the second control signal Sell are low level at the same time (the area circled by the dotted box A and the dotted box B in the figure). In this case , the first NMOS transistor MN1 (ie, the first output unit) and the second NMOS transistor MN2 (ie, the second output unit) are both in a closed state, resulting in no effective output at the output node Q, which reduces the reliability of the power switching circuit.

In view of the above reasons, the second embodiment of the present disclosure also provides a power switching circuit. The power switching circuit includes: a first output unit configured to provide a first power supply voltage signal to an output node in response to a first control signal; a first control a unit coupled to the first output unit and configured to generate the first control signal in response to a first driving signal and a first input signal; a second output unit configured to provide the output node with a response to a second control signal. a second power supply voltage signal; a second control unit coupled to the second output unit for generating the second control signal in response to the second drive signal and the second input signal; wherein the first input signal and The second input signal has an opposite phase, the first drive signal and the second control signal have an opposite phase, and the second drive signal and the first control signal have an opposite phase.

The power switching circuit provided in the second embodiment of the present disclosure uses the first input signal and the first drive signal with an opposite phase to the second control signal to jointly generate the first control signal, and uses the second input signal to jointly generate the first control signal. signal and the second drive signal with an opposite phase to the first control signal jointly generate the second control signal, greatly reducing or even eliminating the time for the first output unit and the second output unit to be turned on or off at the same time, That is, the overlap time realizes the effective output of the output node and improves the reliability of the device. Moreover, compared with using the delay to eliminate the overlap time, the control logic is simple and reliable by using the power switching circuit of the present disclosure to eliminate the overlap time. And it is not sensitive to the process, further improving the reliability of the device.

The structure of the power switching circuit provided by the second embodiment of the present disclosure is described in detail below.

Figure 3 is a schematic circuit diagram of a power switching circuit provided by a second embodiment of the present disclosure. Please refer to Figure 3. The power switching circuit includes a first output unit 30, a first control unit 31, a second output unit 40 and a second control unit. Unit 41.

The first output unit 30 is configured to provide a first power supply voltage signal Vddh to the output node Q in response to the first control signal Selh. In this embodiment, the first output unit 30 includes a first NMOS transistor MN1. The gate of the first NMOS transistor MN1 receives the first control signal Selh. The first electrode of the first NMOS transistor MN1 Receiving the first power supply voltage signal Vddh, the second pole of the first NMOS transistor MN1 is connected to the output node Q. When the first NMOS transistor MN1 is turned on, the output node Q outputs the first power supply voltage signal Vddh. Wherein, the first power supply voltage signal Vddh may be a device operating voltage signal.

The first control unit 31 is coupled to the first output unit 30 and configured to generate the first control signal Selh in response to the first driving signal D1 and the first input signal IN1. That is, the first driving signal D1 and the first input signal IN1 are used as input signals of the first control unit 31, and the first control unit 31 outputs the first control signal Selh.

In this embodiment, the first control unit 31 includes a first logic gate circuit, which is used to perform a logical AND operation on the first input signal IN1 and the first driving signal D1 , and generate the first control signal Selh. For example, in this embodiment, the first logic gate circuit includes a first AND gate, a first input terminal of the first AND gate receives the first input signal IN1, and a second terminal of the first AND gate receives the first input signal IN1. The input terminal receives the first driving signal D1, and the output terminal of the first AND gate outputs the first control signal Selh.

In the second embodiment, the first logic gate circuit achieves the purpose of performing a logical AND operation on the first input signal IN1 and the first driving signal D1 through a first AND gate. In other aspects of this disclosure, In an embodiment, the first logic gate circuit may also include other logic circuits to perform a logical AND operation on the first input signal IN1 and the first driving signal D1.

For example, please refer to FIG. 4. In the third embodiment of the present disclosure, the first logic gate circuit includes a first NAND gate and a first NOT gate connected in series. The first input terminal of the first NAND gate The first input signal IN1 is received, the second input terminal of the first NAND gate receives the first drive signal D1, and the output signal of the output terminal of the first NAND gate is used as the output signal of the first NAND gate. The input signal of the input terminal, the output terminal of the first NOT gate outputs the first control signal Selh. In the third embodiment, the first logic gate circuit performs a logical AND operation on the first input signal IN1 and the first driving signal D1 through a first NAND gate and a first NOT gate connected in series. the goal of.

The second output unit 40 is configured to provide a second power supply voltage signal Vddl to the output node Q in response to the second control signal Sell. In this embodiment, the second output unit 40 includes a second NMOS transistor MN2. The gate of the second NMOS transistor MN2 receives the second control signal Sell. The first electrode of the second NMOS transistor MN2 Receiving the second power supply voltage signal Vddl, the second pole of the second NMOS transistor MN2 is connected to the output node Q. When the second NMOS transistor MN2 is turned on, the output node Q outputs the second power supply voltage signal Vddl. Wherein, the second power supply voltage signal Vddl may be a ground terminal voltage signal.

The second control unit 41 is coupled to the second output unit 40 and configured to generate the second control signal Sell in response to the second driving signal D2 and the second input signal IN2. That is, the second drive signal D2 and the second input signal IN2 are used as input signals of the second control unit 41, and the second control unit 41 outputs the second control signal Sell. Wherein, the first input signal IN1 and the second input signal IN2 have opposite phases, the first driving signal D1 and the second control signal Sell have opposite phases, and the second driving signal D2 and the second control signal Sell have opposite phases. A control signal Selh has an opposite phase.

In this embodiment, the second control unit 41 includes a second logic gate circuit, and the second logic gate circuit is used to perform a logical AND operation on the second input signal IN2 and the second driving signal D2. , and generate the second control signal Sell. For example, in this embodiment, the second logic gate circuit includes a third inverting unit P3 and a second AND gate. The input terminal of the third inverting unit P3 receives the first input signal IN1. The output terminal of the third inverting unit P3 outputs the second input signal IN2, the first input terminal of the second AND gate receives the second input signal IN2, and the second input terminal of the second AND gate receives The second drive signal D2, the output terminal of the second AND gate outputs the second control signal Sell. The third inverting unit P3 includes an odd number of series-connected inverters. For example, in this embodiment, the third inverting unit P3 only includes one inverter, while in other embodiments, the third inverting unit P3 includes an odd number of series-connected inverters. The three-inverter unit P3 may include three series-connected inverters.

In the second embodiment, the second logic gate circuit achieves the purpose of inverting the first input signal IN1 through the third inverting unit P3, and achieves the purpose of inverting the second input signal IN2 and the second input signal IN2 through the second AND gate. The purpose of performing a logical AND operation on the second driving signal D2, and in other embodiments of the present disclosure, the first logic gate circuit may also include other logic circuits to implement the operation of the second input signal IN2 and the The purpose of the second driving signal D2 is to perform a logical AND operation.

For example, please refer to Figure 4. In the third embodiment of the present disclosure, the second logic gate circuit includes a fourth inverting unit P4 and a second NAND gate and a second NOT gate connected in series. The input terminal of the phase unit P4 receives the first input signal, the output terminal of the fourth inverting unit P4 outputs the second input signal IN2, and the first input terminal of the second NAND gate receives the first input signal IN2. Two input signals IN2, the second input terminal of the second NAND gate receives the second drive signal D2, and the output signal of the output terminal of the second NAND gate serves as the input signal of the input terminal of the second NOT gate. , the output terminal of the second NOT gate outputs the second control signal Sell. In the third embodiment, the second logic gate circuit achieves the purpose of inverting the first input signal IN1 through the fourth inversion unit P4, and achieves the purpose of inverting the first input signal IN1 through the first NAND gate and the first NOT gate connected in series. The second input signal IN2 and the second driving signal D2 perform a logical AND operation. The fourth inverting unit 4 includes an odd number of series-connected inverters. For example, in this embodiment, the fourth inverting unit P4 only includes one inverter, while in other embodiments, the fourth inverting unit P4 includes an odd number of series-connected inverters. The quad-inverter unit P4 may include three series-connected inverters.

In some embodiments of the present disclosure, the first logic gate circuit and the second logic gate circuit use the same logic circuit to avoid the second error caused by the difference between the first control unit 31 and the second control unit 41 . The deviation between the first control signal and the second control signal further improves the control accuracy of the first control signal and the second control signal, and reduces the time for the first output unit and the second output unit to be turned on or off at the same time.

In some embodiments of the present disclosure, the first output unit 30 and the second output unit 40 include the same type of transistors, for example, both include NMOS transistors or PMOS transistors, to further prevent the first output unit 30 from being connected to the first output unit 30 and the second output unit 40 . The second output units 40 are turned on or off at the same time.

In the embodiment of the present disclosure, a method of forming a driving signal is also provided. For example, please continue to refer to Figure 3. In the second embodiment of the present disclosure, the power switching circuit further includes a first inverter unit P1 and a second inverter unit P2.

The first inverting unit P1 is coupled between the output terminal of the second control unit 41 and an input terminal of the first output unit 30 and is used to generate the said second control signal Sell in response to the second control signal Sell. The first driving signal D1. That is, in this embodiment, the second control signal Sell is inverted by the first inverting unit P1 to form the first driving signal D1.

In an embodiment of the present disclosure, the first inverter unit P1 includes an odd number of first inverters connected in series. For example, in the second embodiment of the present disclosure, the first inverting unit P1 includes a first inverter, and the second control signal Sell is inverted by the first inverter to form the first driving signal D1 . In other embodiments of the present disclosure, the first inverter unit P1 may include three, five, or other odd numbers of first inverters.

In an embodiment of the present disclosure, the first inverter includes a PMOS transistor and an NMOS transistor, wherein the size of the NMOS transistor of at least one first inverter is larger than the size of the PMOS transistor, so that the size of the After the second control signal Sell becomes low enough (that is, the second output unit 40 has been turned off), the first drive signal D1 can be generated to the first input terminal of the first control unit 31. At this time, the first control signal Selh will be pulled high, the first output unit 30 is turned on, and the power switching circuit is turned on. If the second control signal Sell does not become low enough (that is, the second output unit 40 has not been turned off), at this time, if the third A driving signal D1 to the first input end of the first control unit 31 will cause both the first output unit 30 and the second output unit 40 to be turned on, thereby causing the power switching circuit to have the first output unit 30 and the second output unit. 40 are turned on at the same time.

Specifically, please refer to FIG. 5. The first inverter includes a PMOS transistor MP1 and an NMOS transistor MN3. The second control signal Sell serves as the input signal of the first inverter, that is, the second control signal Sell. The signal Sell serves as the control signal of the PMOS transistor MP1 and the NMOS transistor MN3. The first pole of the PMOS transistor MP1 receives the power supply voltage signal VDD, and the second pole of the PMOS transistor MP1 is connected to the output of the first inverter. terminal, the first terminal of the NMOS transistor MN3 is connected to the ground, and the second terminal of the NMOS transistor MN3 is connected to the output terminal of the first inverter. The size of the NMOS transistor MN3 is larger than the size of the PMOS transistor MP1, that is, the width-to-length ratio of the NMOS transistor MN3 is larger than the width-to-length ratio of the PMOS transistor MP1 to further avoid the existence of the first output unit 30 and the second output unit in the power switching circuit. 40 are turned on at the same time.

The second inverting unit P2 is coupled between the output terminal of the first control unit 31 and an input terminal of the second output unit 40 and is used to generate the said first control signal Selh in response to the first control signal Selh. The second driving signal D2.

In an embodiment of the present disclosure, the second inverter unit P2 includes an odd number of second inverters connected in series. For example, in the second embodiment of the present disclosure, the second inverting unit P2 includes a second inverter, and the first control signal Selh is inverted by the second inverter to form the second driving signal D2 . In other embodiments of the present disclosure, the second inverter unit P2 may include three, five, or other odd numbers of first inverters.

In an embodiment of the present disclosure, the second inverter includes a PMOS transistor and an NMOS transistor, wherein the size of the NMOS transistor of at least one second inverter is larger than the size of the PMOS transistor, so that the After the first control signal Selh becomes low enough (that is, the first output unit 30 has been turned off), the second drive signal D2 can be generated to the first input terminal of the second control unit 41. At this time, the second control signal Sell will be pulled high, the second output unit 40 is turned on, and the power switching circuit is turned on. If the first control signal Selh does not become low enough (that is, the first output unit 30 has not been turned off), at this time, if the third The second driving signal D2 is sent to the first input end of the second control unit 41, which will cause both the first output unit 30 and the second output unit 40 to be turned on, thereby causing the first output unit 30 and the second output unit to exist in the power switching circuit. 40 are turned on at the same time.

In an embodiment of the present disclosure, the number of first inverters included in the first inverting unit P1 is the same as the number of second inverters included in the second inverting unit P2 to avoid the problem due to the first inverter. The difference between the inverting unit P1 and the second inverting unit P2 causes the first output unit 30 and the second output unit 40 to be turned on or off at the same time.

Figure 6 is a timing diagram of the power switching circuit provided by the second embodiment of the present disclosure. Please refer to Figure 6. The first control signal Selh and the second control signal Sell do not open and close at the same time, achieving effective output of the output node. , improve the reliability of the device.

The fourth embodiment of the present disclosure also provides a power switching circuit that uses a delay unit to further reduce the overlap time of the first output unit 30 and the second output unit 40 . Specifically, please refer to FIG. 7 , which is a schematic circuit diagram of a power switching circuit provided by a fourth embodiment of the present disclosure. The difference between the fourth embodiment and the second embodiment is that the power switching circuit further includes a first Delay unit delay1, the first delay unit delay1 is coupled between the first control unit 31 and the first output unit 30. Specifically, the input terminal of the first delay unit delay1 is connected to the output terminal of the first control unit 31, and the output terminal of the first delay unit delay1 is connected to the first output unit 30 to further reduce The overlap time of the first output unit 30 and the second output unit 40 is small. The first delay unit delay1 may be an even number of series-connected inverters, flip-flops, shift registers, etc.

In the fourth embodiment of the present disclosure, the power switching circuit further includes a third delay unit delay3 coupled between the second control unit 41 and the second output unit 40 . Specifically, the input terminal of the third delay unit delay3 is connected to the output terminal of the second control unit 41, and the output terminal of the second delay unit delay2 is connected to the second output unit 40 to further reduce The overlap time of the first output unit 30 and the second output unit 40 is small. The second delay unit delay2 may be an even number of series-connected inverters, flip-flops, shift registers, etc.

The fifth embodiment of the present disclosure also provides a power switching circuit that uses a delay unit to further reduce the overlap time of the first output unit 30 and the second output unit 40 . Specifically, please refer to FIG. 8 , which is a schematic circuit diagram of a power switching circuit provided by a fifth embodiment of the present disclosure. The difference between the fifth embodiment and the third embodiment is that the power switching circuit further includes a second Delay unit delay2, the second delay unit delay2 is coupled between the first NAND gate circuit and the first NOT gate circuit. Specifically, the input terminal of the second delay unit delay2 is connected to the output terminal of the first NAND gate circuit, and the output terminal of the second delay unit delay2 is connected to the input terminal of the first NOT gate circuit. , to further reduce the overlap time between the first output unit 30 and the second output unit 40 .

In the fifth embodiment of the present disclosure, the power switching circuit further includes a fourth delay unit delay4. The fourth delay unit delay4 is coupled between the second NAND circuit and the second NOT gate circuit. . Specifically, the input terminal of the fourth delay unit delay4 is connected to the output terminal of the second NAND gate circuit, and the output terminal of the fourth delay unit delay4 is connected to the input terminal of the second NOT gate circuit. , to further reduce the overlap time between the first output unit 30 and the second output unit 40 .

An embodiment of the present disclosure also provides a memory, which includes the power switching circuit as described above. For example, the memory may be DRAM memory. The memory uses the first input signal of the power switching circuit and the first drive signal that is opposite in phase to the second control signal to jointly generate the first control signal, and uses the second input signal and the first drive signal that is in phase with the second control signal to jointly generate the first control signal. The second drive signal with the opposite phase of the first control signal jointly generates the second control signal, which greatly reduces or even eliminates the time when the first output unit and the second output unit are turned on or off at the same time, that is, overlap. ) time, realize the effective output of the output node of the power switching circuit, improve the reliability of the memory, and use the power switching circuit of the present disclosure to eliminate the overlap time, compared with using delay to eliminate the overlap time, the control logic is simple and reliable, And it is not sensitive to the process, further improving the reliability of the memory.

The above are only preferred embodiments of the present invention. It should be noted that those of ordinary skill in the art can also make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as It is the protection scope of the present invention.

Claims

A power switching circuit including:

a first output unit configured to provide a first power supply voltage signal to the output node in response to the first control signal;

A first control unit, coupled to the first output unit, used to generate the first control signal in response to the first driving signal and the first input signal;

a second output unit configured to provide a second power supply voltage signal to the output node in response to the second control signal;

A second control unit, coupled to the second output unit, is used to generate the second control signal in response to the second driving signal and the second input signal; wherein

The first input signal has an opposite phase to the second input signal, the first drive signal and the second control signal have an opposite phase, and the second drive signal and the first control signal have an opposite phase.
The power switching circuit according to claim 1, further comprising:

A first inverting unit, coupled between the output terminal of the second control unit and an input terminal of the first output unit, for generating the first driving signal in response to the second control signal;

A second inverting unit is coupled between an output terminal of the first control unit and an input terminal of the second output unit, and is used to generate the second driving signal in response to the first control signal.
The power switching circuit of claim 2, wherein the first inverting unit includes an odd number of first inverters connected in series.
The power switching circuit of claim 3, wherein the first inverter includes a PMOS transistor and an NMOS transistor, wherein the NMOS transistor of at least one first inverter has a size larger than that of the PMOS transistor. size.
The power switching circuit of claim 2, wherein the second inverting unit includes an odd number of second inverters connected in series.
The power switching circuit of claim 5, wherein the second inverter includes a PMOS transistor and an NMOS transistor, wherein the NMOS transistor of at least one second inverter has a size larger than that of the PMOS transistor. size.
The power switching circuit of claim 2, wherein the first inverting unit includes the same number of first inverters as the second inverting unit includes the second inverters.
The power switching circuit of claim 1, wherein the first output unit includes a first NMOS transistor, a gate of the first NMOS transistor receives the first control signal, and a first gate of the first NMOS transistor receives the first control signal. The second pole of the first NMOS transistor receives the first power supply voltage signal, and the second pole of the first NMOS transistor is connected to the output node; the second output unit includes a second NMOS transistor, and the gate of the second NMOS transistor receives the The second control signal, the first pole of the second NMOS transistor receives the second power supply voltage signal, and the second pole of the second NMOS transistor is connected to the output node.
The power switching circuit of claim 1, wherein the first control unit includes a first logic gate circuit for performing logic on the first input signal and the first driving signal. AND operation.
The power switching circuit of claim 9, wherein the first logic gate circuit includes a first AND gate, a first input terminal of the first AND gate receives the first input signal, and the first AND gate The second input terminal of the gate receives the first driving signal, and the output terminal of the first AND gate outputs the first control signal.
The power switching circuit of claim 1, further comprising a first delay unit coupled between the first control unit and the first output unit.
The power switching circuit of claim 9, wherein the first logic gate circuit includes a first NAND gate and a first NOT gate connected in series, and a first input terminal of the first NAND gate receives the first An input signal, the second input terminal of the first NAND gate receives the first drive signal, and the output terminal of the first NOT gate outputs the first control signal.
The power switching circuit of claim 12, further comprising a second delay unit coupled between the first NAND gate circuit and the first NOT gate circuit.
The power switching circuit of claim 1, wherein the second control unit includes a second logic gate circuit for performing logic on the second input signal and the second driving signal. AND operation.
The power switching circuit of claim 14, wherein the second logic gate circuit includes a third inverting unit and a second AND gate, and an input end of the third inverting unit receives the first input signal, so The output terminal of the third inverting unit outputs the second input signal, the first input terminal of the second AND gate receives the second input signal, and the second input terminal of the second AND gate receives the second input signal. The second driving signal, the output terminal of the second AND gate outputs the second control signal.
The power switching circuit of claim 1, further comprising a third delay unit coupled between the second control unit and the second output unit.
The power switching circuit of claim 14, wherein the second logic gate circuit includes a fourth inverting unit and a second NAND gate and a second NOT gate connected in series, and the input terminal of the fourth inverting unit Receive the first input signal, the output terminal of the fourth inverting unit outputs the second input signal, the first input terminal of the second NAND gate receives the second input signal, and the second The second input terminal of the NAND gate receives the second driving signal, and the output terminal of the second NOT gate outputs the second control signal.
The power switching circuit of claim 17, further comprising a fourth delay unit coupled between the second NAND gate circuit and the second NOT gate circuit.
The power switching circuit of claim 1, wherein the first power supply voltage signal is a device operating voltage signal, and the second power supply voltage signal is a ground terminal voltage signal.
A memory, comprising the power switching circuit of claim 1.