WO2023223640A1

WO2023223640A1 - Electron source and method for manufacturing electron source

Info

Publication number: WO2023223640A1
Application number: PCT/JP2023/008756
Authority: WO
Inventors: 昌善長尾; 勝久村上; 博雅村田
Original assignee: 国立研究開発法人産業技術総合研究所
Priority date: 2022-05-17
Filing date: 2023-03-08
Publication date: 2023-11-23
Also published as: JP2023169459A

Abstract

This field-emission electron source is formed so as to define a curved surface, and comprises: an etching stop layer that has a first region that is supported by a substrate, and a second region that is not supported by the substrate; and an electron emission structure formed on at least the second region. Nothing needs to be formed or disposed at the portion below the second region. In the second region, the etch stop layer and the electron emission structure naturally define a convex surface or a concave surface. This focuses or scatters an electron beam.

Description

Electron source and method for manufacturing the electron source

The present invention relates to a field emission type electron source and a method for manufacturing the electron source.

For example, in Patent Document 1, the surface of the electron source (also called a cathode) is shaped like a concave spherical surface in order to focus the electron beam emitted from the electron source used in traveling wave tubes (TWTs) to one point. It is disclosed that it can be partially processed. Such techniques use so-called thermionic sources (hot cathodes) and photoelectron sources, which emit electrons into a vacuum by applying heat or light energy to the electrons.

On the other hand, regarding an electron source that emits electrons into a vacuum by tunneling using only an electric field,

Patent Documents

2 and 3, for example, disclose that the electron sources are arranged on a part of a concave spherical surface.

However, in these methods, a field emission type electron source fabricated on a flat substrate is pasted onto a concave spherical surface, and the electron source itself is not spherical. Beams have their limits.

On the other hand, it is difficult to manufacture a field emission type electron source array on a concave surface. Field emission electron source arrays are usually manufactured on flat silicon or glass substrates using semiconductor microfabrication technology, so the manufacturing process includes steps such as photolithography and dry etching. In photolithography, the process of applying photoresist is essential, and when resist is applied to a curved concave surface, the photoresist becomes thicker at the bottom of the curved surface, which prevents film thickness distribution within the surface. I can't do it. That is, it is impossible to fabricate a field emission type electron source array of uniform size on a curved concave surface.

Patent No. 4134000 Japanese Patent Application Publication No. 2005-261502 Patent No. 5424098

Accordingly, one aspect of the present invention is to provide a field emission type electron source formed into a curved surface and a method for manufacturing the electron source.

The electron source of the present invention includes an etch stop layer having a first region supported by a substrate, a second region not supported by the substrate, and an etch stop layer formed on at least the second region. and a release structure.

The method for manufacturing an electron source of the present invention includes the steps of: forming an electron emitting structure on at least a partial region of an etch stop layer on a substrate; and removing the substrate by etching in a lower part of at least a portion of the region. and a step of doing so.

FIG. 1 is a diagram showing a configuration example of an electron source according to a first embodiment. FIG. 2 is a diagram showing an example of the outline of the electron emission area. FIG. 3 is a diagram for explaining the method for manufacturing the electron source according to the first embodiment. FIG. 4 is a diagram showing an example of the outline of the electron emission area. FIG. 5 is a diagram showing an example of the configuration of an electron source when a stress adjustment layer is added. FIG. 6 is a diagram showing an example of adjusting internal stress. FIG. 7 is a diagram showing an example of the configuration of an electron source when a convex curved surface is formed. FIG. 8 is a diagram showing a configuration example of an electron source according to Modification 1 of the first embodiment. FIG. 9 is a diagram for explaining a method of manufacturing an electron source using an SOI wafer. FIG. 10 is a diagram showing a configuration example of an electron source according to the second embodiment. FIG. 11 is a diagram for explaining a method of manufacturing an electron source according to the second embodiment. FIG. 12 is a diagram showing a configuration example of an electron source according to Modification 1 of the second embodiment.

[Embodiment 1]
[composition]
FIG. 1 shows an example of a field emission type electron source according to this embodiment. The electron source according to this embodiment includes an emitter array 70 in which a plurality of emitters 80 having sharp electron emission ends are formed in an array. This emitter array 70 has a concave curved surface in this embodiment. Since the emitter array 70 has a concave curved surface in this way, it becomes easier to focus the electrons emitted from the tips of each emitter 80.

In this electron source, an opening 60 is formed in the substrate 100 under the emitter array 70 (that is, on the opposite side), and an etch stop layer 40 is formed above the opening 60. Since the membrane including the conductive layer 30 and the like is not supported by the substrate 100, the membrane naturally forms a concave curved surface due to its own stress. Note that the substrate 100 remains in the portion other than the opening 60, and the etch stop layer 40 and the like formed above the substrate 100 are supported by the substrate 100.

As shown in FIG. 2, the shape of the opening 60 is preferably circular, for example, from the viewpoint of performance and manufacturing. This is because in the case of a rectangular shape, stress is concentrated at the corner portions, which increases the possibility that the desired concave curved surface will not be obtained or that the shape will break.

A conductive layer 30 is formed for the emitter array 70 formed on the etch stop layer 40, and an insulating layer 20 having a plurality of small openings and a gate electrode 10 are formed on the conductive layer 30. An emitter 80 is formed in each of these small openings.

In such an electron source, electrons are emitted from the emitter 80 by applying a predetermined voltage to the gate electrode and the conductive layer 30.

[Manufacturing method of Embodiment 1]
A method for manufacturing an electron source according to this embodiment will be explained using FIGS. 3(a) to 3(d).

As shown in FIG. 3A, an etch stop layer 40 is formed on the substrate 100 so that it will not be etched when an opening 60 is later formed on the back surface. Although the material for the substrate 100 is not particularly limited, a silicon substrate is suitable as a material in which the opening 60 can be easily formed on the back surface. The material of the etch stop layer 40 is selected depending on the method of etching the opening 60 on the back side. A silicon substrate is selected as the substrate 100, and a CF-based material such as SF6 gas and C4F8, which are often used to deeply etch a silicon substrate, is selected. When using the Bosch process using gas, select a material that cannot be etched with SF6 or CF gas. For example, silicon oxide film (SiO ₂ ), aluminum, chromium, etc. can be used. Alternatively, a laminated film of these may be used.

A conductive layer 30 for supplying current to the emitter is formed on the etch stop layer 40. If a conductive film is selected for the etch stop layer 40, it is possible to omit the conductive layer, but generally the conductive layer is often patterned into the required shape, so the etch stop layer is The degree of freedom in design will be higher if it is provided separately.

Next, as shown in FIG. 3(b), there are many methods for forming the insulating layer 20, the gate electrode 30, and the emitter 80 on the conductive layer 30, so any method may be selected. Spindt described in Patent No. 6093968, C. A. Spindt, et al. “Physical Properties of thin-film field emission cathode with molybdenum cones”, Journal of applied Physics, vol. 47, (1976) p.5248, etc. A mold emitter manufacturing method may also be adopted. As described above, since a well-known method may be adopted, a description thereof will be omitted here, and the latter document will be incorporated into the present specification.

Next, as shown in FIG. 3C, after forming the emitter array 70 as shown in FIG. etching. To do this, first, the surface on which the emitter array 70 is formed is protected with a coated protective film 200. For the protective film 200, a photoresist or a resin film that can be applied thicker than the height of structures such as the emitter 80 is suitable. Further, a photoresist is applied to the back surface of the silicon substrate, and a mask 300 is formed in accordance with the pattern to be deeply dug. As the Bosch process, it is possible to use, for example, a method in which SF6 gas and C4F8 gas are alternately introduced and etching is repeated.

It is also possible to etch a silicon substrate using an alkaline liquid such as tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH), but in this case, the etching speed depends on the crystal orientation of the silicon. Since these are different, etching progresses in such a way that the (111) plane remains. As a result, the shape of the etched hole becomes rectangular regardless of the original mask shape. If the hole formed by etching is rectangular, there is a high possibility that a tear will occur at the corner of the rectangle, as described above. Further, even if etching can be performed without tearing, there is a high possibility that wrinkles (deflections) will occur when curved, which is not preferable.

The shape of the aperture 60 is selected depending on the desired shape of the finally focused electron beam. For example, when focusing an electron beam on a point, it is preferable that the concave curved surface formed by the membrane has a structure cut out from a part of a spherical surface, so the shape of the hole to be etched should be as shown in FIG. It is desirable that it be circular. In addition, when the objective is to obtain an electron beam focused in a line, as shown in Fig. 4, the short side of a rectangle is shaped like a semicircle, that is, the circle is moved in a straight line to cover the beam. It is preferable that the shape is as follows.

Then, as shown in FIG. 3D, after the deep etching, the unnecessary protective film 200 and mask 300 are removed using oxygen plasma, a stripping solution, or the like. By eliminating the silicon substrate on the back surface, the emitter array 70 forms a curved surface due to the stress of the laminated thin films (ie, membranes). Whether a curved surface is a convex curved surface or a concave curved surface is determined by whether the total stress of the laminated thin films (that is, membranes) is tensile stress or compressive stress.

The degree of curvature (radius of curvature (R)) of the membrane that emits electrons is determined by the distance between the electron source and the focal point of the electron beam. In order to achieve that R, the stress of the membrane is adjusted. To this end, as shown in FIG. 5, a stress adjustment layer 400 (also referred to as a curvature adjustment layer that adjusts the degree of curvature) may be inserted between the etch stop layer 40 and the conductive layer 30. Since the purpose of the stress adjustment layer 400 is to adjust the degree of curvature according to the stress, a film that can adjust the stress is desirable. For example, a SiO ₂ film formed by plasma CVD (Chemical Vapor Deposition) using tetraethoxysilane (TEOS) gas is as shown in Figure 6. By adjusting the substrate temperature Ts, it is possible to control the stress to a certain extent, from tensile stress (the part above 0 on the vertical axis) to compressive stress (the part below 0 on the vertical axis). It is possible to use it as a layer.

Note that when the stress of the membrane becomes tensile stress, the membrane forms a convex curved surface as shown in FIG. A membrane with such a convex curved surface can be used in a light emitting device such as a light bulb by diverging the electron beam rather than focusing it.

[Modification 1 of Embodiment 1]
Instead of the Spindt emitter described above, an emitter array with an integrated volcano-type focusing electrode may be formed, as shown in FIG. A method for manufacturing an emitter array in which this volcano-type focusing electrode is integrated is described in, for example, Japanese Unexamined Patent Application Publication No. 2021-018846, so a description thereof will be omitted here. Briefly explaining the structure, an emitter 80 is formed in the opening of the extraction gate electrode 94, and a focusing electrode 92 for focusing electrons emitted from the emitter 80 is also formed. In the case of an electron source as shown in FIG. 1, it is said that the electrons emitted from each emitter 80 are emitted with a spread angle of about 30 degrees, and the configuration of FIG. It may not be possible to focus on the On the other hand, in this configuration, since the focusing electrode 92 can be formed integrally with each emitter 80, an electron beam aligned in a direction perpendicular to the emitter 80 can be emitted from the beginning, so that it can be easily focused at one point. You will be able to do so.

[Modification 2 of Embodiment 1]
Furthermore, a method of forming a sharp emitter by etching silicon or the like may also be applied. In this case, an SOI (Silicon on Insulator) wafer may be used. For example, as shown in FIG. 9A, the SOI wafer 80 has a so-called BOX layer (SiO ₂ layer) 80b formed above a silicon substrate 80c, and a silicon layer 80a further above. A circular mask 81 made of SiO ₂ is formed thereon. Then, as shown in FIG. 9(b), the general shape of the emitter is formed by reactive etching. The approximate shape of the emitter can be obtained by adjusting the reactive etching conditions such as the type of gas so that side etching occurs. In this case, if you etch until the tip is completely sharp, the mask will come off and the emitter tip will be etched rapidly and its shape will deteriorate, so stop etching just before it becomes sharp. In FIG. 9B, it can be seen that a silicon layer 82 including an emitter with a flat tip is formed.

Thereafter, as shown in FIG. 9(c), an emitter tip is formed by thermal oxidation. During the thermal oxidation process, stress is generated in areas that are not flat, such as near the tip of the emitter, and the oxidation rate is slower than in flat areas. By utilizing this phenomenon, a very sharp tip can be formed. That is, a SiO ₂ film 82' is formed on the surface of a silicon layer 82 including an emitter with a flat tip, and a silicon layer 84 including an emitter 83 with a sharp tip is formed below it. Then, as shown in FIG. 9(d), the SiO ₂ remaining above the emitter 83 is etched using buffered hydrofluoric acid.

When forming an emitter in this manner, the BOX layer 80b of the SOI wafer becomes an etch stop layer. The thickness of the uppermost silicon layer 80a of the SOI wafer 80 is set depending on the height of the emitter to be manufactured. If the emitter height is 1 micron, an SOI wafer 80 with a silicon layer thicker than 1 μm is used.

[Embodiment 2]
FIG. 10 shows a configuration example of a MIS (Metal/Insulator/Semiconductor) type electron source according to the second embodiment. Note that it is also called an MIM (Metal/Insulator/Metal) type electron source.

In this electron source, an etch stop layer 40 and a conductive layer 30 are provided on a substrate 100, and an insulating layer 20 for accelerating electrons and a gate electrode 10 for applying a voltage are further formed thereon. has been done. In this embodiment, the insulating layer 20 is thinned only in the electron emission area 700, and an opening 60 is formed in the substrate 100 below the electron emission area 700 (ie, on the opposite side). That is, the lower part of the electron emission area 700 is not supported by the substrate 100, and the emblem including the gate electrode 10, the insulating layer 20, the conductive layer 30, and the etch stop layer 40 in the electron emission area 700 naturally has a concave curved surface. has been achieved. Note that the substrate 100 remains in the portion other than the opening 60, and the etch stop layer 40 and the like formed above the substrate 100 are supported by the substrate 100. Since electrons are emitted perpendicularly to the surface, a focusing electrode is not necessary.If the emblem in the electron emission area 700 forms a concave curved surface, a predetermined voltage is applied between the conductive layer 30 and the gate electrode. By applying this, it becomes possible to focus the electron beam on one point.

Note that as long as the etch stop layer 40 has conductivity, the etch stop layer 40 may be a film that also serves as the conductive layer 30, as in the first embodiment.

Basically, the conductive layer 30 may be made of any material as long as it is conductive, but since it is preferable to emit electrons perpendicular to the substrate, it is better to make the film as flat as possible. preferable. In the case of a metal film, it is generally polycrystalline and has an uneven surface, so in that case it is preferable to flatten it by a technique such as CMP (Chemical-Mechanical Polishing). Alternatively, it is also possible to use an SOI (Silicon On Insulator) wafer, in which case the SOI BOX layer (SiO ₂ ) becomes the etch stop layer 40 and the SOI layer becomes the conductive layer 30.

The thickness of the insulating layer 20 within the electron emission area 700 is preferably 4 nm to 20 nm, more preferably 4 nm to 10 nm. The thickness of the area other than the electron emission area 70 is preferably about 100 nm to 1000 nm. By forming the insulating layer 20 in the electron emission area 70 thinly, it contributes to preventing the electrons emitted from the conductive layer 30 from being scattered in the insulating layer 20, and has the advantage of reducing the operating voltage. If it is too thin, it will not be possible to apply the voltage necessary to accelerate electrons, so it should be within the above range.

Examples of the material for the insulating layer 20 include materials with good insulation performance, such as boron nitride (BN), SiO ₂ , and Al ₂ O ₃ . However, since electrons tunnel through this material and travel along the conductive band of the insulating layer 20, it is desirable to use a material that has little interaction with electrons, and more preferably to be composed of light elements. . Therefore, BN is more preferable, and among these, hexagonal-Boron Nitride (hereinafter referred to as h-BN), which can be formed into a layered film, is the most preferable.

Since electrons pass through this part of the gate electrode 10 and are emitted into the vacuum, it is desirable that the interaction with the electrons be as small as possible. Therefore, the thickness of the gate electrode 10 is preferably 7 nm or less. If so, even better. The material is also preferably conductive, capable of forming a continuous film, composed of light elements, and capable of being made thin. In this sense, a carbon layered film, that is, graphene is preferable. If it is difficult to form a single layer film, multilayer graphene can be used, but the film thickness is preferably 7 nm or less as described above. In addition, in order to properly cover portions with different thicknesses in the insulating layer 20, single-crystal graphene is not suitable because it has a structure in which hexagons are laid out, so it is only a flat surface. Graphene is preferably polycrystalline.

[Manufacturing method of Embodiment 2]
A method for manufacturing an electron source according to this embodiment will be explained using FIGS. 11(a) to 11(d).

First, as shown in FIG. 11A, an etch stop layer 40, a conductive layer 30, and an insulating layer 20 are formed on a silicon substrate 100. When using an SOI wafer, the etch stop layer 40 corresponds to the BOX layer and the conductive layer 30 corresponds to the SOI layer (silicon layer). The insulating layer 20 will eventually define the electron emitting area 700 (it will be removed from the electron emitting area 700 and the insulating layer 20 will be left in areas where you do not want electrons to be emitted), so good insulation can be maintained. You can choose from a variety of materials. Commonly used materials include SiO ₂ and Al ₂ O ₃ . The thickness can be freely selected from a film thickness of 100 nm or more and 10 μm or less. Note that the thickness that is usually easy to use is about 300 nm to 1 μm. In some cases, stress adjustment layer 400 may be formed between etch stop layer 40 and conductive layer 30.

Next, as shown in FIG. 11B, the insulating layer 20 is removed from the electron emission area 700 in order to define the electron emission area 700. At this point, since it is formed on a flat substrate, it may be carried out using normal photolithography and dry etching or wet etching.

Furthermore, as shown in FIG. 11C, a thin insulating layer 21 for tunneling and accelerating electrons is formed on the electron emission area 700. The quality of the insulating layer 21 greatly influences the characteristics of this electron source. For example, when single crystal silicon is used as the conductive layer 30, cleaning such as RCA cleaning is performed to reduce defects as much as possible, and then thermal oxidation is performed to form an insulating layer on the exposed portion of the conductive layer 30. 21 is formed. In addition to this, h-BN can also be used as the insulating layer 21. Since h-BN is composed only of light elements such as nitrogen and boron and has little interaction with electrons, it is expected to improve electron emission efficiency and is one of the most desirable forms.

The thickness of the insulating layer 21 is preferably adjusted to about 4 nm to 20 nm. When the insulating layer 21 is thinner than 4 nm, a tunnel current flows between the conductive layer 30 and the gate electrode 10 that will be formed later, before a sufficient voltage is applied. Even if a tunnel current flows in a state where the potential of the gate electrode 10 is lower than the work function, electrons cannot be emitted because their energy is low and cannot pass through the gate electrode 10. Therefore, it is preferable that the insulating layer 21 has a thickness of 4 nm or more. When the insulating layer 21 is thicker than 20 nm, the distance that tunneled electrons travel within the insulating layer 21 becomes long, and during the movement, they are affected by scattering due to lattice vibration and lose energy. Therefore, in this case as well, the number of electrons having energy higher than the work function decreases, resulting in poor electron emission efficiency. As a result of repeated research by the inventors of the present application, the thickness of the insulating layer 21 is preferably 20 nm or less, more preferably 10 nm or less.

Next, a gate electrode 10 is formed. It is possible to use a metal or a semiconductor for the gate electrode 10, but if the electrons that have passed through the insulating layer 21 do not also pass through the gate electrode 10, the electrons will not be emitted into the vacuum. A transparent material is preferred. Ordinary metals have large atoms, and in order to obtain a continuous film, a film thickness of 10 nm or more is required. The gate electrode 10 is preferably made of a conductive material made of a light element, and is preferably a continuous film that is as thin as possible. Therefore, graphene consisting of a single layer of carbon atoms is most preferred. As a method for directly forming graphene on the insulating layer 21, a CVD method (for example, the method described in Japanese Patent No. 6,983,404) in which the graphene is exposed to a mixed atmosphere of gallium vapor and methane gas can be employed.

As shown in FIG. 11(d), finally, the substrate 100 on the opposite side of the electron emission area 700 is etched. When etching the substrate 100, the electron emitting area 700 on the surface is protected as in the first embodiment.

[Modification of Embodiment 2]
FIG. 12 shows an electron source according to a modification of the second embodiment. Here, unlike the electron emission area 700 of the electron source shown in FIG. 10, the electron emission area 750 has an array shape. By doing this, even if there is a defect in one part, only that part will not function, and the other parts will be able to function. It should be noted that the parts other than the etch stop layer 40 and the opening 60 at the bottom of the substrate 100 are not the main parts and are described in, for example, Japanese Patent No. 7057972, so the description thereof will be omitted here.

In this way, by introducing an etch stop layer and providing an opening on the back side of the substrate, the electron emitting area that is not supported by the substrate forms a convex or concave curve depending on the stress caused by the etch stop layer. As a result, electrons can be focused or diverged and emitted. Note that the electron emitting structure formed above the etch stop layer in the electron emitting area for emitting electrons can take various forms, and may have a structure other than the one described above. Note that even when the etch stop layer is used as a conductive layer, some structure that contributes to emitting electrons is formed above the etch stop layer, so this structure is a type of electron emitting structure.

Furthermore, when using an SOI wafer, an etch stop layer is not formed when manufacturing an electron source, but an electron emitting structure that contributes to electron emission is formed.

Although the embodiments of the present invention have been described above, the present invention is not limited to these. For example, any technical matters of each embodiment may be deleted, or technical matters of any of the embodiments may be arbitrarily combined.

Further, when a large current is emitted from the electron source, the temperature of the electron source becomes high due to Joule heat. In the structure according to this embodiment, since the lower part of the electron source is not supported by the substrate, the heat dissipation characteristics are poor, and destruction due to heat may occur when operating at a large current. Therefore, in order to improve heat dissipation characteristics, a heat dissipation layer may be inserted between the etch stop layer and the conductive layer. The heat dissipation layer is preferably made of metal such as copper or aluminum, which has good thermal conductivity.

The embodiments described above can be summarized as follows.

An electron source according to an embodiment includes an etch stop layer having a first region supported by a substrate and a second region not supported by the substrate, and formed on at least the second region. It has an electron emitting structure. The electron emitting structure for emitting electrons formed in the second region not supported by the substrate naturally forms a curved surface.

More specifically, the lower portion of the second region of the etch stop layer may be hollow. That is, there is no need to form or arrange anything in the lower part of the second region. Further, in the second region, the etch stop layer and the electron emitting structure may have a convex curved surface or a concave curved surface. It focuses or diverges the electron beam. Further, the second area may have a circular shape or a shape covered by moving a circle along a straight line or a curved line. The shape should match the condensed shape or diverging shape of the electron beam, but preferably a shape that does not cause any problems in manufacturing. In some cases, it may be an ellipse.

The electron source described above may further include a stress adjustment layer formed between the etch stop layer and the layer containing the electron emitting structure. This controls the degree of curvature (including unevenness) of the curved surface.

A method for manufacturing an electron source according to an embodiment includes the steps of: forming an electron emitting structure on at least a partial region of an etch stop layer on a substrate; and removing by etching. In this way, the layers above the etch stop layer are divided into regions supported by the substrate and regions not supported by the substrate, and the regions not supported by the substrate naturally form an appropriate curved surface. Become.

The manufacturing method may further include the step of forming a stress adjustment layer between the etch stop layer and the layer including the electron emitting structure. It becomes possible to control the degree of curvature of areas not supported by the base.

Furthermore, the manufacturing method may further include the step of forming an etch stop layer on the substrate. For SOI wafers, the BOX layer can be used as an etch stop layer, so it is not necessary to form it. However, when using a silicon substrate, forming an etch stop layer like this prevents the effects of etching from the back side of the substrate. can be stopped with an etch stop layer.

Claims

an etch stop layer having a first region supported by a substrate and a second region not supported by the substrate;
an electron emitting structure formed on at least the second region;
An electron source with
The electron source according to claim 1, wherein a lower portion of the second region of the etch stop layer is hollow.
The electron source according to claim 1, wherein the etch stop layer has a convex curved surface or a concave curved surface in the second region.
The electron source according to claim 1, wherein the second region has a circular shape or a shape covered by moving a circle along a straight line or a curved line.
The electron source according to claim 1, further comprising: a stress adjustment layer formed between the etch stop layer and the layer including the electron emitting structure.
forming an electron emitting structure over at least a portion of the etch stop layer on the substrate;
etching away the substrate below at least a portion of the region;
A method of manufacturing an electron source including.
7. The manufacturing method according to claim 6, further comprising: forming a stress adjustment layer between the etch stop layer and the layer including the electron emitting structure.
7. The manufacturing method according to claim 6, further comprising: forming the etch stop layer on the substrate.