WO2023220417A1 - Co-dopage de zone active de micro-del pour suppression de pertes en surface - Google Patents

Co-dopage de zone active de micro-del pour suppression de pertes en surface Download PDF

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WO2023220417A1
WO2023220417A1 PCT/US2023/022107 US2023022107W WO2023220417A1 WO 2023220417 A1 WO2023220417 A1 WO 2023220417A1 US 2023022107 W US2023022107 W US 2023022107W WO 2023220417 A1 WO2023220417 A1 WO 2023220417A1
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layer
light
quantum well
display
micro
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PCT/US2023/022107
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English (en)
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Pavel Gorlachuk
Arjun AJAYKUMAR
Alexander TONKIKH
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Meta Platforms Technologies, Llc
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Priority claimed from US18/132,305 external-priority patent/US20230369537A1/en
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Publication of WO2023220417A1 publication Critical patent/WO2023220417A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/305—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table characterised by the doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • LEDs Light emitting diodes convert electrical energy into optical energy, and offer many benefits over other light sources, such as reduced size, improved durability, and increased efficiency. LEDs can be used as light sources in many display systems, such as televisions, computer monitors, laptop computers, tablets, smartphones, projection systems, and wearable electronic devices.
  • micro-LEDs micro light emitting diodes
  • This disclosure relates generally to micro light emitting diodes (micro-LEDs). More specifically, this disclosure relates to improving the quantum efficiencies of small micro-LEDs, such as small AlGalnP-based red micro-LED.
  • a light source comprising: a p-type semiconductor layer; an n-type semiconductor layer; and an active region between the p-type semiconductor layer and the n-type semiconductor layer and configured to emit light, the active region including a plurality of barrier layers and one or more quantum well layers, wherein the one or more quantum well layers of the active region include at least one quantum well layer that is doped with both n-type dopants and p-type dopants.
  • An electron concentration of the at least one quantum well layer may be between IxlO 17 /cm 3 and 5xl0 18 /cm 3 .
  • a hole concentration of the at least one quantum well layer may be between IxlO 17 /cm 3 and 5xl0 18 /cm 3 .
  • a net carrier concentration of the at least one quantum well layer may be within 1-lOxlO 17 /cm 3 .
  • the active region may be configured to emit light characterized by a wavelength equal to or greater than 590 nm.
  • the plurality of barrier layers may include AkGai-xIno.sP, where x is between 0.2 and 0.5.
  • a carrier mobility of the at least one quantum well layer may be less than 50 cm 2 /(V s).
  • a carrier mobility of the at least one quantum well layer may be equal to or less than 30 cm 2 /(V s).
  • FIG. 2 is a perspective view of an example of a near-eye display in the form of a headmounted display (HMD) device for implementing some of the examples disclosed herein.
  • HMD headmounted display
  • near-eye display 300 may also include a high-resolution camera 340.
  • Camera 340 may capture images of the physical environment in the field of view.
  • the captured images may be processed, for example, by a virtual reality engine (e.g., artificial reality engine 116 of FIG. 1) to add virtual objects to the captured images or modify physical objects in the captured images, and the processed images may be displayed to the user by display 310 for AR or MR applications.
  • a virtual reality engine e.g., artificial reality engine 116 of FIG. 1
  • the processed images may be displayed to the user by display 310 for AR or MR applications.
  • Scanning mirror 570 and/or freeform optical element 560 may reflect and project the light emitted by light source 540 to waveguide display 580, which may include a coupler 582 for coupling the light emitted by light source 540 into waveguide display 580.
  • the light coupled into waveguide display 580 may propagate within waveguide display 580 through, for example, total internal reflection as described above with respect to FIG. 4.
  • Coupler 582 may also couple portions of the light propagating within waveguide display 580 out of waveguide display 580 and towards user’s eye 590.
  • the multiple layers of semiconductor materials may include different compound materials or a same base material with different dopants and/or different doping densities.
  • the multiple layers of semiconductor materials may include an n-type material layer, an active region that may include hetero-structures (e. , one or more quantum wells), and a p-type material layer.
  • the multiple layers of semiconductor materials may be grown on a surface of a substrate having a certain orientation.
  • a mesa that includes at least some of the layers of semiconductor materials may be formed.
  • Controller 620 may control the image rendering operations of image source assembly 610, such as the operations of light source 642 and/or projector 650.
  • controller 620 may determine instructions for image source assembly 610 to render one or more display images.
  • the instructions may include display instructions and scanning instructions.
  • the display instructions may include an image file (c.g, a bitmap file).
  • the display instructions may be received from, for example, a console, such as console 110 described above with respect to FIG. 1.
  • the scanning instructions may be used by image source assembly 610 to generate image light.
  • the scanning instructions may specify, for example, a type of a source of image light (e.g., monochromatic or polychromatic), a scanning rate, an orientation of a scanning apparatus, one or more illumination parameters, or any combination thereof.
  • Controller 620 may include a combination of hardware, software, and/or firmware not shown here so as not to obscure other aspects of the present disclosure.
  • Projector 650 may perform a set of optical functions, such as focusing, combining, conditioning, or scanning the image light generated by light source 642.
  • projector 650 may include a combining assembly, a light conditioning assembly, or a scanning mirror assembly.
  • Projector 650 may include one or more optical components that optically adjust and potentially re-direct the light from light source 642.
  • One example of the adjustment of light may include conditioning the light, such as expanding, collimating, correcting for one or more optical errors (e.g., field curvature, chromatic aberration, etc.), some other adjustments of the light, or any combination thereof.
  • the optical components of projector 650 may include, for example, lenses, mirrors, apertures, gratings, or any combination thereof.
  • the light sources, image sources, or other displays described above may include one or more LEDs.
  • each pixel in a display may include three subpixels that include a red micro-LED, a green micro-LED, and a blue micro-LED.
  • a semiconductor light emitting diode generally includes an active light emitting layer within multiple layers of semiconductor materials.
  • the multiple layers of semiconductor materials may include different compound materials or a same base material with different dopants and/or different doping densities.
  • the multiple layers of semiconductor materials may generally include an n-type material layer, an active layer that may include hetero-structures (e.g, one or more quantum wells), and a p-type material layer.
  • the multiple layers of semiconductor materials may be grown on a surface of a substrate having a certain orientation.
  • Photons can be generated in a semiconductor LED (e.g, a micro-LED) at a certain internal quantum efficiency through the recombination of electrons and holes within the active layer (e.g, including one or more semiconductor layers).
  • the generated light may then be extracted from the LEDs in a particular direction or within a particular solid angle.
  • the ratio between the number of emitted photons extracted from the LED and the number of electrons passing through the LED is referred to as the external quantum efficiency, which describes how efficiently the LED converts injected electrons to photons that are extracted from the device.
  • the external quantum efficiency may be proportional to the injection efficiency, the internal quantum efficiency, and the extraction efficiency.
  • the injection efficiency refers to the proportion of electrons passing through the device that are injected into the active region.
  • the extraction efficiency is the proportion of photons generated in the active region that escape from the device.
  • a mesa that includes at least some of the layers of semiconductor materials may be formed.
  • FIG. 7A illustrates an example of an LED 700 having a vertical mesa structure.
  • LED 700 may be a light emitter in light source 510, 540, or 642.
  • LED 700 may be a micro-LED made of inorganic materials, such as multiple layers of semiconductor materials.
  • the layered semiconductor light emitting device may include multiple layers of III-V semiconductor materials.
  • a III-V semiconductor material may include one or more Group III elements, such as aluminum (Al), gallium (Ga), or indium (In), in combination with a Group V element, such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb).
  • the Group V element of the III-V semiconductor material includes nitrogen, the III-V semiconductor material is referred to as a Ill-nitride material.
  • the layered semiconductor light emitting device may be manufactured by growing multiple epitaxial layers on a substrate using techniques such as vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular beam epitaxy (MBE), or metalorganic chemical vapor deposition (MOCVD).
  • VPE vapor-phase epitaxy
  • LPE liquid-phase epitaxy
  • MBE molecular beam epitaxy
  • MOCVD metalorganic chemical vapor deposition
  • the layers of the semiconductor materials may be grown layer-by-layer on a substrate with a certain crystal lattice orientation (e.g., polar, nonpolar, or semi-polar orientation), such as a GaN, GaAs, or GaP substrate, or a substrate including, but not limited to, sapphire, silicon carbide, silicon, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinels, or quaternary tetragonal oxides sharing the beta-Li AIO2 structure, where the substrate may be cut in a specific direction to expose a specific plane as the growth surface.
  • a certain crystal lattice orientation e.g., polar, nonpolar, or semi-polar orientation
  • Active layer 730 may include III-V materials, such as one or more InGaN layers, one or more AlGalnP layers, and/or one or more GaN layers, which may form one or more heterostructures, such as one or more quantum wells or MQWs.
  • a semiconductor layer 740 may be grown on active layer 730.
  • Semiconductor layer 740 may include a III-V material, such as GaN, and may be p-doped e.g., with Mg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge).
  • One of semiconductor layer 720 and semiconductor layer 740 may be a p-type layer and the other one may be an n-type layer.
  • Passivation layer 770 may include an oxide layer, such as a SiCh layer, and may act as a reflector to reflect emitted light out of LED 700.
  • a contact layer 780 which may include a metal layer, such as Al, Au, Ni, Ti, or any combination thereof, may be formed on semiconductor layer 720 and may act as an electrode of LED 700.
  • another contact layer 790 such as an Al/Ni/Au metal layer, may be formed on conductive layer 760 and may act as another electrode of LED 700.
  • electrical contact 765 and metal layer 795 include same material(s) and can be formed using the same processes.
  • an additional conductive layer (not shown) may be included as an intermediate conductive layer between the electrical contacts 765 and 785 and the semiconductor layers.
  • the internal quantum efficiency of an LED may be determined by: where A, B and C are the rates of SRH recombination, bimolecular (radiative) recombination, and Auger recombination, respectively, and N is the charge-carrier density (i.e., charge-carrier concentration) in the active region.
  • Auger recombination is a non-radiative process involving three carriers. Auger recombination may be a major cause of efficiency droop and may be direct or indirect. For example, direct Auger recombination occurs when an electron and a hole recombine, but instead of producing light, either an electron is raised higher into the conduction band or a hole is pushed deeper into the valence band. Auger recombination may be reduced to mitigate the efficiency droop by lowering the charge-carrier density N in the active region for a given injection current density J, which may be written as:
  • the active region in proximity to the exposed sidewalls may have a higher density of defects, such as dislocations, pores, grain boundaries, vacancies, inclusion of precipitates, and the like.
  • the defects may introduce energy states having deep or shallow energy levels in the bandgap. Carriers may be trapped by these energy states until they combine non-radiatively. Therefore, the active region in proximity to the exposed sidewalls may have a higher rate of SRH recombination than the bulk region that is far from the sidewalls.
  • the carrier lifetime r is the average time that a carrier can spend in an excited state after the electron-hole generation before it recombines with another carrier.
  • the carrier lifetime T generally depends on the carrier concentration and the recombination rate in the active region.
  • the carrier diffusion length L characterizes the width of the region that is adjacent to a sidewall surface of the active region and where the contribution of surface recombination to the carrier losses is significant. Charge carriers injected or diffused into the regions that are within a minority carrier diffusion length from the sidewall surfaced may be subject to the higher SRH recombination rate.
  • the increased surface area to volume ratio may lead to a high carrier surface recombination rate, because a greater proportion of the total active region may fall within the minority carrier diffusion length from the LED sidewall surface. Therefore, more injected carriers are subjected to the higher SRH recombination rate. This can cause the leakage current of the LED to increase and the efficiency of the LED to decrease as the size of the LED decreases, and/or cause the peak efficiency operating current to increase as the size of the LED decreases.
  • AlGalnP material may have a high surface recombination velocity and minority carrier diffusion length than some other light emission materials, such as Ill-nitride materials.
  • red AlGalnP LEDs may generally operate at a reduced carrier concentration ( .g, about 10 i7 to 10 i8 cm' 3 ), and thus may have a relatively long carrier lifetime T.
  • the carrier diffusivity D in the active region in the undoped quantum wells of red AlGalnP LEDs may also be rather large.
  • FIG. 9 illustrates surface recombination velocities of various III-V semiconductor materials. Bars 910 in FIG. 9 show the ranges of reported SRV values of the III-V semiconductor materials, whereas symbols 920 on bars 910 indicate the common or averaged SRVs. A box 930 shows a general trend of the variation of the surface recombination velocity with the change of the material bandgap. As illustrated in FIG. 9, the SRV is high in GaAs (e.g., about 10 6 cm/s) compared to InP (e.g., about 10 3 cm/s) or GaN (e.g., less than about O.5xlO 5 cm/s).
  • GaAs e.g., about 10 6 cm/s
  • InP e.g., about 10 3 cm/s
  • GaN e.g., less than about O.5xlO 5 cm/s
  • the surface recombination velocity of AlGalnP material may be at least an order of magnitude higher than the surface recombination velocity of Ill-nitride materials (e.g., ⁇ 10 5 cm/s).
  • SRVs may scale appreciably with the Al fraction. For example, the SRV may increase from about 10 5 cm/s for (Alo.iGao.9)o.5lno.5P to about 10 6 cm/s for Alo.51Ino.49P.
  • the non-radiative surface recombination described above may be reduced by, for example, passivating the mesa surface with a suitable dielectric material, such as SiCh, SiNx, or AI2O3.
  • the SRV may be reduced by etching away highly defective surface material using a chemical treatment.
  • surface recombination may be reduced by decreasing the lateral carrier mobility.
  • the lateral carrier mobility may be decreased by using ion implantation to disrupt the semiconductor lattice outside of a central portion of the micro-LED.
  • the lateral carrier mobility may be decreased by using quantum well intermixing to change the composition of areas of the semiconductor layer outside of the central portion of the micro-LED.
  • the quantum wells may be doped with n-type dopants at a doping density about l.OxlO 18 cm' 3 , and may also be doped with p-type dopants at a doping density about 1.5x l0 18 cm' 3 , to achieve of an effective p-dopant concentration about 5x l0 17 cm' 3 .
  • the carrier mobility may be reduced significantly to about 10-30 cm 2 /(V s) at the effective dopant concentration of about 5x 10 17 cm' 3 . As shown in FIGS.
  • the carrier mobility may be significantly decreased when the carrier concentration is higher than undoped or unintentional doped (e.g., with a carrier concentration about 10 15 - 10 15 cm' 3 ).
  • the carrier mobility may be reduced to about 10-30 cm 2 /(V s) at an effective carrier concentration about 5xlO i7 cm' 3 . Reducing the carrier mobility may reduce the diffusion of carriers to the sidewall regions where the carriers may be subject to a high non-radiative recombination rate, thereby reducing non- radiative recombination and improving quantum efficiency.
  • FIG. 12 illustrates an example of a red-light emitting micro-LED epitaxial layer stack 1200 with the active layers (e.g., quantum well layers) co-doped with n-type dopants and p-type dopants according to certain embodiments.
  • the red-light emitting micro-LED epitaxial layer stack 1200 may be grown on an n-type GaAs substrate 1210.
  • the epitaxial layers may include a buffer layer 1212, which may include n-doped GaAs.
  • an etch stop layer 1214 may be grown on buffer layer 1212 and may include, for example, n- doped GalnP.
  • An n-contact layer 1216 may be grown on etch stop layer 1214, and may include n-doped GaAs.
  • An n-type cladding layer 1218 e.g., including n-doped AlGalnP
  • a first spacer layer 1220 e.g., a quantum barrier layer including undoped or unintentionally doped AlGalnP
  • active layer(s) 1222 e.g., quantum well layers including n/p co-doped GalnP
  • a second spacer layer 1224 e.g., a quantum barrier layer including undoped or unintentionally doped AlGalnP
  • a p-type cladding layer 1226 e.g., including p-doped AlGalnP
  • a p-contact layer 1228 e.g., including p-doped GaP
  • a curve 1230 in FIG. 12 shows the energy bandgap of the different semiconductor layers in red-light emitting micro-LED epitaxial layer stack 1200.
  • the composition of active layer(s) 1222 may be selected such that the energy bandgap of active layer(s) 1222 may be low such that red light may be emitted in active layer(s) 1222.
  • FIG. 13 illustrates an example of a red-light emitting micro-LED epitaxial layer stack 1300 with the active layers co-doped with n-type dopants and p-type dopants according to certain embodiments.
  • Red-light emitting micro-LED epitaxial layer stack 1300 may be an example of red-light emitting micro-LED epitaxial layer stack 1200.
  • layer 0 of red-light emitting micro-LED epitaxial layer stack 1300 may include a gallium arsenide substrate 1310 with a diameter about 4-12" and an offcut angle about 10-15 degrees, and may be doped with Si at a doping density, for example, about l-20> ⁇ 10 18 cm' 3 .
  • Layer 1 may be an n-type GaAs buffer layer 1312 with a thickness about 100-3000 nm, and may be doped with one of the following dopants: Si, Ge, S, Se, and Te, at a doping density, for example, about 1-20* 10 18 cm' 3 .
  • Layer 2 may be an n-type GaxIni- x P etch-stop layer 1314 with a thickness about 0-1000 nm and x value about 0.45-0.55, and may be doped with one of the following dopants: Si, Ge, S, Se, and Te, at a doping density, for example, about l-20x 10 18 cm' 3 .
  • Layer 3 may be an n-type GaAs contact layer 1316 with a thickness about 10-500 nm, and may be doped with one of the following dopants: Si, Ge, S, Se, and Te, at a doping density, for example, about 1-20* 10 19 cm' 3 .
  • Layer 4 may be an n-type AkGai-xIno.sP cladding layer 1318 with a thickness about 50-2500 nm and x value about 0.5-1.0, and may be doped with one of the following dopants: Si, Ge, S, Se, and Te, at a doping density , for example, about 5-50x 10 17 cm' 3 .
  • Layer 5 may be an AlxGai-xIno.sP spacer layer 1320 with a thickness about 0-500 nm and x value about 0.2-0.5, and may be undoped or doped with n-type dopants (e.g., Si, Ge, S, Se, or Te) and/or p-type dopants (e.g., C, Mg, Zn, or Be) at a doping density, for example, about 1-50* 10 16 cm' 3 .
  • n-type dopants e.g., Si, Ge, S, Se, or Te
  • p-type dopants e.g., C, Mg, Zn, or Be
  • Layer 6 may be a GaxIni-xP active layer 1322 with a thickness about 2-10 nm and x value about 0.4-0.6, and may be doped with both n-type dopants (e.g., Si, Ge, S, Se, or Te) and p-type dopants (e g., C, Mg, Zn, or Be) at doping densities about 5-50 10 17 cm' 3 to achieve an effective doping density, for example, about l-10> ⁇ 10 17 cm' 3 , such as about 5* 10 17 cm' 3 .
  • the resulting concentration and conductivity type may be determined by the difference between the p-type dopant concentration and the n-type dopant concentration.
  • Layer 7 may be an AkGai-xIno.sP spacer layer 1324 with a thickness about 0-500 nm and x value about 0.2-0.5, and may be undoped or doped with n-type dopants (e.g., Si, Ge, S, Se, or Te) and/or p-type dopants (e.g., C, Mg, Zn, or Be) at a doping density, for example, about 1-50* 10 16 cm' 3 .
  • n-type dopants e.g., Si, Ge, S, Se, or Te
  • p-type dopants e.g., C, Mg, Zn, or Be
  • Layers 6 and 7 may be repeated, for example, up to 10 times to form one or more quantum wells that include quantum well layers (e.g., layer 6) and quantum barrier layers (e.g., layer 7).
  • a curve 1330 in FIG. 13 shows the energy bandgap of the different semiconductor layers in red-light emitting micro-LED epitaxial layer stack 1300.
  • the composition of Ga x Ini-xP active layer 1322 may be selected such that the energy bandgap of Ga x Ini-xP active layer 1322 may be low (e.g., about 1.9 eV) such that red light may be emitted in Ga x Ini- x P active layer 1322.
  • x in GaxIni-xP may be between about 0.4 and 0.6.
  • the epitaxial layers may include various materials, such as GaN, InGaN, (AlGaln)P, (AlGaln)AsP, (AlGaln)AsN, (Eu:InGa)N, (AlGaIn)N, or the like, and may include an n-type layer, a p-type layer, and an active layer that includes one or more heterostructures, such as one or more quantum wells or MQWs.
  • the electrical contacts may include various conductive materials, such as a metal or a metal alloy.
  • LED array 1401 may be bonded to wafer 1403 via bonding layer 1413 or patterned layer 1415.
  • patterned layer 1415 may include metal pads or bumps made of various materials, such as CuSn, AuSn, or nanoporous Au, that may be used to align LEDs 1407 of LED array 1401 with corresponding driver circuits 1411 on wafer 1403.
  • LED array 1401 may be brought toward wafer 1403 until LEDs 1407 come into contact with respective metal pads or bumps corresponding to driver circuits 1411. Some or all of LEDs 1407 may be aligned with driver circuits 1411, and may then be bonded to wafer 1403 via patterned layer 1415 by various bonding techniques, such as metal-to-metal bonding. After LEDs 1407 have been bonded to wafer 1403, carrier substrate 1405 may be removed from LEDs 1407.
  • FIG. 14B illustrates an example of a method of wafer-to-wafer bonding for arrays of LEDs according to certain embodiments.
  • a first wafer 1402 may include a substrate 1404, a first semiconductor layer 1406, active layers 1408, and a second semiconductor layer 1410.
  • Substrate 1404 may include various materials, such as GaAs, InP, GaN, AIN, sapphire, SiC, Si, or the like.
  • first semiconductor layer 1406 may be an n-doped GaN layer (e.g., doped with Si or Ge), and second semiconductor layer 1410 may be a p-doped GaN layer (e.g., doped with Mg, Ca, Zn, or Be).
  • Active layers 1408 may include, for example, one or more GaN layers, one or more InGaN layers, one or more AlGalnP layers, and the like, which may form one or more heterostructures, such as one or more quantum wells or MQWs.
  • first wafer 1402 may also include a bonding layer.
  • Bonding layer 1412 may include various materials, such as a metal, an oxide, a dielectric, CuSn, AuTi, or the like.
  • bonding layer 1412 may include p-contacts and/or n-contacts (not shown). In some embodiments, other layers may also be included on first wafer 1402, such as a buffer layer between substrate 1404 and first semiconductor layer 1406.
  • the buffer layer may include various materials, such as polycrystalline GaN or AIN.
  • a contact layer may be between second semiconductor layer 1410 and bonding layer 1412. The contact layer may include any suitable material for providing an electrical contact to second semiconductor layer 1410 and/or first semiconductor layer 1406.
  • first wafer 1402 may be bonded to wafer 1403 with the p-side (e.g, second semiconductor layer 1410) of first wafer 1402 facing down (i.e., toward wafer 1403).
  • substrate 1404 may be removed from first wafer 1402, and first wafer 1402 may then be processed from the n-side.
  • the processing may include, for example, the formation of certain mesa shapes for individual LEDs, as well as the formation of optical components corresponding to the individual LEDs.
  • FIGS. 15A-15D illustrate an example of a method of hybrid bonding for arrays of LEDs according to certain embodiments.
  • the hybrid bonding may generally include wafer cleaning and activation, high-precision alignment of contacts of one wafer with contacts of another wafer, dielectric bonding of dielectric materials at the surfaces of the wafers at room temperature, and metal bonding of the contacts by annealing at elevated temperatures.
  • FIG. 15A shows a substrate 1510 with passive or active circuits 1520 manufactured thereon. As described above with respect to FIGS. 14A-26B, substrate 1510 may include, for example, a silicon wafer. Circuits 1520 may include driver circuits for the arrays of LEDs.
  • a bonding layer may include dielectric regions 1540 and contact pads 1530 connected to circuits 1520 through electrical interconnects 1522.
  • Contact pads 1530 may include, for example, Cu, Ag, Au, Al, W, Mo, Ni, Ti, Pt, Pd, or the like.
  • Dielectric materials in dielectric regions 1540 may include SiCN, SiCh, SiN, AI2O3, HfCh, ZrCh, Ta2Os, or the like.
  • the bonding layer may be planarized and polished using, for example, chemical mechanical polishing, where the planarization or polishing may cause dishing (a bowl like profde) in the contact pads.
  • FIG. 15B illustrates a wafer 1550 including an array of micro-LEDs 1570 fabricated thereon as described above with respect to, for example, FIGS. 7A, 7B, 14A, and 14B.
  • Wafer 1550 may be a carrier wafer and may include, for example, GaAs, InP, GaN, AIN, sapphire, SiC, Si, or the like.
  • Micro-LEDs 1570 may include an n-type layer, an active region, and a p-type layer epitaxially grown on wafer 1550.
  • the epitaxial layers may include various IILV semiconductor materials described above, and may be processed from the p-type layer side to etch mesa structures in the epitaxial layers, such as substantially vertical structures, parabolic structures, conical structures, or the like. Passivation layers and/or reflection layers may be formed on the sidewalls of the mesa structures.
  • P-contacts 1580 and n-contacts 1582 may be formed in a dielectric material layer 1560 deposited on the mesa structures and may make electrical contacts with the p-type layer and the n-type layers, respectively.
  • Dielectric materials in dielectric material layer 1560 may include, for example, SiCN, SiCh, SiN, AI2O3, HfCh, ZrCh, Ta2Os, or the like.
  • FIG. 15C illustrates a room temperature bonding process for bonding the dielectric materials in the bonding layers.
  • wafer 1550 and microLEDs 1570 may be turned upside down and brought into contact with substrate 1510 and the circuits formed thereon.
  • compression pressure 1525 may be applied to substrate 1510 and wafer 1550 such that the bonding layers are pressed against each other.
  • dielectric regions 1540 and dielectric material layer 1560 may be in direct contact because of the surface attractive force, and may react and form chemical bonds between them because the surface atoms may have dangling bonds and may be in unstable energy states after the activation.
  • the dielectric materials in dielectric regions 1540 and dielectric material layer 1560 may be bonded together with or without heat treatment or pressure.
  • the substrate on which the micro-LEDs are fabricated may be thinned or removed, and various secondary optical components may be fabricated on the light-emitting surfaces of the micro-LEDs to, for example, extract, collimate, and redirect the light emitted from the active regions of the micro-LEDs.
  • micro-lenses may be formed on the micro-LEDs, where each micro-lens may correspond to a respective micro-LED and may help to improve the light extraction efficiency and collimate the light emitted by the micro-LED.
  • the secondary optical components may be fabricated in the substrate or the n-type layer of the micro-LEDs.
  • the secondary optical components may be fabricated in a dielectric layer deposited on the n-type side of the micro-LEDs.
  • the secondary optical components may include a lens, a grating, an antireflection (AR) coating, a prism, a photonic crystal, or the like.
  • FIG. 16 illustrates an example of an LED array 1600 with secondary optical components fabricated thereon according to certain embodiments.
  • LED array 1600 may be made by bonding an LED chip or wafer with a silicon wafer including electrical circuits fabricated thereon, using any suitable bonding techniques described above with respect to, for example, FIGS. 14A-15D.
  • LED array 1600 may be bonded using a wafer-to-wafer hybrid bonding technique as described above with respect to FIG. 15A-15D.
  • LED array 1600 may include a substrate 1610, which may be, for example, a silicon wafer.
  • Integrated circuits 1620 such as LED driver circuits, may be fabricated on substrate 1610.
  • Integrated circuits 1620 may be connected to p-contacts 1674 and n-contacts 1672 of micro- LEDs 1670 through interconnects 1622 and contact pads 1630, where contact pads 1630 may form metallic bonds with p-contacts 1674 and n-contacts 1672.
  • Dielectric layer 1640 on substrate 1610 may be bonded to dielectric layer 1660 through fusion bonding.
  • the substrate (not shown) of the LED chip or wafer may be thinned or may be removed to expose the n-type layer 1650 of micro-LEDs 1670.
  • Various secondary optical components such as a spherical micro-lens 1682, a grating 1684, a micro-lens 1686, an antireflection layer 1688, and the like, may be formed in or on top of n-type layer 1650.
  • spherical micro-lens arrays may be etched in the semiconductor materials of micro-LEDs 1670 using a gray-scale mask and a photoresist with a linear response to exposure light, or using an etch mask formed by thermal reflowing of a patterned photoresist layer.
  • the secondary optical components may also be etched in a dielectric layer deposited on n-type layer 1650 using similar photolithographic techniques or other techniques.
  • micro-lens arrays may be formed in a polymer layer through thermal reflowing of the polymer layer that is patterned using a binary mask.
  • the micro-lens arrays in the polymer layer may be used as the secondary optical components or may be used as the etch mask for transferring the profiles of the micro-lens arrays into a dielectric layer or a semiconductor layer.
  • the dielectric layer may include, for example, SiCN, SiCh, SiN, AI2O3, HfCb, ZrCh, Ta2Os, or the like.
  • a micro-LED 1670 may have multiple corresponding secondary optical components, such as a micro-lens and an anti -reflection coating, a micro-lens etched in the semiconductor material and a micro-lens etched in a dielectric material layer, a micro-lens and a grating, a spherical lens and an aspherical lens, and the like.
  • secondary optical components such as a micro-lens and an anti -reflection coating, a micro-lens etched in the semiconductor material and a micro-lens etched in a dielectric material layer, a micro-lens and a grating, a spherical lens and an aspherical lens, and the like.
  • Three different secondary optical components are illustrated in FIG. 16 to show some examples of secondary optical components that can be formed on micro-LEDs 1670, which does not necessary imply that different secondary optical components are used simultaneously for every LED array.
  • Embodiments disclosed herein may be used to implement components of an artificial reality system or may be implemented in conjunction with an artificial reality system.
  • Artificial reality is a form of reality that has been adjusted in some manner before presentation to a user, which may include, for example, a virtual reality, an augmented reality, a mixed reality, a hybrid reality, or some combination and/or derivatives thereof.
  • Artificial reality content may include completely generated content or generated content combined with captured (e.g, real -world) content.
  • the artificial reality content may include video, audio, haptic feedback, or some combination thereof, and any of which may be presented in a single channel or in multiple channels (such as stereo video that produces a three-dimensional effect to the viewer).
  • artificial reality may also be associated with applications, products, accessories, services, or some combination thereof, that are used to, for example, create content in an artificial reality and/or are otherwise used in (e.g, perform activities in) an artificial reality.
  • the artificial reality system that provides the artificial reality content may be implemented on various platforms, including an HMD connected to a host computer system, a standalone HMD, a mobile device or computing system, or any other hardware platform capable of providing artificial reality content to one or more viewers.
  • FIG. 17 is a simplified block diagram of an example electronic system 1700 of an example near-eye display (e.g., HMD device) for implementing some of the examples disclosed herein.
  • Electronic system 1700 may be used as the electronic system of an HMD device or other near-eye displays described above.
  • electronic system 1700 may include one or more processors) 1710 and a memory 1720.
  • Processor(s) 1710 may be configured to execute instructions for performing operations at a number of components, and can be, for example, a general-purpose processor or microprocessor suitable for implementation within a portable electronic device.
  • Processor(s) 1710 may be communicatively coupled with a plurality of components within electronic system 1700.
  • Bus 1740 may be any subsystem adapted to transfer data within electronic system 1700.
  • Bus 1740 may include a plurality of computer buses and additional circuitry to transfer data.
  • Memory 1720 may be coupled to processor(s) 1710. In some embodiments, memory 1720 may offer both short-term and long-term storage and may be divided into several units. Memory 1720 may be volatile, such as static random access memory (SRAM) and/or dynamic random access memory (DRAM) and/or non-volatile, such as read-only memory (ROM), flash memory, and the like. Furthermore, memory 1720 may include removable storage devices, such as secure digital (SD) cards. Memory 1720 may provide storage of computer-readable instructions, data structures, program modules, and other data for electronic system 1700. In some embodiments, memory 1720 may be distributed into different hardware modules. A set of instructions and/or code might be stored on memory 1720.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • ROM read-only memory
  • SD secure digital
  • memory 1720 may store a plurality of application modules 1722 through 1724, which may include any number of applications. Examples of applications may include gaming applications, conferencing applications, video playback applications, or other suitable applications. The applications may include a depth sensing function or eye tracking function. Application modules 1722-1724 may include particular instructions to be executed by processor(s) 1710. In some embodiments, certain applications or parts of application modules 1722-1724 may be executable by other hardware modules 1780. In certain embodiments, memory 1720 may additionally include secure memory, which may include additional security controls to prevent copying or other unauthorized access to secure information.
  • wireless communication subsystem 1730 may include separate transceivers to communicate with base transceiver stations and other wireless devices and access points, which may include communicating with different data networks and/or network types, such as wireless wide-area networks (WWANs), wireless local area networks (WLANs), or wireless personal area networks (WPANs).
  • WWAN may be, for example, a WiMax (IEEE 802.16) network.
  • WLAN may be, for example, an IEEE 802.1 lx network.
  • a WPAN may be, for example, a Bluetooth network, an IEEE 802.15x, or some other types of network.
  • the techniques described herein may also be used for any combination of WWAN, WLAN, and/or WPAN.
  • Wireless communications subsystem 1730 may permit data to be exchanged with a network, other computer systems, and/or any other devices described herein.
  • Wireless communication subsystem 1730 may include a means for transmitting or receiving data, such as identifiers of HMD devices, position data, a geographic map, a heat map, photos, or videos, using antenna(s) 1734 and wireless link(s) 1732.
  • Wireless communication subsystem 1730, processor(s) 1710, and memory 1720 may together comprise at least a part of one or more of a means for performing some functions disclosed herein.
  • Embodiments of electronic system 1700 may also include one or more sensors 1790.
  • Sensor(s) 1790 may include, for example, an image sensor, an accelerometer, a pressure sensor, a temperature sensor, a proximity sensor, a magnetometer, a gyroscope, an inertial sensor (e.g., a module that combines an accelerometer and a gyroscope), an ambient light sensor, or any other similar module operable to provide sensory output and/or receive sensory input, such as a depth sensor or a position sensor.
  • sensor(s) 1790 may include one or more inertial measurement units (IMUs) and/or one or more position sensors.
  • IMUs inertial measurement units
  • Electronic system 1700 may include a display module 1760.
  • Display module 1760 may be a near-eye display, and may graphically present information, such as images, videos, and various instructions, from electronic system 1700 to a user. Such information may be derived from one or more application modules 1722-1724, virtual reality engine 1726, one or more other hardware modules 1780, a combination thereof, or any other suitable means for resolving graphical content for the user (e.g., by operating system 1725).
  • Display module 1760 may use LCD technology, LED technology (including, for example, OLED, ILED, p-LED, AMOLED, TOLED, etc. light-emitting polymer display (LPD) technology, or some other display technology.
  • LED technology including, for example, OLED, ILED, p-LED, AMOLED, TOLED, etc. light-emitting polymer display (LPD) technology, or some other display technology.
  • electronic system 1700 may include a plurality of other hardware modules 1780.
  • Each of other hardware modules 1780 may be a physical module within electronic system 1700. While each of other hardware modules 1780 may be permanently configured as a structure, some of other hardware modules 1780 may be temporarily configured to perform specific functions or temporarily activated.
  • Examples of other hardware modules 1780 may include, for example, an audio output and/or input module (e.g, a microphone or speaker), a near field communication (NFC) module, a rechargeable battery, a battery management system, a wired/wireless battery charging system, etc.
  • one or more functions of other hardware modules 1780 may be implemented in software.
  • the above-described hardware and modules may be implemented on a single device or on multiple devices that can communicate with one another using wired or wireless connections.
  • some components or modules such as GPUs, virtual reality engine 1726, and applications (e.g, tracking application), may be implemented on a console separate from the head-mounted display device.
  • one console may be connected to or support more than one HMD.
  • the term “at least one of’ if used to associate a list, such as A, B, or C, can be interpreted to mean any combination of A, B, and/or C, such as A, AB, AC, BC, AA, ABC, AAB, AABBCCC, etc.
  • Such configuration can be accomplished, for example, by designing electronic circuits to perform the operation, by programming programmable electronic circuits (such as microprocessors) to perform the operation such as by executing computer instructions or code, or processors or cores programmed to execute code or instructions stored on a non-transitory memory medium, or any combination thereof.
  • Processes can communicate using a variety of techniques, including, but not limited to, conventional techniques for inter-process communications, and different pairs of processes may use different techniques, or the same pair of processes may use different techniques at different times.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
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Abstract

Une source de lumière comprend une couche semi-conductrice de type p, une couche semi-conductrice de type n, et une zone active entre la couche semi-conductrice de type p et la couche semi-conductrice de type n et configurée pour émettre de la lumière. La zone active comprend une pluralité de couches barrières et une ou plusieurs couches de puits quantiques. La ou les couches de puits quantique comprennent au moins une couche de puits quantique qui est dopée à la fois avec des dopants de type n et des dopants de type p. Une concentration de porteurs nette de la ou des couches de puits quantique est comprise entre environ 1 x 1017/cm3 et environ 10 x 1017/cm3. Les dopants de type n comprennent, par exemple, Si, Ge, S, Se, ou Te. Les dopants de type p comprennent, par exemple, C, Mg, Be ou Zn. La zone active est caractérisée par une dimension linéaire latérale égale ou inférieure à environ 10 µm.
PCT/US2023/022107 2022-05-13 2023-05-12 Co-dopage de zone active de micro-del pour suppression de pertes en surface WO2023220417A1 (fr)

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US18/132,305 US20230369537A1 (en) 2022-05-13 2023-04-07 Micro-led active region co-doping for surface losses suppression

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5555271A (en) * 1993-12-27 1996-09-10 Sanyo Electric Co., Ltd. Semiconductor laser device
US6822266B2 (en) * 2001-05-24 2004-11-23 Sharp Kabushiki Kaisha Semiconductor light-emitting device
EP0732754B1 (fr) * 1995-03-17 2007-10-31 Toyoda Gosei Co., Ltd. Dispositif semi-conducteur émetteur de lumière comprenant un composé nitride III-V
US10396241B1 (en) * 2016-08-04 2019-08-27 Apple Inc. Diffusion revealed blocking junction

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5555271A (en) * 1993-12-27 1996-09-10 Sanyo Electric Co., Ltd. Semiconductor laser device
EP0732754B1 (fr) * 1995-03-17 2007-10-31 Toyoda Gosei Co., Ltd. Dispositif semi-conducteur émetteur de lumière comprenant un composé nitride III-V
US6822266B2 (en) * 2001-05-24 2004-11-23 Sharp Kabushiki Kaisha Semiconductor light-emitting device
US10396241B1 (en) * 2016-08-04 2019-08-27 Apple Inc. Diffusion revealed blocking junction

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