WO2023218941A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

This semiconductor device comprises: a first semiconductor element that has an element main surface and an element rear surface oriented toward opposite sides from each other in a z-direction; a sealing resin that covers the first semiconductor element; a first terminal that is electrically continuous with the first semiconductor element, and that protrudes from the sealing resin; and a tip plating layer disposed on a tip surface on the side of the first terminal that protrudes from the sealing resin.

Description

Semiconductor device and method for manufacturing semiconductor device

The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

Various configurations of semiconductor devices including semiconductor elements have been proposed. Patent Document 1 discloses an example of an SOP (Small Outline Package) type semiconductor device. The semiconductor device disclosed in the document includes a semiconductor element, a die pad, a terminal, and a sealing resin. A semiconductor element is mounted on a die pad and is electrically connected to a terminal via a bonding wire. The semiconductor element, die pad, and a portion of the terminal are covered with a sealing resin. An exterior plating layer made of an alloy containing Sn is formed on the portion of the terminal exposed from the sealing resin in order to improve solder adhesion when the terminal is bonded to the wiring board with solder.

Japanese Patent Application Publication No. 2016-207714

Since the outer plating layer is formed before the terminal is separated from the lead frame, no outer plating layer is formed on the tip end surface of the terminal. Therefore, when a terminal is bonded to a wiring board with solder, the solder is difficult to adhere to the tip end surface of the terminal, and a solder fillet may not be formed. In this case, a visual inspection determines that solder adhesion is defective.

An object of the present disclosure is to provide a semiconductor device that is improved over the conventional semiconductor device. In particular, in view of the above-mentioned circumstances, one object of the present disclosure is to provide a semiconductor device that can suppress solder adhesion defects when mounted on a wiring board.

A semiconductor device provided by a first aspect of the present disclosure includes a semiconductor element having an element main surface and an element back surface facing opposite to each other in a thickness direction, a sealing resin that covers the semiconductor element, and a sealing resin that covers the semiconductor element. The terminal includes a terminal that is electrically conductive and protrudes from the sealing resin, and a tip plating layer that is disposed on a distal end surface that is an end surface of the terminal that protrudes from the sealing resin.

A method for manufacturing a semiconductor device provided by a second aspect of the present disclosure includes a step of preparing a lead frame including a terminal portion, a step of forming a plating layer on the terminal portion, and a cutting die to form the terminal portion. and a step of cutting. The cutting mold includes a cutting die and a cutting punch. The cut punch includes a first edge portion that cuts the terminal portion. The first edge portion has a curved surface.

According to the above configuration, it is possible to suppress poor solder adhesion when mounted on a wiring board.

Other features and advantages of the present disclosure will become more apparent from the detailed description given below with reference to the accompanying drawings.

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing the semiconductor device of FIG. 1, and is a view through a sealing resin. FIG. 3 is a front view showing the semiconductor device of FIG. 1. 4 is a left side view showing the semiconductor device of FIG. 1. FIG. FIG. 5 is a sectional view taken along line VV in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. FIG. 7 is a partially enlarged view of FIG. 5. FIG. 8 is a partially enlarged view of FIG. 4. FIG. 9 is a plan view showing steps related to the method for manufacturing the semiconductor device of FIG. 1. FIG. 10 is a plan view showing steps related to the method for manufacturing the semiconductor device of FIG. 1. FIG. 11 is a plan view showing steps related to the method for manufacturing the semiconductor device shown in FIG. FIG. 12 is a cross-sectional view showing steps related to the method for manufacturing the semiconductor device shown in FIG. FIG. 13 is a cross-sectional view showing steps related to the method for manufacturing the semiconductor device shown in FIG. FIG. 14 is a partially enlarged view of FIG. 13. FIG. 15 is a partially enlarged sectional view showing the semiconductor device of FIG. 1 mounted on a wiring board. FIG. 16 is a partially enlarged cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure.

Hereinafter, preferred embodiments of the present disclosure will be specifically described with reference to the accompanying drawings.

First embodiment:
1 to 8 show an example of a semiconductor device according to the present disclosure. The semiconductor device A10 of this embodiment includes a first semiconductor element 11, a second semiconductor element 12, an insulating element 13, a conductive member 2, a plurality of wires 61 to 64, and a sealing resin 7. The conductive member 2 includes a first die pad 3, a second die pad 4, a plurality of first terminals 51, a plurality of second terminals 52, a plurality of pad portions 53, 55, a pair of connection portions 54, and a pair of connection portions 56. Contains. The semiconductor device A10 is surface mounted on a wiring board of an inverter device such as an electric vehicle or a hybrid vehicle. Note that the use and function of the semiconductor device A10 are not limited. The package format of the semiconductor device A10 is SOP (Small Outline Package). However, the package format of the semiconductor device A10 is not limited to SOP.

FIG. 1 is a plan view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. In FIG. 2, for convenience of understanding, the outer shape of the sealing resin 7 is shown by an imaginary line (two-dot chain line) that is transmitted through the sealing resin 7. FIG. 3 is a front view showing the semiconductor device A10. FIG. 4 is a left side view showing the semiconductor device A10. FIG. 5 is a sectional view taken along line VV in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. FIG. 7 is a partially enlarged view of FIG. 5. FIG. 8 is a partially enlarged view of FIG. 4.

The semiconductor device A10 has a rectangular shape when viewed in the thickness direction (planar view). For convenience of explanation, the thickness direction (direction in plan view) of the semiconductor device A10 is referred to as the z direction, and the direction along one side of the semiconductor device A10 perpendicular to the z direction (the left-right direction in FIGS. 1 and 2) is referred to as the x direction. The direction perpendicular to the z direction and the x direction (vertical direction in FIGS. 1 and 2) is defined as the y direction. Further, one side in the z direction (the upper side in FIGS. 3 and 4) is the z1 side, and the other side (the lower side in FIGS. 3 and 4) is the z2 side. One side in the x direction (the left side in FIGS. 1 and 2) is the x1 side, and the other side (the right side in FIGS. 1 and 2) is the x2 side. One side in the y direction (the upper side in FIGS. 1 and 2) is the y1 side, and the other side (the lower side in FIGS. 1 and 2) is the y2 side. The z direction corresponds to the "thickness direction" of the present disclosure, the z2 side corresponds to the "first side" of the present disclosure, and the z1 side corresponds to the "second side" of the present disclosure. Note that the shape and dimensions of the semiconductor device A10 are not limited.

The first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are elements that serve as the functional center of the semiconductor device A10.

As shown in FIG. 2, the first semiconductor element 11 is mounted on a part of the conductive member 2 (the first die pad 3 described later), and is located at the center of the semiconductor device A10 in the y direction and closer to the x1 side in the x direction. It is located. The first semiconductor element 11 has a rectangular shape that is long in the y direction when viewed in the z direction. The first semiconductor element 11 is a control element. The first semiconductor element 11 includes a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmission circuit that transmits the PWM control signal to the second semiconductor element 12, and an electrical signal from the second semiconductor element 12. and a receiving circuit for receiving. The first semiconductor element 11 has an element main surface 111 and an element back surface 112 facing oppositely to each other in the z direction. The element main surface 111 faces the z1 side in the z direction. The back surface 112 of the element faces the z2 side in the z direction. A plurality of electrodes 11A are provided on the main surface 111 of the element. The plurality of electrodes 11A are electrically connected to a circuit configured in the first semiconductor element 11.

As shown in FIG. 2, the second semiconductor element 12 is mounted on a part of the conductive member 2 (second die pad 4, which will be described later), and is located at the center of the semiconductor device A10 in the y direction and closer to the x2 side in the x direction. It is located. The second semiconductor element 12 has a rectangular shape that is long in the y direction when viewed in the z direction. The second semiconductor element 12 is a driving element. The second semiconductor element 12 includes a receiving circuit that receives the PWM control signal transmitted from the first semiconductor element 11, and generates a drive signal for a switching element (eg, IGBT, MOSFET, etc.) based on the received PWM control signal. It has an output circuit (gate driver) and a transmission circuit that transmits an electrical signal to the first semiconductor element 11. The second semiconductor element 12 has an element main surface 121 and an element back surface 122 facing oppositely to each other in the z direction. The element main surface 121 faces the z1 side in the z direction. The back surface 122 of the element faces the z2 side in the z direction. A plurality of electrodes 12A are provided on the element main surface 121. The plurality of electrodes 12A are electrically connected to a circuit configured in the second semiconductor element 12.

As shown in FIG. 2, the insulating element 13 is mounted on a part of the conductive member 2 (first die pad 3) and is placed at the center of the semiconductor device A10 in the y direction. The insulating element 13 is located on the x2 side in the x direction with respect to the first semiconductor element 11, and is located on the x1 side in the x direction with respect to the second semiconductor element 12. That is, the insulating element 13 is located between the first semiconductor element 11 and the second semiconductor element 12 in the x direction. The insulating element 13 has a rectangular shape that is long in the y direction when viewed in the z direction. The insulating element 13 is an element for transmitting PWM control signals and other electrical signals in an insulated state. The insulating element 13 receives the PWM control signal from the first semiconductor element 11 via the wire 63 and transmits the received PWM control signal to the second semiconductor element 12 via the wire 64 in an insulated state. Further, the insulating element 13 receives an electrical signal from the second semiconductor element 12 via the wire 64, and transmits the received electrical signal to the first semiconductor element 11 via the wire 63 in an insulated state. That is, the insulating element 13 insulates the first semiconductor element 11 and the second semiconductor element 12 from each other while relaying signals between the first semiconductor element 11 and the second semiconductor element 12.

In this embodiment, the insulation element 13 is an inductive insulation element. An inductive insulating element performs electrical signal transmission in an insulated state by inductively coupling two inductors (coils). The insulating element 13 has a substrate made of Si, and an inductor made of Cu is formed on the substrate. The inductors include a transmitting inductor and a receiving inductor, and these inductors are stacked on each other in the thickness direction (z direction) of the insulating element 13. A dielectric layer made of SiO ₂ or the like is interposed between the transmitting inductor and the receiving inductor. The transmitting inductor and the receiving inductor are electrically insulated by the dielectric layer. Although the present embodiment shows a case where the insulating element 13 is of an inductive type, the insulating element 13 may be of a capacitive type. An example of the capacitive insulation element is a capacitor.

The insulating element 13 has an element main surface 131 and an element back surface 132 facing oppositely to each other in the z direction. The element main surface 131 faces the z1 side in the z direction. The back surface 132 of the element faces the z2 side in the z direction. The element main surface 131 is provided with a plurality of first electrodes 13A and a plurality of second electrodes 13B. Each of the plurality of first electrodes 13A and the plurality of second electrodes 13B is electrically connected to either the transmitting inductor or the receiving inductor. In the insulating element 13, the plurality of first electrodes 13A are arranged along the y direction closer to the x1 side in the x direction. The plurality of second electrodes 13B are arranged along the y direction near the center in the x direction.

The first semiconductor element 11 transmits the PWM control signal to the second semiconductor element 12 via the insulation element 13. Note that the first semiconductor element 11 may also transmit signals other than the PWM control signal to the second semiconductor element 12. The second semiconductor element 12 transmits an electrical signal to the first semiconductor element 11 via the insulation element 13. Note that the information indicated by the electrical signal transmitted from the second semiconductor element 12 to the first semiconductor element 11 is not limited.

A half-bridge circuit in which a low-side switching element and a high-side switching element are connected in a totem pole shape is generally used in a motor driver circuit in an inverter device such as a hybrid vehicle. In an insulated gate driver, only one of the low-side switching elements and the high-side switching elements is turned on at any given time. In the high voltage region, the source of the low-side switching element and the reference potential of the insulated gate driver that drives the switching element are connected to ground, so the gate-source voltage operates based on ground. On the other hand, the source of the high-side switching element and the reference potential of the insulated gate driver that drives the switching element are connected to the output node of the half-bridge circuit. Since the potential of the output node of the half-bridge circuit changes depending on whether the low-side switching element or the high-side switching element is on, the reference potential of the insulated gate driver that drives the high-side switching element changes. When the high-side switching element is on, the reference potential becomes a voltage (for example, 600 V or more) equivalent to the voltage applied to the drain of the high-side switching element. The ground of the first semiconductor element 11 and the second semiconductor element 12 is separated to ensure insulation. When the semiconductor device A10 is used as an insulated gate driver that drives a high-side switching element, a voltage of 600 V or more is transiently applied to the second semiconductor element 12 compared to the ground of the first semiconductor element 11. be done. Since a significant potential difference occurs between the first semiconductor element 11 and the second semiconductor element 12, in the semiconductor device A10, an input side circuit including the second semiconductor element 12 and an output side circuit including the first semiconductor element 11 are insulated by an insulating element 13. That is, the insulating element 13 insulates the input side circuit, which has a relatively low potential, and the output side circuit, which has a relatively high potential.

The conductive member 2 is a member that constitutes a conductive path between the first semiconductor element 11 and the second semiconductor element 12 and the wiring board of the inverter device in the semiconductor device A10. The conductive member 2 is made of an alloy containing Cu in its composition, for example. The conductive member 2 is formed from a lead frame 81, which will be described later. The conductive member 2 mounts a first semiconductor element 11 , a second semiconductor element 12 , and an insulating element 13 . As shown in FIG. 2, the conductive member 2 includes a first die pad 3, a second die pad 4, a plurality of first terminals 51, a plurality of second terminals 52, a plurality of pad portions 53, 55, a pair of connection portions 54, and a pair of connection parts 56.

The first die pad 3 is located at the center of the semiconductor device A10 in the y direction and closer to the x1 side in the x direction. The second die pad 4 is arranged on the x2 side in the x direction with respect to the first die pad 3 and away from the first die pad 3.

As shown in FIGS. 2 and 5, the first die pad 3 has a first semiconductor element 11 and an insulating element 13 mounted thereon. The first die pad 3 is electrically connected to the first semiconductor element 11 and is one element of the input side circuit described above. The first die pad 3 has, for example, a substantially rectangular shape when viewed in the z direction. The first die pad 3 has a main surface 31 and a back surface 32. The main surface 31 and the back surface 32 are located apart from each other in the z direction, as shown in FIGS. 5 and 6. The main surface 31 faces the z1 side, and the back surface 32 faces the z2 side. The first semiconductor element 11 and the insulating element 13 are mounted on the main surface 31 .

The first semiconductor element 11 and the insulating element 13 are bonded to the main surface 31 of the first die pad 3 with a conductive bonding material 19, as shown in FIGS. 6 and 8. In this embodiment, the conductive bonding material 19 is, for example, solder. Note that the conductive bonding material 19 is not limited, and may be a metal paste, sintered metal, or the like.

As shown in FIGS. 2 and 5, the second die pad 4 has a second semiconductor element 12 mounted thereon. The second die pad 4 is electrically connected to the second semiconductor element 12 and is one element of the output side circuit described above. The second die pad 4 has, for example, a substantially rectangular shape when viewed in the z direction. The second die pad 4 has a main surface 41 and a back surface 42. The main surface 41 and the back surface 42 are located apart from each other in the z direction, as shown in FIG. The main surface 41 faces the z1 side, and the back surface 42 faces the z2 side. The second semiconductor element 12 is mounted on the main surface 41 .

The plurality of first terminals 51 are members that constitute a conductive path between the semiconductor device A10 and the wiring board by being joined to the wiring board of the inverter device. Each first terminal 51 is appropriately electrically connected to the first semiconductor element 11 and is one element of the input side circuit described above. As shown in FIGS. 1, 2, and 4, the plurality of first terminals 51 are spaced apart from each other and arranged at regular intervals along the y direction. Each of the plurality of first terminals 51 is located on the x1 side in the x direction with respect to the first die pad 3, and protrudes from the sealing resin 7 (resin side surface 73 to be described later) on the x1 side in the x direction. The plurality of first terminals 51 include a power supply terminal to which voltage is supplied, a ground terminal, an input terminal to which a control signal is input, an input terminal to which other electric signals are input, and an output terminal to output other electric signals. Contains such as. In this embodiment, the semiconductor device A10 includes ten first terminals 51. Note that the number of first terminals 51 is not limited. Moreover, the signals that each first terminal 51 inputs and outputs are not limited.

Each first terminal 51 has an elongated rectangular shape extending along the x direction, and includes a portion exposed from the sealing resin 7 and a portion covered with the sealing resin 7. As shown in FIGS. 3 and 5, the portion of the first terminal 51 exposed from the sealing resin 7 is bent into a gullwing shape bent toward the z2 side in the z direction. As shown in FIG. 7, the first terminal 51 includes a bottom surface 512. The bottom surface 512 is a surface that is bonded to face the wiring board when the semiconductor device A10 is surface mounted on the wiring board of the inverter device, and faces the z2 side in the z direction. A plating layer 25 is disposed on the entire portion of the first terminal 51 exposed from the sealing resin 7 except for a tip surface 511 to be described later. The plating layer 25 contains, for example, Sn. Note that the constituent material of the plating layer 25 is not limited. When the semiconductor device A10 is surface-mounted on the wiring board of an inverter device by solder bonding, the plating layer 25 makes sure that the solder adheres well to the exposed portion and prevents the exposed portion caused by the solder bonding. Prevent erosion.

As shown in FIGS. 7 and 8, each first terminal 51 includes a tip surface 511. The tip surface 511 is the end surface of the first terminal 51 that protrudes from the sealing resin 7 . The tip surface 511 is a cross section formed by cutting the lead frame in a cutting process described later. A tip plating layer 26 is disposed on a portion of the tip surface 511. In FIG. 8, the tip plating layer 26 is dotted. In this embodiment, as will be described later, the edge portion 852a of the cut punch 852 of the cutting die 85 used in the cutting process has a curved surface. Therefore, by cutting the lead frame, a part of the plating layer disposed on the lead frame is extended, and is disposed as the tip plating layer 26 on the tip surface 511, which is the cross section of the lead frame. Therefore, the tip plating layer 26 is made of the same material as the plating layer 25.

The distal end surface 511 includes a first region 511a and a second region 511b. The first region 511a is a region of the tip surface 511 where the tip plating layer 26 is arranged. The second region 511b is a region of the tip surface 511 where the tip plating layer 26 is not disposed. As described later, in this embodiment, cutting is performed from the z2 side to the z1 side in the cutting process, so the first region 511a is located on the z2 side in the z direction from the second region 511b. The dimension L1 of the first region 511a in the z direction is about 1/4 or more and 3/4 or less of the dimension L2 of the distal end surface 511 in the z direction. Further, the area S1 of the first region 511a is about 1/4 or more and 3/4 or less of the area of the tip surface 511.

As shown in FIGS. 7 and 8, the tip surface 511 has a burr 511c that protrudes in the z-direction z1 side. Further, as shown in FIG. 7, the tip surface 511 has an inclined region 511d connected to the bottom surface 512. The inclined region 511d is inclined with respect to the z direction.

The plurality of first terminals 51 include a first terminal 51a and a first terminal 51b. The first terminal 51a is disposed closest to the y1 side in the y direction among the plurality of first terminals 51. The first terminal 51b is disposed closest to the y2 side in the y direction among the plurality of first terminals 51.

The plurality of pad portions 53 are connected to the x2 side in the x direction of the plurality of first terminals 51 other than the first terminals 51a and 51b, respectively. The shape of each pad portion 53 when viewed in the z direction is not limited. The upper surface (the surface facing the z1 side) of each pad portion 53 is substantially flat, and a wire 61 described later is bonded thereto. The upper surface of each pad portion 53 may be plated. The plating layer formed by the plating process is made of a metal containing Ag, for example, and covers the upper surface of the pad portion 53. The plating layer protects the lead frame 81 (described later) from impact during wire bonding of the wire 61 while increasing the bonding strength of the wire 61. The entire surface of the pad portion 53 is covered with the sealing resin 7.

The pair of connecting portions 54 are connected to the first terminal 51a or the first terminal 51b and the first die pad 3, respectively. The connecting portion 54 connected to the first terminal 51a extends in the y direction, and the end portion on the y direction y2 side is connected to the vicinity of the center in the x direction of the end portion on the y direction y1 side of the first die pad 3. The connecting portion 54 connected to the first terminal 51b extends in the y direction, and the end portion on the y direction y1 side is connected to the vicinity of the center in the x direction of the end portion on the y direction y2 side of the first die pad 3. In this way, the first terminal 51a and the first terminal 51b are connected to the first die pad 3 via the pair of connecting portions 54, and support the first die pad 3. The upper surface (the surface facing the z1 side) of each connection portion 54 is substantially flat, and a wire 61 described later is bonded thereto. The upper surface of each connection portion 54 may be covered with a plating layer (for example, a metal containing Ag) similarly to the upper surface of the pad portion 53. The entire surface of the connecting portion 54 is covered with the sealing resin 7.

The plurality of second terminals 52, like the plurality of first terminals 51, are members that are joined to the wiring board of the inverter device, thereby forming a conductive path between the semiconductor device A10 and the wiring board. Each second terminal 52 is appropriately electrically connected to the second semiconductor element 12 and is one element of the output side circuit described above. As shown in FIGS. 1 and 2, the plurality of second terminals 52 are spaced apart from each other and arranged at regular intervals along the y direction. Each of the plurality of second terminals 52 is located on the x2 side in the x direction with respect to the second die pad 4, and protrudes from the sealing resin 7 (resin side surface 74 to be described later) in the x2 side in the x direction. The plurality of second terminals 52 include a power terminal to which a voltage is supplied, a ground terminal, an output terminal to output a drive signal, an input terminal to which other electric signals are input, an output terminal to output other electric signals, etc. Contains. In this embodiment, the semiconductor device A10 includes ten second terminals 52. Note that the number of second terminals 52 is not limited. Moreover, the signals that each second terminal 52 inputs and outputs are not limited.

Each second terminal 52 has an elongated rectangular shape extending along the x direction, and includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIGS. 3 and 5, the portion of the second terminal 52 exposed from the sealing resin 7 is bent into a gullwing shape bent toward the z2 side in the z direction. As shown in FIG. 5, the second terminal 52 includes a bottom surface 522. The bottom surface 522 is a surface that is bonded to face the wiring board when the semiconductor device A10 is surface mounted on the wiring board of the inverter device, and faces the z2 side in the z direction. Similar to the first terminal 51, the plating layer 25 is disposed on the entire portion of the second terminal 52 exposed from the sealing resin 7, except for a tip surface 521, which will be described later.

As shown in FIG. 5, each second terminal 52 includes a tip surface 521. The distal end surface 521 is the end surface of the second terminal 52 that protrudes from the sealing resin 7 . Like the tip surface 511, the tip surface 521 is a cross section formed by cutting the lead frame, and the tip plating layer 26 is disposed in a part thereof.

The tip surface 521, like the first terminal 51, includes a first region 521a and a second region 521b. The first region 521a is a region of the tip surface 521 where the tip plating layer 26 is arranged. The second region 521b is a region of the tip surface 521 where the tip plating layer 26 is not disposed. The tip surface 521 has a burr 521c that protrudes in the z direction z1 side. Further, the tip surface 521 has an inclined region 521d connected to the bottom surface 522. The inclined region 521d is inclined with respect to the z direction.

The plurality of second terminals 52 include a second terminal 52a and a second terminal 52b. The second terminal 52a is arranged second from the y1 side in the y direction among the plurality of second terminals 52. The second terminal 52b is arranged second from the y2 side in the y direction among the plurality of second terminals 52.

The plurality of pad portions 55 are respectively connected to the x1 side in the x direction of the plurality of second terminals 52 other than the second terminals 52a and 52b. The shape of each pad portion 55 when viewed in the z direction is not limited. The upper surface (the surface facing the z1 side) of each pad portion 55 is substantially flat, and a wire 62 described later is bonded thereto. The upper surface of each pad section 55 may be covered with a plating layer (for example, a metal containing Ag) similarly to the upper surface of the pad section 53. The entire surface of the pad portion 55 is covered with the sealing resin 7.

The pair of connecting portions 56 are connected to the second terminal 52a or 52b and the second die pad 4, respectively. The end of the connecting portion 56 connected to the second terminal 52a on the y-direction y2 side is connected to the vicinity of the center of the end of the second die pad 4 on the y-direction y1 side in the x-direction. The end of the connecting portion 56 connected to the second terminal 52b on the y-direction y1 side is connected to the vicinity of the center of the end of the second die pad 4 on the y-direction y2 side in the x-direction. In this way, the second terminal 52a and the second terminal 52b are connected to the second die pad 4 via the pair of connection parts 56, and support the second die pad 4. The upper surface (the surface facing the z1 side) of each connection portion 56 is substantially flat, and a wire 62 described later is bonded thereto. The upper surface of each connection portion 56 may be covered with a plating layer (for example, a metal containing Ag) similarly to the upper surface of the pad portion 53. The entire surface of the connecting portion 56 is covered with the sealing resin 7.

Note that the shape of the conductive member 2 is not limited to the above. For example, the first die pad 3 may be supported by any first terminal 51. That is, the pair of connection parts 54 may be connected to the first die pad 3 and any first terminal 51. Further, the second die pad 4 may be supported by any second terminal 52. That is, the pair of connecting portions 56 may be connected to any second terminal 52 and second die pad 4.

As shown in FIG. 2, the plurality of wires 61 to 64, together with the conductive member 2, constitute a conduction path for the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 to perform predetermined functions. There is. The material of each of the plurality of wires 61 to 64 is, for example, a metal containing Au, Cu, or Al.

The plurality of wires 61 constitute a conduction path between the first semiconductor element 11 and the plurality of first terminals 51, as shown in FIGS. 2 and 5. The first semiconductor element 11 is electrically connected to at least one of the plurality of first terminals 51 through the plurality of wires 61 . The plurality of wires 61 are one element of the input side circuit described above. As shown in FIG. 2, each of the plurality of wires 61 has one end electrically connected to one of the electrodes 11A of the first semiconductor element 11, and the other end connected to one of the plurality of pad portions 53 and the pair of connection portions 54. It is electrically conductive. Note that the number of wires 61 connected to each pad portion 53 and each connection portion 54 is not limited.

The plurality of wires 62 constitute a conduction path between the second semiconductor element 12 and the plurality of second terminals 52, as shown in FIGS. 2 and 5. The second semiconductor element 12 is electrically connected to at least one of the plurality of second terminals 52 through the plurality of wires 62 . The plurality of wires 62 are one element of the output side circuit described above. As shown in FIG. 2, each of the plurality of wires 62 has one end electrically connected to one of the electrodes 12A of the second semiconductor element 12, and the other end connected to one of the plurality of pad portions 55 and the pair of connection portions 56. It is electrically conductive. Note that the number of wires 62 joined to each pad portion 55 and each connection portion 54 is not limited.

The plurality of wires 63 constitute a conduction path between the first semiconductor element 11 and the insulating element 13, as shown in FIGS. 2 and 5. The first semiconductor element 11 and the insulating element 13 are electrically connected to each other by the plurality of wires 63 . The plurality of wires 63 are one element of the input side circuit described above. As shown in FIG. 2, each of the plurality of wires 63 is electrically connected to one of the electrodes 11A of the first semiconductor element 11 and one of the first electrodes 13A of the insulating element 13.

The plurality of wires 64 constitute a conduction path between the second semiconductor element 12 and the insulating element 13, as shown in FIGS. 2 and 5. The second semiconductor element 12 and the insulating element 13 are electrically connected to each other by the plurality of wires 64 . The plurality of wires 64 are one element of the output side circuit described above. As shown in FIG. 2, each of the plurality of wires 64 is electrically connected to one of the electrodes 12A of the second semiconductor element 12 and one of the second electrodes 13B of the insulating element 13.

As shown in FIG. 1, the sealing resin 7 includes a first semiconductor element 11, a second semiconductor element 12, an insulating element 13, a first die pad 3, a second die pad 4, a pair of connecting parts 54, and a pair of connecting parts 56. , respectively, cover a plurality of pad portions 53, 55, a plurality of wires 61 to 64, and a portion of each of a plurality of first terminals 51 and second terminals 52, respectively. The sealing resin 7 has electrical insulation properties. The sealing resin 7 is made of a material containing, for example, a black epoxy resin. The sealing resin 7 has a rectangular shape when viewed in the z direction.

As shown in FIGS. 3 and 4, the sealing resin 7 has a resin top surface 71, a resin bottom surface 72, and resin side surfaces 73 to 76.

The resin top surface 71 and the resin bottom surface 72 are located apart from each other in the z direction. The resin top surface 71 and the resin bottom surface 72 face opposite to each other in the z direction. The resin top surface 71 is located on the z1 side in the z direction, and faces the z1 side similarly to the main surface 31 of the first die pad 3. The resin bottom surface 72 is located on the z2 side in the z direction, and faces the z2 side similarly to the back surface 32 of the first die pad 3. Each of resin top surface 71 and resin bottom surface 72 is substantially flat.

Each of the resin side surfaces 73 to 76 is connected to the resin top surface 71 and the resin bottom surface 72, and is sandwiched between the resin top surface 71 and the resin bottom surface 72 in the z direction. The resin side surface 73 and the resin side surface 74 are located apart from each other in the x direction. The resin side surface 73 and the resin side surface 74 face oppositely to each other in the x direction. The resin side surface 73 is located on the x1 side in the x direction, and the resin side surface 74 is located on the x2 side in the x direction. The resin side surface 75 and the resin side surface 76 are located apart from each other in the y direction, and are connected to the resin side surface 73 and the resin side surface 74. The resin side surface 75 and the resin side surface 76 face opposite to each other in the y direction. The resin side surface 75 is located on the y1 side in the y direction, and the resin side surface 76 is located on the y2 side in the y direction. As shown in FIG. 1, a portion of each of the plurality of first terminals 51 protrudes from the resin side surface 73. Furthermore, a portion of each of the plurality of second terminals 52 protrudes from the resin side surface 74.

As shown in FIGS. 3 and 4, the resin side surface 73 includes a first resin region 731, a second resin region 732, and a third resin region 733. The first resin region 731 has one end in the z direction connected to the resin top surface 71 and the other end in the z direction connected to the third resin region 733 . The first resin region 731 is inclined with respect to the resin top surface 71 and the yz plane. The second resin region 732 has one end in the z direction connected to the resin bottom surface 72 and the other end in the z direction connected to the third resin region 733 . The second resin region 732 is inclined with respect to the resin bottom surface 72 and the yz plane. The third resin region 733 has one end in the z direction connected to the first resin region 731 and the other end in the z direction connected to the second resin region 732 . The third resin region 733 is along the yz plane. When viewed in the z direction, the third resin region 733 is located outward from the resin top surface 71 and the resin bottom surface 72. A portion of each of the plurality of first terminals 51 is exposed from the third resin region 733.

As shown in FIG. 3, the resin side surface 74 includes a fourth resin region 741, a fifth resin region 742, and a sixth resin region 743. The fourth resin region 741 has one end in the z direction connected to the resin top surface 71 and the other end in the z direction connected to the sixth resin region 743 . The fourth resin region 741 is inclined with respect to the resin top surface 71 and the yz plane. The fifth resin region 742 has one end in the z direction connected to the resin bottom surface 72 and the other end in the z direction connected to the sixth resin region 743 . The fifth resin region 742 is inclined with respect to the resin bottom surface 72 and the yz plane. The sixth resin region 743 is connected to the fourth resin region 741 at one end in the z direction, and connected to the fifth resin region 742 at the other end in the z direction. The sixth resin region 743 is along the yz plane. When viewed in the z direction, the sixth resin region 743 is located outward from the resin top surface 71 and the resin bottom surface 72. A portion of each of the plurality of second terminals 52 is exposed from the sixth resin region 743.

As shown in FIG. 4, the resin side surface 75 includes a seventh resin region 751, an eighth resin region 752, and a ninth resin region 753. The seventh resin region 751 has one end in the z direction connected to the resin top surface 71 and the other end in the z direction connected to the ninth resin region 753 . The seventh resin region 751 is inclined with respect to the resin top surface 71 and the xz plane. The eighth resin region 752 has one end in the z direction connected to the resin bottom surface 72 and the other end in the z direction connected to the ninth resin region 753 . The eighth resin region 752 is inclined with respect to the resin bottom surface 72 and the xz plane. The ninth resin region 753 is connected to the seventh resin region 751 at one end in the z direction, and connected to the eighth resin region 752 at the other end in the z direction. The ninth resin region 753 is along the xz plane. When viewed in the z direction, the ninth resin region 753 is located outward from the resin top surface 71 and the resin bottom surface 72.

As shown in FIGS. 3 and 4, the resin side surface 76 includes a tenth resin region 761, an eleventh resin region 762, and a twelfth resin region 763. The tenth resin region 761 has one end in the z direction connected to the resin top surface 71 and the other end in the z direction connected to the twelfth resin region 763 . The tenth resin region 761 is inclined with respect to the resin top surface 71 and the xz plane. The 11th resin region 762 has one end in the z direction connected to the resin bottom surface 72 and the other end in the z direction connected to the 12th resin region 763. The eleventh resin region 762 is inclined with respect to the resin bottom surface 72 and the xz plane. The twelfth resin region 763 has one end in the z direction connected to the tenth resin region 761 and the other end in the z direction connected to the eleventh resin region 762 . The twelfth resin region 763 is along the xz plane. When viewed in the z direction, the twelfth resin region 763 is located outward from the resin top surface 71 and the resin bottom surface 72.

Next, an example of a method for manufacturing the semiconductor device A10 will be described below with reference to FIGS. 9 to 14. 9 to 11 are plan views showing steps related to the method of manufacturing the semiconductor device A10. 12 and 13 are cross-sectional views showing steps related to the method for manufacturing the semiconductor device A10, and show cross-sections corresponding to the cross-section taken along line VV in FIG. 2. FIG. 14 is a partially enlarged view of FIG. 13. Note that the x direction, y direction, and z direction shown in these figures indicate the same directions as in FIGS. 1 to 8.

First, as shown in FIG. 9, a lead frame 81 is prepared. Lead frame 81 is a plate-shaped material. In this embodiment, the base material of the lead frame 81 is made of Cu. The lead frame 81 may be formed by etching or the like on a metal plate, or may be formed by punching a metal plate. In this embodiment, the lead frame 81 is formed by etching. Lead frame 81 has a main surface 81A and a back surface 81B that are spaced apart in the z direction. Further, the lead frame 81 includes an outer frame 811, a first die pad 812A, a second die pad 812B, a plurality of first leads 813, a plurality of second leads 814, a plurality of connection parts 815, and a dam bar 816. Of these, the outer frame 811 and the dam bar 816 do not constitute the semiconductor device A10. The first die pad 812A is a portion that will become the first die pad 3 later. The second die pad 812B is a portion that will become the second die pad 4 later. The plurality of first leads 813 are portions that will later become the plurality of first terminals 51 and pad portions 53. The plurality of second leads 814 are portions that will become the plurality of second terminals 52 and pad portions 55 later. The plurality of connecting portions 815 are portions that will later become a pair of connecting portions 54 and a pair of connecting portions 56.

Next, as shown in FIG. 10, the first semiconductor element 11 and the insulating element 13 are bonded to the first die pad 812A by die bonding, and the second semiconductor element 12 is bonded to the second die pad 812B by die bonding. Next, each of the plurality of wires 61 to 64 is formed by wire bonding.

Next, as shown in FIG. 11, a sealing resin 7 is formed. The sealing resin 7 is formed by transfer molding. In this step, the lead frame 81 is housed in a mold having a plurality of cavities. At this time, a portion of the lead frame 81 that will become the conductive member 2 covered with the sealing resin 7 in the semiconductor device A10 is accommodated in one of the plurality of cavities. Thereafter, fluidized resin is poured into each of the plurality of cavities from the pot via a runner. After the fluidized sealing resin 7 is solidified in the plurality of cavities, resin burrs located outside of each of the plurality of cavities are removed using high-pressure water or the like. With the above steps, the formation of the sealing resin 7 is completed.

Next, a plating layer 82 is formed on the lead frame 81 exposed from the sealing resin 7. As a result, the plating layer 82 is placed on the terminal portion 813a that includes the portion that will become the first terminal 51 of the first lead 813, and the terminal portion 814a that includes the portion that will become the second terminal 52 of the second lead 814. .

Next, as shown in FIG. 12, the terminal portion 813a and the terminal portion 814a are bent. In this step, a forming mold is used to bend the terminal portions 813a and 814a. As a result, the terminal portion 813a and the terminal portion 814a are formed in a gull wing shape bent toward the z2 side in the z direction.

Next, as shown in FIGS. 13 and 14, the lead frame 81 is cut. In this step, the cutting die 85 is used to cut the terminal portion 813a and the terminal portion 814a. In this embodiment, the cutting die 85 employs a so-called upper cut method in which the terminal portion 813a and the terminal portion 814a are cut from the z2 side in the z direction. The cutting die 85 includes a cut die 851, a cut punch 852, and a stripper block 853. A lead frame 81 covered with sealing resin 7 is placed on the stripper block 853 . The cut die 851 presses and fixes the terminal portions 813a and 814a with the stripper block 853. The cut punch 852 is fixed, and the cut die 851 and stripper block 853 move toward the z2 side in the z direction. Thereby, the cut punch 852 moves from the z2 side to the z1 side in the z direction relative to the cut die 851 and the stripper block 853. The cut punch 852 cuts the terminal portion 813a and the terminal portion 814a protruding outward from the cut die 851 between the cut punch 852 and the cut die 851. By cutting the terminal portion 813a, the first terminal 51 is separated from the first lead 813, and by cutting the terminal portion 814a, the second terminal 52 is separated from the second lead 814.

As shown in FIG. 14, the cut punch 852 includes an edge portion 852a that cuts the terminal portion 813a. In this embodiment, the edge portion 852a has a curved surface. The edge portion 852a has a larger radius of curvature than the edge portion 851a of the cut die 851 that cuts the terminal portion 813a. By cutting at the edge portion 852a having a curved surface, a part of the plating layer 82 disposed on the terminal portion 813a extends and is disposed on the cut surface. As a result, the tip plating layer 26 is placed on the tip surface 511 (see FIG. 7). Similarly, the tip plating layer 26 is arranged on the tip surface 521.

Through the steps shown above, the semiconductor device A10 is manufactured.

Next, mounting of the semiconductor device A10 onto the wiring board will be described. FIG. 15 is a partially enlarged cross-sectional view showing a state in which the semiconductor device A10 is mounted on the wiring board 9. As shown in FIG.

As shown in FIG. 15, the semiconductor device A10 is mounted on a wiring board 9, and a plurality of first terminals 51 and second terminals 52 are bonded to wiring (not shown) formed on the wiring board 9 by solder 95. . At this time, since the tip plating layer 26 is disposed on the tip surface 511 of the first terminal 51, the solder 95 also adheres to the tip surface 511, forming a solder fillet. Similarly, since the tip plating layer 26 is disposed on the tip surface 521 of the second terminal 52, the solder 95 also adheres to the tip surface 521, forming a solder fillet.

Next, the effects of the semiconductor device A10 will be explained.

According to this embodiment, the tip plating layer 26 is arranged in the first region 511a located on the z-direction z2 side of the tip surface 511. Therefore, when the first terminal 51 is bonded to the wiring board 9 with the solder 95 during mounting of the semiconductor device A10, the solder 95 also adheres to the tip surface 511, forming a solder fillet. Similarly, the solder 95 adheres to the tip surface 521, forming a solder fillet. Thereby, the semiconductor device A10 can suppress solder adhesion defects when mounted on the wiring board 9.

Further, according to the present embodiment, in the cutting process, the terminal portion 813a and the terminal portion 814a are cut from the z-direction z2 side by the upper cut cutting die 85. Therefore, the tip plating layer 26 is arranged in the first region 511a of the tip surface 511 on the z-direction z2 side. As a result, a tip plating layer 26 that is continuous with the plating layer 25 on the bottom surface 512 is disposed on the tip surface 511 . Similarly, a tip plating layer 26 that is continuous with the plating layer 25 on the bottom surface 522 is arranged on the tip surface 521 as well. Therefore, good solder fillets are likely to be formed. Further, since the burr 511c (521c) protrudes in the z direction z1 side, it does not become an obstacle when the first terminal 51 (second terminal 52) is joined to the wiring board 9.

Note that the package format of the semiconductor device A10, the type and number of semiconductor elements mounted, the shape and arrangement of the conductive member 2, the number of terminals, etc. are not particularly limited. The semiconductor device A10 may have terminals protruding from the sealing resin 7 and may be surface mounted on a wiring board or the like.

FIG. 16 shows another embodiment of the present disclosure. In addition, in these figures, the same or similar elements as in the above embodiment are given the same reference numerals as in the above embodiment.

Second embodiment:
FIG. 16 is a diagram for explaining a semiconductor device A20 according to a second embodiment of the present disclosure. FIG. 16 is a partially enlarged sectional view showing the semiconductor device A20, and corresponds to FIG. 7. The semiconductor device A20 of this embodiment differs from the first embodiment in that the tip plating layer 26 is disposed on the entire surface of the tip surface 511. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. In addition, each part of the said 1st Embodiment may be combined arbitrarily.

In this embodiment, the tip plating layer 26 is disposed on the tip surface 511 and the entire surface of the tip surface 511. The method of manufacturing the semiconductor device A20 according to the second embodiment is different from that of the first embodiment. In the manufacturing method according to the second embodiment, after forming the sealing resin 7 and before forming the plating layer 82, the terminal portions 813a and 814a are bent and cut. The edge portion 852a of the cut punch 852 of the cutting die 85 used in the cutting process does not have the intended curved surface as in the first embodiment. Therefore, the tip surface 511 is not formed with the burr 511c and the inclined region 511d as in the first embodiment. The same applies to the tip surface 521. After cutting the terminal portion 813a and the terminal portion 814a, a plating layer 82 is formed on the first terminal 51 and the second terminal 52 exposed from the sealing resin 7. The plating layer 82 formed on the tip surface 511 and the tip surface 521 is the tip plating layer 26 , and the plating layer 82 formed on a location other than the tip surface 511 and the tip surface 521 is the plating layer 25 .

In this embodiment as well, the tip plating layer 26 is arranged on the tip surface 511. Therefore, when the first terminal 51 is bonded to the wiring board 9 with the solder 95 during mounting of the semiconductor device A20, the solder 95 also adheres to the tip surface 511, forming a solder fillet. Similarly, the solder 95 adheres to the tip surface 521, forming a solder fillet. Thereby, the semiconductor device A20 can suppress solder adhesion defects when mounted on the wiring board 9.

The semiconductor device and the method for manufacturing a semiconductor device according to the present disclosure are not limited to the embodiments described above. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the semiconductor device manufacturing method according to the present disclosure can be variously changed in design. The present disclosure includes the embodiments described in the appendix below.

Appendix 1:
a semiconductor element (11) having an element main surface (111) and an element back surface (112) facing oppositely to each other in the thickness direction (z direction);
a sealing resin (7) covering the semiconductor element;
a terminal (51) electrically connected to the semiconductor element and protruding from the sealing resin;
a tip plating layer (26) disposed on a tip surface (511) that is an end surface of the terminal protruding from the sealing resin;
A semiconductor device (A10) comprising:
Addendum 2:
The tip surface has a first region (511a) in which the tip plating layer is arranged, and a second region (511b) in which the tip plating layer is not arranged.
The semiconductor device according to supplementary note 1.
Appendix 3:
The area (S1) of the first region is 1/4 or more and 3/4 or less of the area (S2) of the tip surface,
The semiconductor device according to appendix 2.
Appendix 4:
The thickness direction dimension (L1) of the first region is 1/4 or more and 3/4 or less of the thickness direction dimension (L2) of the tip surface,
The semiconductor device according to appendix 2.
Appendix 5:
The terminal is bent toward a first side in the thickness direction (z2 side in the z direction),
The first region is located closer to the first side than the second region,
The semiconductor device according to any one of Supplementary Notes 2 to 4.
Appendix 6, Figure 7, Figure 8:
The tip surface has a burr (511c) that protrudes toward a second side (z1 side in the z direction) opposite to the first side in the thickness direction.
The semiconductor device according to appendix 5.
Appendix 7, Figure 7:
The terminal includes a first surface (512) facing the first side,
The tip surface has a one side region (511d) connected to the first surface,
the one side region is inclined with respect to the thickness direction;
The semiconductor device according to appendix 5 or 6.
Appendix 8:
The tip plating layer contains Sn.
The semiconductor device according to any one of Supplementary Notes 1 to 7.
Appendix 9:
further comprising a first plating layer (25) disposed on the terminal,
The tip plating layer and the first plating layer are made of the same material,
The semiconductor device according to any one of Supplementary Notes 1 to 8.
Appendix 10, Figure 15:
The first plating layer is disposed on the entire portion of the terminal exposed from the sealing resin other than the tip surface,
The semiconductor device according to appendix 9.
Appendix 11, Figure 13, Figure 14:
preparing a lead frame (81) including a terminal portion;
forming a plating layer (82) on the terminal portion (813a);
cutting the terminal portion with a cutting die (85);
Equipped with
The cutting mold includes a cut die (851) and a cut punch (852),
The cut punch includes a first edge portion (852a) for cutting the terminal portion,
The method for manufacturing a semiconductor device, wherein the first edge portion has a curved surface.
Appendix 12:
The cut die includes a second edge portion (851a) for cutting the terminal portion,
the first edge portion has a larger radius of curvature than the second edge portion;
The method for manufacturing a semiconductor device according to appendix 11.
Appendix 13:
Further comprising a step of bending the terminal portion before the cutting step.
A method for manufacturing a semiconductor device according to appendix 11 or 12.

A10, A20: Semiconductor device 11: First semiconductor element 111: Element main surface 112: Element back surface 11A: Electrode 12: Second semiconductor element 121: Element main surface 122: Element back surface 12A: Electrode 13: Insulating element 131: Element main surface Surface 132: Element back surface 13A: First electrode 13B: Second electrode 19: Conductive bonding material 2: Conductive member 25: Plating layer 26: Tip plating layer 3: First die pad 31: Main surface 32: Back surface 4: Second Die pad 41: Main surface 42: Back surface 51, 51a, 51b: First terminal 511: Tip surface 511a: First region 511b: Second region 511c: Burr 511d: Slanted region 512: Bottom surface 53: Pad portion 54: Connection portion 52 , 52a, 52b: Second terminal 521: Tip surface 521a: First region 521b: Second region 521c: Burr 521d: Inclined region 522: Bottom surface 55: Pad portion 56: Connection portions 61 to 64: Wire 7: Sealing resin 71: Resin top surface 72: Resin bottom surface 73 to 76: Resin side surface 731: Resin first region 732: Resin second region 733: Resin third region 741: Resin fourth region 742: Resin fifth region 743: Resin sixth region Region 751: Seventh resin region 752: Eighth resin region 753: Ninth resin region 761: Tenth resin region 762: Eleventh resin region 763: Twelfth resin region 81: Lead frame 81A: Main surface 81B: Back surface 811: Outer frame 812A: First die pad 812B: Second die pad 813: First lead 813a: Terminal portion 814: Second lead 814a: Terminal portion 815: Connection portion 816: Dam bar 82: Plating layer 85: Cutting mold 851: Cut die 851a : Edge part 852: Cut punch 852a: Edge part 853: Stripper block 9: Wiring board 95: Solder

Claims (13)

1. a semiconductor element having an element main surface and an element back surface facing oppositely to each other in the thickness direction;
   a sealing resin that covers the semiconductor element;
   a terminal electrically connected to the semiconductor element and protruding from the sealing resin;
   a tip plating layer disposed on a tip surface that is an end surface of the terminal protruding from the sealing resin;
   A semiconductor device equipped with
2. The tip surface has a first region where the tip plating layer is arranged and a second region where the tip plating layer is not arranged.
   The semiconductor device according to claim 1.
3. The area of the first region is 1/4 or more and 3/4 or less of the area of the tip surface,
   The semiconductor device according to claim 2.
4. The dimension of the first region in the thickness direction is 1/4 or more and 3/4 or less of the dimension of the tip surface in the thickness direction.
   The semiconductor device according to claim 2.
5. The terminal is bent toward the first side in the thickness direction,
   The first region is located closer to the first side than the second region,
   A semiconductor device according to any one of claims 2 to 4.
6. The tip surface has a burr that protrudes toward a second side opposite to the first side in the thickness direction.
   The semiconductor device according to claim 5.
7. The terminal includes a first surface facing the first side,
   The tip surface has a one side region connected to the first surface,
   the one side region is inclined with respect to the thickness direction;
   The semiconductor device according to claim 5 or 6.
8. The tip plating layer contains Sn.
   A semiconductor device according to any one of claims 1 to 7.
9. further comprising a first plating layer disposed on the terminal,
   The tip plating layer and the first plating layer are made of the same material,
   A semiconductor device according to any one of claims 1 to 8.
10. The first plating layer is disposed on the entire portion of the terminal exposed from the sealing resin other than the tip surface,
    The semiconductor device according to claim 9.
11. a step of preparing a lead frame including a terminal portion;
    forming a plating layer on the terminal portion;
    cutting the terminal portion using a cutting die;
    Equipped with
    The cutting mold includes a cutting die and a cutting punch,
    The cut punch includes a first edge portion that cuts the terminal portion,
    the first edge portion has a curved surface;
    A method for manufacturing a semiconductor device.
12. The cutting die includes a second edge portion for cutting the terminal portion,
    the first edge portion has a larger radius of curvature than the second edge portion;
    The method for manufacturing a semiconductor device according to claim 11.
13. Further comprising a step of bending the terminal portion before the cutting step.
    The method for manufacturing a semiconductor device according to claim 11 or 12.

Images