WO2023212424A2 - Cold source and negative capacitance field-effect transistor and methods - Google Patents

Cold source and negative capacitance field-effect transistor and methods Download PDF

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WO2023212424A2
WO2023212424A2 PCT/US2023/026955 US2023026955W WO2023212424A2 WO 2023212424 A2 WO2023212424 A2 WO 2023212424A2 US 2023026955 W US2023026955 W US 2023026955W WO 2023212424 A2 WO2023212424 A2 WO 2023212424A2
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transistor
region
channel
gate
semiconductor
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PCT/US2023/026955
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French (fr)
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WO2023212424A3 (en
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Jiechen WANG
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Futurewei Technologies, Inc.
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Publication of WO2023212424A3 publication Critical patent/WO2023212424A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Definitions

  • MOSFET metal oxide semiconductor field effect transistor
  • sub-threshold swing measures the mutual conversion rate between the turn-ON and turn-OFF of a transistor. The lower the sub-threshold swing, the higher the turn-ON and turn-OFF rate of the transistor.
  • the limit of sub-threshold swing at room temperature is 60mV/decade. This, in turn, limits the minimum supply voltage to about 0.5V.
  • a transistor includes a source region, a drain region, a channel and a gate.
  • the source region has a silicide region and a semiconductor region doped with a first dopant type.
  • the drain region includes a semiconductor region doped with a second dopant type.
  • the channel is located between the source region and the drain region.
  • the gate is located above the channel, and includes a ferroelectric material.
  • the silicide region is located between the semiconductor region and the channel.
  • the gate includes a negative capacitance.
  • the source region includes a cold source.
  • the channel has a doping concentration less than a doping concentration of the semiconductor region.
  • the transistor is configured to have a subthreshold swing of less than 60 mV/decade at room temperature.
  • the silicide region includes one or more of a nickel silicide or a cobalt silicide.
  • the silicide region includes one or more of NiSi2, CoSi2, MoSi2, and WSi2.
  • the ferroelectric layer includes one or more of HfO2, ZrO2, HfZrOx, HfSiOx, A12O3, La2O3, TiO2, BaSrTiO3, PbTiO3, and PbZrxTiyOz.
  • the ferroelectric layer has a crystalline structure.
  • the ferroelectric layer has an orthorhombic crystalline structure.
  • the transistor is any of a planar transistor, a three-dimensional transistor, a FinFET transistor, a gate-all-around transistor, a forksheet FET transistor, and complimentary FET transistor.
  • the first dopant type includes an n- type dopant and the second dopant type includes a p-type dopant.
  • the first dopant type includes a p-type dopant and the second dopant type includes an n-type dopant.
  • a method of forming a field effect transistor includes forming a semiconductor channel, forming a cold source at one end of the channel, forming a drain at a second end of the channel, and forming a gate that comprises a negative capacitance above the channel.
  • the field effect transistor is configured to have a subthreshold swing of less than 60 mV/decade at room temperature.
  • the cold source includes a semiconductor region and a silicide region.
  • the drain includes a semiconductor region and a silicide region.
  • the gate includes a ferroelectric material.
  • a transistor that includes a semiconductor channel located between a source region and a drain region, a gate dielectric, and a gate.
  • the source region includes a silicide and a semiconductor that has a crystal lattice mismatch with the semiconductor channel.
  • the gate dielectric is disposed above the semiconductor channel.
  • the gate is disposed above the gate dielectric, and includes a first gate stack, a ferroelectric material and a second gate stack.
  • the crystal lattice mismatch is configured to introduce a compressive stress to the semiconductor channel.
  • the transistor is configured to operate at a supply voltage less than 0.5 volts.
  • the transistor has a subthreshold swing of less than 60 mV/decade at room temperature.
  • the source region includes a cold source and the gate includes a negative capacitance.
  • FIG. l is a diagram depicting drain current versus gate voltage for a conventional MOSFET device at room temperature.
  • FIG. 2A is a simplified diagram of a cross-sectional view of an embodiment of a p-channel transistor according to the disclosed technology.
  • FIG. 2B is a simplified diagram of a cross-sectional view of an embodiment of an n-channel transistor according to the disclosed technology.
  • FIG. 3 A is a simplified diagram of a cross-sectional view of an embodiment of a p-channel transistor that includes symmetric source and drain regions according to the disclosed technology.
  • FIG. 3B is a simplified diagram of a cross-sectional view of an embodiment of an n-channel transistor that includes symmetric source and drain regions according to the disclosed technology.
  • FIG. 4A is a simplified diagram of a cross-sectional view of an embodiment of a p-channel transistor that includes compressive stress according to the disclosed technology.
  • FIG. 4B is a simplified diagram of a cross-sectional view of an embodiment of an n-channel transistor that includes compressive stress according to the disclosed technology.
  • FIG. 5 is a flow chart of an embodiment of a process for forming a field effect transistor according to the disclosed technology.
  • the following presents field effect transistors that include a negative capacitance gate and a cold source structure to provide a transistor that has a sub-threshold swing below 60 mV/dec and is compatible with conventional VLSI processing technology and materials.
  • FIG. 1 is a diagram depicting example drain current versus gate voltage for a conventional MOSFET device at room temperature. The curve on the left is plotted on a log- linear scale. Below the threshold voltage Vth (about 0.5V in the drawing), the drain current increases linearly with gate voltage V g . As depicted in the diagram, the sub-threshold swing is the inverse of the slope of the straight line portion, and is 60 mV/decade.
  • a second is a capacitive coupling and voltage divider term, which is related to the gate voltage across the device.
  • a transistor having a sub-threshold swing below 60 mV/dec can therefore theoretically be achieved by engineering the first term and/or the second term.
  • a tunnel field effect transistor can achieve a steep slope by controlling the field-effect transport term.
  • the working principle of a TFET is modulating quantum tunneling through a barrier instead of modulating thermionic emission over a barrier as in conventional MOSFET devices.
  • TFETs are not limited by a Boltzmann distribution of carriers.
  • the ON current of TFETs are generally small and not suitable for many applications.
  • NC-CS transistors To provide a transistor having a sub-threshold swing below 60 mV/dec and having a higher ON-current than a TFET, technology is described that combines a negative capacitance gate and a cold source structure in a transistor that has a sub-threshold swing below 60 mV/dec and is compatible with conventional VLSI processing technology and materials. For simplicity, such transistors will be referred to herein as NC-CS transistors.
  • cold source refers a source in which charge carriers are not thermally excited from a valence band to a conduction band. Instead, a cold source injects “cold” charge carriers into the channel. In embodiments, a cold source provides an energy filtering effect able to cut off a thermal tail of a Boltzmann distribution of carriers.
  • a “cold source transistor” is a transistor in which band-to-band tunneling occurs in which charge carriers tunnel from a conduction band to a valence band (or vice versa) through a barrier.
  • a ferroelectric material exhibits negative capacitance behavior in certain voltage regions. That is, in certain voltage regions, as the voltage across the ferroelectric material increases, the charge decreases, and thus the ferroelectric material exhibits a negative capacitance.
  • negative capacitance is not a stable state in an isolated ferroelectric material, and a stabilization technique is necessary to access the negative capacitance state of a ferroelectric material.
  • one such stabilization technique may be accomplished by forming a transistor gate that includes a stack of a ferroelectric material and a conventional gate dielectric.
  • a “negative capacitance gate” refers to a transistor gate that includes a negative capacitance effect or operation as described herein.
  • a negative capacitance gate is achieved by integrating a ferroelectric layer having ferroelectric properties in a gate stack of a field effect transistor.
  • a negative capacitance gate can amplify the gate voltage, allowing the transistor to operate at a lower supply voltage.
  • FIG. 2A is a simplified diagram of a cross-sectional view of an embodiment of a p-channel NC-CS transistor 200a.
  • p-channel NC-CS transistor 200a is a planar transistor formed on a substrate 202p, and includes a source region 204n, a p-doped drain region 206p, a p-type channel region 208p, a gate 210 that includes a gate dielectric 212, a first gate stack 214, a ferroelectric layer 216, and a second gate stack 218, and spacers 220.
  • gate 210 is a negative capacitance gate. To avoid overcrowding the drawing, source, gate and drain electrodes are not depicted in FIG. 2A.
  • substrate 202p has a silicon-on-insulator structure that includes an insulator layer 202i disposed on a p-type silicon layer 202ps.
  • substrate 202p may include semiconductor materials other than silicon, such as germanium or other similar semiconductor materials, or a combination of different semiconductor materials, such as silicon-germanium.
  • p-type silicon layer 202ps is doped with p-type dopants.
  • source region 204n includes an n-doped silicon region 222n and a silicide region 224, which collectively form a cold source. Accordingly, source region 204n also will be referred to herein as “cold source region 204n.”
  • n-doped silicon region 222n is heavily n-doped
  • p-doped drain region 206p is heavily p-doped.
  • n-doped silicon region 222n, silicide region 224 and p-doped drain region 206p may be formed using various semiconductor processing techniques.
  • n-doped silicon region 222n and p-doped drain region 206p may be formed using ion implantation or other suitable process.
  • silicide region 224 includes one or more of a nickel silicide (e.g., NiSi2 or other nickel silicides), a cobalt silicide (e.g., CoSi2 or other cobalt silicides), molybdenum disilicide (MoSi2), tungsten disilicide (WSi2), or other similar silicide materials.
  • a nickel silicide e.g., NiSi2 or other nickel silicides
  • a cobalt silicide e.g., CoSi2 or other cobalt silicides
  • MoSi2 molybdenum disilicide
  • WSi2 tungsten disilicide
  • silicide region 224 may be formed by forming a metal layer on top of a silicon region (e.g., using a chemical vapor deposition (CVD), a plasma vapor deposition (PVD), an electroplating process or other suitable process) and then annealing the metal layer to react with the silicon and form silicide region 224.
  • CVD chemical vapor deposition
  • PVD plasma vapor deposition
  • electroplating process electroplating process
  • p-type channel region 208p is disposed between cold source region 204n and drain region 206p.
  • p-type channel region 208p is lightly doped (sometimes referred to as “near intrinsic”).
  • p-type channel region 208p has a doping concentration that is less than a doping concentration of n-doped silicon region 222n, and is less than a doping concentration of p-doped drain region 206p.
  • p-type channel region 208p may be formed using various semiconductor processing techniques. For example, p-type channel region 208p may be formed using ion implantation or other suitable process.
  • gate dielectric 212 includes silicon dioxide (SiCh). In other embodiments, gate dielectric 212 may include a nitride, a high-K dielectric material (e.g., hafnium oxide (HfCh)), or other similar dielectric materials. In an embodiment, gate dielectric 212 is a single dielectric layer. In other embodiments, gate dielectric 212 includes multiple dielectric layers that include multiple different dielectric materials.
  • gate dielectric 212 may be formed using various semiconductor processing techniques.
  • gate dielectric 212 may be formed using CVD, high density plasma CVD, PVD, spin-on, sputtering, or other suitable processes.
  • first gate stack 214 is formed on gate dielectric 212 and includes a conductive material, such as tungsten, tungsten nitride (WN), tantalum nitride (TaN), ruthenium, aluminum or other similar conductive materials.
  • first gate stack 214 may be a single layer or may be multiple layers.
  • first gate stack 214 may be formed using various semiconductor processing techniques.
  • first gate stack 214 may be formed using CVD, high density plasma CVD, PVD, spin-on, sputtering, or other suitable processes.
  • ferroelectric layer 216 is formed on first gate stack 214 and is a layer of material with ferroelectric properties, such as having a reversible electrical polarization.
  • ferroelectric layer 216 may be made of one or more of hafnium oxide (HfCh), zirconium oxide (ZrCh), hafnium zirconium oxide (HfZrOx), hafnium silicon oxide (HfSiOx), aluminum oxide (AI2O3), lanthanum oxide (LaiCh), titanium oxide (TiCh), barium titanate (BaSrTiCh), lead titanate (PbTiCh), lead zirconate titanates (PbZr x TiyO z ), or other similar materials or combinations thereof with various ratios, doped or undoped.
  • ferroelectric layer 216 has a crystalline structure.
  • ferroelectric layer 216 may have an orthorhombic crystalline structure.
  • an annealing process is performed to change the phase of ferroelectric layer 216 such that ferroelectric layer 216 has ferroelectric properties.
  • ferroelectric layer 216 may be in an amorphous state when it is formed on first gate stack 214, and may be subsequently annealed to change the phase of ferroelectric layer 216 from an amorphous state to a crystalline state.
  • ferroelectric layer 216 may be annealed in a gas atmosphere (e.g., an oxygen atmosphere) between 650 to 900 degrees Celsius.
  • a gas atmosphere e.g., an oxygen atmosphere
  • ferroelectric layer 216 is annealed using a spike anneal process in which ferroelectric layer 216 is heated between 750 and 900 degrees Celsius for 25 to 35 seconds. After annealing, ferroelectric layer 216 is in a crystalline state and has ferroelectric properties.
  • second gate stack 218 is formed on ferroelectric layer 216 and includes a conductive material, such as tungsten, WN, TaN, ruthenium, aluminum or other similar conductive materials.
  • second gate stack 218 may be a single layer or may be multiple layers.
  • second gate stack 218 may be formed using various semiconductor processing techniques. For example, second gate stack 218 may be formed using CVD, high density plasma CVD, PVD, spin-on, sputtering, or other suitable processes.
  • spacers 220 are formed on an upper surface of each of cold source region 204n and p-doped drain region 206p, and are positioned on opposite sides of gate 210. In an embodiment, spacers 220 protect sidewalls of gate dielectric 212, first gate stack 214, ferroelectric layer 216, and second gate stack 218.
  • spacers 220 are made of a dielectric material, such as a nitride, a low K dielectric material such as silicon oxynitride (SiO x N y ), silicon nitride (SiaN4), silicon monoxide (SiO), silicon oxynitrocarbide (SiONC), silicon oxycarbide (SiOC), or other suitable materials or combinations thereof.
  • a dielectric material such as a nitride, a low K dielectric material such as silicon oxynitride (SiO x N y ), silicon nitride (SiaN4), silicon monoxide (SiO), silicon oxynitrocarbide (SiONC), silicon oxycarbide (SiOC), or other suitable materials or combinations thereof.
  • spacers 220 may be formed using various semiconductor processing techniques.
  • spacers 220 may be formed using CVD, high density plasma CVD, PVD, spin-on, sputtering, or other suitable processes.
  • p-channel NC-CS transistor 200a may include materials other than silicon and silicides (e.g., germanium and germanides or other similar semiconductor and compound semiconductor materials).
  • p-channel NC-CS transistor 200a may have a sub-threshold swing below 60 mV/dec.
  • silicide region 224 may increase charge carrier tunneling from n-doped silicon region 222n to p-doped drain region 206p compared to that of a TFET device.
  • silicide region 224 may increase band-to-band tunneling efficiency of p-channel NC-CS transistor 200a compared to that of a TFET device. [0067] Without wanting to be bound by any particular theory, it is believed that silicide region 224 may increase the ON-current of p-channel NC-CS transistor 200a compared to that of a TFET device.
  • n-doped silicon region 222n and near-intrinsic p-type channel region 208p as a heterojunction combined with silicide region 224 increase band-to-band tunneling of p- channel NC-CS transistor 200a compared to that of a TFET device.
  • ferroelectric layer 216 may be used to add a negative capacitance to gate 210 and may amplify the gate voltage of p-channel NC-CS transistor 200a and may allow p-channel NC-CS transistor 200a to operate at a lower supply voltage compared to that of a conventional MOSFET device.
  • p-channel NC-CS transistor 200a may achieve lower power consumption compared to conventional MOSFET devices.
  • NC-CS transistor 200a is compatible with contemporary VLSI fabrication techniques and materials.
  • p-channel NC-CS transistor 200a is a planar transistor device.
  • the techniques described above can be used to form p-channel NC-CS three-dimensional (3D) transistor devices, such as p-channel NC-CS FinFET devices, p-channel NC-CS gate-all-around devices, p-channel NC-CS forksheet FET devices, p-channel NC-CS complimentary FET (CFET) devices or other p-channel NC-CS 3D transistor devices.
  • 3D three-dimensional
  • FIG. 2B is a simplified diagram of a cross-sectional view of an embodiment of an n-channel NC-CS transistor 200b.
  • n-channel NC-CS transistor 200b is a planar transistor formed on a substrate 202n, and includes a source region 204p, an n-doped drain region 206n, an n-type channel region 208n, gate 210 and spacers 220.
  • source, gate and drain electrodes are not depicted in FIG. 2B.
  • the following description of n-channel NC-CS transistor 200b will not repeat descriptions above of elements and features in common with p-channel NC-CS transistor 200a of FIG. 2A.
  • substrate 202n has a silicon-on-insulator structure that includes an insulator layer 202i disposed on an n-type silicon layer 202ns.
  • substrate 202n may include semiconductor materials other than silicon, such as germanium or other similar semiconductor materials, or a combination of different semiconductor materials, such as silicon-germanium.
  • n-type silicon layer 202ns is doped with n-type dopants.
  • source region 204p includes a p-doped silicon region 222p and silicide region 224, which collectively form a cold source. Accordingly, source region 204p also will be referred to herein as “cold source region 204p.”
  • p-doped silicon region 222p is heavily p-doped
  • n-doped drain region 206n is heavily n-doped.
  • p-doped silicon region 222p and n-doped drain region 206n may be formed using various semiconductor processing techniques.
  • p-doped silicon region 222p and n-doped drain region 206n may be formed using ion implantation or other suitable process.
  • n-type channel region 208n is disposed between cold source region 204p and drain region 206n.
  • n-type channel region 208n is lightly doped (e.g., near intrinsic).
  • n-type channel region 208n has a doping concentration that is less than a doping concentration of p-doped silicon region 222p, and is less than a doping concentration of n-doped drain region 206n.
  • n-type channel region 208n may be formed using various semiconductor processing techniques. For example, n-type channel region 208n may be formed using ion implantation or other suitable process.
  • spacers 220 are formed on an upper surface of each of cold source region 204p and n-doped drain region 206n, and are positioned on opposite sides of gate 210.
  • n-channel NC-CS transistor 200b may include materials other than silicon and silicides (e.g., germanium and germanides or other similar semiconductor and compound semiconductor materials).
  • n-channel NC-CS transistor 200b may have a sub-threshold swing below 60 mV/dec.
  • silicide region 224 may increase charge carrier tunneling from p-doped silicon region 222p to n- doped drain region 206n compared to that of a TFET device.
  • silicide region 224 may increase band-to-band tunneling efficiency compared to that of a TFET device.
  • silicide region 224 may increase the ON-current of n-channel NC-CS transistor 200b compared to that of a TFET device.
  • ferroelectric layer 216 may be used to add a negative capacitance to gate 210 and may amplify the gate voltage of n-channel NC-CS transistor 200b and may allow n-channel NC-CS transistor 200b to operate at a lower supply voltage compared to that of a conventional MOSFET device.
  • n-channel NC-CS transistor 200b may achieve lower power consumption compared to conventional MOSFET devices.
  • n-channel NC-CS transistor 200b is compatible with contemporary VLSI fabrication techniques and materials.
  • n-channel NC-CS transistor 200b is a planar transistor structure.
  • the techniques described above can be used to form n-channel NC-CS 3D transistor devices, such as n-channel NC-CS FinFET devices, n-channel NC-CS gate-all-around devices, n-channel NC-CS forksheet FET devices, n-channel NC-CS complimentary CFET devices or other n-channel NC-CS 3D transistor devices.
  • FIG. 3 A is a simplified diagram of cross-sectional views of another embodiment of a p-channel NC-CS transistor 300a that includes symmetric source and drain regions
  • FIG. 3B is a simplified diagram of cross-sectional views of another embodiment of an n-channel NC-CS transistor 300b that includes symmetric source and drain regions.
  • p-channel NC-CS transistor 300a includes a drain region 204ps that includes a p-doped silicon region 302p and a silicide region 224d
  • n-channel NC-CS transistor 300b includes a drain region 204ns that includes an n-doped silicon region 302n and silicide region 224d.
  • p-doped silicon region 302p is heavily p-doped
  • n-doped silicon region 302n is heavily n-doped.
  • silicide region 224d includes same materials and is formed using a same process used to form silicide region 224, as described above.
  • p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b may include materials other than silicon and silicides (e.g., germanium and germanides or other similar semiconductor and compound semiconductor materials).
  • p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b may have a sub-threshold swing below 60 mV/dec.
  • silicide regions 224 and 224d may increase charge carrier tunneling from n-doped silicon region 222n to p-doped silicon region 302p of p-channel NC-CS transistor 300a, may increase charge carrier tunneling from p-doped silicon region 222p to n-doped silicon region 302nn of n-channel NC-CS transistor 300b, may increase band-to-band tunneling efficiency, and may increase the ON-current of p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b compared to that of a TFET device.
  • ferroelectric layer 216 may be used to add a negative capacitance to gate 210 and may amplify the gate voltage of p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b and may allow p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b to operate at a lower supply voltage compared to that of a conventional MOSFET device.
  • p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b may achieve lower power consumption compared to conventional MOSFET devices.
  • p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b are compatible with contemporary VLSI fabrication techniques and materials.
  • example p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b may increase flexibility in design of NC-CS transistors because the source electrode and drain and drain electrode can be switched when necessary.
  • the techniques described above with respect to FIGS. 3 A-3B can be used to form p-channel and n-channel NC-CS 3D transistor devices having symmetric source and drain regions.
  • source/drain strain engineering can be added to increase charge mobility in the channel and further enhance ON current.
  • silicon source and drain materials can be substituted with a silicon- germanium (Si-Ge) material.
  • silicon source and drain materials can be substituted with a silicon carbide (SiC) material.
  • FIG. 4A is a simplified diagram of a cross-sectional view of still another embodiment of a p-channel NC-CS transistor 400a.
  • p-channel NC-CS transistor 400a is a planar transistor formed on a substrate 202p.
  • p-channel NC-CS transistor 400a is identical to p-channel NC-CS transistor 200a of FIG. 2A, except that p-channel NC-CS transistor 400a includes a source region 204ng that includes an n-doped Si-Ge region 222ng.
  • n-doped Si-Ge region 222ng is heavily n-doped, and may be formed using various semiconductor processing techniques.
  • epitaxial Si-Ge may be used as a stressor material to form n-doped Si-Ge region 222ng.
  • crystal lattice mismatch between Si-Ge region 222ng and silicon in p-type channel region 208p may introduce compressive stress to the channel, which may increase hole mobility for p-channel NC-CS transistor 400a.
  • FIG. 4B is a simplified diagram of a cross-sectional view of still another embodiment of an n-channel NC-CS transistor 400b.
  • n-channel NC-CS transistor 400b is a planar transistor formed on a substrate 202n.
  • n-channel NC-CS transistor 400b is identical to n-channel NC-CS transistor 200b of FIG. 2B, except that n-channel NC-CS transistor 400b includes a source region 204pc that includes a p-doped SiC region 222pc.
  • p-doped SiC region 222pc is heavily p-doped, and may be formed using various semiconductor processing techniques.
  • epitaxial SiC may be used as a stressor material to form p-doped SiC region 222pc.
  • crystal lattice mismatch between SiC region 222pc and silicon in n-type channel region 208n may introduce compressive stress to the channel, which may increase electron mobility for n-channel NC-CS transistor 400b.
  • FIG. 5 is a is a flow chart of an embodiment of a process for forming a field effect transistor according to the disclosed technology.
  • the method includes forming a semiconductor channel at step 502. Forming a cold source at one end of the channel at step 504. Forming a drain at a second end of the channel at step 506. Forming a gate that comprises a negative capacitance above the channel at step 508.
  • the field effect transistor is configured to have a subthreshold swing of less than 60 mV/decade at room temperature.
  • One embodiment includes a transistor that includes a source region, a drain region, a channel and a gate.
  • the source region has a silicide region and a semiconductor region doped with a first dopant type.
  • the drain region includes a semiconductor doped with a second dopant type.
  • the channel is located between the source region and the drain region.
  • the gate is located above the channel, and includes a ferroelectric material.
  • the silicide region is located between the semiconductor region and the channel.
  • One embodiment includes a method of forming a field effect transistor.
  • the method includes forming a semiconductor channel, forming a cold source at one end of the channel, forming a drain at a second end of the channel, and forming a gate that comprises a negative capacitance above the channel.
  • the field effect transistor is configured to have a subthreshold swing of less than 60 mV/decade at room temperature.
  • One embodiment includes a transistor that includes a semiconductor channel, a source region, a drain region, a gate dielectric and a gate.
  • the semiconductor channel is located between the source region and the drain region.
  • the source region includes a silicide and a semiconductor that has a crystal lattice mismatch with the semiconductor channel.
  • the gate dielectric is located above the semiconductor channel.
  • the gate is located above the gate dielectric, and includes a first gate stack, a ferroelectric material and a second gate stack.
  • the crystal lattice mismatch is configured to introduce a compressive stress to the semiconductor channel.
  • the transistor is configured to operate at a supply voltage less than 0.5 volts.
  • the computer-readable non-transitory media includes all types of computer readable media, including magnetic storage media, optical storage media, and solid state storage media and specifically excludes signals.
  • the software can be installed in and sold with the device. Alternatively the software can be obtained and loaded into the device, including obtaining the software via a disc medium or from any manner of network or distribution system, including, for example, from a server owned by the software creator or from a server not owned but used by the software creator.
  • the software can be stored on a server for distribution over the Internet, for example.
  • Computer-readable storage media exclude (excludes) propagated signals per se, can be accessed by a computer and/or processor(s), and include volatile and non-volatile internal and/or external media that is removable and/or non-removable.
  • the various types of storage media accommodate the storage of data in any suitable digital format.
  • other types of computer readable medium can be employed such as zip drives, solid state drives, magnetic tape, flash memory cards, flash drives, cartridges, and the like, for storing computer executable instructions for performing the novel methods (acts) of the disclosed architecture.
  • each process associated with the disclosed technology may be performed continuously and by one or more computing devices.
  • Each step in a process may be performed by the same or different computing devices as those used in other steps, and each step need not necessarily be performed by a single computing device.

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Abstract

A transistor is provided that includes a source region, a drain region, a channel and a gate. The source region has a silicide region and a semiconductor region doped with a first dopant type. The drain region includes a semiconductor doped with a second dopant type. The channel is located between the source region and the drain region. The gate is located above the channel, and includes a ferroelectric material. The silicide region is located between the semiconductor region and the channel.

Description

COLD SOURCE AND NEGATIVE CAPACITANCE FIELD-EFFECT TRANSISTOR AND METHODS
Inventor Ji echen Wang
BACKGROUND
[0001] Dimension scaling of metal oxide semiconductor field effect transistor (MOSFET) devices has followed Moore’s law for decades, and has brought significant improvements in device density, functionality and switching speed of integrated circuits. However, a rapid rise in power consumption significantly hinders the continuous shrinking of MOSFET devices. Indeed, as transistor dimensions have decreased, power consumption per unit area has increased, which also has made heat dissipation requirements more demanding. Thus, reducing power consumption is critical to further scaling of integrated circuits.
[0002] Reducing power consumption of MOSFET devices requires reducing supply voltage (e.g., VDD). An impediment to reducing supply voltage is a parameter referred to as sub-threshold swing, which measures the mutual conversion rate between the turn-ON and turn-OFF of a transistor. The lower the sub-threshold swing, the higher the turn-ON and turn-OFF rate of the transistor. For a conventional MOSFET device using bulk material for the source, the limit of sub-threshold swing at room temperature is 60mV/decade. This, in turn, limits the minimum supply voltage to about 0.5V.
[0003] Reducing the sub-threshold swing of a transistor to below 60mV/decade provides an opportunity to further reduce the supply voltage below 0.5V. However, many challenges exist to designing and manufacturing a field effect transistor that has a sub-threshold swing below 60mV/decade and that also is compatible with conventional VLSI fabrication processes and materials. SUMMARY
[0004] According to one aspect of the present disclosure, a transistor includes a source region, a drain region, a channel and a gate. The source region has a silicide region and a semiconductor region doped with a first dopant type. The drain region includes a semiconductor region doped with a second dopant type. The channel is located between the source region and the drain region. The gate is located above the channel, and includes a ferroelectric material. The silicide region is located between the semiconductor region and the channel.
[0005] Optionally, in the preceding aspect, the gate includes a negative capacitance.
[0006] Optionally, in any of the preceding aspects, the source region includes a cold source.
[0007] Optionally, in any of the preceding aspects, the channel has a doping concentration less than a doping concentration of the semiconductor region.
[0008] Optionally, in any of the preceding aspects, the transistor is configured to have a subthreshold swing of less than 60 mV/decade at room temperature.
[0009] Optionally, in any of the preceding aspects, the silicide region includes one or more of a nickel silicide or a cobalt silicide.
[0010] Optionally, in any of the preceding aspects, the silicide region includes one or more of NiSi2, CoSi2, MoSi2, and WSi2.
[0011] Optionally, in any of the preceding aspects, the ferroelectric layer includes one or more of HfO2, ZrO2, HfZrOx, HfSiOx, A12O3, La2O3, TiO2, BaSrTiO3, PbTiO3, and PbZrxTiyOz.
[0012] Optionally, in any of the preceding aspects, the ferroelectric layer has a crystalline structure.
[0013] Optionally, in any of the preceding aspects, the ferroelectric layer has an orthorhombic crystalline structure. [0014] Optionally, in any of the preceding aspects, the transistor is any of a planar transistor, a three-dimensional transistor, a FinFET transistor, a gate-all-around transistor, a forksheet FET transistor, and complimentary FET transistor.
[0015] Optionally, in any of the preceding aspects, the first dopant type includes an n- type dopant and the second dopant type includes a p-type dopant.
[0016] Optionally, in any of the preceding aspects, the first dopant type includes a p-type dopant and the second dopant type includes an n-type dopant.
[0017] According to an additional aspect of the present disclosure, there is provided a method of forming a field effect transistor. The method includes forming a semiconductor channel, forming a cold source at one end of the channel, forming a drain at a second end of the channel, and forming a gate that comprises a negative capacitance above the channel. The field effect transistor is configured to have a subthreshold swing of less than 60 mV/decade at room temperature.
[0018] Optionally, in the preceding aspect of the method, the cold source includes a semiconductor region and a silicide region.
[0019] Optionally, in any of the preceding aspects of the method, the drain includes a semiconductor region and a silicide region.
[0020] Optionally, in any of the preceding aspects of the method, the gate includes a ferroelectric material.
[0021] According to a further aspect of the present disclosure, a transistor that includes a semiconductor channel located between a source region and a drain region, a gate dielectric, and a gate. The source region includes a silicide and a semiconductor that has a crystal lattice mismatch with the semiconductor channel. The gate dielectric is disposed above the semiconductor channel. The gate is disposed above the gate dielectric, and includes a first gate stack, a ferroelectric material and a second gate stack. The crystal lattice mismatch is configured to introduce a compressive stress to the semiconductor channel. The transistor is configured to operate at a supply voltage less than 0.5 volts. [0022] Optionally, in the preceding aspect, the transistor has a subthreshold swing of less than 60 mV/decade at room temperature.
[0023] Optionally, in any of the preceding aspects, the source region includes a cold source and the gate includes a negative capacitance.
[0024] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the Background.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Like-numbered elements refer to common components in the different figures.
[0026] FIG. l is a diagram depicting drain current versus gate voltage for a conventional MOSFET device at room temperature.
[0027] FIG. 2A is a simplified diagram of a cross-sectional view of an embodiment of a p-channel transistor according to the disclosed technology.
[0028] FIG. 2B is a simplified diagram of a cross-sectional view of an embodiment of an n-channel transistor according to the disclosed technology.
[0029] FIG. 3 A is a simplified diagram of a cross-sectional view of an embodiment of a p-channel transistor that includes symmetric source and drain regions according to the disclosed technology.
[0030] FIG. 3B is a simplified diagram of a cross-sectional view of an embodiment of an n-channel transistor that includes symmetric source and drain regions according to the disclosed technology. [0031] FIG. 4A is a simplified diagram of a cross-sectional view of an embodiment of a p-channel transistor that includes compressive stress according to the disclosed technology.
[0032] FIG. 4B is a simplified diagram of a cross-sectional view of an embodiment of an n-channel transistor that includes compressive stress according to the disclosed technology.
[0033] FIG. 5 is a flow chart of an embodiment of a process for forming a field effect transistor according to the disclosed technology.
DETAILED DESCRIPTION
[0034] The following presents field effect transistors that include a negative capacitance gate and a cold source structure to provide a transistor that has a sub-threshold swing below 60 mV/dec and is compatible with conventional VLSI processing technology and materials.
[0035] FIG. 1 is a diagram depicting example drain current versus gate voltage for a conventional MOSFET device at room temperature. The curve on the left is plotted on a log- linear scale. Below the threshold voltage Vth (about 0.5V in the drawing), the drain current increases linearly with gate voltage Vg. As depicted in the diagram, the sub-threshold swing is the inverse of the slope of the straight line portion, and is 60 mV/decade.
[0036] A conventional transistor has sub-threshold swing values in the range of 60 - 100 mV/decade, and has a threshold voltage of about 0.25 - 0.5 V. Assuming an overdrive voltage (VDD - Vth) = Vth, a minimum supply voltage VDD for such conventional transistors is about 0.5 - IV.
[0037] For a transistor having a sub-threshold swing below 60 mV/decade, the straight line portion of the curve of FIG. 1 therefore would be steeper. Such transistors are sometimes referred to as “steep slope transistors.” The threshold voltage of a steep slope transistor would therefore be lower than that of a conventional transistor. As a result, again assuming an overdrive voltage (VDD - Vth) = Vth, a minimum supply voltage VDD for such steep slope transistors could be reduced below 0.5V and therefore reduce power consumption. [0038] Two factors determine the sub-threshold swing of a transistor. One is a field effect transport term, which relates to how carriers transfer from the source electrode to the drain electrode of the transistor. A second is a capacitive coupling and voltage divider term, which is related to the gate voltage across the device. A transistor having a sub-threshold swing below 60 mV/dec can therefore theoretically be achieved by engineering the first term and/or the second term.
[0039] A tunnel field effect transistor (TFET) can achieve a steep slope by controlling the field-effect transport term. The working principle of a TFET is modulating quantum tunneling through a barrier instead of modulating thermionic emission over a barrier as in conventional MOSFET devices. As a result, TFETs are not limited by a Boltzmann distribution of carriers. However, because low tunneling efficiency is low, the ON current of TFETs are generally small and not suitable for many applications.
[0040] To provide a transistor having a sub-threshold swing below 60 mV/dec and having a higher ON-current than a TFET, technology is described that combines a negative capacitance gate and a cold source structure in a transistor that has a sub-threshold swing below 60 mV/dec and is compatible with conventional VLSI processing technology and materials. For simplicity, such transistors will be referred to herein as NC-CS transistors.
[0041] As used herein, “cold source” refers a source in which charge carriers are not thermally excited from a valence band to a conduction band. Instead, a cold source injects “cold” charge carriers into the channel. In embodiments, a cold source provides an energy filtering effect able to cut off a thermal tail of a Boltzmann distribution of carriers. As used herein, a “cold source transistor” is a transistor in which band-to-band tunneling occurs in which charge carriers tunnel from a conduction band to a valence band (or vice versa) through a barrier.
[0042] A ferroelectric material exhibits negative capacitance behavior in certain voltage regions. That is, in certain voltage regions, as the voltage across the ferroelectric material increases, the charge decreases, and thus the ferroelectric material exhibits a negative capacitance. However, negative capacitance is not a stable state in an isolated ferroelectric material, and a stabilization technique is necessary to access the negative capacitance state of a ferroelectric material. In the context of a field effect transistor, one such stabilization technique may be accomplished by forming a transistor gate that includes a stack of a ferroelectric material and a conventional gate dielectric.
[0043] As used herein, a “negative capacitance gate” refers to a transistor gate that includes a negative capacitance effect or operation as described herein. In embodiments, a negative capacitance gate is achieved by integrating a ferroelectric layer having ferroelectric properties in a gate stack of a field effect transistor. In embodiments, a negative capacitance gate can amplify the gate voltage, allowing the transistor to operate at a lower supply voltage.
[0044] FIG. 2A is a simplified diagram of a cross-sectional view of an embodiment of a p-channel NC-CS transistor 200a. In an embodiment, p-channel NC-CS transistor 200a is a planar transistor formed on a substrate 202p, and includes a source region 204n, a p-doped drain region 206p, a p-type channel region 208p, a gate 210 that includes a gate dielectric 212, a first gate stack 214, a ferroelectric layer 216, and a second gate stack 218, and spacers 220. As described in more detail below, gate 210 is a negative capacitance gate. To avoid overcrowding the drawing, source, gate and drain electrodes are not depicted in FIG. 2A.
[0045] In an embodiment, substrate 202p has a silicon-on-insulator structure that includes an insulator layer 202i disposed on a p-type silicon layer 202ps. In other embodiments, substrate 202p may include semiconductor materials other than silicon, such as germanium or other similar semiconductor materials, or a combination of different semiconductor materials, such as silicon-germanium. In an embodiment, p-type silicon layer 202ps is doped with p-type dopants.
[0046] In an embodiment, source region 204n includes an n-doped silicon region 222n and a silicide region 224, which collectively form a cold source. Accordingly, source region 204n also will be referred to herein as “cold source region 204n.” In an embodiment, n-doped silicon region 222n is heavily n-doped, and p-doped drain region 206p is heavily p-doped.
[0047] In embodiments, n-doped silicon region 222n, silicide region 224 and p-doped drain region 206p may be formed using various semiconductor processing techniques. For example, n-doped silicon region 222n and p-doped drain region 206p may be formed using ion implantation or other suitable process.
[0048] In an embodiment, silicide region 224 includes one or more of a nickel silicide (e.g., NiSi2 or other nickel silicides), a cobalt silicide (e.g., CoSi2 or other cobalt silicides), molybdenum disilicide (MoSi2), tungsten disilicide (WSi2), or other similar silicide materials.
[0049] In an embodiment, silicide region 224 may be formed by forming a metal layer on top of a silicon region (e.g., using a chemical vapor deposition (CVD), a plasma vapor deposition (PVD), an electroplating process or other suitable process) and then annealing the metal layer to react with the silicon and form silicide region 224.
[0050] In an embodiment, p-type channel region 208p is disposed between cold source region 204n and drain region 206p. In an embodiment, p-type channel region 208p is lightly doped (sometimes referred to as “near intrinsic”). In an embodiment, p-type channel region 208p has a doping concentration that is less than a doping concentration of n-doped silicon region 222n, and is less than a doping concentration of p-doped drain region 206p. In embodiments, p-type channel region 208p may be formed using various semiconductor processing techniques. For example, p-type channel region 208p may be formed using ion implantation or other suitable process.
[0051] In an embodiment, gate dielectric 212 includes silicon dioxide (SiCh). In other embodiments, gate dielectric 212 may include a nitride, a high-K dielectric material (e.g., hafnium oxide (HfCh)), or other similar dielectric materials. In an embodiment, gate dielectric 212 is a single dielectric layer. In other embodiments, gate dielectric 212 includes multiple dielectric layers that include multiple different dielectric materials.
[0052] In embodiments, gate dielectric 212 may be formed using various semiconductor processing techniques. For example, gate dielectric 212 may be formed using CVD, high density plasma CVD, PVD, spin-on, sputtering, or other suitable processes.
[0053] In an embodiment, first gate stack 214 is formed on gate dielectric 212 and includes a conductive material, such as tungsten, tungsten nitride (WN), tantalum nitride (TaN), ruthenium, aluminum or other similar conductive materials. In embodiments, first gate stack 214 may be a single layer or may be multiple layers.
[0054] In embodiments, first gate stack 214 may be formed using various semiconductor processing techniques. For example, first gate stack 214 may be formed using CVD, high density plasma CVD, PVD, spin-on, sputtering, or other suitable processes.
[0055] In an embodiment, ferroelectric layer 216 is formed on first gate stack 214 and is a layer of material with ferroelectric properties, such as having a reversible electrical polarization. For example, ferroelectric layer 216 may be made of one or more of hafnium oxide (HfCh), zirconium oxide (ZrCh), hafnium zirconium oxide (HfZrOx), hafnium silicon oxide (HfSiOx), aluminum oxide (AI2O3), lanthanum oxide (LaiCh), titanium oxide (TiCh), barium titanate (BaSrTiCh), lead titanate (PbTiCh), lead zirconate titanates (PbZrxTiyOz), or other similar materials or combinations thereof with various ratios, doped or undoped. In an embodiment, ferroelectric layer 216 has a crystalline structure. For example, ferroelectric layer 216 may have an orthorhombic crystalline structure.
[0056] In an embodiment, an annealing process is performed to change the phase of ferroelectric layer 216 such that ferroelectric layer 216 has ferroelectric properties. For example, ferroelectric layer 216 may be in an amorphous state when it is formed on first gate stack 214, and may be subsequently annealed to change the phase of ferroelectric layer 216 from an amorphous state to a crystalline state.
[0057] For example, ferroelectric layer 216 may be annealed in a gas atmosphere (e.g., an oxygen atmosphere) between 650 to 900 degrees Celsius. In an embodiment, ferroelectric layer 216 is annealed using a spike anneal process in which ferroelectric layer 216 is heated between 750 and 900 degrees Celsius for 25 to 35 seconds. After annealing, ferroelectric layer 216 is in a crystalline state and has ferroelectric properties.
[0058] In an embodiment, second gate stack 218 is formed on ferroelectric layer 216 and includes a conductive material, such as tungsten, WN, TaN, ruthenium, aluminum or other similar conductive materials. In embodiments, second gate stack 218 may be a single layer or may be multiple layers. [0059] In embodiments, second gate stack 218 may be formed using various semiconductor processing techniques. For example, second gate stack 218 may be formed using CVD, high density plasma CVD, PVD, spin-on, sputtering, or other suitable processes.
[0060] In an embodiment, spacers 220 are formed on an upper surface of each of cold source region 204n and p-doped drain region 206p, and are positioned on opposite sides of gate 210. In an embodiment, spacers 220 protect sidewalls of gate dielectric 212, first gate stack 214, ferroelectric layer 216, and second gate stack 218.
[0061] In embodiments, spacers 220 are made of a dielectric material, such as a nitride, a low K dielectric material such as silicon oxynitride (SiOxNy), silicon nitride (SiaN4), silicon monoxide (SiO), silicon oxynitrocarbide (SiONC), silicon oxycarbide (SiOC), or other suitable materials or combinations thereof.
[0062] In embodiments, spacers 220 may be formed using various semiconductor processing techniques. For example, spacers 220 may be formed using CVD, high density plasma CVD, PVD, spin-on, sputtering, or other suitable processes.
[0063] In other embodiments, p-channel NC-CS transistor 200a may include materials other than silicon and silicides (e.g., germanium and germanides or other similar semiconductor and compound semiconductor materials).
[0064] Without wanting to be bound by any particular theory, it is believed that p-channel NC-CS transistor 200a may have a sub-threshold swing below 60 mV/dec.
[0065] Without wanting to be bound by any particular theory, it is believed that silicide region 224 may increase charge carrier tunneling from n-doped silicon region 222n to p-doped drain region 206p compared to that of a TFET device.
[0066] Without wanting to be bound by any particular theory, it is believed that silicide region 224 may increase band-to-band tunneling efficiency of p-channel NC-CS transistor 200a compared to that of a TFET device. [0067] Without wanting to be bound by any particular theory, it is believed that silicide region 224 may increase the ON-current of p-channel NC-CS transistor 200a compared to that of a TFET device.
[0068] Without wanting to be bound by any particular theory, it is believed that heavily doped n-doped silicon region 222n and near-intrinsic p-type channel region 208p as a heterojunction, combined with silicide region 224 increase band-to-band tunneling of p- channel NC-CS transistor 200a compared to that of a TFET device.
[0069] In addition, without wanting to be bound by any particular theory, it is believed that ferroelectric layer 216 may be used to add a negative capacitance to gate 210 and may amplify the gate voltage of p-channel NC-CS transistor 200a and may allow p-channel NC-CS transistor 200a to operate at a lower supply voltage compared to that of a conventional MOSFET device.
[0070] In addition, without wanting to be bound by any particular theory, it is believed that p-channel NC-CS transistor 200a may achieve lower power consumption compared to conventional MOSFET devices.
[0071] In addition, without wanting to be bound by any particular theory, it is believed that p-channel NC-CS transistor 200a is compatible with contemporary VLSI fabrication techniques and materials.
[0072] As described above, p-channel NC-CS transistor 200a is a planar transistor device. In other embodiments, the techniques described above can be used to form p-channel NC-CS three-dimensional (3D) transistor devices, such as p-channel NC-CS FinFET devices, p-channel NC-CS gate-all-around devices, p-channel NC-CS forksheet FET devices, p-channel NC-CS complimentary FET (CFET) devices or other p-channel NC-CS 3D transistor devices.
[0073] FIG. 2B is a simplified diagram of a cross-sectional view of an embodiment of an n-channel NC-CS transistor 200b. In an embodiment, n-channel NC-CS transistor 200b is a planar transistor formed on a substrate 202n, and includes a source region 204p, an n-doped drain region 206n, an n-type channel region 208n, gate 210 and spacers 220. To avoid overcrowding the drawing, source, gate and drain electrodes are not depicted in FIG. 2B. To avoid unnecessary repetition, the following description of n-channel NC-CS transistor 200b will not repeat descriptions above of elements and features in common with p-channel NC-CS transistor 200a of FIG. 2A.
[0074] In an embodiment, substrate 202n has a silicon-on-insulator structure that includes an insulator layer 202i disposed on an n-type silicon layer 202ns. In other embodiments, substrate 202n may include semiconductor materials other than silicon, such as germanium or other similar semiconductor materials, or a combination of different semiconductor materials, such as silicon-germanium. In an embodiment, n-type silicon layer 202ns is doped with n-type dopants.
[0075] In an embodiment, source region 204p includes a p-doped silicon region 222p and silicide region 224, which collectively form a cold source. Accordingly, source region 204p also will be referred to herein as “cold source region 204p.” In an embodiment, p-doped silicon region 222p is heavily p-doped, and n-doped drain region 206n is heavily n-doped.
[0076] In embodiments, p-doped silicon region 222p and n-doped drain region 206n may be formed using various semiconductor processing techniques. For example, p-doped silicon region 222p and n-doped drain region 206n may be formed using ion implantation or other suitable process.
[0077] In an embodiment, n-type channel region 208n is disposed between cold source region 204p and drain region 206n. In an embodiment, n-type channel region 208n is lightly doped (e.g., near intrinsic). In an embodiment, n-type channel region 208n has a doping concentration that is less than a doping concentration of p-doped silicon region 222p, and is less than a doping concentration of n-doped drain region 206n. In embodiments, n-type channel region 208n may be formed using various semiconductor processing techniques. For example, n-type channel region 208n may be formed using ion implantation or other suitable process.
[0078] In an embodiment, spacers 220 are formed on an upper surface of each of cold source region 204p and n-doped drain region 206n, and are positioned on opposite sides of gate 210. [0079] In other embodiments, n-channel NC-CS transistor 200b may include materials other than silicon and silicides (e.g., germanium and germanides or other similar semiconductor and compound semiconductor materials).
[0080] Without wanting to be bound by any particular theory, it is believed that n-channel NC-CS transistor 200b may have a sub-threshold swing below 60 mV/dec.
[0081] Without wanting to be bound by any particular theory, it is believed that silicide region 224 may increase charge carrier tunneling from p-doped silicon region 222p to n- doped drain region 206n compared to that of a TFET device.
[0082] Without wanting to be bound by any particular theory, it is believed that silicide region 224 may increase band-to-band tunneling efficiency compared to that of a TFET device.
[0083] Without wanting to be bound by any particular theory, it is believed that silicide region 224 may increase the ON-current of n-channel NC-CS transistor 200b compared to that of a TFET device.
[0084] Without wanting to be bound by any particular theory, it is believed that heavily doped p-doped silicon region 222p and near-intrinsic n-type channel region 208n as a heterojunction, combined with silicide region 224 increase band-to-band tunneling of n-channel NC-CS transistor 200b compared to that of a TFET device.
[0085] In addition, without wanting to be bound by any particular theory, it is believed that ferroelectric layer 216 may be used to add a negative capacitance to gate 210 and may amplify the gate voltage of n-channel NC-CS transistor 200b and may allow n-channel NC-CS transistor 200b to operate at a lower supply voltage compared to that of a conventional MOSFET device.
[0086] In addition, without wanting to be bound by any particular theory, it is believed that n-channel NC-CS transistor 200b may achieve lower power consumption compared to conventional MOSFET devices. [0087] In addition, without wanting to be bound by any particular theory, it is believed that n-channel NC-CS transistor 200b is compatible with contemporary VLSI fabrication techniques and materials.
[0088] As described above, n-channel NC-CS transistor 200b is a planar transistor structure. In other embodiments, the techniques described above can be used to form n-channel NC-CS 3D transistor devices, such as n-channel NC-CS FinFET devices, n-channel NC-CS gate-all-around devices, n-channel NC-CS forksheet FET devices, n-channel NC-CS complimentary CFET devices or other n-channel NC-CS 3D transistor devices.
[0089] The example p-channel NC-CS transistor 200a and n-channel NC-CS transistor 200b of FIGS. 2A and 2B respectively, have asymmetric source and drain regions, with silicide region 224 included only in cold source region 204n and 204p, respectively. FIG. 3 A is a simplified diagram of cross-sectional views of another embodiment of a p-channel NC-CS transistor 300a that includes symmetric source and drain regions, and FIG. 3B is a simplified diagram of cross-sectional views of another embodiment of an n-channel NC-CS transistor 300b that includes symmetric source and drain regions.
[0090] In particular, p-channel NC-CS transistor 300a includes a drain region 204ps that includes a p-doped silicon region 302p and a silicide region 224d, and n-channel NC-CS transistor 300b includes a drain region 204ns that includes an n-doped silicon region 302n and silicide region 224d. In an embodiment, p-doped silicon region 302p is heavily p-doped, and n-doped silicon region 302n is heavily n-doped. In embodiments, silicide region 224d includes same materials and is formed using a same process used to form silicide region 224, as described above.
[0091] In other embodiments, p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b may include materials other than silicon and silicides (e.g., germanium and germanides or other similar semiconductor and compound semiconductor materials).
[0092] Without wanting to be bound by any particular theory, it is believed that p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b may have a sub-threshold swing below 60 mV/dec. [0093] In particular, without wanting to be bound by any particular theory, it is believed that silicide regions 224 and 224d may increase charge carrier tunneling from n-doped silicon region 222n to p-doped silicon region 302p of p-channel NC-CS transistor 300a, may increase charge carrier tunneling from p-doped silicon region 222p to n-doped silicon region 302nn of n-channel NC-CS transistor 300b, may increase band-to-band tunneling efficiency, and may increase the ON-current of p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b compared to that of a TFET device.
[0094] In addition, without wanting to be bound by any particular theory, it is believed that ferroelectric layer 216 may be used to add a negative capacitance to gate 210 and may amplify the gate voltage of p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b and may allow p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b to operate at a lower supply voltage compared to that of a conventional MOSFET device.
[0095] In addition, without wanting to be bound by any particular theory, it is believed that p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b may achieve lower power consumption compared to conventional MOSFET devices.
[0096] In addition, without wanting to be bound by any particular theory, it is believed that p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b are compatible with contemporary VLSI fabrication techniques and materials.
[0097] In addition, without wanting to be bound by any particular theory, it is believed that the example p-channel NC-CS transistor 300a and n-channel NC-CS transistor 300b may increase flexibility in design of NC-CS transistors because the source electrode and drain and drain electrode can be switched when necessary.
[0098] In other embodiments, the techniques described above with respect to FIGS. 3 A-3B can be used to form p-channel and n-channel NC-CS 3D transistor devices having symmetric source and drain regions.
[0099] In still other embodiments, source/drain strain engineering can be added to increase charge mobility in the channel and further enhance ON current. For example, for a p-type NC-CS transistor, silicon source and drain materials can be substituted with a silicon- germanium (Si-Ge) material. In another example, for an n-type NC-CS transistor, silicon source and drain materials can be substituted with a silicon carbide (SiC) material.
[00100] FIG. 4A is a simplified diagram of a cross-sectional view of still another embodiment of a p-channel NC-CS transistor 400a. In an embodiment, p-channel NC-CS transistor 400a is a planar transistor formed on a substrate 202p. In an embodiment, p-channel NC-CS transistor 400a is identical to p-channel NC-CS transistor 200a of FIG. 2A, except that p-channel NC-CS transistor 400a includes a source region 204ng that includes an n-doped Si-Ge region 222ng.
[00101] In an embodiment, n-doped Si-Ge region 222ng is heavily n-doped, and may be formed using various semiconductor processing techniques. In an embodiment, epitaxial Si-Ge may be used as a stressor material to form n-doped Si-Ge region 222ng. Without wanting to be bound by any particular theory, it is believed that crystal lattice mismatch between Si-Ge region 222ng and silicon in p-type channel region 208p may introduce compressive stress to the channel, which may increase hole mobility for p-channel NC-CS transistor 400a.
[00102] FIG. 4B is a simplified diagram of a cross-sectional view of still another embodiment of an n-channel NC-CS transistor 400b. In an embodiment, n-channel NC-CS transistor 400b is a planar transistor formed on a substrate 202n. In an embodiment, n-channel NC-CS transistor 400b is identical to n-channel NC-CS transistor 200b of FIG. 2B, except that n-channel NC-CS transistor 400b includes a source region 204pc that includes a p-doped SiC region 222pc.
[00103] In an embodiment, p-doped SiC region 222pc is heavily p-doped, and may be formed using various semiconductor processing techniques. In an embodiment, epitaxial SiC may be used as a stressor material to form p-doped SiC region 222pc. Without wanting to be bound by any particular theory, it is believed that crystal lattice mismatch between SiC region 222pc and silicon in n-type channel region 208n may introduce compressive stress to the channel, which may increase electron mobility for n-channel NC-CS transistor 400b.
[00104] FIG. 5 is a is a flow chart of an embodiment of a process for forming a field effect transistor according to the disclosed technology. The method includes forming a semiconductor channel at step 502. Forming a cold source at one end of the channel at step 504. Forming a drain at a second end of the channel at step 506. Forming a gate that comprises a negative capacitance above the channel at step 508. The field effect transistor is configured to have a subthreshold swing of less than 60 mV/decade at room temperature.
[00105] One embodiment includes a transistor that includes a source region, a drain region, a channel and a gate. The source region has a silicide region and a semiconductor region doped with a first dopant type. The drain region includes a semiconductor doped with a second dopant type. The channel is located between the source region and the drain region. The gate is located above the channel, and includes a ferroelectric material. The silicide region is located between the semiconductor region and the channel.
[00106] One embodiment includes a method of forming a field effect transistor. The method includes forming a semiconductor channel, forming a cold source at one end of the channel, forming a drain at a second end of the channel, and forming a gate that comprises a negative capacitance above the channel. The field effect transistor is configured to have a subthreshold swing of less than 60 mV/decade at room temperature.
[00107] One embodiment includes a transistor that includes a semiconductor channel, a source region, a drain region, a gate dielectric and a gate. The semiconductor channel is located between the source region and the drain region. The source region includes a silicide and a semiconductor that has a crystal lattice mismatch with the semiconductor channel. The gate dielectric is located above the semiconductor channel. The gate is located above the gate dielectric, and includes a first gate stack, a ferroelectric material and a second gate stack. The crystal lattice mismatch is configured to introduce a compressive stress to the semiconductor channel. The transistor is configured to operate at a supply voltage less than 0.5 volts.
[00108] It is understood that the present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete and will fully convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. However, it will be clear to those of ordinary skill in the art that the present subject matter may be practiced without such specific details.
[00109] Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatuses (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
[00110] The computer-readable non-transitory media includes all types of computer readable media, including magnetic storage media, optical storage media, and solid state storage media and specifically excludes signals. It should be understood that the software can be installed in and sold with the device. Alternatively the software can be obtained and loaded into the device, including obtaining the software via a disc medium or from any manner of network or distribution system, including, for example, from a server owned by the software creator or from a server not owned but used by the software creator. The software can be stored on a server for distribution over the Internet, for example.
[00111] Computer-readable storage media (medium) exclude (excludes) propagated signals per se, can be accessed by a computer and/or processor(s), and include volatile and non-volatile internal and/or external media that is removable and/or non-removable. For the computer, the various types of storage media accommodate the storage of data in any suitable digital format. It should be appreciated by those skilled in the art that other types of computer readable medium can be employed such as zip drives, solid state drives, magnetic tape, flash memory cards, flash drives, cartridges, and the like, for storing computer executable instructions for performing the novel methods (acts) of the disclosed architecture. [00112] The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure herein were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure with various modifications as are suited to the particular use contemplated.
[00113] For purposes of this document, each process associated with the disclosed technology may be performed continuously and by one or more computing devices. Each step in a process may be performed by the same or different computing devices as those used in other steps, and each step need not necessarily be performed by a single computing device.
[00114] Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A transi stor compri sing : a source region comprising silicide region and a semiconductor region doped with a first dopant type; a drain region comprising a semiconductor doped with a second dopant type; a channel disposed between the source region and the drain region; and a gate disposed above the channel, the gate comprising a ferroelectric material, wherein the silicide region is disposed between the semiconductor region and the channel.
2. The transistor of claim 1, wherein the gate comprises a structure configured to operate with a negative capacitance.
3. The transistor of any of claims 1-2, wherein the source region comprises a cold source.
4. The transistor of any of claims 1-3, wherein the channel has a doping concentration less than a doping concentration of the semiconductor region.
5. The transistor of any of claims 1-4, wherein the transistor is configured to have a subthreshold swing of less than 60 mV/decade at room temperature.
6. The transistor of any of claims 1-5, wherein the silicide region comprises one or more of a nickel silicide or a cobalt silicide.
7. The transistor of any of claims 1-5, wherein the silicide region comprises one or more of NiSi2, CoSi2, MoSi2, and WSi2.
8. The transistor of any of claims 1-7, wherein the ferroelectric layer comprises one or more of HfO2, ZrO2, HfZrOx, HfSiOx, AI2O3, La2O3, TiO2, BaSrTiO3, PbTiO3, and PbZrxTiyOz.
9. The transistor of any of claims 1-8, wherein the ferroelectric layer comprises a crystalline structure.
10. The transistor of any of claims 1-9, wherein the ferroelectric layer comprises an orthorhombic crystalline structure.
11. The transistor of any of claims 1-10, comprising any of a planar transistor, a three-dimensional transistor, a FinFET transistor, a gate-all-around transistor, a forksheet FET transistor, and complimentary FET transistor.
12. The transistor of any of claims 1-11, wherein the first dopant type comprises an n-type dopant and the second dopant type comprises a p-type dopant.
13. The transistor of any of claims 1-11, wherein the first dopant type comprises a p- type dopant and the second dopant type comprises an n-type dopant.
14. A method of forming a field effect transistor, comprising: forming a semiconductor channel; forming a cold source at one end of the channel; forming a drain at a second end of the channel; and forming a gate that comprises a negative capacitance above the channel wherein the field effect transistor is configured to have a subthreshold swing of less than 60 mV/decade at room temperature.
15. The method of claim 14, wherein the cold source comprises a semiconductor region and a silicide region.
16. The method of any of claims 14-15, wherein the drain comprises a semiconductor region and a silicide region.
17. The method of any of claims 14-16, wherein the gate comprises a ferroelectric material.
18. A transi stor compri sing : a semiconductor channel disposed between a source region and a drain region, the source region comprising a silicide and a semiconductor comprising a crystal lattice mismatch with the semiconductor channel; a gate dielectric disposed above the semiconductor channel; and a gate disposed above the gate dielectric, the gate comprising a first gate stack, a ferroelectric material and a second gate stack, wherein: the crystal lattice mismatch is configured to introduce a compressive stress to the semiconductor channel; and the transistor is configured to operate at a supply voltage less than 0.5 volts.
19. The transistor of claim 18, comprising a subthreshold swing of less than 60 mV/decade at room temperature.
20. The transistor of any of claims 18-19, wherein the source region comprises a cold source and the gate comprises a negative capacitance.
PCT/US2023/026955 2023-07-05 2023-07-05 Cold source and negative capacitance field-effect transistor and methods WO2023212424A2 (en)

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