WO2023211029A1

WO2023211029A1 - Neuronal circuit

Info

Publication number: WO2023211029A1
Application number: PCT/KR2023/005101
Authority: WO
Inventors: 최우석; 송중현; 신지원; 김한석
Original assignee: 서울대학교산학협력단
Priority date: 2022-04-27
Filing date: 2023-04-14
Publication date: 2023-11-02
Also published as: KR20230152336A

Abstract

A neuronal circuit according to one aspect of the present invention comprises: a current provision unit for providing a current adjusted according to one or more spike signals; a signal accumulation unit for adjusting the accumulated state of the spike signals at the time domain by using a clock signal of which the frequency is adjusted by means of the current; and a firing unit for outputting the spike signals if the spike signals are accumulated at a critical value or higher through the signal accumulation unit.

Description

neuron circuit

The present invention relates to a neuron circuit used in a spiking neural network provision device.

With the recent advancement of computing technology based on artificial neural networks, research and development on spiking neural networks (SNNs) is also being actively conducted. Although the spiking neural network began as an imitation of the actual biological nervous system (concepts about memory, learning, and reasoning), it only adopts a similar network structure and differs from the actual biological nervous system in various aspects such as signal transmission, information expression method, and learning method. There is a difference. Meanwhile, hardware-based SNN, which operates almost identically to the actual nervous system, can implement ultra-low-power computing systems with high accuracy, and research on this is actively underway.

A typical neuron circuit is configured to accumulate (integrate) spike signals transmitted from the previous neuron circuit and perform a fire operation to output a new spike signal when the signal accumulates above a reference value.

Figure 1 is a diagram showing the structure of a typical neuron circuit.

As shown in Figure 1(a), a typical neuron circuit uses a capacitor to accumulate signals. When a voltage above a certain level is accumulated in the capacitor, the neuron circuit generates a spike signal through a firing operation and transmits it to the next neuron circuit. For this purpose, a current mirror circuit or operational amplifier is used to accumulate the spike signal transmitted from the previous neuron circuit in the form of a membrane potential. In other words, a typical neuron circuit uses a method of processing signals at the voltage domain level.

In particular, in a method using a current mirror, the amount of current flowing in the current mirror changes depending on the value of the membrane potential due to channel length modulation. Therefore, there is a problem that the amount of increase in membrane potential is not constant even for the same spike signal. This nonlinearity causes the performance of SNN to deteriorate. Additionally, the method using an operational amplifier consumes large power because a high supply voltage is required to ensure the gain and linearity of the operational amplifier. These problems become worse as process miniaturization and supply voltage decrease. Low output impedance, intrinsic gain, and increased leakage current occurring in the device worsen linearity and degrade the performance of the SNN. Low supply voltage also causes performance degradation of the SNN because it limits the voltage headroom and membrane potential range. To solve this problem, when increasing the device size, an increase in power consumption and area is inevitable. Therefore, in order to implement a more complex and larger artificial neural network, it is necessary to solve the problems of neuron circuits at the voltage domain level.

The present invention is intended to solve the problems of the prior art described above, and aims to provide a neuron circuit capable of accumulating and firing spiking signals in the time domain.

However, the technical challenge that this embodiment aims to achieve is not limited to the technical challenges described above, and other technical challenges may exist.

As a technical means for solving the above-described technical problem, a neuron circuit according to one aspect of the present invention includes a current provider that provides a current adjusted according to one or more spike signals; a first current-controlled oscillator that generates a clock signal whose frequency is adjusted by the current; and an ignition unit that determines whether to generate a spike signal according to the phase difference between the clock signal of the first current-controlled oscillator and the reference clock signal.

In addition, a neuron circuit according to another aspect of the present invention includes a current provider that provides a current adjusted according to one or more spike signals; A signal accumulator that adjusts the accumulation state of the spike signal in the time domain using a clock signal whose frequency is adjusted by the current, and a spike signal when the spike signal is accumulated above the threshold through the signal accumulator. Includes an output utterance unit.

According to the neuron circuit of the present invention described above, the problems of the neuron circuit that accumulates and fires spike signals according to the conventional voltage domain method can be solved. The present invention uses a time domain method to generate a clock signal whose frequency is adjusted according to a spike signal received from the outside, and through this, the weight of the spike signal can be accumulated. Through this, the linearity of the neuron circuit can be greatly improved, and inference accuracy can also be greatly improved.

Figure 1 is a diagram showing the structure of a typical neuron circuit.

Figure 2 is a block diagram showing the configuration of a neuron circuit according to an embodiment of the present invention.

Figure 3 is a diagram showing the detailed configuration of a neuron circuit according to an embodiment of the present invention.

Figure 4 is a diagram for explaining the operating mechanism of a neuron circuit according to an embodiment of the present invention.

Figure 5 is a diagram showing simulation results of a neuron circuit according to an embodiment of the present invention.

Below, with reference to the attached drawings, embodiments of the present application will be described in detail so that those skilled in the art can easily implement them. However, the present application may be implemented in various different forms and is not limited to the embodiments described herein. In order to clearly explain the present application in the drawings, parts that are not related to the description are omitted, and similar reference numerals are assigned to similar parts throughout the specification.

Throughout this specification, when a part is said to be “connected” to another part, this includes not only the case where it is “directly connected,” but also the case where it is “electrically connected” with another element in between. do.

Throughout the specification of the present application, when a member is said to be located “on” another member, this includes not only the case where the member is in contact with the other member, but also the case where another member exists between the two members.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the attached drawings.

As shown, the neuron circuit 100 includes a current providing unit 110, a signal accumulating unit 120, and an ignition unit 130. In the present invention, unlike the prior art, spike signals transmitted from synaptic elements are accumulated in the time domain and ignition is performed.

The current provider 110 provides a current that is adjusted according to one or more spike signals transmitted from a neuron circuit or synapse element connected to the front end of the neuron circuit 100. When the spike signal indicates a positive weight, the current providing unit 110 increases the current and provides it to the signal accumulating unit 120. When the spike signal indicates a negative weight, the current providing unit 110 decreases the current and provides it to the signal accumulating unit 120. to provide.

The signal accumulation unit 120 controls the accumulation state of the spike signal in the time domain using a clock signal whose frequency is adjusted by current. In other words, when the spike signal represents a positive weight, the frequency of the clock signal is increased by an increased current, and when the spike signal represents a negative weight, the frequency of the clock signal is decreased by a reduced current. It is possible to control the accumulation state of the spike signal through this. In other words, as more spike signals with positive weights are received, the frequency of the clock signal increases, allowing the firing operation to occur faster.

The ignition unit 130 outputs a spike signal when the spike signal is accumulated above the threshold through the signal accumulation unit 120.

The current provider 110 includes a constant current source 112 that supplies current at a preset level and a plurality of

current mirror circuits

114 and 116 connected in parallel to the constant current source 112. Additionally, a plurality of current providing units 110 may be coupled to the signal accumulating unit 120 in parallel.

The constant current source 112 includes a switching element whose one terminal is connected to a high voltage terminal and the other terminal is connected to each of the

current mirror circuits

114 and 116, and whose switching is controlled by a control signal (V _B ). The constant current source 112 supplies current at a preset level in response to the application of the control signal (V _B ).

A spike signal transmitted from the previous neuron circuit, etc. is input to the input unit of each current mirror circuit (114, 116). At this time, the current applied to the input portion of each

current mirror circuit

114 and 116 varies depending on the weight value of the spike signal. That is, when a spike signal with a positive weight is applied, a certain level of current flows, and then the current does not flow or decreases for a certain period of time when the spike signal is received. Additionally, when a spike signal with a negative weight is applied, a certain level of current flows, and then the current flows further or increases for a predetermined period of time when the spike signal is applied.

Meanwhile, due to the current applied to the input portion of each current mirror circuit, the same current is reflected and applied to the output portion of the current mirror circuit that is symmetrical to the current mirror circuit. At this time, the current provided to the output portion of the current mirror circuit is a constant current source (112). ) is supplied by. In addition, the output terminal of the constant current source 112 is also connected to the signal accumulation unit 120, and since the sum of the current provided to each current mirror circuit and the signal accumulation unit 120 to the constant current source 112 is constant, each current mirror If the current applied to the output part of the circuit changes, the current supplied to the signal accumulation unit 120 also changes accordingly.

That is, as shown in the current mirror circuit 114, when the spike signal is a value representing a positive weight, the current applied to the input portion of the current mirror circuit 114 temporarily decreases, and accordingly, the current mirror circuit 114 ) also temporarily decreases, so the current supplied to the first current control oscillator 122 of the signal accumulation unit 120 by the constant current source 112 temporarily increases.

In addition, as shown in the current mirror circuit 116, when the spike signal has a value representing a negative weight, the current applied to the input portion of the current mirror circuit 116 temporarily increases, and accordingly, the current mirror circuit 116 ) also temporarily increases, so the current supplied to the first current control oscillator 122 of the signal accumulation unit 120 by the constant current source 112 temporarily decreases.

In this way, the level of current provided by the current providing unit 110 to the signal accumulating unit 120 varies depending on the weight of the spike signal applied to the plurality of current mirror circuits.

Meanwhile, the current providing unit 110 includes a plurality of switching elements, and NMOS or PMOS elements may be used. Preferably, only NMOS elements can be used as each switching element. A mismatch may occur between PMOS and NMOS, and weight errors may reduce the accuracy of inference, so using NMOS can help improve performance. However, the use of both PMOS and NMOS as the current providing unit 110 is not excluded from the scope of the present invention.

The signal accumulation unit 120 adjusts the accumulation state of the spike signal by adjusting the phase difference between the clock signal, the frequency of which is adjusted by current, and the reference clock signal. At this time, the phase difference between clock signals is used to accumulate spike signals, similar to the membrane potential for accumulating spike signals in the prior art.

A first current control oscillator 122 that generates a clock signal (CLK) whose frequency is adjusted by the current (I _CLK ) provided by the current provider 110 and a reference clock signal (I REF) generated by the reference current (I _REF ) and a second current controlled oscillator 124 that generates REF).

A current controlled oscillator (ICO) outputs a clock signal with a predetermined frequency, and the frequency is controlled by current. That is, the first current control oscillator 122 increases the frequency of the clock signal output as the current value of the current provider 110 increases, and the clock signal output as the current value of the current provider 110 decreases. The frequency of the signal decreases. Meanwhile, the current controlled oscillator may have a structure in which a plurality of inverters are connected in series as shown, but the present invention is not limited thereto.

Meanwhile, the second current control oscillator 124 does not need to be included in all neuron circuits, and can be used by providing the reference clock signal provided by the second current control oscillator 124 to other neuron circuits. That is, some neuron circuits may be implemented with a built-in second current control oscillator 124, and other neuron circuits may be implemented by receiving a reference clock signal from an external circuit. In this case, the increase in area due to the addition of the second current control oscillator 124 can be minimized.

The ignition unit 130 determines whether to generate a spike signal according to the phase difference between the clock signal of the first current control oscillator 122 and the reference clock signal. For this purpose, the ignition unit 130 includes a first counter 131 that counts the number of clocks of the clock signal (CLK) output by the first current control oscillator 122, a reference clock signal (REF) received from the outside, or 2 A second counter 133 that counts the number of clocks of the reference clock signal (REF) output by the current control oscillator 124, and a spike signal based on the output values of the first counter 131 and the second counter 133. It includes a flip-flop 134 that outputs.

In addition, the ignition unit 130 includes a first operator 135 that compares the output of the first counter 131 and the output of the second counter 133 and transfers the difference value to the flip-flop 136. A mux 137 that outputs a value corresponding to the difference value to the second counter 133 according to the output of 135, and a second operator that adds the output of the mux 137 to the output of the second counter 133. It may include (136).

The first counter 131 and the second counter 133 may count the number of clocks of each clock signal in a manner that increases by 1 for each rising edge of each clock signal.

The first operator 135 calculates the difference between the first counter 131 and the second counter 133 and provides the difference to the flip-flop 134. For example, when the difference between the first counter 131 and the second counter 133 becomes 1, a spike signal is ignited through the flip-flop 134. Meanwhile, the result of the first operator 135 is transmitted to the mux 137, and when the difference is 1, the mux 137 transmits 1 corresponding to the difference to the

second operator

136, 2 The value of the counter 133 is increased by 1. Through this process, after the spike signal is ignited, the number of clocks of the first counter 131 and the second counter 133 are made to be the same.

According to this configuration, when the phase difference between the clock of the first current controlled oscillator 122 and the reference clock becomes 2π, the difference between the number of clocks of the first counter 131 and the second counter 133 becomes 1, Accordingly, a spike signal is output. In addition, after the spike signal is output, processing is performed so that the number of clocks of the first counter 131 and the second counter 133 are immediately equal. Through this configuration, ‘reset by subtraction’, which will be explained later, is implemented.

Meanwhile, there may be a case where the number of clocks of the first counter 131 is smaller than the number of clocks of the second counter 133, and in this case, the spike signal is prevented from being fired.

In a conventional neuron circuit, a spike signal is generated when the voltage accumulated at the membrane potential is above the threshold, and a 'reset to zero' mechanism is used to discharge the membrane potential to 0V.

In contrast, the present invention implements 'reset by subtraction' in which only the increased spike signal is subtracted. For this purpose, as described above, when there is a difference in the number of clocks of the first counter 131 and the second counter 133, the first operator 135, the second operator 136, and the mux 137 are used. Thus, a value that can compensate for the difference in the number of clocks is added to the reference clock signal. Through this, the phase difference of each clock or the number of clocks can be accurately subtracted.

As shown, it can be confirmed that a spike signal is generated when the number of pulses of the clock output from the first current control oscillator 122 and the number of pulses of the reference clock differ by 1 (i.e., the phase difference of the pulse is 2π). I was able to.

For example, when LeNet-5 was trained on MNIST and converted to SNN using the ANN-to-SNN conversion tool, the inference accuracy on MNIST was 99.01% (ideal neuron) and 95.69% (conventional voltage domain), respectively. neurons) and 99.02% (time domain neurons of the present invention), confirming that the inference accuracy of the neuron circuit according to the present invention was higher than that of the conventional neuron circuit. This is a result obtained by improving linearity through time domain signal processing according to the present invention.

Additionally, the neuron circuit of the present invention can achieve higher energy efficiency compared to conventional methods.

Meanwhile, in the present invention, 2π (corresponding to 1 difference between the output values of each counter) is used as a threshold to minimize the number of bits of the digital circuit, which has the effect of minimizing power consumption and area. Additionally, energy efficiency can be greatly improved by lowering the supply voltage by configuring the main circuit digitally.

One embodiment of the present invention may also be implemented in the form of a recording medium containing instructions executable by a computer, such as program modules executed by a computer. Computer-readable media can be any available media that can be accessed by a computer and includes both volatile and non-volatile media, removable and non-removable media. Additionally, computer-readable media may include computer storage media. Computer storage media includes both volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data.

Although the methods and systems of the present invention have been described with respect to specific embodiments, some or all of their components or operations may be implemented using a computer system having a general-purpose hardware architecture.

The description of the present application described above is for illustrative purposes, and those skilled in the art will understand that the present application can be easily modified into other specific forms without changing its technical idea or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. For example, each component described as unitary may be implemented in a distributed manner, and similarly, components described as distributed may also be implemented in a combined form.

The scope of the present application is indicated by the claims described below rather than the detailed description above, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present application.

Claims

In neuron circuits,

A current provider that provides a current adjusted according to one or more spike signals;

a first current-controlled oscillator that generates a clock signal whose frequency is adjusted by the current; and

A neuron circuit comprising a firing unit that determines whether to generate a spike signal according to the phase difference between the clock signal of the first current-controlled oscillator and the reference clock signal.
According to paragraph 1,

The current providing unit

A constant current source that supplies a preset level of current and

A plurality of current mirror circuits connected in parallel to the constant current source and receiving the spike signal,

When the spike signal is a value representing a positive weight, the current applied to the input portion of the current mirror circuit temporarily decreases, and thus the current supplied to the first current control oscillator by the constant current source temporarily increases. become,

When the spike signal is a value representing a negative weight, the current applied to the input portion of the current mirror circuit temporarily increases, and accordingly, the current supplied to the first current control oscillator by the constant current source temporarily decreases. It is a neuron circuit.
According to paragraph 1,

The first current control oscillator is a neuron in which the frequency of the clock signal output increases as the current value of the current provider increases, and the frequency of the clock signal output decreases as the current value of the current provider decreases. Circuit.
According to paragraph 1,

The ignition part

A first counter counting the number of clocks of the clock signal output from the first current controlled oscillator, a second counter counting the number of clocks of the reference clock signal, and a spike based on the output values of the first counter and the second counter A neuron circuit that includes a flip-flop that outputs a signal.
According to paragraph 4,

The ignition unit compares the output of the first counter and the output of the second counter and transmits the difference to the flip-flop;

A mux that outputs a value corresponding to the difference value to the second counter according to the output of the first operator, and

A neuron circuit comprising a second operator that adds the output of the mux to the output of the second counter.
According to paragraph 1,

A neuron, wherein the current value of the current provider increases or decreases according to the weight of the spike signal, and the frequency of the clock signal output from the first current control oscillator increases or decreases according to the increase or decrease of the current value. Circuit.
According to paragraph 1,

A neuron circuit further comprising a second current-controlled oscillator that receives a reference current and generates the reference clock signal.
In neuron circuits,

A current provider that provides a current adjusted according to one or more spike signals;

A signal accumulation unit that controls the accumulation state of the spike signal in the time domain using a clock signal whose frequency is adjusted by the current, and

A neuron circuit comprising a firing unit that outputs a spike signal when the spike signal is accumulated above a threshold through the signal accumulation unit.
According to clause 8,

The signal accumulation unit

A neuron circuit that adjusts the accumulation state of the spike signal by adjusting the phase difference between a clock signal whose frequency is adjusted by the current and a reference clock signal.
According to clause 8,

The current providing unit

A constant current source that supplies a preset level of current and

A plurality of current mirror circuits connected in parallel to the constant current source and receiving the spike signal,

When the spike signal is a value representing a positive weight, the current applied to the input portion of the current mirror circuit temporarily decreases, and thus the current supplied to the first current control oscillator by the constant current source temporarily increases. become,

When the spike signal is a value representing a negative weight, the current applied to the input portion of the current mirror circuit temporarily increases, and accordingly, the current supplied to the first current control oscillator by the constant current source temporarily decreases. It is a neuron circuit.
According to clause 8,

The signal accumulation unit

A first current-controlled oscillator that generates a clock signal whose frequency is adjusted by the current,

The ignition part

A neuron circuit that outputs the spike signal when the phase difference between the clock signal of the first current-controlled oscillator and the reference clock signal is greater than or equal to a threshold.
According to clause 8,

As the current value of the current provider increases, the frequency of the output clock signal increases, and as the frequency of the clock signal increases, the accumulation state of the spike signal is processed as increased,

A neuron circuit that processes the frequency of the output clock signal as the current value of the current provider decreases, and the accumulation state of the spike signal decreases as the frequency of the clock signal decreases.
According to clause 8,

The ignition part

A first counter that counts the number of clocks of the clock signal whose frequency is adjusted by the current,

a second counter that counts the number of clocks of the reference clock signal output by the reference current;

A neuron circuit comprising a flip-flop that outputs a spike signal based on the output values of the first counter and the second counter.
According to clause 13,

The ignition unit compares the output of the first counter and the output of the second counter and transmits the difference to the flip-flop;

A mux that outputs a value corresponding to the difference value to the second counter according to the output of the first operator, and

A neuron circuit comprising a second operator that adds the output of the mux to the output of the second counter.
According to clause 11,

The signal accumulation unit further includes a second current-controlled oscillator that receives a reference current and generates the reference clock signal.