WO2023207487A1 - 一种电路走线确定方法及相关设备 - Google Patents

一种电路走线确定方法及相关设备 Download PDF

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Publication number
WO2023207487A1
WO2023207487A1 PCT/CN2023/084681 CN2023084681W WO2023207487A1 WO 2023207487 A1 WO2023207487 A1 WO 2023207487A1 CN 2023084681 W CN2023084681 W CN 2023084681W WO 2023207487 A1 WO2023207487 A1 WO 2023207487A1
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Prior art keywords
information
candidate connection
connection path
candidate
connection paths
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PCT/CN2023/084681
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English (en)
French (fr)
Inventor
唐振韬
开昰雄
王滨
舒琴
黄宇
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华为技术有限公司
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Publication of WO2023207487A1 publication Critical patent/WO2023207487A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00—Computing arrangements using knowledge-based models
    • G06N5/01—Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/04—Constraint-based CAD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]

Definitions

  • the present application relates to the field of circuit layout, and in particular, to a circuit routing determination method and related equipment.
  • the matching wiring between ports and pins in the circuit is one of the important processes of chip design, which is time-consuming and requires inspection. Difficulty, high demand and other characteristics, usually need to rely on the manual experience of chip designers to troubleshoot, manually adjust the corresponding pin matching routing through interactive software, and maximize the improvement under the premise of meeting the pin multi-priority type constraints.
  • the actual number of connections between the I/O unit and the bump is one of the important processes of chip design, which is time-consuming and requires inspection. Difficulty, high demand and other characteristics, usually need to rely on the manual experience of chip designers to troubleshoot, manually adjust the corresponding pin matching routing through interactive software, and maximize the improvement under the premise of meeting the pin multi-priority type constraints.
  • the actual number of connections between the I/O unit and the bump is one of the important processes of chip design, which is time-consuming and requires inspection. Difficulty, high demand and other characteristics, usually need to rely on the manual experience of chip designers to troubleshoot,
  • This application provides a circuit routing determination method that can increase the number of connections during routing matching between ports and pins.
  • this application provides a method for determining circuit wiring.
  • the method includes: obtaining information describing ports and pins, determining multiple candidate connection paths based on the information about ports and pins, and using a machine learning model, Obtain the cost value of each candidate connection path.
  • the cost value is used to indicate the impact of the candidate connection path on the number of total connection paths between multiple ports and multiple pins.
  • the cost value at least one is determined from multiple candidate connection paths.
  • a destination connection path uses a machine learning model to effectively evaluate the cost value of candidate connection paths, and determines the preferred target connection path through the cost value, thereby increasing the number of connections between the ports and pins of the overall chip.
  • the impact of each candidate connection path on the total number of connection paths between multiple ports and multiple pins can be calculated (that is, in the embodiment of the present application cost value), and select the connection path between the port and the pin based on the cost value.
  • the implementation of "according to the first information and the second information” here can be: input the first information and the second information themselves into the machine learning model, or can also be the combination of the first information and the second information.
  • the results obtained by performing certain processing or screening on the two information are input into the machine learning model.
  • the first information of the ports included in each candidate connection path and the second information of the included pins is input into the machine learning model.
  • the cost value is used to indicate the impact of candidate connection paths on the number of total connection paths between multiple ports and multiple pins, since the individual connection paths of the finalized ports and pins do not intersect (e.g., there is A common relay point can be considered as the connection path intersecting). Furthermore, the determination of each connection path will have a certain impact on the selection of connection paths between other ports and pins (connection paths with overlapping paths can no longer be selected).
  • the "influence” here can be understood as: if this candidate connection path is used as the connection path between ports and pins, it will have a positive or negative impact on the number of total connection paths between multiple ports and multiple pins. To influence. Taking the negative impact as an example, the cost value can be expressed as: if this candidate connection path is used as the connection path between ports and pins, it will reduce the number of total connection paths between multiple ports and multiple pins. degree.
  • the machine learning model can output multiple values, and each value can correspond to a candidate connection path.
  • the size of the value can indicate the overall impact on the final result between the port and the pin if the corresponding candidate connection path is adopted.
  • candidate connection path A among the M candidate connection paths
  • the cost value of candidate connection path A is 0.8
  • the cost value of candidate connection path A is 0.2. If candidate connection path A is selected from M candidate connection paths as the connection path between pin A and port A, ultimately multiple ports and the multiple
  • the total number of connection paths between pins is the number A.
  • candidate connection path B is selected from M candidate connection paths as the connection path between pin A and port A, eventually multiple ports and the multiple pins
  • the total number of connection paths between legs is quantity B, and quantity A will be less than quantity B.
  • the influence of quantity is due to the ability given to the machine learning model in the process of training the machine learning model.
  • the port is an input/output I/O unit and the pin is a transfer unit bump.
  • the method further includes: determining at least one target connection path from multiple candidate connection paths according to the cost value; or, sending a cost value to the terminal device, where the cost value is used to instruct the terminal device to select the target connection path from the multiple candidate connection paths. At least one target connection path is determined among the connection paths.
  • the first information may include one or more of location characteristics, functional characteristics, or priority characteristics of the port.
  • the second information may be one or more of the pin's location characteristics, function characteristics or priority characteristics.
  • the position feature can be expressed as the coordinate position of a circuit element (such as a port and a pin).
  • the position feature can be a coordinate position on a 2D plane.
  • the position feature can be a coordinate position in a Cartesian coordinate system. XY coordinates.
  • Positional features can represent the arrangement of circuit components in space. When matching circuit components, the positional characteristics of each component are used as the input of the model. The positional characteristics can be used to ensure that the wiring path cannot match the wiring path. Other components overlap, resulting in accurate trace matching results.
  • functional characteristics may represent functions performed by circuit elements.
  • functions may include signal transmission functions, energy transmission functions, grounding, etc.
  • the functional characteristics of each component are used as the input of the model. The functional characteristics can be used to ensure that both ends of the wiring are components with the same function, thereby obtaining accurate wiring matching results.
  • the priority feature may represent the importance of a circuit element, which may describe The requirements for the number of connections of circuit components are described above. The higher the priority, the higher the importance of the circuit components, and the higher the requirements for the number of connections of the circuit components.
  • circuit elements with different functions may have different priorities, or circuit elements with different functions may have the same priority, or circuit elements with the same function may have different priorities.
  • the priority can be determined based on the function of the circuit element, or specified based on attribute information (such as first information or second information) input to the circuit element.
  • the first information and the second information includes: information according to the candidate connection path; the candidate connection path includes ports and pins at both ends, and at least one relay point through which the candidate connection path passes, The relay point is an intermediate point between adjacent pins; the information of each candidate connection path includes: the first information of the port included in the candidate connection path, the second information of the pin included in the candidate connection path, and Location information of at least one relay point.
  • the information on the multiple candidate connection paths may include information on each of the multiple candidate connection paths. Since each candidate connection path may be composed of a starting point, at least one relay point, and an end point, the information of each candidate connection path may include information about the starting point, location information of at least one relay point, and information about the end point.
  • the starting point may be a port, the information of the starting point may include the first information of the port (for example, the location, function, priority of the port, etc.), the location information of the relay point may include the location of the relay point, the end point may be a pin, and the end point may be a pin.
  • the information may include second information about the pin (for example, the port's location, function, priority, etc.).
  • the path is divided to obtain each relay point.
  • the relay point can be used as the end point of each sub-segment on the path.
  • the location information of the relay point is used as model input to obtain the cost value with each sub-segment as the granularity. , and then a more accurate cost value of the path can be obtained.
  • ports, pins, and relay points can be coded.
  • Each port, each pin, and each relay point can uniquely correspond to a coding result.
  • the corresponding circuit unit can be uniquely determined. (e.g. port, pin, or relay point).
  • Candidate connection paths can be characterized by encoding the resulting sequence.
  • the multiple ports include multiple first ports and multiple second ports, the multiple pins include multiple first pins and multiple second pins, and the multiple first ports and multiple A first pin is used to implement a first function; a plurality of second ports and a plurality of second pins are used to implement a second function, and the first function and the second function are different; the plurality of candidate connection paths include multiple first A plurality of first candidate connection paths formed between the port and the plurality of first pins, and a plurality of second candidate connection paths formed between the plurality of second ports and the plurality of second pins; according to the first information and The second information is to obtain the cost value of each candidate connection path through the machine learning model, including: based on the information of multiple first candidate connection paths and the information of multiple second candidate connection paths, to obtain the cost value of each candidate connection path through the machine learning model.
  • a cost value of the first candidate connection path determining at least one target connection path from a plurality of candidate connection paths according to the cost value, including: according to a cost value of each first candidate connection path, determining from the plurality of first candidate connection paths At least one first target connection path is determined.
  • ports and pins with different functions The importance of pins is different. For some ports and pins with more important functions, a greater number of connections are needed to ensure the performance of the chip. For some ports and pins with relatively important functions, the number of connections is The reduction will have a greater impact on the performance of the chip (compared to less important ports and pins). For some ports and pins with relatively unimportant functions, the reduction in the number of connections will not have a major impact on chip performance. In the embodiment of the present application, the above importance can be described as priority.
  • routing calculations for ports and pins of each priority are performed separately according to the priority level, thereby improving the routing calculation accuracy.
  • high-priority lines are multiple first candidate connection paths
  • low-priority lines are multiple second candidate connection paths.
  • At least two of the multiple first candidate connection paths are The first candidate connection paths may intersect (or may not overlap at all).
  • each second candidate connection path does not intersect with multiple first candidate connection paths.
  • the low-priority lines that intersect with higher-priority candidate connection paths can be removed (that is, intersecting lines), even if If this part of the line is not removed, this part of the line will not be used as the final connection path. Therefore, the embodiment of the present application reduces the size of the solution space by removing low-priority lines that intersect with higher-priority candidate connection paths. , while ensuring the accuracy of routing calculations, while reducing the computational complexity.
  • At least one second candidate connection path may intersect with at least one first candidate connection path among the plurality of first candidate connection paths.
  • At least two second candidate connection paths among the plurality of second candidate connection paths may intersect (or may not overlap at all).
  • the method further includes: outputting a plurality of first initial candidate connection paths formed between the plurality of first ports and the plurality of first pins, and based on analyzing the plurality of first initial candidate connection paths. Modify instructions for at least one first initial candidate connection path to obtain a plurality of first candidate connection paths.
  • the method further includes: outputting at least one first target connection path.
  • the first function or the second function is one of the following: signal transmission, grounding, or power transmission.
  • obtaining the cost value of each candidate connection path through a machine learning model based on the first information and the second information also includes: based on the information of at least one first target connection path and a plurality of second The information of the candidate connection paths is used through the machine learning model to obtain the cost value of each second candidate connection path; based on the cost value, determining at least one target connection path from multiple candidate connection paths also includes: according to each second candidate The cost value of the connection path determines at least one second target connection path from a plurality of second candidate connection paths.
  • the information based on the at least one first target connection path can be understood as: the first information based on the ports included in the at least one first target connection path, and the second information about the pins included in the at least one first target connection path (optionally, it can also be Including the position information of other position points in the candidate connection path) is input into the machine learning model.
  • the information based on the plurality of second candidate connection paths can be understood as: the first information about the ports included in at least one second target connection path, the second information about the included pins (optionally, it can also be Including the position information of other position points in the candidate connection path) is input into the machine learning model.
  • the information of at least one first target connection path and the information of multiple second candidate connection paths can be used as the input of the machine learning model. Since the multiple first candidate connection paths except at least one first target connection Other first candidate connection paths other than the path will no longer be used as connection paths between the first port and the first pin. Therefore, the plurality of first candidate connection paths may not be used except for at least one first target connection path.
  • the other first candidate connection paths are used as the input of the machine learning model, thereby reducing the complexity of the operation while ensuring the accuracy of routing determination.
  • the plurality of candidate connection paths further include at least one third candidate connection path formed between the plurality of second ports and the plurality of second pins, based on the information of the at least one first target connection path and
  • the information of a plurality of second candidate connection paths includes: information based on at least one first target connection path, a plurality of second candidate connection paths, and information on at least one third candidate connection path.
  • first candidate connection paths except at least one first target connection path among the plurality of first candidate connection paths may be Intersecting paths (at least one third candidate connection path) are used as input to the model, which can increase the amount of input information. That is, the information input into the model can more comprehensively describe the characteristics of the ports and pins, and thus obtain more accurate value.
  • the method further includes: outputting a plurality of second initial candidate connection paths formed between the plurality of second ports and the plurality of second pins, and based on analyzing the plurality of second initial candidate connection paths. Modify instructions for at least one second initial candidate connection path to obtain a plurality of second candidate connection paths.
  • the method further includes: outputting at least one second target connection path.
  • any two target connection paths in at least one target connection path do not intersect with each other.
  • the method further includes: obtaining modified at least one first target connection path based on the modification information of the at least one first target connection path; and based on the information of the at least one first target connection path and a plurality of The information of the second candidate connection path includes: the modified information of at least one first target connection path and the information of a plurality of second candidate connection paths.
  • the first information indicates that the priority of the first port is higher than the priority of the second port; or the second information indicates that the priority of the first pin is higher than the priority of the second pin.
  • determining at least one target connection path from multiple candidate connection paths based on the cost value includes: determining at least one target from multiple candidate connection paths based on the cost value through a minimum cost maximum flow algorithm Connection path.
  • this application provides a method for determining circuit routing, which includes:
  • first information of multiple input and output ports of the circuit and second information of multiple transfer unit pins the multiple ports include multiple first ports and multiple second ports, and the multiple pins include multiple third One pin and multiple second pins; multiple first candidate connection paths are formed between multiple first ports and multiple first pins, and multiple first candidate connection paths are formed between multiple second ports and multiple second pins. a second candidate connection path, the first information indicates the location characteristics of the port, and the second information indicates the location characteristics of the pin;
  • At least one second target connection path is determined from the plurality of second candidate connection paths based on the information of the at least one first target connection path and the information of the plurality of second candidate connection paths.
  • the port is an input/output I/O unit and the pin is a transfer unit bump.
  • At least two first candidate connection paths among the plurality of first candidate connection paths intersect; or,
  • Each second candidate connection path does not intersect with multiple first candidate connection paths; or,
  • the method also includes:
  • the method also includes:
  • the first function or the second function is one of the following: signal transmission, grounding, or power transmission.
  • based on the information of at least one first target connection path and a plurality of second candidate connections Path information including:
  • the method also includes:
  • the method also includes:
  • any two connection paths in at least one first target connection path do not intersect each other, and any two connection paths in at least one second target connection path do not intersect each other.
  • the target connection path does not intersect with any of the at least one second target connection path.
  • the method also includes:
  • Information based on at least one first target connection path and information on a plurality of second candidate connection paths includes: information based on modified at least one first target connection path and information on a plurality of second candidate connection paths.
  • this application provides a circuit routing determination device, which includes:
  • An acquisition module is used to acquire first information of multiple ports of the circuit and second information of multiple pins; multiple candidate connection paths are included between the multiple ports and multiple pins; the candidate connection paths are ports and pins. The connecting path between the feet;
  • a cost value determination module configured to obtain the cost value of each candidate connection path through a machine learning model based on the first information and the second information.
  • the cost value indicates the total connection between multiple ports and multiple pins of the candidate connection path. The influence of the number of paths; the cost value is used to determine at least one target connection path from multiple candidate connection paths.
  • This application uses a machine learning model to effectively evaluate the cost value of candidate connection paths, and determines the preferred target connection path through the cost value, thereby increasing the number of connections between the ports and pins of the overall chip.
  • the port is an input/output I/O unit and the pin is a transfer unit bump.
  • the device further includes:
  • a routing determination module configured to determine at least one target connection path from multiple candidate connection paths based on the cost value
  • the sending module is used to send a cost value to the terminal device.
  • the cost value is used to instruct the terminal device to select from multiple candidate connection paths. Determine at least one target connection path in the path.
  • a cost value is used to indicate a negative impact of a candidate connection path on the number of total connection paths between multiple ports and multiple pins;
  • the plurality of candidate connection paths includes multiple sets of candidate connection paths, multiple Each set of candidate connection paths in the set of candidate connection paths corresponds to a pair of ports and pins;
  • Routing determination module specifically used for:
  • the candidate connection path with the lowest cost value is determined as the target connection path from each group of candidate connection paths.
  • the first information also indicates at least one of the following information: the function of the port or the priority of the port;
  • the second information also indicates at least one of the following information: a function of the pin or a priority of the pin.
  • the candidate connection path includes ports and pins at both ends, and at least one relay point through which the candidate connection path passes, where the relay point is an intermediate point between adjacent pins;
  • the method based on the first information and the second information includes:
  • the first information of the ports included in the candidate connection path the second information of the pins included in the candidate connection path, and the location information of the at least one relay point.
  • the multiple ports include multiple first ports and multiple second ports, the multiple pins include multiple first pins and multiple second pins, and the multiple first ports and multiple A first pin is used to implement the first function; a plurality of second ports and a plurality of second pins are used to implement the second function, and the first function and the second function are different;
  • the plurality of candidate connection paths include a plurality of first candidate connection paths formed between a plurality of first ports and a plurality of first pins, and a plurality of third candidate connection paths formed between a plurality of second ports and a plurality of second pins.
  • the cost value determination module is specifically used to: obtain the cost value of each first candidate connection path through a machine learning model based on the information of multiple first candidate connection paths and the information of multiple second candidate connection paths;
  • the wiring determination module is specifically configured to: determine at least one first target connection path from a plurality of first candidate connection paths according to the cost value of each first candidate connection path.
  • At least two first candidate connection paths among the plurality of first candidate connection paths intersect; or,
  • Each second candidate connection path does not intersect with multiple first candidate connection paths; or,
  • the device further includes:
  • An output module is configured to output at least one first target connection path.
  • the output module is also used to:
  • the cost value determination module is also used to: obtain each second candidate connection through a machine learning model based on the information of at least one first target connection path and the information of multiple second candidate connection paths. The cost of the path;
  • the wiring determination module is also configured to determine at least one second target connection path from a plurality of second candidate connection paths according to the cost value of each second candidate connection path.
  • the plurality of candidate connection paths also include at least one third candidate connection path formed between the plurality of second ports and the plurality of second pins, and the cost value determination module is specifically used for:
  • the first function or the second function is one of the following: signal transmission, grounding, or power transmission.
  • the output module is also used to:
  • any two target connection paths in at least one target connection path do not intersect with each other.
  • the output module is also used to:
  • any two target connection paths in at least one target connection path do not intersect with each other.
  • the get module is also used to:
  • Information based on at least one first target connection path and information on a plurality of second candidate connection paths includes: information based on modified at least one first target connection path and information on a plurality of second candidate connection paths.
  • the first information indicates that the priority of the first port is higher than the priority of the second port; or the second information indicates that the priority of the first pin is higher than the priority of the second pin.
  • the wiring determination module is specifically used for:
  • At least one target connection path is determined from multiple candidate connection paths through the minimum cost maximum flow algorithm.
  • this application provides a circuit routing determination device, which includes:
  • An acquisition module is used to acquire first information of multiple input and output ports of the circuit and second information of multiple transfer unit pins; the multiple ports include multiple first ports and multiple second ports, and the multiple pins
  • the pins include a plurality of first pins and a plurality of second pins; a plurality of first candidate connection paths are formed between the plurality of first ports and the plurality of first pins, and the plurality of second ports and the plurality of second pins are Multiple second candidate connection paths are formed between the feet;
  • a routing determination module configured to indicate that the importance of the first port is higher than that of the second port based on the first information and the second information, and based on the information of the plurality of first candidate connection paths and the plurality of second candidate connection paths.
  • Information determining at least one first target connection path from a plurality of first candidate connection paths;
  • At least one second target connection path is determined from the plurality of second candidate connection paths based on the information of the at least one first target connection path and the information of the plurality of second candidate connection paths.
  • the port is an input/output I/O unit and the pin is a transfer unit bump.
  • At least two first candidate connection paths among the plurality of first candidate connection paths intersect; or,
  • Each second candidate connection path does not intersect with multiple first candidate connection paths; or,
  • the device further includes:
  • An output module configured to output a plurality of first initial candidate connection paths formed between the plurality of first ports and the plurality of first pins, and based on at least one first initial candidate connection among the plurality of first initial candidate connection paths.
  • the path modification instruction obtains multiple first candidate connection paths.
  • the device further includes:
  • An output module is configured to output at least one first target connection path.
  • the first function or the second function is one of the following: signal transmission, grounding, power transmission lose.
  • based on the information of at least one first target connection path and the information of a plurality of second candidate connection paths including:
  • the output module is also used to:
  • the output module is also used to:
  • any two connection paths in at least one first target connection path do not intersect each other, and any two connection paths in at least one second target connection path do not intersect each other.
  • the target connection path does not intersect with any of the at least one second target connection path.
  • the get module is also used to:
  • Information based on at least one first target connection path and information on a plurality of second candidate connection paths includes: information based on modified at least one first target connection path and information on a plurality of second candidate connection paths.
  • embodiments of the present application provide a circuit wiring determination device, which may include a memory, a processor, and a bus system, wherein the memory is used to store programs, and the processor is used to execute the program in the memory to execute the above-mentioned step.
  • a circuit wiring determination device which may include a memory, a processor, and a bus system, wherein the memory is used to store programs, and the processor is used to execute the program in the memory to execute the above-mentioned step.
  • embodiments of the present application provide a computer-readable storage medium.
  • a computer program is stored in the computer-readable storage medium. When it is run on a computer, it causes the computer to execute the above-mentioned first aspect and any of its options. method, or the above second aspect and any optional method thereof.
  • embodiments of the present application provide a computer program product including instructions that, when run on a computer, cause the computer to execute the above-mentioned first aspect and any of its optional methods, or the above-mentioned second aspect and any of its optional methods. Any optional method.
  • the present application provides a chip system, which includes a processor and is used to support a circuit routing determination device to implement some or all of the functions involved in the above aspects, for example, sending or processing involved in the above methods. data; or, information.
  • the chip system also includes a memory for saving execution necessary program instructions and data for operating equipment or training equipment.
  • the chip system may be composed of chips, or may include chips and other discrete devices.
  • Figure 1 is a schematic diagram of an application architecture
  • Figure 2 is a schematic diagram of an application architecture
  • Figure 3 is a schematic diagram of an application architecture
  • Figure 4 is a schematic diagram of an application architecture
  • Figure 5a is a schematic diagram of an application architecture
  • Figure 5b is a schematic diagram of an application architecture
  • Figure 6 is a schematic diagram of an application architecture
  • Figure 7a is a schematic diagram of an embodiment of a circuit routing determination method provided by an embodiment of the present application.
  • Figure 7b is a schematic diagram of an embodiment of a circuit routing determination method provided by an embodiment of the present application.
  • Figure 7c is a schematic diagram of an embodiment of a circuit routing determination method provided by an embodiment of the present application.
  • Figure 7d is a schematic diagram of an embodiment of a circuit routing determination method provided by an embodiment of the present application.
  • Figure 7e is a schematic diagram of an embodiment of a circuit routing determination method provided by an embodiment of the present application.
  • Figure 7f is a schematic diagram of an embodiment of a circuit routing determination method provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 9 is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 10a is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 10b is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 11a is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 11b is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 12 is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 13 is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 14 is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 15 is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 16 is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 17 is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 18 is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 19 is a schematic diagram of an interface in an embodiment of the present application.
  • Figure 20 is a schematic diagram of an embodiment of a circuit routing determination method provided by an embodiment of the present application.
  • Figure 21 is a schematic diagram of an embodiment of a circuit routing determination method provided by an embodiment of the present application.
  • Figure 22 is a schematic diagram of an embodiment of a circuit routing determination method provided by an embodiment of the present application.
  • Figure 23 is a schematic diagram of an embodiment of a circuit routing determination device provided by an embodiment of the present application.
  • Figure 24 is a schematic diagram of an embodiment of a circuit routing determination device provided by an embodiment of the present application.
  • Figure 25 is a schematic structural diagram of an execution device provided by an embodiment of the present application.
  • Figure 26 is a schematic structural diagram of a server provided by an embodiment of the present application.
  • Figure 27 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • the terms “substantially”, “about” and similar terms are used as terms of approximation, not as terms of degree, and are intended to take into account measurements or values that would be known to one of ordinary skill in the art. The inherent bias in calculated values.
  • the use of “may” when describing embodiments of the present invention refers to “one or more possible embodiments.”
  • the terms “use”, “using”, and “used” may be deemed to be the same as the terms “utilize”, “utilizing”, and “utilize”, respectively. Synonymous with “utilized”.
  • the term “exemplary” is intended to refer to an example or illustration.
  • This application can be, but is not limited to, applied in circuit design applications or cloud services provided by cloud-side servers. Next, we will introduce them respectively:
  • the product form of the embodiment of the present application may be a circuit design application, such as a chip design application, or specifically, electronic design automation (EDA) software.
  • EDA can run on terminal devices or cloud-side servers.
  • EDA can realize the task of automatically connecting the pins of the circuit, wherein EDA can generate the circuit layout in response to the input circuit parameters (for example, the circuit can be expressed in the form of a circuit schematic diagram layout).
  • the circuit parameters may be information about the pin units, and the generated circuit schematic diagram or circuit layout may include the connection relationship between the pin units.
  • the schematic may optionally be processed by an electronic design automation (EDA) software system (e.g., transistor schematic and layout editing tools (e.g., Mentor or )) to generate layout and perform layout versus schematic (LVS) and/or design rule check (DRC), and the schematics can be sent to a fabrication facility (e.g., semiconductor fabrication or "FAB") to, for example, produce an integrated circuit (e.g., a chip) with the desired properties .
  • a fabrication facility e.g., semiconductor fabrication or "FAB”
  • FAB design rule check
  • analog circuit design professionals can spend a lot of time and effort designing schematic diagrams for analog integrated circuits.
  • systems and methods using the techniques described herein can generate circuits for electronic circuits (e.g., complete chip) schematic diagram.
  • the port in the embodiment of the present application may be an input/output (I/O) unit, and the pin may be a transfer unit bump.
  • I/O input/output
  • the pin may be a transfer unit bump.
  • the I/O unit can be located in the edge area of the circuit (such as a chip).
  • the I/O unit can be responsible for connecting to external components.
  • the I/O unit can be used for data exchange, energy transfer, etc. with external components. Functional port.
  • the transfer unit can also be called a wafer, bump or bump. It is located in the internal area of the circuit (such as a chip).
  • the bump can be connected to the I/O unit and exchange data with the I/O unit. Energy transfer etc.
  • connection between the I/O unit and the bump is one of the important processes of circuit design. In order to improve the performance of the circuit itself, it is necessary to maximize the number of I/O-bump connections.
  • Figure 1 is a schematic diagram of the functional architecture of a circuit design application in an embodiment of the present application:
  • embodiments of the present application include a system (such as a circuit design application) that can automatically generate circuit schematic diagrams based on input parameters, where inputting different parameter values into the system can cause different circuit schematic diagrams to be automatically generated.
  • the circuit design application 102 can receive input parameters 101 and generate a circuit schematic diagram 103 .
  • Circuit design application 102 may be executed, for example, on at least one computer system, and includes computer code that, when executed by one or more computers, causes the computers to perform operations described herein. The circuit routing determination method.
  • parameters may include text specifying a circuit component (e.g., "I/O unit,” “bump”) or, for example, be used to uniquely determine which circuit component applies to the corresponding circuit component.
  • IDs identifiers
  • Parameters can be used to describe characteristics of circuit components (e.g., “I/O unit”, “bump”), such as location characteristics, functional characteristics, and priority characteristics (the above three characteristics will be described in subsequent embodiments and will not be repeated here. (no more details).
  • the circuit design application may include a machine learning model, and a connection algorithm (such as the minimum cost maximum flow algorithm in the embodiment of the present application).
  • a connection algorithm such as the minimum cost maximum flow algorithm in the embodiment of the present application.
  • the I/O unit information and bump information can be input into the machine learning model to obtain the cost value of each candidate connection path, and then the wiring design results can be obtained and output through the connection algorithm based on the cost value ( For example, circuit diagram).
  • routing design results may be sent to a manufacturing facility to, for example, produce integrated circuits (eg, chips) with desired properties.
  • integrated circuits eg, chips
  • the circuit design software can run on a terminal device on the end side or in a server on the cloud side.
  • the terminal device may be installed with circuit design software, and actions including data input, data processing (such as the circuit routing determination method in the embodiment of the present application), and data output may be performed by the terminal device.
  • actions including data input, data processing (such as the circuit routing determination method in the embodiment of the present application), and data output may be performed by the terminal device.
  • the terminal device can be installed with a client of circuit design software. Actions including data input and data output can be performed by the terminal device, and actions of data processing (such as the circuit routing determination method in the embodiment of the present application) can be It is executed by the server on the cloud side, that is to say, the terminal device can transmit the data required for data processing (such as the circuit routing determination method in the embodiment of this application) to the server on the cloud side. After the execution, the server on the cloud side After the data processing action, the data processing results can be returned to the terminal device on the end side, and the terminal device outputs based on the processing results.
  • actions of data processing such as the circuit routing determination method in the embodiment of the present application
  • the server on the cloud side After the execution, the server on the cloud side After the data processing action, the data processing results can be returned to the terminal device on the end side, and the terminal device outputs based on the processing results.
  • Figure 4 is a schematic diagram of the physical architecture of running a circuit design application in an embodiment of the present application:
  • FIG. 4 shows a schematic diagram of a system architecture.
  • the system may include a terminal 100 and a server 200.
  • the server 200 may include one or more servers (one server is used as an example for illustration in FIG. 4 ), and the server 200 may provide circuit wiring services for one or more terminals.
  • the terminal 100 can be installed with a circuit design application, or open a web page related to circuit design.
  • the above application program and web page can provide a circuit design interface, and the terminal 100 can receive user input on the circuit design interface.
  • Relevant parameters are sent to the server 200.
  • the server 200 can obtain the processing results based on the received parameters and return the processing results to the terminal 100.
  • the terminal 100 can also complete the action of obtaining data processing results based on the received parameters by itself without requiring the cooperation of the server, which is not limited by the embodiments of this application.
  • the terminal 100 in the embodiment of the present application can be a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (AR)/virtual reality (VR) device, a notebook computer, or an ultra mobile personal computer (ultra mobile personal computer).
  • - mobile personal computer UMPC
  • netbook personal digital assistant
  • PDA personal digital assistant
  • Figure 5a shows an optional hardware structure diagram of the terminal 100.
  • the terminal 100 may include a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), Microphone 162 (optional), processor 170, external interface 180, power supply 190 and other components.
  • a radio frequency unit 110 may include a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), Microphone 162 (optional), processor 170, external interface 180, power supply 190 and other components.
  • Figure 5a is only an example of a terminal or a multi-function device, and does not constitute a limitation to the terminal or multi-function device. It may include more or fewer components than shown in the figure, or combine certain components. Or different parts.
  • the input unit 130 may be used to receive input numeric or character information and generate key signal input related to user settings and function control of the portable multi-function device.
  • the input unit 130 may include a touch screen 131 (optional) and/or other input devices 132.
  • the touch screen 131 can collect the user's touch operations on or near it (such as the user's operations on or near the touch screen using fingers, knuckles, stylus, or any other suitable objects), and drive the corresponding according to the preset program. Connect the device.
  • the touch screen can detect the user's touch action on the touch screen, convert the touch action into a touch signal and send it to the processor 170, and can receive and execute commands from the processor 170; the touch signal at least includes contact point coordinate information.
  • the touch screen 131 can provide an input interface and an output interface between the terminal 100 and the user.
  • touch screens can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave.
  • the input unit 130 may also include other input devices. Specifically, other input settings
  • the device 132 may include, but is not limited to, one or more of a physical keyboard, function keys (such as the volume control button 132, the switch button 133, etc.), a trackball, a mouse, a joystick, etc.
  • the input device 132 can receive parameters related to the circuit routing design, such as the first information of the I/O unit in the embodiment of the present application, the second information of the bump, modification instructions for candidate connection paths, and so on.
  • the display unit 140 may be used to display information input by the user or information provided to the user, various menus of the terminal 100, interactive interfaces, file display, and/or playback of any kind of multimedia files.
  • the display unit 140 may be used to display the interface of a circuit design application, wiring design results, diagrams of candidate connection paths, etc.
  • the memory 120 can be used to store instructions and data.
  • the memory 120 can mainly include a storage instruction area and a storage data area.
  • the storage data area can store various data, such as multimedia files, text, etc.;
  • the storage instruction area can store operating systems, applications, at least Software units such as instructions required for a function, or their subsets or extensions.
  • Non-volatile random access memory may also be included; providing the processor 170 with management of hardware, software and data resources in the computing processing device and supporting control software and applications. It is also used for storage of multimedia files, as well as storage of running programs and applications.
  • the processor 170 is the control center of the terminal 100. It uses various interfaces and lines to connect various parts of the entire terminal 100, and executes various functions of the terminal 100 by running or executing instructions stored in the memory 120 and calling data stored in the memory 120. functions and process data to provide overall control of the terminal device.
  • the processor 170 may include one or more processing units; preferably, the processor 170 may integrate an application processor and a modem processor, where the application processor mainly processes operating systems, user interfaces, application programs, etc. , the modem processor mainly handles wireless communications. It can be understood that the above-mentioned modem processor may not be integrated into the processor 170 .
  • the processor and memory can be implemented on a single chip, and in some embodiments, they can also be implemented on separate chips.
  • the processor 170 can also be used to generate corresponding operation control signals, send them to corresponding components of the computing processing device, read and process data in the software, especially read and process the data and programs in the memory 120, so that the Each functional module performs a corresponding function, thereby controlling the corresponding components to act according to the instructions.
  • the memory 120 can be used to store software codes related to the circuit routing determination method, and the processor 170 can execute the steps of the circuit routing determination method of the chip, and can also schedule other units (such as the above-mentioned input unit 130 and the display unit 140) to Implement corresponding functions.
  • the radio frequency unit 110 (optional) can be used to send and receive information or receive and send signals during calls. For example, after receiving downlink information from the base station, it is processed by the processor 170; in addition, the designed uplink data is sent to the base station.
  • RF circuits include but are not limited to antennas, at least one amplifier, transceivers, couplers, low noise amplifiers (LNA), duplexers, etc.
  • the radio frequency unit 110 can also communicate with network devices and other devices through wireless communication.
  • the wireless communication can use any communication standard or protocol, including but not limited to Global System of Mobile communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (Code Division) Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), etc.
  • GSM Global System of Mobile communication
  • GPRS General Packet Radio Service
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • LTE Long Term Evolution
  • SMS Short Messaging Service
  • the radio frequency unit 110 can send the chip parameters to the server 200 and receive the wiring design results sent by the server 200.
  • radio frequency unit 110 is optional and can be replaced by other communication interfaces, such as a network port.
  • the terminal 100 also includes a power supply 190 (such as a battery) that supplies power to various components.
  • a power supply 190 such as a battery
  • the power supply can be logically connected to the processor 170 through a power management system, so that functions such as charging, discharging, and power consumption management can be implemented through the power management system.
  • the terminal 100 also includes an external interface 180, which can be a standard Micro USB interface or a multi-pin connector, which can be used to connect the terminal 100 to communicate with other devices, or can be used to connect a charger to charge the terminal 100. .
  • an external interface 180 can be a standard Micro USB interface or a multi-pin connector, which can be used to connect the terminal 100 to communicate with other devices, or can be used to connect a charger to charge the terminal 100.
  • the terminal 100 may also include a flash light, a wireless fidelity (WiFi) module, a Bluetooth module, sensors with different functions, etc., which will not be described again here. Some or all of the methods described below may be applied to the terminal 100 shown in Figure 5a.
  • WiFi wireless fidelity
  • Bluetooth Bluetooth
  • Figure 5b provides a schematic structural diagram of a server 200.
  • the server 200 includes a bus 201, a processor 202, a communication interface 203 and a memory 204.
  • the processor 202, the memory 204 and the communication interface 203 communicate through the bus 201.
  • the bus 201 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in Figure 5b, but it does not mean that there is only one bus or one type of bus.
  • the processor 202 may be a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP) or a digital signal processor (DSP). any one or more of them.
  • CPU central processing unit
  • GPU graphics processing unit
  • MP microprocessor
  • DSP digital signal processor
  • Memory 204 may include volatile memory, such as random access memory (RAM).
  • RAM random access memory
  • the memory 204 may also include non-volatile memory (non-volatile memory), such as read-only memory (ROM), flash memory, mechanical hard drive (hard drive drive, HDD) or solid state drive (solid state drive). ,SSD).
  • ROM read-only memory
  • HDD hard drive drive
  • SSD solid state drive
  • the memory 204 can be used to store software codes related to the circuit routing determination method, and the processor 202 can execute the steps of the circuit routing determination method of the chip, and can also schedule other units to implement corresponding functions.
  • the terminal 100 and the server 200 may be centralized or distributed devices, and the processors (such as the processor 170 and the processor 202) in the terminal 100 and the server 200 may be hardware circuits (such as application specific integrated circuits) application specific integrated circuit (ASIC), field-programmable gate array (FPGA), general-purpose processor, digital signal processing (DSP), microprocessor or microcontroller, etc.), Or a combination of these hardware circuits.
  • the processor can be a hardware system with the function of executing instructions, such as CPU, DSP, etc., or a hardware system without the function of executing instructions, such as ASIC, FPGA, etc., or the above-mentioned processor without the function of executing instructions.
  • circuit routing determination method in the embodiment of the present application involves AI-related operations.
  • the instruction execution architecture of the terminal device and the server is not limited to the processor combined with the memory shown in Figure 5a and Figure 5b architecture.
  • the system architecture provided by the embodiment of the present application will be introduced in detail below with reference to Figure 6 .
  • FIG. 6 is a schematic diagram of the system architecture provided by an embodiment of the present application.
  • system architecture 500 includes execution devices equipment 510, training equipment 520, database 530, client equipment 540, data storage system 550 and data collection system 560.
  • the execution device 510 includes a computing module 511, an I/O interface 512, a preprocessing module 513 and a preprocessing module 514.
  • the target model/rule 501 may be included in the calculation module 511, and the preprocessing module 513 and the preprocessing module 514 are optional.
  • the execution device 510 may be the above-mentioned terminal device or server that runs the circuit design application program.
  • Data collection device 560 is used to collect training samples. Training samples can be I/O unit information, bump information, total number of connections, etc. After collecting the training samples, the data collection device 560 stores the training samples into the database 530 .
  • the training device 520 can maintain the training samples in the database 530 and the neural network to be trained (such as the machine learning model in the embodiment of the present application, etc.) to obtain the target model/rule 501.
  • the training samples maintained in the database 530 are not necessarily collected from the data collection device 560, and may also be received from other devices.
  • the training device 520 may not necessarily train the target model/rules 501 based entirely on the training samples maintained by the database 530. It may also obtain training samples from the cloud or other places for model training. The above description should not be used as a guarantee for this application. Limitations of Examples.
  • the target model/rules 501 trained according to the training device 520 can be applied to different systems or devices, such as the execution device 510 shown in Figure 6.
  • the execution device 510 can be a terminal, such as a mobile phone terminal, a tablet computer, and a notebook.
  • AR augmented reality
  • VR virtual reality
  • the training device 520 can transfer the trained model to the execution device 510 .
  • the execution device 510 is configured with an input/output (I/O) interface 512 for data interaction with external devices.
  • the user can input data to the I/O interface 512 through the client device 540 (such as this The first information of the I/O unit, the second information of the bump, etc. in the application embodiment).
  • the preprocessing module 513 and the preprocessing module 514 are used to perform preprocessing according to the input data received by the I/O interface 512. It should be understood that there may be no preprocessing module 513 and 514 or only one preprocessing module. When the preprocessing module 513 and the preprocessing module 514 do not exist, the computing module 511 can be directly used to process the input data.
  • the execution device 510 When the execution device 510 preprocesses input data, or when the calculation module 511 of the execution device 510 performs calculations and other related processes, the execution device 510 can call data, codes, etc. in the data storage system 550 for corresponding processing. , the data, instructions, etc. obtained by corresponding processing can also be stored in the data storage system 550.
  • the I/O interface 512 provides the processing result (such as the target connection path in the embodiment of the present application) to the client device 540, thereby providing it to the user.
  • the user can manually set the input data, and the "manually set input data" can be operated through the interface provided by the I/O interface 512 .
  • the client device 540 can automatically send input data to the I/O interface 512. If requiring the client device 540 to automatically send the input data requires the user's authorization, the user can set corresponding permissions in the client device 540.
  • the user can view the results output by the execution device 510 on the client device 540, and the specific presentation form may be display, sound, action, etc.
  • the client device 540 can also be used as a data collection terminal to collect the input data of the input I/O interface 512 and the output results of the output I/O interface 512 as new data.
  • the sample data is stored in the database 530.
  • the I/O interface 512 directly uses the input data input to the I/O interface 512 and the output result of the output I/O interface 512 as a new sample as shown in the figure.
  • the data is stored in database 530.
  • Figure 6 is only a schematic diagram of a system architecture provided by an embodiment of the present application.
  • the positional relationship between the devices, devices, modules, etc. shown in the figure does not constitute any limitation.
  • the data The storage system 550 is an external memory relative to the execution device 510. In other cases, the data storage system 550 can also be placed in the execution device 510. It should be understood that the above execution device 510 may be deployed in the client device 540.
  • the computing module 511 of the above-mentioned execution device 520 can obtain the code stored in the data storage system 550 to implement the circuit wiring determination method in the embodiment of the present application.
  • the computing module 511 of the execution device 520 may include hardware circuits (such as application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processing (DSP), microprocessor or microcontroller, etc.), or a combination of these hardware circuits.
  • the training device 520 can be a hardware system with the function of executing instructions, such as a CPU, DSP, etc. , or it is a hardware system that does not have the function of executing instructions, such as ASIC, FPGA, etc., or it is a combination of the above-mentioned hardware system that does not have the function of executing instructions and a hardware system that has the function of executing instructions.
  • the calculation module 511 of the execution device 520 can be a hardware system with the function of executing instructions.
  • the connection relationship prediction method provided by the embodiment of the present application can be a software code stored in the memory.
  • the calculation module 511 of the execution device 520 can obtain the information from the memory. Obtain the software code and execute the acquired software code to implement the circuit routing determination method provided by the embodiment of the present application.
  • the computing module 511 of the execution device 520 can be a combination of a hardware system that does not have the function of executing instructions and a hardware system that has the function of executing instructions. Some steps of the circuit routing determination method provided by the embodiment of the present application can also be performed by the execution device.
  • the computing module 511 of 520 is implemented by a hardware system that does not have the function of executing instructions, which is not limited here.
  • the above-mentioned training device 520 can obtain the code stored in the memory (not shown in Figure 6, which can be integrated with the training device 520 or deployed separately from the training device 520) to implement the model training in the embodiment of the present application. Related steps.
  • the training device 520 may include hardware circuits (such as application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (digital signal processing, DSP, microprocessor or microcontroller, etc.), or a combination of these hardware circuits.
  • ASICs application specific integrated circuits
  • FPGAs field-programmable gate arrays
  • DSP digital signal processors
  • the training device 520 can be a hardware system with the function of executing instructions, such as a CPU, DSP, etc., or a combination of other hardware circuits.
  • a hardware system with the function of executing instructions such as ASIC, FPGA, etc., or a combination of the above-mentioned hardware systems without the function of executing instructions and a hardware system with the function of executing instructions.
  • the training device 520 can be a combination of a hardware system that does not have the function of executing instructions and a hardware system that has the function of executing instructions. Some of the steps related to model training provided by the embodiments of the present application can also be implemented by the training device 520 that does not have the function of executing instructions. It is implemented by the hardware system that executes the instruction function, which is not limited here.
  • the server can provide circuit routing determination services for the terminal side through an application programming interface (API).
  • API application programming interface
  • the terminal device can send relevant parameters (such as I/O unit information, bump information, etc.) to the server through the API provided by the cloud.
  • the server can obtain the processing results based on the received parameters and send the processing results ( For example, the target connection path, etc.) returns to the terminal.
  • the neural network can be composed of neural units.
  • the neural unit can refer to an operation unit that takes xs (ie, input data) and intercept 1 as input.
  • the output of the operation unit can be:
  • s 1, 2,...n, n is a natural number greater than 1
  • Ws is the weight of xs
  • b is the bias of the neural unit.
  • f is the activation function of the neural unit, which is used to introduce nonlinear characteristics into the neural network to convert the input signal in the neural unit into an output signal.
  • the output signal of this activation function can be used as the input of the next convolutional layer, and the activation function can be a sigmoid function.
  • a neural network is a network formed by connecting multiple above-mentioned single neural units together, that is, the output of one neural unit can be the input of another neural unit.
  • the input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field.
  • the local receptive field can be an area composed of several neural units.
  • Deep Neural Network also known as multi-layer neural network
  • DNN Deep Neural Network
  • the neural network inside DNN can be divided into three categories: input layer, hidden layer, and output layer.
  • the first layer is the input layer
  • the last layer is the output layer
  • the layers in between are hidden layers.
  • the layers are fully connected, that is to say, any neuron in the i-th layer must be connected to any neuron in the i+1-th layer.
  • the coefficient from the k-th neuron in layer L-1 to the j-th neuron in layer L is defined as It should be noted that the input layer has no W parameter.
  • deep neural networks In , more hidden layers make the network more capable of depicting complex situations in the real world. Theoretically, a model with more parameters has higher complexity and greater "capacity", which means it can complete more complex learning tasks. Training a deep neural network is the process of learning the weight matrix. The ultimate goal is to obtain the weight matrix of all layers of the trained deep neural network (a weight matrix formed by the vectors W of many layers).
  • a graph is a data structure that includes at least one vertex and at least one edge.
  • the vertices in the graph can be mapped to entities, and the edges in the graph can be mapped to relationships between entities.
  • Graphs can be directed or undirected.
  • the graph can also include other data besides vertices and edges, such as vertex labels and edge labels.
  • each vertex in the graph can represent a user, and each edge in the graph can represent the social relationship between different users.
  • the data of each vertex in the graph is The user's portrait data and the user's behavioral data, such as the user's age, occupation, hobbies, education, etc.
  • each vertex in the graph when applied to product recommendation scenarios, can represent a user or a product, and each edge in the graph can represent the interactive relationship between the user and the product, such as purchase relationship, collection relationship, etc. .
  • each vertex in the graph when applied to financial risk control scenarios, can represent an account number, transaction or fund.
  • the edges in the graph can represent the flow relationship of funds.
  • the loops in the graph can represent circular transfers.
  • each vertex in the graph can represent a network element, such as a router, switch, terminal, etc., and each edge in the graph can represent a different network element. connection relationship between them.
  • GNN is a deep learning method with structural information that can be used to calculate the current state of a node.
  • the information transfer of the graph neural network is carried out according to the given graph structure, and the status of each node can be updated according to the adjacent nodes. Specifically, it can use the neural network as the aggregation function of point information according to the structure diagram of the current node, transfer the information of all adjacent nodes to the current node, and update it in combination with the status of the current node.
  • the output of the graph neural network is the state of all nodes.
  • the convolutional neural network can use the error back propagation (BP) algorithm to modify the size of the parameters in the initial super-resolution model during the training process, so that the reconstruction error loss of the super-resolution model becomes smaller and smaller.
  • BP error back propagation
  • forward propagation of the input signal until the output will produce an error loss
  • the parameters in the initial super-resolution model are updated by back-propagating the error loss information, so that the error loss converges.
  • the backpropagation algorithm is a backpropagation movement dominated by error loss, aiming to obtain the optimal parameters of the super-resolution model, such as the weight matrix.
  • a port is the edge of a circuit (such as a chip) and is used as an interface for communication or energy transfer with peripheral circuits.
  • a pin is a pin with a certain function in a circuit.
  • a pin is a section at the end of a lead. This section and the pad on the circuit board are jointed together to form a solder joint through soldering.
  • the relay point is a logical point defined on the bare board area.
  • the relay point is a point on the connection path between the port and the pin. .
  • the I/O unit can be located in the edge area of the circuit (such as a chip).
  • the I/O unit can be responsible for connecting to external components.
  • the I/O unit can be used as a port for data exchange, energy transfer and other functions with external components.
  • the transfer unit can also be called a wafer, a bump or a bump. It is located in the internal area of the circuit (such as a chip).
  • the bump can be connected to the I/O unit and perform data exchange and energy transfer with the I/O unit. wait.
  • the matching wiring between the ports and pins in the circuit is one of the important processes of chip design. It is time-consuming, difficult to inspect, and has high demand. Usually It is necessary to rely on the manual experience of the chip designer for troubleshooting, manually adjust the corresponding pin matching routing through interactive software, and maximize the connection between the I/O unit and the bump under the premise of meeting the pin multi-priority type constraints. Actual number of connections.
  • analytical methods based on rule construction constraints are commonly used in the industry to deal with automatic chip pin matching and wiring problems, and realize automatic wiring functions based on chip pin types and predefined wiring rules.
  • the analytical method based on rule construction constraints has poor generalization, complex coupling of wiring rules, high computational complexity, and is easy to fall into local extreme solutions, resulting in poor overall performance of circuit wiring.
  • FIG. 7a is a flowchart of a circuit routing determination method provided by an embodiment of the present application.
  • a circuit routing determination method provided by an embodiment of the present application includes:
  • step 701 may be a terminal device or a server.
  • the execution subject of step 701 may be a terminal device or a server.
  • the port is an input/output I/O unit
  • the pin is a transfer unit bump
  • the first information of the multiple ports may be understood as the first information of each port in the multiple ports.
  • the second information of the plurality of pins can be understood as the second information of each of the plurality of pins.
  • the first information may include one or more of location characteristics, functional characteristics, or priority characteristics of the port.
  • the second information may be one or more of the pin's location characteristics, function characteristics or priority characteristics.
  • the position feature can be expressed as the coordinate position of the circuit element.
  • the position feature can be the coordinate position on the 2D plane.
  • the position feature can be the XY coordinate in the Cartesian coordinate system.
  • the first information may include the coordinate location of the port.
  • the second information may include the coordinate location of the pin.
  • functional characteristics may represent functions performed by circuit elements.
  • functions may include signal transmission functions, energy transmission functions, grounding, etc.
  • the first information may include functions implemented by the port.
  • the second information may include the function implemented by the pin.
  • the priority feature can represent the importance of the circuit element, and the importance can describe the requirements of the circuit element for the number of connections. The higher the priority, the higher the importance of the circuit element, and the circuit element has The higher the number of connections required.
  • circuit elements with different functions may have different priorities.
  • a circuit element with a signal transmission function has a higher priority than a circuit element with an energy transmission function
  • a circuit element with an energy transmission function has a higher priority than a circuit element with a grounding function
  • circuit elements with different functions may have the same priority.
  • a circuit element with a signal transmission function has a higher priority than a circuit element with an energy transmission function, and a circuit element with an energy transmission function has the same priority as a circuit element with a grounding function.
  • circuit elements with the same function may have different priorities.
  • one part of a circuit element in a grounding function may have a higher priority than another part of a circuit element in a grounding function.
  • the port information (such as the first information in the embodiment of the present application) and the pin information (such as the third information in the embodiment of the present application) can be input based on the interface of circuit design software (such as EDA). 2 information).
  • the circuit design software can provide a component library of circuit components for selection.
  • the component library can include a variety of circuit units, such as ports and pins.
  • the position characteristics of the pin can be expressed as the coordinate position of the circuit element.
  • the position characteristics can be the coordinate position on the 2D plane.
  • the position characteristics can be the XY coordinates in the Cartesian coordinate system.
  • the first information and the second information can be input in the form of a file, and the file can express the information of the circuit to be routed and designed.
  • the file can include port and pin location characteristics.
  • the first information and the second information can be input in the form of a file, and the file can express the information of the circuit to be routed and designed.
  • This file can include port and pin functional characteristics.
  • the priority of the circuit unit can be selected (for example, priority 1, priority 2 shown in Figure 10a and priority 3, etc.), and place the components in the corresponding positions, so that the priority characteristics of the ports and pins can be obtained.
  • an editing control for a port can be selected and triggered, and the control can edit priorities. For example, priority 1, priority 2, priority 3, etc. shown in Figure 10b can be selected.
  • the first information and the second information can be input in the form of a file, and the file can express the information of the circuit to be routed and designed.
  • This file can include port and pin priority characteristics.
  • multiple candidate connection paths may be included between the multiple ports and the multiple pins, wherein the candidate connection paths are connection paths (feasible connections) between the ports and the pins. path).
  • connection path between the port and the pin can be understood as the two ends of the candidate connection path are the port and the pin respectively.
  • the port and the pin can be connected through the candidate connection path, and the candidate connection path
  • the area passed is the blank area excluding ports and pins, that is, the area not occupied by ports and pins.
  • a group of ports and pins can include one or more candidates.
  • a connection path that is, starting from a port, can be connected to a pin through one or more paths.
  • the finalized target connection path between the port and the pin may be selected from the candidate connection paths.
  • a candidate connection path when determining a candidate connection path, can be formed between ports and pins with the same function.
  • the functional characteristics of the ports and pins indicated by the first information and the second information can be known.
  • the objects forming the candidate connection path that is, the ports and pins with the same functions indicated by the first information and the second information, can be used as the starting point and the end point to form the candidate connection path.
  • candidate connection paths can be formed between ports and pins of the same color shown in Figure 11a.
  • the first information and the second information may indicate location characteristics of the port and the pin.
  • the arrangement of each port and pins can be known based on the location characteristics, and then at least one candidate connection path can be determined based on the spatial arrangement of each port and pins.
  • the number of paths may be retained.
  • the number of paths may be selected to be less than a preset value (for example, The default value is 3, 4, 5, 6, 7) and at least one candidate connection path with a relatively small path length.
  • a preset value for example, The default value is 3, 4, 5, 6, 7
  • relatively close ports and pins can be selected to determine candidate connection paths.
  • At least one candidate connection path between the port and the pin can be realized through interaction with the user.
  • the user can manually input the connection path between the port and the pin on the interface of the circuit design application.
  • the cost value of each candidate connection path through a machine learning model.
  • the cost value is used to indicate the relationship between the candidate connection path and the multiple ports.
  • the influence of the number of total connection paths between the plurality of pins; the cost value is used to determine at least one target connection path from the plurality of candidate connection paths.
  • the execution subject of step 702 may be a server or a terminal device.
  • the terminal device may obtain first information of multiple ports of the circuit and second information of multiple pins, and combine the first information with The second information (for example, information about multiple candidate connection paths obtained based on the first information and the second information) is sent to the server, and the server can obtain, based on the first information and the second information, through a machine learning model. Based on the cost value of each candidate connection path, at least one target connection path is determined from the plurality of candidate connection paths, and at least one target connection path is transmitted back to the terminal device.
  • the second information for example, information about multiple candidate connection paths obtained based on the first information and the second information
  • the terminal device can obtain first information of multiple ports of the circuit and second information of multiple pins, and combine the first information and the second information (for example, based on The information of multiple candidate connection paths obtained from the first information and the second information) is sent to the server.
  • the server can obtain the information of each candidate connection path through a machine learning model based on the first information and the second information.
  • the cost value is sent to the terminal device, and the terminal device can determine at least one target connection path from the plurality of candidate connection paths based on the cost value.
  • the terminal device can obtain first information of multiple ports of the circuit and second information of multiple pins, based on the first information and the second information (for example It can be the information of multiple candidate connection paths obtained based on the first information and the second information).
  • the cost value of each candidate connection path is obtained, and the cost value is sent to the server, and then the server can be based on The cost value is determined, and at least one target connection path is determined from the plurality of candidate connection paths, and the at least one target connection path is transmitted back to the terminal device.
  • the terminal device can obtain first information of multiple ports of the circuit and second information of multiple pins, based on the first information and the second information (for example It can be the information of multiple candidate connection paths obtained based on the first information and the second information), through the machine learning model, obtain the cost value of each candidate connection path, based on the cost value, from the multiple candidate connection paths Determine at least one target connection path in .
  • the server can obtain the first information of multiple ports of the circuit and the second information of multiple pins (which can be sent from the terminal device); for example, the server can obtain multiple Information on candidate connection paths (which may be sent from the terminal device), based on the first information and the second information (for example, it may be information on multiple candidate connection paths obtained based on the first information and the second information) , obtain the cost value of each candidate connection path through the machine learning model, determine at least one target connection path from the multiple candidate connection paths based on the cost value, and transmit at least one target connection path back to the terminal device .
  • the server can obtain the first information of multiple ports of the circuit and the second information of multiple pins (which can be sent from the terminal device); for example, the server can obtain multiple Information on candidate connection paths (which may be sent from the terminal device), based on the first information and the second information (for example, it may be information on multiple candidate connection paths obtained based on the first information and the second information) , obtain the cost value of each candidate connection path through the machine learning model, determine at least one target
  • the candidate connection path may include ports and pins at both ends, and at least one relay point through which the candidate connection path passes.
  • the relay point is a link between adjacent pins.
  • the information of each candidate connection path includes: first information of ports included in the candidate connection path, second information of pins included in the candidate connection path, and at least one of the The location information of the relay point.
  • the information of the plurality of candidate connection paths may include information of each candidate connection path in the plurality of candidate connection paths. Since each candidate connection path may be composed of a starting point, at least one relay point, and an end point, the information of each candidate connection path may include information about the starting point, location information of at least one relay point, and information about the end point.
  • the starting point may be a port, the information of the starting point may include the first information of the port (for example, the location, function, priority of the port, etc.), the end point may be a pin, and the information of the end point may include the second information of the pin (for example, the port location, function, priority, etc.).
  • the candidate connection path between the port and the pin may include a starting point, an ending point, and at least one relay point, where the starting point and the ending point may be: a port and a pin, and the relay point may be an adjacent
  • the location points between pins, and thus the connection path can be represented as a starting point, at least one relay point, and an end point.
  • ports, pins, and relay points can be coded.
  • Each port, each pin, and each relay point can uniquely correspond to a coding result. Based on each coding result, the corresponding circuit unit can be uniquely determined. (e.g. port, pin, or relay point).
  • Candidate connection paths can be characterized by encoding the resulting sequence.
  • the impact of each candidate connection path on the total number of connection paths between multiple ports and the multiple pins can be calculated (that is, the impact of the application The cost value in the embodiment), and the connection path between the port and the pin is selected based on the cost value.
  • the cost value is used to indicate the impact of candidate connection paths on the number of total connection paths between the multiple ports and the multiple pins, since there are no differences between the final connection paths between the ports and the pins. Intersection (for example, connection paths can be considered to intersect when there is a common relay point). Furthermore, the determination of each connection path will have a certain impact on the selection of connection paths between other ports and pins (connection paths with overlapping paths can no longer be selected).
  • the "influence" here can be understood as: if this candidate connection path is adopted as the connection path between the port and the pin, it will have a positive impact on the number of total connection paths between multiple ports and the multiple pins. or negative impact. Taking the negative impact as an example, the cost value can be expressed as: if this candidate connection path is used as the connection path between ports and pins, it will reduce the number of total connection paths between multiple ports and multiple pins. degree.
  • the cost value of each candidate connection path can be obtained through a machine learning model based on the first information and the second information.
  • the machine learning model can be trained to have the ability to obtain the cost value of each candidate connection path based on the information of multiple candidate connection paths.
  • the machine learning model may include a feature extraction network and a task network, where the machine learning model may be a graph neural network model, the feature extraction network may (exemplarily) be a graph embedding network, and multiple The information of the candidate connection path is characterized through the graph neural network model to obtain the feature representation of each node and the feature representation of the edge.
  • the node can correspond to a port, pin unit or relay point in the candidate connection path, and the edge can be a port.
  • the candidate connection path can be expressed as a bipartite graph and input into the feature extraction network in the form of a bipartite graph.
  • the graph embedding representation process can be aggregated using the GraphSAGE method.
  • the aggregation tool The body process is described as: aggregating the adjacent nodes N(v) of each node v ⁇ V to obtain the aggregation vector h N(v) .
  • the aggregation function uses mean pooling, specifically expressed as:
  • mean is the mean pooling function
  • W is the aggregation weight
  • b is the aggregation deviation
  • h u is the hidden state obtained by node u through graph embedding
  • ⁇ is the sigmoid activation function.
  • the feature representation output by the feature extraction network can include connection features of multiple candidate connection paths (such as global connection arrangement features, etc.), and the candidate connection paths can obtain the representation of each candidate connection path through the task network. value.
  • the task network can obtain the cost value of each edge, and then can synthesize the cost values of the edges included in each candidate connection path to obtain the cost value of each candidate connection path.
  • the task network can be a policy network ⁇ ⁇ , and a two-layer fully connected network structure can be used, which is called the decision output layer.
  • the ReLU activation function can be used to act on the decision fully connected layer.
  • Hidden layer Since the decision-making process is a multi-priority sequence decision-making behavior, the decision-making processes cannot influence each other. Define the action corresponding to the i-th priority as a i . According to the Markov decision process, the action in the current priority state is related to the actions at all previous moments. For example, it can be expressed as:
  • the decision output layer of the policy network corresponds to the decision evaluation cost of the feasible path, which can be limited to the range of [0,1] in the continuous domain.
  • reinforcement learning can be used to optimize the graph neural network model, which is mainly divided into two parts: building the graph neural network decision-making model and the Markov decision-making optimization process.
  • the graph neural network model mainly consists of a graph coding model and a policy decision model.
  • the graph coding model consists of a node model, an edge model and a global model.
  • the policy decision model is a two-layer fully connected network; the node model is used for coding. Input node information, the edge model is used to encode the input edge information, and the global model is used to encode global node and edge information.
  • the location, type and priority between the port and the pin are used as the node status, the feasible path and the node adjacency relationship between the port and the pin are used as the edge status, and the two are combined as the decision input status.
  • Action Pass the input state to the graph neural network model, generate a feasible path cost evaluation in the current state, and use the evaluation value as the current decision action.
  • Reward Pass the decision action to the minimum cost maximum flow algorithm to generate the number of connections between ports and pins, and compare the number of connections with the number of connections between ports and pins obtained by the rule-based method based on common strategies Compare to Gain difference as reward.
  • the graph neural network model was updated using the reinforcement learning method.
  • the specific objective function is defined as follows:
  • ⁇ is the policy model parameter
  • s t and a t represent the input state and decision action corresponding to time t
  • ⁇ is the experience replay pool
  • R is the corresponding reward function
  • H is the policy entropy function
  • ⁇ is the equilibrium factor
  • the cold start sampling process can be arbitrarily experienced in the early stage of the model training phase.
  • the experience replay pool D is an empty set. Random uniform sampling is used to generate the evaluation cost corresponding to the feasible path, which is used as the model decision output in the matching routing. Act on the task, generate the original conversion data pair (s t , a t , r t , s t+1 ), and store it in the experience playback pool D.
  • the neural network model is randomly initialized based on the Xavier method, the target network model is constructed to stabilize the model update process, and the target network model parameters are updated through the soft update mechanism.
  • the model training sampling process is entered, and the state representation s t is performed based on the current feasible solution path and the location, type and priority node information between the port and the pin, and the strategy is input into the graph neural network model
  • the cost mean and variance of the edges to be connected are generated.
  • the corresponding cost evaluation value is obtained through Gaussian sampling as the action output a t .
  • the cost evaluation value corresponding to the feasible path is calculated through the minimum cost maximum flow algorithm to obtain the number of connected paths.
  • the number of connected paths is compared with the original The difference in the number of connections between the port and the pin obtained by the regular method is used as the reward signal r t , and the next stage state representation s t+1 after the corresponding connection is obtained. Finally, the converted data pair (s t , a t , r t , s t+1 ) is recorded in the experience playback pool D to form model sampling data.
  • the model training process is performed during the sampling process, and the batch experience data B is obtained by sampling through the experience replay pool D.
  • the Soft Actor-Critic reinforcement learning method is used to further balance the relationship between exploration and utilization, and define the Q target value. for:
  • d t+1 indicates whether the environment is in the terminated state at time t+1.
  • the mean square error loss function is used to update the value network Q ⁇ parameters, defined as:
  • ⁇ is the exploration entropy factor, which is used to balance the update weight between exploration and utilization.
  • the update goal is to maximize the final number of connections between ports and pins, so the final reward signal is simultaneously allocated as the reward for making decisions at each priority level.
  • random experience playback is adopted, and the update target and exploration entropy value are maximized based on the reinforcement learning method, so as to avoid the failure of only pursuing the maximum reward. Falling into local extreme solutions improves model exploration efficiency and generalization performance. Optimize the graph neural network model parameters through the above update method.
  • This application can be based on the graph neural network matching routing decision model of reinforcement learning, taking into account factors such as the position, type and priority of the corresponding pins between all ports and pins, and can solve high-dimensional problems through the graph neural network model.
  • the problem of difficult representation of spatial states Through effective combination with the minimum cost maximum flow, the number of connections of the rule-based method is increased to avoid falling into a local extreme solution.
  • the reinforcement learning method can be used to explore independently in the solution space, reducing human participation and reducing the difficulty of manual design.
  • the cost value of each candidate connection path can represent that the candidate connection path is used as a connection path between a port and a pin, and the cost value between multiple ports and the multiple pins will be The number of total connection paths has a positive or negative impact. Furthermore, for each group of ports and pins, the connection path with the smallest negative impact or the largest positive impact among multiple candidate connection paths can be selected as the target connection path.
  • At least one target connection path may be determined from the plurality of candidate connection paths through a minimum cost maximum flow algorithm (which may also be called a minimum cost maximum flow algorithm).
  • the starting node S and the target node T can be constructed respectively on both sides of the candidate connection path, and correspond to the nodes corresponding to other ports, nodes corresponding to pins, or relay points. nodes are connected.
  • 2+(
  • any two target connection paths in the at least one target connection path do not intersect with each other.
  • Figure 12 is an interface diagram of a circuit design application program according to an embodiment of the present application, in which the information on the input port and pin (such as the first information and the second information in the embodiment of the present application) information), you can click the trigger in the interface to open the control of the routing design operation, and then trigger the circuit design application to perform the routing matching process of the port and pin.
  • the information on the input port and pin such as the first information and the second information in the embodiment of the present application
  • Figure 13 is an interface diagram of a circuit design application program according to an embodiment of the present application, wherein the circuit design application program determines at least one target connection path from the plurality of candidate connection paths. , at least one target connection path can be displayed in the form of a circuit diagram.
  • the importance of ports and pins with different functions is different.
  • a larger number of connections are needed to ensure the performance of the chip.
  • the reduction in the number of connections will have a greater impact on the performance of the chip (compared to less important ports and pins).
  • the reduction in the number of connections will not have a major impact on chip performance.
  • the above importance can be described as priority.
  • routing calculations for ports and pins of each priority are performed separately according to the priority level, thereby improving the routing calculation accuracy.
  • the embodiment of the present application takes multiple priority levels including priority level 1 and priority level 2 as an example for description.
  • priority level 1 can be ports and pins with signal transmission functions
  • priority level 2 can be ports and pins with energy transmission functions
  • priority 1 can be ports and pins with signal transmission functions
  • priority 2 can be ports and pins with grounding functions.
  • priority 1 can be ports and pins that transmit energy
  • priority 2 can be ports and pins with grounding functions.
  • priority 1 can be some ports and pins with grounding function
  • priority 2 can be some ports and pins with grounding function
  • the first information indicates that the importance of the first port is higher than the importance of the second port; or, the second information indicates the importance of the first pin. higher importance than the second pin.
  • the plurality of ports may include a plurality of first ports and a plurality of second ports
  • the plurality of pins may include a plurality of first pins and a plurality of second pins
  • the The plurality of first ports and the plurality of first pins are used to implement a first function
  • the plurality of second ports and the plurality of second pins are used to implement a second function
  • the first function and The second function is different.
  • the priority of the plurality of first ports and the plurality of first pins is priority level 1
  • the priority level of the plurality of second ports and the plurality of second pins is priority level 2
  • the first function and the second function may be the same or different functions.
  • the plurality of candidate connection paths may include a plurality of first candidate connection paths formed between the plurality of first ports and the plurality of first pins, and the plurality of A plurality of second candidate connection paths formed between the second port and the plurality of second pins.
  • the embodiment of the present application reduces the size of the solution space by removing low-priority lines that intersect with higher-priority candidate connection paths. , while ensuring the accuracy of routing calculations, while reducing the computational complexity.
  • At least one second candidate connection path may intersect with at least one first candidate connection path among the plurality of first candidate connection paths. That is to say, when determining the model input, low-priority paths that overlap with high-priority lines are not eliminated.
  • the amount of input information can be increased, that is, the information input into the model can be described more comprehensively. Port and pin characteristics can then be used to obtain a more accurate cost value.
  • the high-priority line as a plurality of first candidate connection paths and the low-priority line as a plurality of second candidate connection paths as an example
  • at least two first candidate connection paths among the plurality of first candidate connection paths may intersect (or may not overlap at all)
  • each second candidate connection path may not intersect with the plurality of first candidate connection paths
  • at least two of the plurality of second candidate connection paths The second candidate connection paths may intersect (or may not overlap at all).
  • FIG. 14 is an interface diagram of a circuit design application program according to an embodiment of the present application, in which the information on the input port and pin (such as the first information and the second information in the embodiment of the present application) information), you can click the trigger in the interface to turn on the control of the priority-based routing design function, thereby triggering the circuit design application to perform the routing matching process of ports and pins.
  • the information on the input port and pin such as the first information and the second information in the embodiment of the present application
  • wiring matching can be performed on multiple high-priority ports and multiple first pins. After obtaining the wiring matching results, multiple low-priority second ports and multiple low-priority pins can be matched. A second pin is used for wiring matching, which will be introduced in detail next:
  • the information of the multiple first candidate connection paths and the multiple second The information of the candidate connection paths is used through the machine learning model to obtain the cost value of each first candidate connection path.
  • the cost value of each first candidate connection path can be used to carry out multiple ports and multiple first connection paths. Selection of target connection paths between pins.
  • At least one target connection path may be determined from the plurality of first candidate connection paths according to the cost value of each first candidate connection path.
  • determining at least one target connection path from the plurality of first candidate connection paths may refer to the description in the above embodiment, and will not be described again here.
  • multiple first candidate connection paths may be automatically determined by the system and obtained through user modification (such as filtering or changing).
  • the system can obtain and output multiple first initial candidate connection paths formed between the multiple first ports and the multiple first pins, and the user can modify the multiple first initial candidate connection paths.
  • the system may receive modification instructions to the plurality of first candidate connection paths, and obtain the plurality of first candidate connection paths based on the modification instructions to the plurality of first candidate connection paths. .
  • FIG. 15 is an interface diagram of a circuit design application according to an embodiment of the present application, in which the user can delete or modify multiple first initial candidate connection paths.
  • FIG. 16 is an interface diagram of a circuit design application program according to an embodiment of the present application, wherein the circuit design application program determines at least one first candidate connection path from the plurality of first candidate connection paths. After the target connection path, at least one first target connection path can be displayed in the form of a circuit diagram.
  • the user can modify the at least one first target connection path based on his own needs, and then the system can receive the at least one first target connection path. Modification information of the connection path, and based on the modification information of the at least one first target connection path, obtain the modified at least one first target connection path.
  • FIG. 17 is an interface diagram of a circuit design application according to an embodiment of the present application, in which the user can modify the paths of multiple first target connection paths.
  • a low-priority matching wiring operation can be performed based on the high-priority wiring matching results.
  • the cost value of each second candidate connection path can be obtained through the machine learning model based on the information of the at least one first target connection path and the information of the plurality of second candidate connection paths, At least one second target connection path is determined from the plurality of second candidate connection paths according to the cost value of each of the second candidate connection paths.
  • the information of the at least one first target connection path and the plurality of second candidates may be The information of the connection path is selected as the input of the machine learning model, because other first candidate connection paths among the plurality of first candidate connection paths except the at least one first target connection path will not be used as the first port and connection paths between the first pins, so other first candidate connection paths among the plurality of first candidate connection paths except the at least one first target connection path may not be used as input to the machine learning model, In turn, the complexity of the operation can be reduced while ensuring the accuracy of the routing.
  • first candidate connection paths except at least one first target connection path among the plurality of first candidate connection paths may be Intersecting paths (at least one third candidate connection path) are used as input to the model, which can increase the amount of input information. That is, the information input into the model can more comprehensively describe the characteristics of the ports and pins, and thus obtain more accurate value.
  • constraints can be set when determining the connection path, and the constraints can specify any two connection paths with the same priority. There is no intersection between them.
  • constraints can be set when determining the connection path, and the constraints can specify any two connection paths with different priorities. There is no intersection between them. For example, after at least one first target connection path is determined, a constraint is set when selecting a second target connection path from a plurality of second candidate connection paths. The constraint may specify that any connection path of the second target connection path is consistent with at least one The first destination connection paths do not intersect each other.
  • constraints can be set on the selection of candidate connection paths, and the constraints can specify candidate connections with different priorities. Paths do not intersect each other.
  • the at least one second target connection path may be output.
  • FIG. 18 is an interface diagram of a circuit design application program according to an embodiment of the present application, wherein the circuit design application program determines at least one second connection path from the plurality of second candidate connection paths. After the target connection path, at least one second target connection path can be displayed in the form of a circuit diagram.
  • Figure 19 is a schematic interface diagram of a circuit design application program according to an embodiment of the present application. After completing the path calculation of the connection path of priority 3, the circuit design application program can use the circuit diagram to form to display priority 3 connection paths.
  • FIG. 20 is a flowchart of the wiring determination method according to the embodiment of the present application.
  • the first information of the I/O unit and the second information of the bump can be used to construct multiple candidate connection paths between the I/O unit and the bump, and be expressed as a bipartite graph and input into the machine learning model, for example It can be input into the graph embedding network of the machine learning model.
  • the feature representation obtained by the graph embedding network can be input into the policy network of the machine learning model to obtain the cost value of each candidate connection path. According to the cost value, it can be obtained through the routing determination algorithm. Target connection path.
  • FIG. 21 is a flowchart of a priority-based wiring determination method according to an embodiment of the present application.
  • the first information of the I/O unit and the second information of the bump can be used to construct the relationship between the I/O unit and the bump.
  • the feature representation obtained by the graph embedding network can be input into the policy network of the machine learning model.
  • the first target connection path can be obtained through the routing determination algorithm according to the cost value
  • the bipartite graph can be updated according to the first target connection path
  • the updated bipartite graph can be Input it into the machine learning model to obtain the cost value of each candidate connection path of priority 2.
  • the second target connection path can be obtained through the routing determination algorithm.
  • An embodiment of the present application provides a method for determining circuit wiring.
  • the method includes: obtaining first information of multiple input and output ports of the circuit and second information of multiple transfer unit pins; the multiple ports and the multiple pins include multiple candidate connection paths; the candidate connection paths are connection paths between ports and pins; according to the first information and the second information, through a machine learning model, Obtain a cost value for each candidate connection path, the cost value is used to indicate the impact of the candidate connection path on the number of total connection paths between the multiple ports and the multiple pins; according to the cost value , determining at least one target connection path from the plurality of candidate connection paths.
  • This application uses a machine learning model to effectively evaluate the cost of candidate connection paths, thereby increasing the number of connections between ports and pins.
  • an embodiment of the present application also provides a method for determining circuit wiring.
  • the method includes:
  • the multiple ports include multiple first ports and multiple second ports
  • the multiple The pins include a plurality of first pins and a plurality of second pins
  • a plurality of first candidate connection paths are formed between the plurality of first ports and the plurality of first pins
  • the plurality of second pins are A plurality of second candidate connection paths are formed between the port and the plurality of second pins;
  • At least one second target connection path is determined from the plurality of second candidate connection paths.
  • the port is an input/output I/O unit
  • the pin is a transfer unit bump
  • At least two first candidate connection paths among the plurality of first candidate connection paths intersect; or,
  • Each of the second candidate connection paths does not intersect with the plurality of first candidate connection paths; or,
  • the method also includes:
  • the method also includes:
  • the at least one first target connection path is output.
  • the first function or the second function is one of the following: signal transmission, grounding, or power transmission.
  • based on the information of at least one first target connection path and the information of a plurality of second candidate connection paths including:
  • the method also includes:
  • the method also includes:
  • any two connection paths in at least one first target connection path do not intersect each other, and any two connection paths in at least one second target connection path do not intersect each other.
  • the target connection path does not intersect with any of the at least one second target connection path.
  • the method also includes:
  • Information based on at least one first target connection path and information on a plurality of second candidate connection paths includes: information based on modified at least one first target connection path and information on a plurality of second candidate connection paths.
  • Figure 23 is a structural representation of a circuit routing determination device provided by an embodiment of the present application.
  • the device 2300 includes:
  • the acquisition module 2301 is used to acquire the first information of multiple ports of the circuit and the second information of multiple pins; multiple candidate connection paths are included between the multiple ports and the multiple pins; Candidate connection paths are those between ports and pins;
  • step 701 For a specific description of the acquisition module 2301, reference may be made to the description of step 701 in the above embodiment, which will not be described again here.
  • the cost value determination module 2302 is configured to obtain the cost value of each candidate connection path based on the first information and the second information through a machine learning model, where the cost value indicates the value of the candidate connection path to the plurality of candidate connection paths. The influence of the number of total connection paths between the ports and the plurality of pins; the cost value is used to determine at least one target connection path from the plurality of candidate connection paths.
  • step 702 For a specific description of the cost value determination module 2302, reference may be made to the description of step 702 in the above embodiment, which will not be described again here.
  • This application uses a machine learning model to effectively evaluate the cost value of candidate connection paths and determine the preferred one through the cost value.
  • Target connection paths to increase the number of connections between the overall ports and pins of the chip.
  • the port is an input/output I/O unit
  • the pin is a transfer unit bump
  • the device further includes:
  • the routing determination module 2303 is configured to determine at least one target connection path from the plurality of candidate connection paths according to the cost value; or,
  • the location information of the relay point of the sending module is used to send the cost value to the terminal device, where the cost value is used to instruct the terminal device to determine at least one target connection path from the plurality of candidate connection paths.
  • the cost value is used to indicate a negative impact of the candidate connection paths on the number of total connection paths between the plurality of ports and the plurality of pins;
  • the plurality of candidate connection paths Comprising a plurality of sets of candidate connection paths, each set of the plurality of candidate connection paths corresponding to a pair of ports and pins;
  • the routing determination module 2303 is specifically used for:
  • the candidate connection path with the lowest cost value is determined as the target connection path from each group of candidate connection paths.
  • the first information also indicates at least one of the following information: the function of the port or the priority of the port;
  • the second information also indicates at least one of the following information: the function of the pin or the priority of the pin.
  • the candidate connection path includes ports and pins at both ends, and at least one relay point through which the candidate connection path passes, and the relay point is the middle between adjacent pins. location point;
  • the method based on the first information and the second information includes:
  • the first information of the ports included in the candidate connection path the second information of the pins included in the candidate connection path, and the location information of the at least one relay point.
  • the plurality of ports include a plurality of first ports and a plurality of second ports
  • the plurality of pins include a plurality of first pins and a plurality of second pins
  • the plurality of The first ports and the plurality of first pins are used to implement a first function
  • the plurality of second ports and the plurality of second pins are used to implement a second function
  • the first function and the plurality of second pins are used to implement a second function.
  • the second function mentioned above is different;
  • the plurality of candidate connection paths include a plurality of first candidate connection paths formed between the plurality of first ports and the plurality of first pins, and the plurality of second ports and the plurality of third pins. Multiple second candidate connection paths formed between the two pins;
  • the cost value determination module 2302 is specifically configured to obtain each of the first candidates through a machine learning model based on the information of the plurality of first candidate connection paths and the information of the plurality of second candidate connection paths. The cost of the connection path;
  • the wiring determination module 2303 is specifically configured to determine at least one first target connection path from the plurality of first candidate connection paths according to the cost value of each first candidate connection path.
  • At least two first candidate connection paths among the plurality of first candidate connection paths intersect; or,
  • Each of the second candidate connection paths does not intersect with the plurality of first candidate connection paths; or,
  • the device further includes:
  • an output module configured to output a plurality of first initial candidate connection paths between the plurality of first ports and the plurality of first pins, and based on at least one of the plurality of first initial candidate connection paths Modify instructions for the first initial candidate connection paths to obtain the plurality of first candidate connection paths.
  • the device further includes:
  • the location information of the relay point of the output module is used to output the at least one first target connection path.
  • the first function or the second function is one of the following: signal transmission, grounding, or power transmission.
  • the cost value determination module 2302 is further configured to: based on the information of the at least one first target connection path and the information of the plurality of second candidate connection paths, use the machine learning to model to obtain the cost value of each second candidate connection path;
  • the wiring determination module 2303 is further configured to determine at least one second target connection path from the plurality of second candidate connection paths according to the cost value of each second candidate connection path.
  • the plurality of first candidate connection paths except the at least one first Other first candidate connection paths other than the target connection path are not used as inputs to the machine learning model.
  • the plurality of candidate connection paths further include at least one third candidate connection path formed between the plurality of second ports and the plurality of second pins, and the cost value determines Module 2302, specifically used for:
  • the information of the at least one first target connection path the information of the plurality of second candidate connection paths and the at least one third candidate connection path.
  • the output module is also used to:
  • Output a plurality of second initial candidate connection paths formed between the plurality of second ports and the plurality of second pins, and obtain the said plurality of second initial candidate connection paths based on modification instructions to the plurality of second initial candidate connection paths.
  • the output module is also used to:
  • the at least one second target connection path is output.
  • any two target connection paths in the at least one target connection path do not intersect with each other.
  • the acquisition module 2301 is also used to:
  • the information based on the at least one first target connection path and the information on the plurality of second candidate connection paths includes: the information based on the modified at least one first target connection path and the plurality of second candidate connection paths. Information about the second candidate connection path.
  • the first information indicates that the priority of the first port is higher than the priority of the second port; or, the second information indicates the priority of the first pin. Higher priority than the second pin.
  • the wiring determination module 2303 is specifically used to:
  • At least one target connection path is determined from the plurality of candidate connection paths through a minimum cost maximum flow algorithm.
  • Figure 24 is a structural representation of a circuit routing determination device provided by an embodiment of the present application.
  • the device 2400 includes:
  • the acquisition module 2401 is used to acquire the first information of multiple input and output ports of the circuit and the second information of multiple transfer unit pins;
  • the multiple ports include multiple first ports and multiple second ports,
  • the plurality of pins include a plurality of first pins and a plurality of second pins; a plurality of first candidate connection paths are formed between the plurality of first ports and the plurality of first pins, and the A plurality of second candidate connection paths are formed between the plurality of second ports and the plurality of second pins;
  • the routing determination module 2402 is configured to indicate, based on the first information and the second information, that the importance of the first port is higher than the importance of the second port, according to the plurality of first candidate connection paths.
  • information and information of a plurality of second candidate connection paths at least one first target connection path is determined from the plurality of first candidate connection paths; according to the information of the at least one first target connection path and a plurality of second connection paths Information on candidate connection paths, determining at least one second target connection path from the plurality of second candidate connection paths.
  • step 2202 For a specific description of the wiring determination module 2402, reference may be made to the description of step 2202 in the above embodiment, which will not be described again here.
  • the port is an input/output I/O unit
  • the pin is a transfer unit bump
  • At least two first candidate connection paths among the plurality of first candidate connection paths intersect; or,
  • Each of the second candidate connection paths does not intersect with the plurality of first candidate connection paths; or,
  • the device further includes:
  • the output module 2403 is configured to output a plurality of first initial candidate connection paths formed between the plurality of first ports and the plurality of first pins, and based on the analysis of the plurality of first initial candidate connection paths. Modify the instruction to obtain the plurality of first candidate connection paths.
  • the device further includes:
  • the output module 2403 is used to output the at least one first target connection path.
  • the first function or the second function is one of the following: signal transmission, grounding, or power transmission.
  • the information based on the at least one first target connection path and the information on a plurality of second candidate connection paths include:
  • a candidate connection path According to the information of the at least one first connection path and the information of a plurality of second candidate connection paths, and not according to other third candidate connection paths among the plurality of first connection paths except the at least one first target connection path. a candidate connection path.
  • the output module 2403 is also used to:
  • Output a plurality of second initial candidate connection paths formed between the plurality of second ports and the plurality of second pins, and obtain the said plurality of second initial candidate connection paths based on modification instructions to the plurality of second initial candidate connection paths.
  • the output module 2403 is also used to:
  • the at least one second target connection path is output.
  • any two connection paths in the at least one first target connection path do not intersect each other, and any two connection paths in the at least one second target connection path do not intersect each other, Each of the first target connection paths does not intersect with any second target connection path in the at least one second target connection path.
  • the acquisition module 2401 is also used to:
  • the information based on the at least one first target connection path and the information on the plurality of second candidate connection paths includes: the information based on the modified at least one first target connection path and the plurality of second candidate connection paths. Information about the second candidate connection path.
  • FIG. 25 is a schematic structural diagram of an execution device provided by an embodiment of the present application.
  • the execution device 2500 can be embodied as a mobile phone, a tablet, a notebook computer, Smart wearable devices, etc. are not limited here.
  • the execution device 2500 includes: a receiver 2501, a transmitter 2502, a processor 2503 and a memory 2504 (the number of processors 2503 in the execution device 2500 can be one or more, one processor is taken as an example in Figure 25) , wherein the processor 2503 may include an application processor 25031 and a communication processor 25032.
  • the receiver 2501, the transmitter 2502, the processor 2503, and the memory 2504 may be connected through a bus or other means.
  • Memory 2504 may include read-only memory and random access memory and provides instructions and data to processor 2503. A portion of memory 2504 may also include non-volatile random access memory (NVRAM).
  • NVRAM non-volatile random access memory
  • the memory 2504 stores processor and operating instructions, executable modules or data structures, or a subset thereof, or an extended set thereof, where the operating instructions may include various operating instructions for implementing various operations.
  • the processor 2503 controls the execution of operations of the device.
  • various components of the execution device are coupled together through a bus system.
  • the bus system may also include a power bus, a control bus, a status signal bus, etc.
  • various buses are called bus systems in the figure.
  • the methods disclosed in the above embodiments of the present application can be applied to the processor 2503 or implemented by the processor 2503.
  • the processor 2503 may be an integrated circuit chip with signal processing capabilities. During the implementation process, each step of the above method can be completed by instructions in the form of hardware integrated logic circuits or software in the processor 2503 .
  • the above-mentioned processor 2503 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, and can further include an application specific integrated circuit (ASIC), a field programmable Gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field-programmable gate array
  • the processor 2503 can implement or execute the embodiment of this application The disclosed methods, steps and logical block diagrams in .
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • the steps of the method disclosed in conjunction with the embodiments of the present application can be directly implemented by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other mature storage media in this field.
  • the storage medium is located in the memory 2504.
  • the processor 2503 reads the information in the memory 2504 and completes the steps of the above method in combination with its hardware.
  • the receiver 2501 may be used to receive input numeric or character information and generate signal inputs related to performing relevant settings and functional controls of the device.
  • the transmitter 2502 can be used to output numeric or character information; the transmitter 2502 can also be used to send instructions to the disk group to modify data in the disk group.
  • the processor 2503 is used to execute the steps of the circuit wiring determination method in the corresponding embodiment of FIG. 7a and FIG. 22 .
  • FIG. 26 is a schematic structural diagram of the server provided by the embodiment of the present application.
  • the server 2600 is implemented by one or more servers.
  • the server 2600 can be configured or There are relatively large differences due to different performance, which may include one or more central processing units (CPU) 2626 (for example, one or more processors) and memory 2632, and one or more storage applications 2642 or data 2644 storage medium 2630 (such as one or more mass storage devices).
  • the memory 2632 and the storage medium 2630 can be short-term storage or persistent storage.
  • the program stored in the storage medium 2630 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the server.
  • the central processor 2626 may be configured to communicate with the storage medium 2630 and execute a series of instruction operations in the storage medium 2630 on the server 2600 .
  • the server 2600 may also include one or more power supplies 2626, one or more wired or wireless network interfaces 2650, one or more input and output interfaces 2658; or, one or more operating systems 2641, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM and so on.
  • operating systems 2641 such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM and so on.
  • the central processor 2626 is used to execute the steps of the circuit wiring determination method in the corresponding embodiments of FIG. 7a and FIG. 22 .
  • An embodiment of the present application also provides a computer program product including computer readable instructions, which when run on a computer causes the computer to perform the steps performed by the foregoing execution device, or causes the computer to perform the steps performed by the foregoing training device. A step of.
  • Embodiments of the present application also provide a computer-readable storage medium.
  • the computer-readable storage medium stores a program for performing signal processing.
  • the program When the program is run on a computer, it causes the computer to perform the steps performed by the aforementioned execution device. , or, causing the computer to perform the steps performed by the aforementioned training device.
  • the execution device, training device or terminal device provided by the embodiment of the present application may specifically be a chip.
  • the chip includes: a processing unit and a communication unit.
  • the processing unit may be, for example, a processor.
  • the communication unit may be, for example, an input/output interface. Pins or circuits, etc.
  • the processing unit can execute the computer execution instructions stored in the storage unit, so that the chip in the execution device executes the circuit wiring determination method described in the above embodiment, or so that the chip in the training device executes the model training related in the above embodiment.
  • the storage unit is a storage unit within the chip, such as a register, cache, etc.
  • the storage unit may also be a memory located outside the chip in the wireless access device.
  • Storage units such as read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (random access memory, RAM), etc.
  • Figure 27 is a structural schematic diagram of a chip provided by an embodiment of the present application.
  • the chip can be represented as a neural network processor NPU 2700.
  • the NPU 2700 serves as a co-processor and is mounted to the main CPU (Host). CPU), tasks are allocated by the Host CPU.
  • the core part of the NPU is the arithmetic circuit 2703.
  • the arithmetic circuit 2703 is controlled by the controller 2704 to extract the matrix data in the memory and perform multiplication operations.
  • the computing circuit 2703 includes multiple processing units (Process Engine, PE).
  • arithmetic circuit 2703 is a two-dimensional systolic array.
  • the arithmetic circuit 2703 may also be a one-dimensional systolic array or other electronic circuit capable of performing mathematical operations such as multiplication and addition.
  • arithmetic circuit 2703 is a general-purpose matrix processor.
  • the arithmetic circuit obtains the corresponding data of matrix B from the weight memory 2702 and caches it on each PE in the arithmetic circuit.
  • the operation circuit takes matrix A data and matrix B from the input memory 2701 to perform matrix operations, and the partial result or final result of the matrix is stored in an accumulator (accumulator) 2708.
  • the unified memory 2706 is used to store input data and output data.
  • the weight data directly passes through the storage unit access controller (Direct Memory Access Controller, DMAC) 2705, and the DMAC is transferred to the weight memory 2702.
  • the input data is also transferred to unified memory 2706 via DMAC.
  • DMAC Direct Memory Access Controller
  • BIU is the Bus Interface Unit, that is, the bus interface unit 2710, which is used for the interaction between the AXI bus and the DMAC and the Instruction Fetch Buffer (IFB) 2709.
  • IFB Instruction Fetch Buffer
  • the bus interface unit 2710 (Bus Interface Unit, BIU for short) is used to fetch the memory 2709 to obtain instructions from the external memory, and is also used for the storage unit access controller 2705 to obtain the original data of the input matrix A or the weight matrix B from the external memory.
  • BIU Bus Interface Unit
  • DMAC is mainly used to transfer the input data in the external memory DDR to the unified memory 2706 or the weight data to the weight memory 2702 or the input data to the input memory 2701 .
  • the vector calculation unit 2707 includes multiple arithmetic processing units, and if necessary, further processes the output of the arithmetic circuit, such as vector multiplication, vector addition, exponential operation, logarithmic operation, size comparison, etc.
  • vector calculation unit 2707 can store the processed output vectors to unified memory 2706 .
  • the vector calculation unit 2707 can apply a linear function; or a nonlinear function to the output of the operation circuit 2703, such as linear interpolation on the feature plane extracted by the convolution layer, or a vector of accumulated values, to generate an activation value.
  • vector calculation unit 2707 generates normalized values, pixel-wise summed values, or both.
  • the processed output vector can be used as an activation input to the arithmetic circuit 2703, such as for use in a subsequent layer in a neural network.
  • the instruction fetch buffer 2709 connected to the controller 2704 is used to store instructions used by the controller 2704;
  • Unified memory 2706, input memory 2701, weight memory 2702 and fetch memory 2709 are all On-Chip memory. External memory is private to the NPU hardware architecture.
  • the processor mentioned in any of the above places can be a general central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of the above programs.
  • the device embodiments described above are only illustrative.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physically separate.
  • the physical unit can be located in one place, or it can be distributed across multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • the connection relationship between modules indicates that there are communication connections between them, which can be specifically implemented as one or more communication buses or signal lines.
  • the present application can be implemented by software plus necessary general hardware. Of course, it can also be implemented by dedicated hardware including dedicated integrated circuits, dedicated CPUs, dedicated memories, Special components, etc. to achieve. In general, all functions performed by computer programs can be easily implemented with corresponding hardware. Moreover, the specific hardware structures used to implement the same function can also be diverse, such as analog circuits, digital circuits or special-purpose circuits. circuit etc. However, for this application, software program implementation is a better implementation in most cases. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence or that contributes to the existing technology.
  • the computer software product is stored in a readable storage medium, such as a computer floppy disk. , U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., including several instructions to cause a computer device (which can be a personal computer, training device, or network device, etc.) to execute the steps described in various embodiments of this application. method.
  • a computer device which can be a personal computer, training device, or network device, etc.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, the computer instructions may be transferred from a website, computer, training device, or data
  • the center transmits to another website site, computer, training equipment or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means.
  • wired such as coaxial cable, optical fiber, digital subscriber line (DSL)
  • wireless such as infrared, wireless, microwave, etc.
  • the computer-readable storage medium may be any available medium that a computer can store, or a data storage device such as a training device or a data center integrated with one or more available media.
  • the available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media (eg, solid state disk (Solid State Disk, SSD)), etc.

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Abstract

一种电路走线确定方法，涉及电路布图领域，方法包括：获取用于描述端口和引脚的信息，根据端口和引脚的信息确定多个候选连接路径，并通过机器学习模型，得到每个候选连接路径的代价值，代价值用于指示候选连接路径对多个端口和多个引脚之间总连接路径的数量的影响，根据代价值，从多个候选连接路径中确定至少一个目标连接路径。本申请通过机器学习模型，有效评估候选连接路径的代价值，通过代价值确定优选的目标连接路径，从而提高电路整体的端口与引脚之间的连接数量。

Description

一种电路走线确定方法及相关设备
本申请要求于2022年4月29日提交中国专利局、申请号为202210469023.1、发明名称为“一种电路走线确定方法及相关设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路布图领域，尤其涉及一种电路走线确定方法及相关设备。
背景技术
电路中的端口和引脚之间的匹配走线，例如输入/输出(input/output，I/O)单元和bump之间的匹配走线是芯片设计的重要流程之一，具有耗时长、检查难、需求量大等特点，通常需要依靠芯片设计师的人工经验进行排查，通过可交互式软件手动调节对应引脚匹配走线，并且在满足引脚多优先级类型约束的前提下最大程度提高I/O单元和bump之间的实际连接数量。
目前，业界常用基于规则构造约束下的解析型方法处理芯片引脚自动匹配走线问题，根据芯片引脚类型和预先定义的走线规则实现自动布线功能。
然而，基于规则构造约束下的解析型方法泛化性不佳、走线规则繁杂耦合，计算复杂度高，并且容易陷入到局部极值解，导致电路走线的整体性能不佳。
发明内容
本申请提供了一种电路走线确定方法，可以提高端口和引脚之间进行走线匹配时的的连接数量。
第一方面，本申请提供了一种电路走线确定方法，方法包括：获取用于描述端口和引脚的信息，根据端口和引脚的信息确定多个候选连接路径，并通过机器学习模型，得到每个候选连接路径的代价值，代价值用于指示候选连接路径对多个端口和多个引脚之间总连接路径的数量的影响，根据代价值，从多个候选连接路径中确定至少一个目标连接路径。本申请通过机器学习模型，有效评估候选连接路径的代价值，通过代价值确定优选的目标连接路径，从而提高芯片整体的端口与引脚之间的连接数量。
在端口和引脚的匹配走线的场景中，需要尽可能的提高端口和引脚之间的连接数量，以便提高芯片的性能。本申请实施例中，为了提高端口和引脚之间的连接数量，可以计算出各个候选连接路径对于多个端口和多个引脚之间总连接路径的数量的影响(也就是本申请实施例中的代价值)，并基于代价值来进行端口和引脚之间连接路径的选择。
应理解，这里的“根据所述第一信息和所述第二信息”的实现可以为：将第一信息和第二信息本身输入到机器学习模型中，还可以为将对第一信息和第二信息进行一定的处理或筛选得到的结果输入到机器学习模型中，例如可以将每个候选连接路径中包括的端口的第一信息、包括的引脚的第二信息(可选的，还可以包括候选连接路径中其他位置点的位置信息)输入到机器学习模型中。
应理解，代价值用于指示候选连接路径对多个端口和多个引脚之间总连接路径的数量的影响，由于最终确定的端口和引脚的各个连接路径之间不相交(例如，存在公共的中继点时可以认为连接路径之间相交)。进而，每条连接路径的确定会对其他端口和引脚之间连接路径的选择造成一定程度的影响(不能再选择存在路径重叠的连接路径)。这里的“影响”可以理解为：若采用了该候选连接路径作为端口和引脚之间的连接路径，会对多个端口和多个引脚之间总连接路径的数量的正向影响或者负向影响。以负向影响为例，代价值可以表示：若采用了该候选连接路径作为端口和引脚之间的连接路径，会对多个端口和多个引脚之间总连接路径的数量造成降低的程度。
应理解，机器学习模型可以输出多个数值，每个数值可以对应一个候选连接路路径，数值的大小可以表征出若采用对应的候选连接路路径，会对最终得到的端口和引脚之间总连接路径的数量所造成的正向影响或者负向影响，在这种情况下，例如，若引脚A和端口A之间包括M个候选连接路径，M个候选连接路径中的候选连接路径A的代价值为0.8，候选连接路径A的代价值为0.2，如果从M个候选连接路径中选择候选连接路径A作为引脚A和端口A之间的连接路径，最终多个端口和所述多个引脚之间总连接路径的数量为数量A，如果从M个候选连接路径中选择候选连接路径B作为引脚A和端口A之间的连接路径，最终多个端口和所述多个引脚之间总连接路径的数量为数量B，数量A会小于数量B。
应理解，之所以机器学习模型可以输出各个候选连接路径的代价值，且代价值还具有上述的含义(指示候选连接路径对所述多个端口和所述多个引脚之间总连接路径的数量的影响)，是因为在对机器学习模型进行训练的过程中，对机器学习模型所赋予的能力。
在一种可能的实现中，端口为输入输出I/O单元，引脚为转接单元bump。
在一种可能的实现中，方法还包括：根据代价值，从多个候选连接路径中确定至少一个目标连接路径；或者，向终端设备发送代价值，代价值用于指示终端设备从多个候选连接路径中确定至少一个目标连接路径。
在一种可能的实现中，第一信息可以包括端口的位置特征、功能特征或者优先级特征中的一种或多种。第二信息可以为引脚的位置特征、功能特征或者优先级特征中的一种或多种。
在一种可能的实现中，位置特征可以表示为电路元件(例如端口以及引脚)的坐标位置，例如位置特征可以为2D平面上的坐标位置，更细节的，位置特征可以为直角坐标系下的XY坐标。位置特征可以表示出电路元件在空间中的排布，在进行电路元件之间的匹配走线时，将各个元件的位置特征作为模型的输入，可以利用位置特征来保证走线的路径上不能与其他元件重叠，进而得到准确的走线匹配结果。
在一种可能的实现中，功能特征可以表示电路元件所实现的功能。例如，功能可以包括信号传输功能、能量传输功能以及接地等。在进行电路元件之间的匹配走线时，将各个元件的功能特征作为模型的输入，可以利用功能特征保证走线两端是相同功能的元件，进而得到准确的走线匹配结果。
在一种可能的实现中，优先级特征可以表示电路元件的重要程度，该重要程度可以描 述电路元件对于连接数量的要求，优先级越高，则电路元件的重要程度越高，则电路元件对于连接数量的要求越高。
在一种可能的实现中，不同功能的电路元件可以具备不同的优先级，或者，不同功能的电路元件可以具备相同的优先级，或者，相同功能的电路元件可以具备不同的优先级。在进行电路元件之间的匹配走线时，输入各个元件的优先级特征，可以利用优先级特征尽可能增加高优先级的元件的走线匹配数量。
在一种可能的实现中，优先级可以基于电路元件的功能确定得到，或者是基于对电路元件输入的属性信息(例如第一信息或第二信息)进行指定。
在一种可能的实现中，根据第一信息和第二信息，包括：根据候选连接路径的信息；候选连接路径包括两端的端口和引脚、以及候选连接路径所经过的至少一个中继点，中继点为相邻引脚之间的中间位置点；每个候选连接路径的信息包括：候选连接路径所包括的端口的第一信息、候选连接路径所包括的引脚的第二信息、以及至少一个中继点的位置信息。
其中，多个候选连接路径的信息可以包括多个候选连接路径中每个候选连接路径的信息。由于每个候选连接路径可以由起点、至少一个中继点以及终点组成，每个候选连接路径的信息可以包括起点的信息、至少一个中继点的位置信息以及终点的信息。起点可以为端口，起点的信息可以包括端口的第一信息(例如，端口的位置、功能、优先级等)，中继点的位置信息可以包括中继点的位置，终点可以为引脚，终点的信息可以包括引脚的第二信息(例如，端口的位置、功能、优先级等)。
本申请实施例中，对路径划分得到各个中继点，中继点可以作为路径上各个子段的端点，将中继点的位置信息作为模型输入，可以得到以各个子段为粒度的代价值，进而可以得到更准确的路径的代价值。
示例性的，可以对端口、引脚以及中继点进行编码，每个端口、每个引脚以及每个中继点可以唯一对应一个编码结果，基于每个编码结果可以唯一确定对应的电路单元(例如端口、引脚或中继点)。通过编码结果的序列可以表征候选连接路径。
在一种可能的实现中，多个端口包括多个第一端口以及多个第二端口，多个引脚包括多个第一引脚以及多个第二引脚，多个第一端口和多个第一引脚用于实现第一功能；多个第二端口和多个第二引脚用于实现第二功能，第一功能和第二功能不同；多个候选连接路径包括多个第一端口和多个第一引脚之间形成的多个第一候选连接路径，以及多个第二端口和多个第二引脚之间形成的多个第二候选连接路径；根据第一信息和第二信息，通过机器学习模型，得到每个候选连接路径的代价值，包括：根据多个第一候选连接路径的信息以及多个第二候选连接路径的信息，通过机器学习模型，得到每个第一候选连接路径的代价值；根据代价值，从多个候选连接路径中确定至少一个目标连接路径，包括：根据每个第一候选连接路径的代价值，从多个第一候选连接路径中确定至少一个第一目标连接路径。
在一种可能的实现中，在进行端口和引脚的匹配走线的场景中，不同功能的端口和引 脚的重要性是不同的，对于一些更为重要功能的端口和引脚来说，需要更多的数量的连接来保证芯片的性能，对于一些功能相对重要的端口和引脚来说，连接数量的减少会对芯片的性能造成较大的影响(相比于重要性较小的端口和引脚来说)。而对于一些功能相对不重要的端口和引脚，连接数量的减少不会对芯片性能造成较大的影响。本申请实施例中可以将上述重要性描述为优先级。
由于多个优先级的存在，若一次性对各个优先级的端口和引脚进行匹配走线，会大大增加机器学习模型运行的复杂度和计算难度，很难保证走线的计算精度，并不能得到较好的走线匹配结果。本申请实施例中，按照优先级的高低，分别进行各个优先级的端口和引脚的走线计算，进而可以提高走线的计算精度。
在一种可能的实现中，以高优先级的线路为多个第一候选连接路径，低优先级的线路为多个第二候选连接路径为例，多个第一候选连接路径中的至少两个第一候选连接路径之间可以相交(也可以完全不重叠)。
在一种可能的实现中，每个第二候选连接路径与多个第一候选连接路径之间不相交。在一种可能的实现中，为了不与高优先级的走线线路产生交叉冲突，可以去除低优先级中与较高优先级的候选连接路径形成交叉的线路(也就是相交的线路)，即使不去除的这部分线路，这部分线路也不会作为最终的连接路径，因此，本申请实施例通过去除低优先级中与较高优先级的候选连接路径形成交叉的线路，减小了解空间大小，在保证了走线计算精准度的同时，降低了运算复杂度。
在一种可能的实现中，至少一个第二候选连接路径可以与多个第一候选连接路径中的至少一个第一候选连接路径之间相交。在确定模型输入时，若不对与高优先级的线路重叠的低优先级的路径进行剔除，可以增加输入信息的数量，也就是输入到模型中的信息可以更全面的描述端口以及引脚的特征，进而可以得到更准确的代价值。
在一种可能的实现中，多个第二候选连接路径中的至少两个第二候选连接路径之间可以相交(也可以完全不重叠)。
在一种可能的实现中，方法还包括：输出多个第一端口和多个第一引脚之间形成的多个第一初始候选连接路径，并基于对多个第一初始候选连接路径中至少一个第一初始候选连接路的修改指令，得到多个第一候选连接路径。
在一种可能的实现中，方法还包括：输出至少一个第一目标连接路径。
在一种可能的实现中，第一功能或第二功能为如下的一种：信号传输、接地、电能传输。
在一种可能的实现中，根据第一信息和第二信息，通过机器学习模型，得到每个候选连接路径的代价值，还包括：根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，通过机器学习模型，得到每个第二候选连接路径的代价值；根据代价值，从多个候选连接路径中确定至少一个目标连接路径，还包括：根据每个第二候选连接路径的代价值，从多个第二候选连接路径中确定至少一个第二目标连接路径。
应理解，根据至少一个第一目标连接路径的信息，可以理解为：根据至少一个第一目标连接路径中包括的端口的第一信息、包括的引脚的第二信息(可选的，还可以包括候选连接路径中其他位置点的位置信息)输入到机器学习模型中。
应理解，根据多个第二候选连接路径的信息，可以理解为：根据至少一个第二目标连接路径中包括的端口的第一信息、包括的引脚的第二信息(可选的，还可以包括候选连接路径中其他位置点的位置信息)输入到机器学习模型中。
在一种可能的实现中，在通过机器学习模型，得到每个第二候选连接路径的代价值时，多个第一候选连接路径中除至少一个第一目标连接路径之外的其他第一候选连接路径不作为机器学习模型的输入。
本申请实施例中，可以将至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息作为机器学习模型的输入，由于多个第一候选连接路径中除至少一个第一目标连接路径之外的其他第一候选连接路径已经不会作为第一端口和第一引脚之间的连接路径，因此可以不将多个第一候选连接路径中除至少一个第一目标连接路径之外的其他第一候选连接路径作为机器学习模型的输入，进而可以在保证走线的确定精度的前提下，降低运算的的复杂度。
在一种可能的实现中，多个候选连接路径还包括多个第二端口和多个第二引脚之间形成的至少一个第三候选连接路径，根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，包括：根据至少一个第一目标连接路径的信息、多个第二候选连接路径以及至少一个第三候选连接路径的信息。
在一种可能的实现中，在进行第二优先级的连接路径确认时，可以将与多个第一候选连接路径中除至少一个第一目标连接路径之外的其他第一候选连接路径之间相交的路径(至少一个第三候选连接路径)作为模型的输入，可以增加输入信息的数量，也就是输入到模型中的信息可以更全面的描述端口以及引脚的特征，进而可以得到更准确的代价值。
在一种可能的实现中，方法还包括：输出多个第二端口和多个第二引脚之间形成的多个第二初始候选连接路径，并基于对多个第二初始候选连接路径中至少一个第二初始候选连接路径的修改指令，得到多个第二候选连接路径。
在一种可能的实现中，方法还包括：输出至少一个第二目标连接路径。
在一种可能的实现中，至少一个目标连接路径中的任意两个目标连接路径之间不相交。
在一种可能的实现中，方法还包括：基于对至少一个第一目标连接路径的修改信息，得到修改后的至少一个第一目标连接路径；根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，包括：根据修改后的至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息。
在一种可能的实现中，第一信息指示第一端口的优先级高于第二端口的优先级；或者，第二信息指示第一引脚的优先级高于第二引脚的优先级。
在一种可能的实现中，根据代价值，从多个候选连接路径中确定至少一个目标连接路径，包括：根据代价值，通过最小代价最大流算法，从多个候选连接路径中确定至少一个目标连接路径。
第二方面，本申请提供了一种电路走线确定方法，方法包括：
获取电路的多个输入输出端口的第一信息、以及多个转接单元引脚的第二信息；多个端口包括多个第一端口以及多个第二端口，多个引脚包括多个第一引脚以及多个第二引脚；多个第一端口和多个第一引脚之间形成多个第一候选连接路径，多个第二端口和多个第二引脚之间形成多个第二候选连接路径，所述第一信息指示端口的位置特征，所述第二信息指示引脚的位置特征；
基于第一信息和第二信息指示第一端口的重要性高于第二端口的重要性，根据多个第一候选连接路径的信息以及多个第二候选连接路径的信息，从多个第一候选连接路径中确定至少一个第一目标连接路径；
根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，从多个第二候选连接路径中确定至少一个第二目标连接路径。
在一种可能的实现中，端口为输入输出I/O单元，引脚为转接单元bump。
在一种可能的实现中，多个第一候选连接路径中的至少两个第一候选连接路径之间相交；或者，
每个第二候选连接路径与多个第一候选连接路径之间不相交；或者，
至少一个第二候选连接路径与多个第一候选连接路径中的至少一个第一候选连接路径之间相交；或者，
多个第二候选连接路径中的至少两个第二候选连接路径之间相交。
在一种可能的实现中，方法还包括：
输出多个第一端口和多个第一引脚之间形成的多个第一初始候选连接路径，并基于对多个第一初始候选连接路径中至少一个第一初始候选连接路径的修改指令，得到多个第一候选连接路径。
在一种可能的实现中，方法还包括：
输出至少一个第一目标连接路径。
在一种可能的实现中，第一功能或第二功能为如下的一种：信号传输、接地、电能传输。
在一种可能的实现中，根据至少一个第一目标连接路径的信息以及多个第二候选连接 路径的信息，包括：
根据至少一个第一连接路径的信息以及多个第二候选连接路径的信息、且不根据多个第一候选连接路径中除至少一个第一目标连接路径之外的其他第一候选连接路径。
在一种可能的实现中，方法还包括：
输出多个第二端口和多个第二引脚之间形成的多个第二初始候选连接路径，并基于对多个第二初始候选连接路径中至少一个第二初始候选连接路径的修改指令，得到多个第二候选连接路径。
在一种可能的实现中，方法还包括：
输出至少一个第二目标连接路径。
在一种可能的实现中，至少一个第一目标连接路径中的任意两个连接路径之间不相交，至少一个第二目标连接路径中的任意两个连接路径之间不相交，每个第一目标连接路径与至少一个第二目标连接路径中的任意第二目标连接路径之间不相交。
在一种可能的实现中，方法还包括：
基于对至少一个第一目标连接路径的修改信息，得到修改后的至少一个第一目标连接路径；
根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，包括：根据修改后的至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息。
第三方面，本申请提供了一种电路走线确定装置，装置包括：
获取模块，用于获取电路的多个端口的第一信息、以及多个引脚的第二信息；多个端口和多个引脚之间包括多个候选连接路径；候选连接路径为端口和引脚之间的连接路径；
代价值确定模块，用于根据第一信息和第二信息，通过机器学习模型，得到每个候选连接路径的代价值，代价值指示候选连接路径对多个端口和多个引脚之间总连接路径的数量的影响；代价值用于从多个候选连接路径中确定至少一个目标连接路径。
本申请通过机器学习模型，有效评估候选连接路径的代价值，通过代价值确定优选的目标连接路径，从而提高芯片整体的端口与引脚之间的连接数量。
在一种可能的实现中，端口为输入输出I/O单元，引脚为转接单元bump。
在一种可能的实现中，装置还包括：
走线确定模块，用于根据代价值，从多个候选连接路径中确定至少一个目标连接路径；或者，
发送模块，用于向终端设备发送代价值，代价值用于指示终端设备从多个候选连接路 径中确定至少一个目标连接路径。
在一种可能的实现中，代价值用于指示候选连接路径对多个端口和多个引脚之间总连接路径的数量的负向影响；多个候选连接路径包括多组候选连接路径，多组候选连接路径中的每组候选连接路径对应于一对端口和引脚；
走线确定模块，具体用于：
根据代价值，从每组候选连接路径中确定代价值最低的候选连接路径为目标连接路径。
在一种可能的实现中，第一信息还指示如下信息的至少一种：端口的功能或端口的优先级；
第二信息还指示如下信息的至少一种：引脚的功能或引脚的优先级。
在一种可能的实现中，候选连接路径包括两端的端口和引脚、以及候选连接路径所经过的至少一个中继点，中继点为相邻引脚之间的中间位置点；
所述根据所述第一信息和所述第二信息，包括：
根据所述候选连接路径所包括的端口的第一信息、所述候选连接路径所包括的引脚的第二信息、以及所述至少一个中继点的位置信息。
在一种可能的实现中，多个端口包括多个第一端口以及多个第二端口，多个引脚包括多个第一引脚以及多个第二引脚，多个第一端口和多个第一引脚用于实现第一功能；多个第二端口和多个第二引脚用于实现第二功能，第一功能和第二功能不同；
多个候选连接路径包括多个第一端口和多个第一引脚之间形成的多个第一候选连接路径，以及多个第二端口和多个第二引脚之间形成的多个第二候选连接路径；
代价值确定模块，具体用于：根据多个第一候选连接路径的信息以及多个第二候选连接路径的信息，通过机器学习模型，得到每个第一候选连接路径的代价值；
走线确定模块，具体用于：根据每个第一候选连接路径的代价值，从多个第一候选连接路径中确定至少一个第一目标连接路径。
在一种可能的实现中，多个第一候选连接路径中的至少两个第一候选连接路径之间相交；或者，
每个第二候选连接路径与多个第一候选连接路径之间不相交；或者，
至少一个第二候选连接路径与多个第一候选连接路径中的至少一个第一候选连接路径之间相交；或者，
多个第二候选连接路径中的至少两个第二候选连接路径之间相交。
在一种可能的实现中，装置还包括：
输出模块，用于输出至少一个第一目标连接路径。
在一种可能的实现中，输出模块，还用于：
输出多个第一端口和多个第一引脚之间的多个第一初始候选连接路径，并基于对多个第一初始候选连接路径中至少一个第一初始候选连接路径的修改指令，得到多个第一候选连接路径。
在一种可能的实现中，代价值确定模块，还用于：根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，通过机器学习模型，得到每个第二候选连接路径的代价值；
走线确定模块，还用于：根据每个第二候选连接路径的代价值，从多个第二候选连接路径中确定至少一个第二目标连接路径。
在一种可能的实现中，多个候选连接路径还包括多个第二端口和多个第二引脚之间形成的至少一个第三候选连接路径，代价值确定模块，具体用于：
根据至少一个第一目标连接路径的信息、多个第二候选连接路径以及至少一个第三候选连接路径的信息。
在一种可能的实现中，第一功能或第二功能为如下的一种：信号传输、接地、电能传输。
在一种可能的实现中，输出模块，还用于：
输出至少一个第二目标连接路径。
在一种可能的实现中，至少一个目标连接路径中的任意两个目标连接路径之间不相交。
在一种可能的实现中，输出模块，还用于：
输出多个第二端口和多个第二引脚之间形成的多个第二初始候选连接路径，并基于对多个第二初始候选连接路径中至少一个第二初始候选连接路径的修改指令，得到多个第二候选连接路径。
在一种可能的实现中，至少一个目标连接路径中的任意两个目标连接路径之间不相交。
在一种可能的实现中，获取模块，还用于：
基于对至少一个第一目标连接路径的修改信息，得到修改后的至少一个第一目标连接路径；
根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，包括：根据修改后的至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息。
在一种可能的实现中，第一信息指示第一端口的优先级高于第二端口的优先级；或者，第二信息指示第一引脚的优先级高于第二引脚的优先级。
在一种可能的实现中，走线确定模块，具体用于：
根据代价值，通过最小代价最大流算法，从多个候选连接路径中确定至少一个目标连接路径。
第四方面，本申请提供了一种电路走线确定装置，装置包括：
获取模块，用于获取电路的多个输入输出端口的第一信息、以及多个转接单元引脚的第二信息；多个端口包括多个第一端口以及多个第二端口，多个引脚包括多个第一引脚以及多个第二引脚；多个第一端口和多个第一引脚之间形成多个第一候选连接路径，多个第二端口和多个第二引脚之间形成多个第二候选连接路径；
走线确定模块，用于基于第一信息和第二信息指示第一端口的重要性高于第二端口的重要性，根据多个第一候选连接路径的信息以及多个第二候选连接路径的信息，从多个第一候选连接路径中确定至少一个第一目标连接路径；
根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，从多个第二候选连接路径中确定至少一个第二目标连接路径。
在一种可能的实现中，端口为输入输出I/O单元，引脚为转接单元bump。
在一种可能的实现中，多个第一候选连接路径中的至少两个第一候选连接路径之间相交；或者，
每个第二候选连接路径与多个第一候选连接路径之间不相交；或者，
至少一个第二候选连接路径与多个第一候选连接路径中的至少一个第一候选连接路径之间相交；或者，
多个第二候选连接路径中的至少两个第二候选连接路径之间相交。
在一种可能的实现中，装置还包括：
输出模块，用于输出多个第一端口和多个第一引脚之间形成的多个第一初始候选连接路径，并基于对多个第一初始候选连接路径中至少一个第一初始候选连接路径的修改指令，得到多个第一候选连接路径。
在一种可能的实现中，装置还包括：
输出模块，用于输出至少一个第一目标连接路径。
在一种可能的实现中，第一功能或第二功能为如下的一种：信号传输、接地、电能传 输。
在一种可能的实现中，根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，包括：
根据至少一个第一连接路径的信息以及多个第二候选连接路径的信息、且不根据多个第一候选连接路径中除至少一个第一目标连接路径之外的其他第一候选连接路径。
在一种可能的实现中，输出模块，还用于：
输出多个第二端口和多个第二引脚之间形成的多个第二初始候选连接路径，并基于对多个第二初始候选连接路径中至少一个第二初始候选连接路径的修改指令，得到多个第二候选连接路径。
在一种可能的实现中，输出模块，还用于：
输出至少一个第二目标连接路径。
在一种可能的实现中，至少一个第一目标连接路径中的任意两个连接路径之间不相交，至少一个第二目标连接路径中的任意两个连接路径之间不相交，每个第一目标连接路径与至少一个第二目标连接路径中的任意第二目标连接路径之间不相交。
在一种可能的实现中，获取模块，还用于：
基于对至少一个第一目标连接路径的修改信息，得到修改后的至少一个第一目标连接路径；
根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，包括：根据修改后的至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息。
第五方面，本申请实施例提供了一种电路走线确定装置，可以包括存储器、处理器以及总线系统，其中，存储器用于存储程序，处理器用于执行存储器中的程序，以执行如上述第一方面及其任一可选的方法、或者上述第二方面及其任一可选的方法。
第六方面，本申请实施例提供了一种计算机可读存储介质，计算机可读存储介质中存储有计算机程序，当其在计算机上运行时，使得计算机执行上述第一方面及其任一可选的方法、或者上述第二方面及其任一可选的方法。
第七方面，本申请实施例提供了一种包括指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面及其任一可选的方法、或者上述第二方面及其任一可选的方法。
第八方面，本申请提供了一种芯片系统，该芯片系统包括处理器，用于支持电路走线确定装置实现上述方面中所涉及的部分或全部功能，例如，发送或处理上述方法中所涉及的数据；或，信息。在一种可能的设计中，芯片系统还包括存储器，存储器，用于保存执 行设备或训练设备必要的程序指令和数据。该芯片系统，可以由芯片构成，也可以包括芯片和其他分立器件。
附图说明
图1为一种应用架构示意；
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图7a为本申请实施例提供的一种电路走线确定方法的实施例示意；
图7b为本申请实施例提供的一种电路走线确定方法的实施例示意；
图7c为本申请实施例提供的一种电路走线确定方法的实施例示意；
图7d为本申请实施例提供的一种电路走线确定方法的实施例示意；
图7e为本申请实施例提供的一种电路走线确定方法的实施例示意；
图7f为本申请实施例提供的一种电路走线确定方法的实施例示意；
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图20为本申请实施例提供的一种电路走线确定方法的实施例示意；
图21为本申请实施例提供的一种电路走线确定方法的实施例示意；
图22为本申请实施例提供的一种电路走线确定方法的实施例示意；
图23为本申请实施例提供的一种电路走线确定装置的实施例示意；
图24为本申请实施例提供的一种电路走线确定装置的实施例示意；
图25为本申请实施例提供的执行设备的一种结构示意图；
图26是本申请实施例提供的服务器一种结构示意图；
图27为本申请实施例提供的芯片的一种结构示意图。
具体实施方式
下面结合本发明实施例中的附图对本发明实施例进行描述。本发明的实施方式部分使用的术语仅用于对本发明的具体实施例进行解释，而非旨在限定本发明。
下面结合附图，对本申请的实施例进行描述。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的术语在适当情况下可以互换，这仅仅是描述本申请的实施例中对相同属性的对象在描述时所采用的区分方式。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，以便包含一系列单元的过程、方法、系统、产品或设备不必限于那些单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它单元。
应理解，当称一元件或层位于另一元件或层“上(on)”、“连接到(connected to)”或“耦合到(coupledto)”另一元件或层时，所述元件或层可直接位于所述另一元件或层上、直接连接到或直接耦合到所述另一元件或层，抑或可存在一个或多个中间元件或层。还应理解，当称一元件或层位于两个元件或层“之间(between)”时，所述元件或层可为所述两个元件或层之间的唯一元件或层，或者也可存在一个或多个中间元件或层。
本文中所用用语“基本(substantially)”、“大约(about)”及类似用语用作近似用语、而并非用作程度用语，且旨在考虑到所属领域中的普通技术人员将知的测量值或计算值的固有偏差。此外，在阐述本发明实施例时使用“可(may)”是指“可能的一个或多个实施例”。本文中所用用语“使用(use)”、“正使用(using)”、及“被使用(used)”可被视为分别与用语“利用(utilize)”、“正利用(utilizing)”、及“被利用(utilized)”同义。另外，用语“示例性(exemplary)”旨在指代实例或例示。
首先介绍本申请的应用场景，本申请可以但不限于应用在电路设计类应用程序或者云侧服务器提供的云服务等，接下来分别进行介绍：
一、电路设计类应用程序
本申请实施例的产品形态可以为电路设计类应用程序，例如芯片设计类应用程序，又例如，具体可以为电子设计自动化(electronic design automation，EDA)软件。EDA可以运行在终端设备或者云侧的服务器上。
以EDA为例，在一种可能的实现中，EDA可以实现电路的引脚的自动连接的任务，其中，EDA可以响应于输入的电路参数而生成电路布局(例如可以以电路示意图的形式表达电路布局)。在本申请实施例中，电路参数可以为引脚单元的信息，生成的电路示意图或者电路布局可以包括引脚单元之间的连接关系。
示意图可任选地由电子设计自动化(EDA)软件系统(例如晶体管示意图及布局编辑工具(例如，Mentor或))处理以产生布局、执行布局与示意图对照(layout versus schematic，LVS) 及/或设计规则检查(design rule check，DRC)，且可将示意图发送到制造设施(例如，半导体制作或“FAB”)以(举例来说)产生具有所要性质的集成电路(例如，芯片)。通常，可由模拟电路设计专业人员花费大量时间及精力来设计针对模拟集成电路的示意图。有利地，使用本文中所描述的技术的系统及方法可非常快地且用比在使用传统技术来设计每一电路的情况下将需要的时间基本上少的时间生成针对电子电路(例如，完整芯片)的示意图。
其中，本申请实施例中的端口可以为输入/输出(input/output，I/O)单元，引脚可以为转接单元bump。
在一种可能的实现中，I/O单元可以位于电路(例如芯片)的边缘区域，I/O单元可以负责和外部元件连接，I/O单元可以作为与外部元件进行数据交换、能量传递等功能的端口。
其中，转接单元(bump)也可以称之为晶圆、凸点或者凸块，位于电路(例如芯片)的内部区域，bump可以和I/O单元连接，和I/O单元进行数据交换、能量传递等。
其中，I/O单元和bump之间的连接是电路设计的重要流程之一，为了提高电路自身的性能，需要最大程度提高I/O-bump的连接数量。
接下来分别从功能架构以及实现功能的产品架构介绍本申请实施例中的电路设计类应用程序。
参照图1，图1为本申请实施例中电路设计类应用程序的功能架构示意：
在一种可能的实现中，本申请实施例包含能够基于输入参数而自动生成电路示意图的系统(例如电路设计类应用程序)，其中，对系统输入不同的参数值可致使不同电路示意图自动生成。如图1所示，电路设计类应用程序102可接收输入的参数101且产生电路示意图103。电路设计类应用程序102可在(举例来说)至少一个计算机系统上执行，且包括计算机代码，所述计算机代码在由一或多个计算机执行时致使所述计算机执行用于执行本文中所描述的电路走线确定方法。
在一种可能的实现中，参照图2，参数可包含规定电路组件(例如，“I/O单元”、“bump”)的文本或(举例来说)用于唯一地确定应用于对应电路组件的规则集合的一或多个标识符(ID)，例如一或多个代码。参数可以用于描述电路组件(例如，“I/O单元”、“bump”)的特征，例如位置特征、功能特征、优先级特征(上述三种特征将在后续实施例中描述，这里不再赘述)。
在一种可能的实现中，参照图3，电路设计应用程序可以包括机器学习模型、以及连接算法(例如本申请实施例中的最小代价最大流算法)。可选的，可以将I/O单元的信息以及bump的信息输入到机器学习模型中，可以得到各个候选连接路径的代价值，进而可以基于代价值通过连接算法，得到并输出走线设计结果(例如电路示意图)。
例如，可将走线设计结果发送到制造设施以(举例来说)生产具有所要性质的集成电路(例如，芯片)。
在一种可能的实现中，电路类设计软件可以运行在端侧的终端设备或者运行在云侧的服务器中。
例如，终端设备可以安装有电路类设计软件，包括数据输入、数据处理(例如本申请实施例中的电路走线确定方法)以及数据输出的动作可以为终端设备执行的。
例如，终端设备可以安装有电路类设计软件的客户端，包括数据输入以及数据输出的动作可以为终端设备执行的，而数据处理(例如本申请实施例中的电路走线确定方法)的动作可以为云侧的服务器执行的，也就是说，终端设备可以将数据处理(例如本申请实施例中的电路走线确定方法)所需的数据传输到云侧的服务器，云侧的服务器在执行完数据处理动作后，可以将数据处理结果返回至端侧的终端设备，由终端设备基于处理结果进行输出。
接下来介绍本申请实施例中运行电路设计类应用程序的实体架构。
参照图4，图4为本申请实施例中运行电路设计类应用程序的实体架构示意：
参见图4，图4示出了一种系统架构示意图。该系统可以包括终端100、以及服务器200。其中，服务器200可以包括一个或者多个服务器(图4中以包括一个服务器作为示例进行说明)，服务器200可以为一个或者多个终端提供电路走线服务。
其中，终端100上可以安装有电路类设计应用程序，或者打开与电路类设计相关的网页，上述应用程序和网页可以提供一个电路类设计界面，终端100可以接收用户在电路类设计界面上输入的相关参数，并将上述参数发送至服务器200，服务器200可以基于接收到的参数，得到处理结果，并将处理结果返回至至终端100。
应理解，在一些可选的实现中，终端100也可以由自身完成基于接收到的参数，得到数据处理结果的动作，而不需要服务器配合实现，本申请实施例并不限定。
接下来描述图4中终端100的产品形态；
本申请实施例中的终端100可以为手机、平板电脑、可穿戴设备、车载设备、增强现实(augmented reality，AR)/虚拟现实(virtual reality，VR)设备、笔记本电脑、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本、个人数字助理(personal digital assistant，PDA)等，本申请实施例对此不作任何限制。
图5a示出了终端100的一种可选的硬件结构示意图。
参考图5a所示，终端100可以包括射频单元110、存储器120、输入单元130、显示单元140、摄像头150(可选的)、音频电路160(可选的)、扬声器161(可选的)、麦克风162(可选的)、处理器170、外部接口180、电源190等部件。本领域技术人员可以理解，图5a仅仅是终端或多功能设备的举例，并不构成对终端或多功能设备的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件。
输入单元130可用于接收输入的数字或字符信息，以及产生与该便携式多功能装置的用户设置以及功能控制有关的键信号输入。具体地，输入单元130可包括触摸屏131(可选的)和/或其他输入设备132。该触摸屏131可收集用户在其上或附近的触摸操作(比如用户使用手指、关节、触笔等任何适合的物体在触摸屏上或在触摸屏附近的操作)，并根据预先设定的程序驱动相应的连接装置。触摸屏可以检测用户对触摸屏的触摸动作，将该触摸动作转换为触摸信号发送给该处理器170，并能接收该处理器170发来的命令并加以执行；该触摸信号至少包括触点坐标信息。该触摸屏131可以提供该终端100和用户之间的输入界面和输出界面。此外，可以采用电阻式、电容式、红外线以及表面声波等多种类型实现触摸屏。除了触摸屏131，输入单元130还可以包括其他输入设备。具体地，其他输入设 备132可以包括但不限于物理键盘、功能键(比如音量控制按键132、开关按键133等)、轨迹球、鼠标、操作杆等中的一种或多种。
其中，输入设备132可以接收到电路走线设计相关的参数，例如本申请实施例中的I/O单元的第一信息、bump的第二信息、针对于候选连接路径的修改指令等等。
该显示单元140可用于显示由用户输入的信息或提供给用户的信息、终端100的各种菜单、交互界面、文件显示和/或任意一种多媒体文件的播放。在本申请实施例中，显示单元140可用于显示电路类设计应用程序的界面、走线设计结果、候选连接路径的示意等。
该存储器120可用于存储指令和数据，存储器120可主要包括存储指令区和存储数据区，存储数据区可存储各种数据，如多媒体文件、文本等；存储指令区可存储操作系统、应用、至少一个功能所需的指令等软件单元，或者他们的子集、扩展集。还可以包括非易失性随机存储器；向处理器170提供包括管理计算处理设备中的硬件、软件以及数据资源，支持控制软件和应用。还用于多媒体文件的存储，以及运行程序和应用的存储。
处理器170是终端100的控制中心，利用各种接口和线路连接整个终端100的各个部分，通过运行或执行存储在存储器120内的指令以及调用存储在存储器120内的数据，执行终端100的各种功能和处理数据，从而对终端设备进行整体控制。可选的，处理器170可包括一个或多个处理单元；优选的，处理器170可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器170中。在一些实施例中，处理器、存储器、可以在单一芯片上实现，在一些实施例中，他们也可以在独立的芯片上分别实现。处理器170还可以用于产生相应的操作控制信号，发给计算处理设备相应的部件，读取以及处理软件中的数据，尤其是读取和处理存储器120中的数据和程序，以使其中的各个功能模块执行相应的功能，从而控制相应的部件按指令的要求进行动作。
其中，存储器120可以用于存储电路走线确定方法相关的软件代码，处理器170可以执行芯片的电路走线确定方法的步骤，也可以调度其他单元(例如上述输入单元130以及显示单元140)以实现相应的功能。
该射频单元110(可选的)可用于收发信息或通话过程中信号的接收和发送，例如，将基站的下行信息接收后，给处理器170处理；另外，将设计上行的数据发送给基站。通常，RF电路包括但不限于天线、至少一个放大器、收发信机、耦合器、低噪声放大器(Low Noise Amplifier，LNA)、双工器等。此外，射频单元110还可以通过无线通信与网络设备和其他设备通信。该无线通信可以使用任一通信标准或协议，包括但不限于全球移动通讯系统(Global System of Mobile communication，GSM)、通用分组无线服务(General Packet Radio Service，GPRS)、码分多址(Code Division Multiple Access，CDMA)、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)、长期演进(Long Term Evolution，LTE)、电子邮件、短消息服务(Short Messaging Service，SMS)等。
其中，在本申请实施例中，该射频单元110可以将芯片的参数发送至服务器200，并接收到服务器200发送的走线设计结果。
应理解，该射频单元110为可选的，其可以被替换为其他通信接口，例如可以是网口。
终端100还包括给各个部件供电的电源190(比如电池)，优选的，电源可以通过电源管理系统与处理器170逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。
终端100还包括外部接口180，该外部接口可以是标准的Micro USB接口，也可以使多针连接器，可以用于连接终端100与其他装置进行通信，也可以用于连接充电器为终端100充电。
尽管未示出，终端100还可以包括闪光灯、无线保真(wireless fidelity，WiFi)模块、蓝牙模块、不同功能的传感器等，在此不再赘述。下文中描述的部分或全部方法均可以应用在如图5a所示的终端100中。
接下来描述图4中服务器200的产品形态；
图5b提供了一种服务器200的结构示意图，如图5b所示，服务器200包括总线201、处理器202、通信接口203和存储器204。处理器202、存储器204和通信接口203之间通过总线201通信。
总线201可以是外设部件互连标准(peripheral component interconnect，PCI)总线或扩展工业标准结构(extended industry standard architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图5b中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
处理器202可以为中央处理器(central processing unit，CPU)、图形处理器(graphics processing unit，GPU)、微处理器(micro processor，MP)或者数字信号处理器(digital signal processor，DSP)等处理器中的任意一种或多种。
存储器204可以包括易失性存储器(volatile memory)，例如随机存取存储器(random access memory，RAM)。存储器204还可以包括非易失性存储器(non-volatile memory)，例如只读存储器(read-only memory，ROM)，快闪存储器，机械硬盘(hard drive drive，HDD)或固态硬盘(solid state drive，SSD)。
其中，存储器204可以用于存储电路走线确定方法相关的软件代码，处理器202可以执行芯片的电路走线确定方法的步骤，也可以调度其他单元以实现相应的功能。
应理解，上述终端100和服务器200可以为集中式或者是分布式的设备，上述终端100和服务器200中的处理器(例如处理器170以及处理器202)可以为硬件电路(如专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)、通用处理器、数字信号处理器(digital signal processing，DSP)、微处理器或微控制器等等)、或这些硬件电路的组合，例如，处理器可以为具有执行指令功能的硬件系统，如CPU、DSP等，或者为不具有执行指令功能的硬件系统，如ASIC、FPGA等，或者为上述不具有执行指令功能的硬件系统以及具有执行指令功能的硬件系统的组合。
应理解，本申请实施例中的电路走线确定方法涉及AI相关的运算，在执行AI运算时，终端设备和服务器的指令执行架构不仅仅局限在图5a以及图5b所示的处理器结合存储器的架构。下面结合图6对本申请实施例提供的系统架构进行详细的介绍。
图6为本申请实施例提供的系统架构示意图。如图6所示，系统架构500包括执行设 备510、训练设备520、数据库530、客户设备540、数据存储系统550以及数据采集系统560。
执行设备510包括计算模块511、I/O接口512、预处理模块513和预处理模块514。计算模块511中可以包括目标模型/规则501，预处理模块513和预处理模块514是可选的。
其中，执行设备510可以为上述运行电路设计类应用程序的终端设备或者服务器。
数据采集设备560用于采集训练样本。训练样本可以为I/O单元的信息、bump的信息以及总连接数量等。在采集到训练样本之后，数据采集设备560将这些训练样本存入数据库530。
训练设备520可以基于数据库530中维护训练样本，对待训练的神经网络(例如本申请实施例中的机器学习模型等)，以得到目标模型/规则501。
需要说明的是，在实际应用中，数据库530中维护的训练样本不一定都来自于数据采集设备560的采集，也有可能是从其他设备接收得到的。另外需要说明的是，训练设备520也不一定完全基于数据库530维护的训练样本进行目标模型/规则501的训练，也有可能从云端或其他地方获取训练样本进行模型训练，上述描述不应该作为对本申请实施例的限定。
根据训练设备520训练得到的目标模型/规则501可以应用于不同的系统或设备中，如应用于图6所示的执行设备510，该执行设备510可以是终端，如手机终端，平板电脑，笔记本电脑，增强现实(augmented reality，AR)/虚拟现实(virtual reality，VR)设备，车载终端等，还可以是服务器等。
具体的，训练设备520可以将训练后的模型传递至执行设备510。
在图6中，执行设备510配置输入/输出(input/output，I/O)接口512，用于与外部设备进行数据交互，用户可以通过客户设备540向I/O接口512输入数据(例如本申请实施例中的I/O单元的第一信息、bump的第二信息等)。
预处理模块513和预处理模块514用于根据I/O接口512接收到的输入数据进行预处理。应理解，可以没有预处理模块513和预处理模块514或者只有的一个预处理模块。当不存在预处理模块513和预处理模块514时，可以直接采用计算模块511对输入数据进行处理。
在执行设备510对输入数据进行预处理，或者在执行设备510的计算模块511执行计算等相关的处理过程中，执行设备510可以调用数据存储系统550中的数据、代码等以用于相应的处理，也可以将相应处理得到的数据、指令等存入数据存储系统550中。
最后，I/O接口512将处理结果(例如本申请实施例中目标连接路径)提供给客户设备540，从而提供给用户。
在图6所示情况下，用户可以手动给定输入数据，该“手动给定输入数据”可以通过I/O接口512提供的界面进行操作。另一种情况下，客户设备540可以自动地向I/O接口512发送输入数据，如果要求客户设备540自动发送输入数据需要获得用户的授权，则用户可以在客户设备540中设置相应权限。用户可以在客户设备540查看执行设备510输出的结果，具体的呈现形式可以是显示、声音、动作等具体方式。客户设备540也可以作为数据采集端，采集如图所示输入I/O接口512的输入数据及输出I/O接口512的输出结果作为新 的样本数据，并存入数据库530。当然，也可以不经过客户设备540进行采集，而是由I/O接口512直接将如图所示输入I/O接口512的输入数据及输出I/O接口512的输出结果，作为新的样本数据存入数据库530。
值得注意的是，图6仅是本申请实施例提供的一种系统架构的示意图，图中所示设备、器件、模块等之间的位置关系不构成任何限制，例如，在图6中，数据存储系统550相对执行设备510是外部存储器，在其它情况下，也可以将数据存储系统550置于执行设备510中。应理解，上述执行设备510可以部署于客户设备540中。
从模型的推理侧来说：
本申请实施例中，上述执行设备520的计算模块511可以获取到数据存储系统550中存储的代码来实现本申请实施例中的电路走线确定方法。
本申请实施例中，执行设备520的计算模块511可以包括硬件电路(如专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)、通用处理器、数字信号处理器(digital signal processing，DSP)、微处理器或微控制器等等)、或这些硬件电路的组合，例如，训练设备520可以为具有执行指令功能的硬件系统，如CPU、DSP等，或者为不具有执行指令功能的硬件系统，如ASIC、FPGA等，或者为上述不具有执行指令功能的硬件系统以及具有执行指令功能的硬件系统的组合。
具体的，执行设备520的计算模块511可以为具有执行指令功能的硬件系统，本申请实施例提供的连接关系预测方法可以为存储在存储器中的软件代码，执行设备520的计算模块511可以从存储器中获取到软件代码，并执行获取到的软件代码来实现本申请实施例提供的电路走线确定方法。
应理解，执行设备520的计算模块511可以为不具有执行指令功能的硬件系统以及具有执行指令功能的硬件系统的组合，本申请实施例提供的电路走线确定方法的部分步骤还可以通过执行设备520的计算模块511中不具有执行指令功能的硬件系统来实现，这里并不限定。
从模型的训练侧来说：
本申请实施例中，上述训练设备520可以获取到存储器(图6中未示出，可以集成于训练设备520或者与训练设备520分离部署)中存储的代码来实现本申请实施例中和模型训练相关的步骤。
本申请实施例中，训练设备520可以包括硬件电路(如专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)、通用处理器、数字信号处理器(digital signal processing，DSP)、微处理器或微控制器等等)、或这些硬件电路的组合，例如，训练设备520可以为具有执行指令功能的硬件系统，如CPU、DSP等，或者为不具有执行指令功能的硬件系统，如ASIC、FPGA等，或者为上述不具有执行指令功能的硬件系统以及具有执行指令功能的硬件系统的组合。
应理解，训练设备520可以为不具有执行指令功能的硬件系统以及具有执行指令功能的硬件系统的组合，本申请实施例提供的中和模型训练相关的部分步骤还可以通过训练设备520中不具有执行指令功能的硬件系统来实现，这里并不限定。
二、服务器提供的云服务：
在一种可能的实现中，服务器可以通过应用程序编程接口(application programming interface，API)为端侧提供电路走线确定的服务。
其中，终端设备可以通过云端提供的API，将相关参数(例如I/O单元的信息等、bump的信息等)发送至服务器，服务器可以基于接收到的参数，得到处理结果，并将处理结果(例如目标连接路径等)返回至至终端。
关于终端以及服务器的描述可以上述实施例的描述，这里不再赘述。
由于本申请实施例涉及大量神经网络的应用，为了便于理解，下面先对本申请实施例涉及的相关术语及神经网络等相关概念进行介绍。
(1)神经网络
神经网络可以是由神经单元组成的，神经单元可以是指以xs(即输入数据)和截距1为输入的运算单元，该运算单元的输出可以为：
其中，s＝1、2、……n，n为大于1的自然数，Ws为xs的权重，b为神经单元的偏置。f为神经单元的激活函数(activation functions)，用于将非线性特性引入神经网络中，来将神经单元中的输入信号转换为输出信号。该激活函数的输出信号可以作为下一层卷积层的输入，激活函数可以是sigmoid函数。神经网络是将多个上述单一的神经单元联结在一起形成的网络，即一个神经单元的输出可以是另一个神经单元的输入。每个神经单元的输入可以与前一层的局部接受域相连，来提取局部接受域的特征，局部接受域可以是由若干个神经单元组成的区域。
(2)深度神经网络
深度神经网络(Deep Neural Network，DNN)，也称多层神经网络，可以理解为具有很多层隐含层的神经网络，这里的“很多”并没有特别的度量标准。从DNN按不同层的位置划分，DNN内部的神经网络可以分为三类：输入层，隐含层，输出层。一般来说第一层是输入层，最后一层是输出层，中间的层数都是隐含层。层与层之间是全连接的，也就是说，第i层的任意一个神经元一定与第i+1层的任意一个神经元相连。虽然DNN看起来很复杂，但是就每一层的工作来说，其实并不复杂，简单来说就是如下线性关系表达式：其中，是输入向量，是输出向量，是偏移向量，W是权重矩阵(也称系数)，α()是激活函数。每一层仅仅是对输入向量经过如此简单的操作得到输出向量由于DNN层数多，则系数W和偏移向量的数量也就很多了。这些参数在DNN中的定义如下所述：以系数W为例：假设在一个三层的DNN中，第二层的第4个神经元到第三层的第2个神经元的线性系数定义为上标3代表系数W所在的层数，而下标对应的是输出的第三层索引2和输入的第二层索引4。总结就是：第L-1层的第k个神经元到第L层的第j个神经元的系数定义为需要注意的是，输入层是没有W参数的。在深度神经网络 中，更多的隐含层让网络更能够刻画现实世界中的复杂情形。理论上而言，参数越多的模型复杂度越高，“容量”也就越大，也就意味着它能完成更复杂的学习任务。训练深度神经网络的也就是学习权重矩阵的过程，其最终目的是得到训练好的深度神经网络的所有层的权重矩阵(由很多层的向量W形成的权重矩阵)。
(3)图(Graph)：
图为包括至少一个顶点以及至少一条边的数据结构。在一些场景中，图中的顶点可以映射为实体，图中的边可以映射为实体与实体之间的关系。图可以是有向图或无向图。当然，图还可以包括顶点以及边以外的其他数据，例如顶点的标签以及边的标签等。在一个示例性场景中，应用于好友推荐的场景中，图中的每个顶点可以表示一个用户，图中的每条边可以表示不同用户之间的社交关系，图中每个顶点的数据为用户的画像数据以及用户的行为数据，例如用户的年龄、职业、爱好、学历等。又如，应用于在商品推荐的场景中，图中的每个顶点可以表示一个用户或一个商品，图中的每条边可以表示用户与商品之间的交互关系，例如购买关系、收藏关系等。又如，应用于金融风控的场景中，图中的每个顶点可以表示账号、交易或资金。图中的边可以表示资金的流动关系，例如图中的环路可以表示循环转账。再如，应用于网络系统中网元之间连接关系确定的场景中，图中的每个顶点可以表示一个网元，例如路由器、交换机、终端等，图中的每条边可以表示不同网元之间的连接关系。
(4)图神经网络(graph neural network，GNN)：
GNN是一种带有结构信息的深度学习方法，可以用于计算节点当前的状态。图神经网络的信息传递按照给定的图结构进行，可以根据相邻节点更新每个节点的状态。具体地，其可以根据当前节点的结构图，以神经网络作为点信息的聚合函数，将所有相邻节点的信息传递到当前节点，结合当前节点的状态进行更新。图神经网络的输出为所有节点的状态。
(5)损失函数
在训练深度神经网络的过程中，因为希望深度神经网络的输出尽可能的接近真正想要预测的值，所以可以通过比较当前网络的预测值和真正想要的目标值，再根据两者之间的差异情况来更新每一层神经网络的权重向量(当然，在第一次更新之前通常会有初始化的过程，即为深度神经网络中的各层预先配置参数)，比如，如果网络的预测值高了，就调整权重向量让它预测低一些，不断的调整，直到深度神经网络能够预测出真正想要的目标值或与真正想要的目标值非常接近的值。因此，就需要预先定义“如何比较预测值和目标值之间的差异”，这便是损失函数(loss function)或目标函数(objective function)，它们是用于衡量预测值和目标值的差异的重要方程。其中，以损失函数举例，损失函数的输出值(loss)越高表示差异越大，那么深度神经网络的训练就变成了尽可能缩小这个loss的过程。
(6)反向传播算法
卷积神经网络可以采用误差反向传播(back propagation，BP)算法在训练过程中修正初始的超分辨率模型中参数的大小，使得超分辨率模型的重建误差损失越来越小。具体地，前向传递输入信号直至输出会产生误差损失，通过反向传播误差损失信息来更新初始的超分辨率模型中参数，从而使误差损失收敛。反向传播算法是以误差损失为主导的反向传播运动，旨在得到最优的超分辨率模型的参数，例如权重矩阵。
(7)端口
端口为电路(例如芯片)的边缘，用于作为与外围电路之间通信或者能量传递的接口。
(8)引脚
引脚为电路中具备一定功能的管脚，引脚为引线末端的一段，通过软钎焊使这一段与电路板上的焊盘共同形成焊点。
(9)中继点
在电路上，相邻引脚之间存在着不包括焊点的裸板区域，中继点为定义在裸板区域上的逻辑点，中继点为端口和引脚之间连接路径上的点。
(10)I/O单元
I/O单元可以位于电路(例如芯片)的边缘区域，I/O单元可以负责和外部元件连接，I/O单元可以作为与外部元件进行数据交换、能量传递等功能的端口。
(11)bump
转接单元(bump)也可以称之为晶圆、凸点或者凸块，位于电路(例如芯片)的内部区域，bump可以和I/O单元连接，和I/O单元进行数据交换、能量传递等。
电路中的端口和引脚之间的匹配走线，例如I/O单元和bump之间的匹配走线是芯片设计的重要流程之一，具有耗时长、检查难、需求量大等特点，通常需要依靠芯片设计师的人工经验进行排查，通过可交互式软件手动调节对应引脚匹配走线，并且在满足引脚多优先级类型约束的前提下最大程度提高I/O单元和bump之间的实际连接数量。目前，业界常用基于规则构造约束下的解析型方法处理芯片引脚自动匹配走线问题，根据芯片引脚类型和预先定义的走线规则实现自动布线功能。然而，基于规则构造约束下的解析型方法泛化性不佳、走线规则繁杂耦合，计算复杂度高，并且容易陷入到局部极值解，导致电路走线的整体性能不佳。
为了解决上述问题，参照图7a，图7a为本申请实施例提供的一种电路走线确定方法的流程示意，如图7a所示，本申请实施例提供的一种电路走线确定方法包括：
701、获取电路的多个端口的第一信息、以及多个引脚的第二信息；所述多个端口和所述多个引脚之间包括多个候选连接路径；所述候选连接路径为端口和引脚之间的连接路径。
其中，步骤701的执行主体可以为终端设备或者服务器，具体可以参照上述实施例中的描述，这里不再赘述。
在一种可能的实现中，所述端口为输入输出I/O单元，所述引脚为转接单元bump。
其中，多个端口的第一信息可以理解为多个端口中每个端口的第一信息。
其中，多个引脚的第二信息可以理解为多个引脚中每个引脚的第二信息。
在一种可能的实现中，第一信息可以包括端口的位置特征、功能特征或者优先级特征中的一种或多种。第二信息可以为引脚的位置特征、功能特征或者优先级特征中的一种或多种。
在一种可能的实现中，位置特征可以表示为电路元件的坐标位置，例如位置特征可以为2D平面上的坐标位置，更细节的，位置特征可以为直角坐标系下的XY坐标。
例如，第一信息可以包括端口的坐标位置。
例如，第二信息可以包括引脚的坐标位置。
在一种可能的实现中，功能特征可以表示电路元件所实现的功能。例如，功能可以包括信号传输功能、能量传输功能以及接地等。
例如，第一信息可以包括端口所实现的功能。
例如，第二信息可以包括引脚所实现的功能。
在一种可能的实现中，优先级特征可以表示电路元件的重要程度，该重要程度可以描述电路元件对于连接数量的要求，优先级越高，则电路元件的重要程度越高，则电路元件对于连接数量的要求越高。
在一种可能的实现中，不同功能的电路元件可以具备不同的优先级。
例如，信号传输功能的电路元件的优先级高于能量传输功能的电路元件的优先级，能量传输功能的电路元件的优先级高于接地功能的电路元件的优先级。
在一种可能的实现中，不同功能的电路元件可以具备相同的优先级。
例如，信号传输功能的电路元件的优先级高于能量传输功能的电路元件的优先级，能量传输功能的电路元件的优先级与接地功能的电路元件的优先级相同。
在一种可能的实现中，相同功能的电路元件可以具备不同的优先级。
例如，接地功能中一部分电路元件的优先级可以大于接地功能中另一部分电路元件的优先级。
在一种可能的实现中，可以基于电路设计软件(例如EDA)的界面来输入端口的信息(例如本申请实施例中的第一信息)以及引脚的信息(例如本申请实施例中的第二信息)。
接下来结合界面的描述，介绍输入第一信息以及第二信息的方式的示意：
1、关于位置特征
在一种可能的实现中，以EDA为例，电路设计软件可以提供电路元件的元件库供选择，元件库可包括多种电路单元，例如端口、引脚。
参照图8，可以通过选择并拖动的方式从元件库中将选择的电路单元放置到对应的位置，将端口和引脚放置到对应位置后，可以基于电路元件在电路图上的位置得到端口以及引脚的位置特征，例如，该位置特征可以表示为电路元件的坐标位置，例如位置特征可以为2D平面上的坐标位置，更细节的，位置特征可以为直角坐标系下的XY坐标。
参照图8，可以通过文件的形式来输入第一信息以及第二信息，该文件可以表达出待走线设计的电路的信息。该文件中可以包括端口以及引脚的位置特征。
2、功能特征
参照图9，可以在元件库中选择要摆放的元件以及元件的功能，并拖动到对应的位置，进而可以获取到端口以及引脚的功能特征。
参照图9，可以通过文件的形式来输入第一信息以及第二信息，该文件可以表达出待走线设计的电路的信息。该文件中可以包括端口以及引脚的功能特征。
3、优先级特征
参照图10a，可以通过选择电路单元的优先级(例如图10a所示的优先级1、优先级2 以及优先级3等)，并将元件放置到对应的位置，进而可以获取到端口以及引脚的优先级特征。
在一种可能的实现中，可以在将元件库中选择要摆放的元件以及元件的功能，并拖动到对应的位置后，再进行优先级的编辑。参照图10b，可以选择并触发对端口的编辑控件，该控件可以对优先级进行编辑，例如可以选择图10b所示的优先级1、优先级2以及优先级3等。
参照图10a，可以通过文件的形式来输入第一信息以及第二信息，该文件可以表达出待走线设计的电路的信息。该文件中可以包括端口以及引脚的优先级特征。
在一种可能的实现中，所述多个端口和所述多个引脚之间可以包括多个候选连接路径，其中，所述候选连接路径为端口和引脚之间的连接路径(可行连接路径)。
在一种可能的实现中，端口和引脚之间的连接路径可以理解为候选连接路径的两端分别为端口和引脚，通过候选连接路径可以将端口和引脚连接起来，且候选连接路径所经过的区域为不包括端口和引脚的空白区域，也就是未被端口和引脚所占据的区域。
参照图11a，图11a中的方框表示端口，圆形框表示引脚，相同颜色表示相同的功能，如图11a所示的那样，一组端口和引脚之间可以包括一个或多个候选连接路径，也就是以一个端口为起点，可以通过一个或多个路径连接至一个引脚。
在一种可能的实现中，最终确定的端口和引脚之间的目标连接路径可以从候选连接路径中选择。
接下来介绍如何确定端口和引脚之间的至少一个候选连接路径：
在一种可能的实现中，在确定候选连接路径时，相同功能的端口和引脚之间才能形成候选连接路径，第一信息以及第二信息所指示的端口以及引脚的功能特征可以知晓可以形成候选连接路径的对象，也就是第一信息以及第二信息所指示的具有相同功能的端口以及引脚可以作为起点和终点而形成候选连接路径。
例如，图11a中所示的相同颜色的端口和引脚之间可以形成候选连接路径。
在一种可能的实现中，第一信息以及第二信息可以指示端口和引脚的位置特征。基于位置特征可以知晓各个端口和引脚的排布，进而可以基于各个端口和引脚在空间上的排布来确定至少一个候选连接路径。
本申请实施例中，端口和引脚之间可以存在很多数量的候选连接路径，为了降低后续的计算量，可以保留部分的候选连接路径，例如可以选择路径数量小于预设值(示例性的，预设值为3、4、5、6、7)且路径长度相对较小的至少一个候选连接路径。此外，由于相同类型的端口和引脚之间都可以进行连接，为了降低后续的计算量，可以选择距离相对较近的端口和引脚进行候选连接路径的确定。
在一种可能的实现中，端口和引脚之间的至少一个候选连接路径可以通过和用户的交互来实现，例如用户可以在电路设计类应用程序的界面上手动输入端口和引脚之间的至少一个候选连接路径，或者是将包含端口和引脚之间的至少一个候选连接路径电路图文件导入到电路设计类应用程序中，或者是将端口和引脚之间的至少一个候选连接路径传输到云侧服务器。
702、根据所述第一信息和所述第二信息，通过机器学习模型，得到每个所述候选连接路径的代价值，所述代价值用于指示候选连接路径对所述多个端口和所述多个引脚之间总连接路径的数量的影响；所述代价值用于从所述多个候选连接路径中确定至少一个目标连接路径。
在一种可能的实现中，步骤702的执行主体可以为服务器或者终端设备。
具体的，从步骤的执行主体上，可以示例性的分为如下几种情况：
在一种可能的实现中，参照图7b，在一种可能的实现中，终端设备可以获取电路的多个端口的第一信息、以及多个引脚的第二信息，并将第一信息和第二信息(例如可以是基于第一信息和第二信息得到的多个候选连接路径的信息)发送至服务器，服务器可以根据所述第一信息和所述第二信息，通过机器学习模型，得到每个所述候选连接路径的代价值，基于代价值，从所述多个候选连接路径中确定至少一个目标连接路径，并将至少一个目标连接路径回传至终端设备。
在一种可能的实现中，参照图7c，终端设备可以获取电路的多个端口的第一信息、以及多个引脚的第二信息，并将第一信息和第二信息(例如可以是基于第一信息和第二信息得到的多个候选连接路径的信息)发送至服务器，服务器可以根据所述第一信息和所述第二信息，通过机器学习模型，得到每个所述候选连接路径的代价值，并将代价值发送至终端设备，进而终端设备可以基于代价值，从所述多个候选连接路径中确定至少一个目标连接路径。
在一种可能的实现中，参照图7d，终端设备可以获取电路的多个端口的第一信息、以及多个引脚的第二信息，根据所述第一信息和所述第二信息(例如可以是基于第一信息和第二信息得到的多个候选连接路径的信息)，通过机器学习模型，得到每个所述候选连接路径的代价值，并将代价值发送至服务器，进而服务器可以基于代价值，从所述多个候选连接路径中确定至少一个目标连接路径，并将至少一个目标连接路径回传至终端设备。
在一种可能的实现中，参照图7e，终端设备可以获取电路的多个端口的第一信息、以及多个引脚的第二信息，根据所述第一信息和所述第二信息(例如可以是基于第一信息和第二信息得到的多个候选连接路径的信息)，通过机器学习模型，得到每个所述候选连接路径的代价值，基于代价值，从所述多个候选连接路径中确定至少一个目标连接路径。
在一种可能的实现中，参照图7f，服务器可以获取电路的多个端口的第一信息、以及多个引脚的第二信息(可以是来自终端设备发送的)；例如，服务器可以获取多个候选连接路径的信息(可以是来自终端设备发送的)，根据所述第一信息和所述第二信息(例如可以是基于第一信息和第二信息得到的多个候选连接路径的信息)，通过机器学习模型，得到每个所述候选连接路径的代价值，基于代价值，从所述多个候选连接路径中确定至少一个目标连接路径，并将至少一个目标连接路径回传至终端设备。
在一种可能的实现中，所述候选连接路径可以包括两端的端口和引脚、以及所述候选连接路径所经过的至少一个中继点，所述中继点为相邻引脚之间的中间位置点，每个所述候选连接路径的信息包括：所述候选连接路径所包括的端口的第一信息、所述候选连接路径所包括的引脚的第二信息、以及所述至少一个中继点的位置信息。
其中，参照图11b，多个候选连接路径的信息可以包括多个候选连接路径中每个候选连接路径的信息。由于每个候选连接路径可以由起点、至少一个中继点以及终点组成，每个候选连接路径的信息可以包括起点的信息、至少一个中继点的位置信息以及终点的信息。起点可以为端口，起点的信息可以包括端口的第一信息(例如，端口的位置、功能、优先级等)，终点可以为引脚，终点的信息可以包括引脚的第二信息(例如，端口的位置、功能、优先级等)。
在一种可能的实现中，端口和引脚之间的候选连接路径可以包括起点、终点以及至少一个中继点，其中，起点和终点可以为：端口和引脚，中继点可以为相邻引脚之间的位置点，进而，连接路径可以表示为起点、至少一个中继点以及终点的形式。示例性的，可以对端口、引脚以及中继点进行编码，每个端口、每个引脚以及每个中继点可以唯一对应一个编码结果，基于每个编码结果可以唯一确定对应的电路单元(例如端口、引脚或中继点)。通过编码结果的序列可以表征候选连接路径。
在端口和引脚的匹配走线的场景中，需要尽可能的提高端口和引脚之间的连接数量，以便提高芯片的性能。本申请实施例中，为了提高端口和引脚之间的连接数量，可以计算出各个候选连接路径对于多个端口和所述多个引脚之间总连接路径的数量的影响(也就是本申请实施例中的代价值)，并基于代价值来进行端口和引脚之间连接路径的选择。
其中，所述代价值用于指示候选连接路径对所述多个端口和所述多个引脚之间总连接路径的数量的影响，由于最终确定的端口和引脚的各个连接路径之间不相交(例如，存在公共的中继点时可以认为连接路径之间相交)。进而，每条连接路径的确定会对其他端口和引脚之间连接路径的选择造成一定程度的影响(不能再选择存在路径重叠的连接路径)。这里的“影响”可以理解为：若采用了该候选连接路径作为端口和引脚之间的连接路径，会对多个端口和所述多个引脚之间总连接路径的数量的正向影响或者负向影响。以负向影响为例，代价值可以表示：若采用了该候选连接路径作为端口和引脚之间的连接路径，会对多个端口和多个引脚之间总连接路径的数量造成降低的程度。
为了得到上述代价值，在一种可能的实现中，可以根据所述第一信息和所述第二信息，通过机器学习模型，得到每个所述候选连接路径的代价值。
在一种可能的实现中，机器学习模型可以通过训练而具备根据多个候选连接路径的信息得到每个候选连接路径的代价值的能力。
接下来介绍机器学习模型的一个示例：
在一种可能的实现中，机器学习模型可以包括特征提取网络以及任务网络，其中，机器学习模型可以为图神经网络模型，特征提取网络可以(示例性的)为图嵌入网络，可以将多个候选连接路径的信息通过图神经网络模型进行表征，以得到每个节点的特征表示以及边的特征表示，节点可以对应于候选连接路径中的端口、引脚单元或者中继点，边可以为端口和中继点之间的连接边、中继点和中继点之间的连接边、中继点和引脚单元之间的连接边等。可选的，候选连接路径可以表示为二分图的形式，并以二分图的形式输入到特征提取网络中。
示例性的，以节点为例，图嵌入表征过程可以采用GraphSAGE方法进行聚合，聚合具 体过程描述为：对每个节点v∈V的相邻节点N(v)进行聚合，得到聚合向量hN(v)。聚合函数采用均值池化，具体表示为：
其中，mean为均值池化函数，W为聚合权重，b为聚合偏差，hu为节点u经过图嵌入得到的隐状态，σ为sigmoid激活函数。
在一种可能的实现中，特征提取网络输出的特征表示能够包含多个候选连接路径的连接特征(例如全局连接排布的特征等)，候选连接路径可以通过任务网络得到各个候选连接路径的代价值。
在一种可能的实现中，任务网络可以得到各个边的代价值，进而可以将各个候选连接路径上包括的边的代价值进行综合，以得到各个候选连接路径的代价值。
示例性的，任务网络可以为策略网络πθ，可以采用两层全连接网络结构，称其为决策输出层，为加快训练效率并且降低模型复杂度，可以采用ReLU激活函数作用于决策全连接层隐层。由于决策过程为多优先级序列决策行为，决策过程无法相互间进行影响。定义第i个优先级对应的动作为ai,根据马尔科夫决策过程，当前优先级状态下的动作与之前所有时刻的动作相关，例如可以表示为：
p(a|s)＝∏i＝1,…,Ip(ai|si,ai-1)；
其中p表示对应决策代价评估输出，也就是代价值。
可选的，策略网络的决策输出层对应可行路径的决策评估代价，其可以限制在连续域的[0,1]范围内。
接下来从模型构建以及训练的角度介绍本申请实施例的机器学习模型：
在一种可能的实现中，可以采用强化学习优化图神经网络模型，主要分为构建图神经网络决策模型与马尔科夫决策优化过程两部分。
其中，基于图神经网络模型构建图神经网络决策模型，实现面向多优先级端口与引脚之间连接的状态表征与动作决策。具体而言，图神经网络模型主要由图编码模型与策略决策模型组成，图编码模型由节点模型、边模型与全局模型组成，策略决策模型则是两层全连接网络；其中节点模型用于编码输入的节点信息，边模型用于编码输入的边信息，全局模型用于编码全局节点与边信息。
在马尔科夫决策优化过程中，可以将多优先级端口与引脚之间连接的序列决策问题转换为马尔科夫决策问题。马尔科夫决策基本元素由状态、动作与奖赏的三元组构成，具体定义为：
状态：以端口与引脚之间的位置、类型与优先级作为节点状态，以端口与引脚之间的可行路径与节点邻接关系作为边状态，将两者联合作为决策输入状态。
动作：将输入状态传递至图神经网络模型，生成当前状态下的可行路径代价评估，并将评估值作为当前决策动作。
奖赏：将决策动作传递至最小代价最大流算法以生成端口与引脚之间连接个数，并将该连接个数与基于常用策略下的规则型方法得到的端口与引脚之间连接个数进行比较，以 增益差值作为奖赏。
随后，在三元组数据驱动下，以最大化优化目标函数作为引导，采用强化学习方法更新图神经网络模型，具体目标函数定义如下：
其中π为策略模型参数，st与at表示对应t时刻的输入状态与决策动作，ρπ为经验回放池，R为对应奖赏函数，H为策略熵函数，α为均衡因子；
在一种可能的实现中，模型训练阶段初期可任意经历冷启动采样过程，经验回放池D为空集，采用随机均匀采样的方式生成对应可行路径的评估代价，作为模型决策输出在匹配走线任务上作用，生成原始转换数据对(st,at,rt,st+1)，存入到经验回放池D。基于Xavier方法随机初始化神经网络模型，构建目标网络模型用于稳定模型更新过程，并且通过软更新机制更新目标网络模型参数。
在冷启动采样过程结束后进入到模型训练采样过程，根据当前的可行解路径与端口与引脚之间位置、类型与优先级节点信息进行状态表征st，输入至图神经网络模型中的策略网络部分，生成待连接边的代价均值与方差。根据相应均值与方差，通过高斯采样得到相应的代价评估值作为动作输出at，将对应可行路径的代价评估值，通过最小代价最大流算法计算得到连通路径个数，将该连通个数与原始规则型方法得到的端口与引脚之间连接个数之差作为奖赏信号rt，并得到对应连接后的下一阶段状态表征st+1。最后将转换数据对(st,at,rt,st+1)记录在经验回放池D，形成模型采样数据。
在采样过程期间进行模型训练过程，通过经验回放池D进行采样得到批经验数据B，采用Soft Actor-Critic强化学习方法进一步平衡探索与利用间关系，定义Q目标值为：
其中dt+1表示t+1时刻环境是否处于终止状态,为价值目标网络，为策略目标网络。随后，采用均方误差损失函数更新价值网络Qφ参数，定义为：
最终通过最大化目标函数更新策略网络πθ参数，定义为：
其中α为探索熵因子，用于平衡探索与利用间的更新权重。
以最大化最终的端口与引脚之间的连接个数作为更新目标，因此将最终的奖赏信号同时分配为每个优先级上进行决策所获得的奖赏。并且，为降低数据关联性而采用随机经验回放的方式，基于强化学习方法最大化更新目标与探索熵值，避免因只追求最大化奖赏而 陷入到局部极值解，提高模型探索效率和泛化性能。通过上述更新方式优化图神经网络模型参数。
本申请可以基于强化学习的图神经网络匹配走线决策模型，将所有端口与引脚之间引脚对应的位置、类型以及优先级等因素考虑在内，并且经过图神经网络模型可以解决高维空间状态表征困难的问题。通过与最小代价最大流的有效结合，提高规则型方法的连通数量，避免陷入局部极值解。另外，采用强化学习的方法可以在解空间中进行自主探索，降低了人为参与性，减少了手工设计的难度。
703、根据所述代价值，从所述多个候选连接路径中确定至少一个目标连接路径。
在一种可能的实现中，每个候选连接路径的代价值可以表征出采用了该候选连接路径作为端口和引脚之间的连接路径，会对多个端口和所述多个引脚之间总连接路径的数量的正向影响或者负向影响，进而，针对于每组端口和引脚，可以选择多个候选连接路径中负向影响最小或者正向影响最大的连接路径作为目标连接路径。
在一种可能的实现中，可以通过最小代价最大流算法(也可以称之为最小费用最大流算法)来从所述多个候选连接路径中确定至少一个目标连接路径。
示例性的，在执行最小代价最大流算法时，可以在候选连接路径的两侧分别构建起始节点S和目标节点T，并且与其他端口对应的节点、引脚对应的节点或者中继点对应的节点相连。根据走线要求，所有节点的个数|V|＝2+(|I|+|B|+|R|)，其中|I|为端口个数，|B|为引脚个数,|R|为中继点个数。由于边的个数取决于是否与上一优先级产生交叉来影响当前的可行走线路径，因此边的个数随不同优先级的变化而发生变化，而边的总容量为每个引脚的连通需求量总和。
在一种可能的实现中，所述至少一个目标连接路径中的任意两个目标连接路径之间不相交。
示例性的，参照图12，图12为本申请实施例的一个电路设计类应用程序的界面示意，其中，在输入端口和引脚的信息(例如本申请实施例中的第一信息和第二信息)之后，可以通过点击界面中的触发开启走线设计运算的控件，进而触发电路设计类应用程序执行端口和引脚的走线匹配过程。
示例性的，参照图13，图13为本申请实施例的一个电路设计类应用程序的界面示意，其中，电路设计类应用程序在从所述多个候选连接路径中确定至少一个目标连接路径之后，可以通过电路图的形式来显示至少一个目标连接路径。
在一种可能的实现中，在进行端口和引脚的匹配走线的场景中，不同功能的端口和引脚的重要性是不同的，对于一些更为重要功能的端口和引脚来说，需要更多的数量的连接来保证芯片的性能，对于一些功能相对重要的端口和引脚来说，连接数量的减少会对芯片的性能造成较大的影响(相比于重要性较小的端口和引脚来说)。而对于一些功能相对不重要的端口和引脚，连接数量的减少不会对芯片性能造成较大的影响。本申请实施例中可以将上述重要性描述为优先级。
由于多个优先级的存在，若一次性对各个优先级的端口和引脚进行匹配走线，会大大增加机器学习模型运行的复杂度和计算难度，很难保证走线的计算精度，并不能得到较好 的走线匹配结果。本申请实施例中，按照优先级的高低，分别进行各个优先级的端口和引脚的走线计算，进而可以提高走线的计算精度。
为了方便描述，本申请实施例以多个优先级包括优先级1和优先级2为例进行说明。
例如，优先级1可以为传输信号功能的端口和引脚，优先级2可以为传输能量功能的端口和引脚。
例如，优先级1可以为传输信号功能的端口和引脚，优先级2可以为接地功能的端口和引脚。
例如，优先级1可以为传输能量的端口和引脚，优先级2可以为接地功能的端口和引脚。
例如，优先级1可以为接地功能的部分端口和引脚，优先级2可以为接地功能的部分端口和引脚。
在一种可能的实现中，所述第一信息指示所述第一端口的重要性高于所述第二端口的重要性；或者，所述第二信息指示所述第一引脚的重要性高于所述第二引脚的重要性。
在一种可能的实现中，所述多个端口可以包括多个第一端口以及多个第二端口，所述多个引脚包括多个第一引脚以及多个第二引脚，所述多个第一端口和所述多个第一引脚用于实现第一功能；所述多个第二端口和所述多个第二引脚用于实现第二功能，所述第一功能和所述第二功能不同。其中，所述多个第一端口和所述多个第一引脚的优先级为优先级1，所述多个第二端口和所述多个第二引脚的优先级为优先级2，第一功能和第二功能可以为相同或不同的功能。
在一种可能的实现中，所述多个候选连接路径可以包括所述多个第一端口和所述多个第一引脚之间形成的多个第一候选连接路径，以及所述多个第二端口和所述多个第二引脚之间形成的多个第二候选连接路径。
在一种可能的实现中，为了不与高优先级的走线线路产生交叉冲突，可以去除低优先级中与较高优先级的候选连接路径形成交叉的线路(也就是相交的线路)，即使不去除的这部分线路，这部分线路也不会作为最终的连接路径，因此，本申请实施例通过去除低优先级中与较高优先级的候选连接路径形成交叉的线路，减小了解空间大小，在保证了走线计算精准度的同时，降低了运算复杂度。
在一种可能的实现中，至少一个所述第二候选连接路径可以与所述多个第一候选连接路径中的至少一个第一候选连接路径之间相交。也就是说，在确定模型输入时，不对与高优先级的线路重叠的低优先级的路径进行剔除，通过上述方式可以增加输入信息的数量，也就是输入到模型中的信息可以更全面的描述端口以及引脚的特征，进而可以得到更准确的代价值。
以高优先级的线路为多个第一候选连接路径，低优先级的线路为多个第二候选连接路径为例，所述多个第一候选连接路径中的至少两个第一候选连接路径之间可以相交(也可以完全不重叠)，每个所述第二候选连接路径与所述多个第一候选连接路径之间不相交，所述多个第二候选连接路径中的至少两个第二候选连接路径之间可以相交(也可以完全不重叠)。
示例性的，参照图14，图14为本申请实施例的一个电路设计类应用程序的界面示意，其中，在输入端口和引脚的信息(例如本申请实施例中的第一信息和第二信息)之后，可以通过点击界面中的触发开启基于优先级的走线设计功能的控件，进而触发电路设计类应用程序执行端口和引脚的走线匹配过程。
在一种可能的实现中，可以对高优先级的多个端口和多个第一引脚进行走线匹配，在得到走线匹配结果之后，再对低优先级的多个第二端口和多个第二引脚进行走线匹配，接下来详细进行介绍：
在一种可能的实现中，在对高优先级的多个端口和多个第一引脚进行走线匹配时，可以根据所述多个第一候选连接路径的信息以及所述多个第二候选连接路径的信息，通过机器学习模型，得到每个所述第一候选连接路径的代价值，该每个所述第一候选连接路径的代价值可以用于进行多个端口和多个第一引脚之间目标连接路径的选择。
具体的，可以根据所述每个所述第一候选连接路径的代价值，从所述多个第一候选连接路径中确定至少一个目标连接路径，关于如何根据所述每个所述第一候选连接路径的代价值，从所述多个第一候选连接路径中确定至少一个目标连接路径可以参照上述实施例中的描述，这里不再赘述。
在一种可能的实现中，多个第一候选连接路径可以为系统自动确定并经过用户的修改(例如筛选或者更改)得到的。具体的，系统可以得到并输出所述多个第一端口和所述多个第一引脚之间形成的多个第一初始候选连接路径，用户可以对多个第一初始候选连接路径进行修改，相应地，系统可以接收到对所述多个第一初始候选连接路径的修改指令，并基于对所述多个第一初始候选连接路径的修改指令，得到所述多个第一候选连接路径。
示例性的，参照图15，图15为本申请实施例的一个电路设计类应用程序的界面示意，其中，用户可以对多个第一初始候选连接路径进行删除或者路径修改。
示例性的，参照图16，图16为本申请实施例的一个电路设计类应用程序的界面示意，其中，电路设计类应用程序在从所述多个第一候选连接路径中确定至少一个第一目标连接路径之后，可以通过电路图的形式来显示至少一个第一目标连接路径。
在一种可能的实现中，系统在输出至少一个第一目标连接路径之后，用户可以基于自身的需求对至少一个第一目标连接路径进行修改，进而系统可以接收到对所述至少一个第一目标连接路径的修改信息，并基于对所述至少一个第一目标连接路径的修改信息，得到修改后的所述至少一个第一目标连接路径。
示例性的，参照图17，图17为本申请实施例的一个电路设计类应用程序的界面示意，其中，用户可以对多个第一目标连接路径进行路径修改。
在一种可能的实现中，在进行了高优先级的走线匹配运算之后，可以基于高优先级的走线匹配结果进行低优先级的匹配走线运算。具体的，可以根据所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息，通过所述机器学习模型，得到每个所述第二候选连接路径的代价值，根据所述每个所述第二候选连接路径的代价值，从所述多个第二候选连接路径中确定至少一个第二目标连接路径。
本申请实施例中，可以将所述至少一个第一目标连接路径的信息以及所述多个第二候 选连接路径的信息作为机器学习模型的输入，由于所述多个第一候选连接路径中除所述至少一个第一目标连接路径之外的其他第一候选连接路径已经不会作为第一端口和第一引脚之间的连接路径，因此可以不将多个第一候选连接路径中除所述至少一个第一目标连接路径之外的其他第一候选连接路径作为所述机器学习模型的输入，进而可以在保证走线的确定精度的前提下，降低运算的的复杂度。
在一种可能的实现中，在进行第二优先级的连接路径确认时，可以将与多个第一候选连接路径中除至少一个第一目标连接路径之外的其他第一候选连接路径之间相交的路径(至少一个第三候选连接路径)作为模型的输入，可以增加输入信息的数量，也就是输入到模型中的信息可以更全面的描述端口以及引脚的特征，进而可以得到更准确的代价值。
在一种可能的实现中，为了保证最终确定出的相同优先级的任意两条连接路径之间不相交，可以在确定连接路径时设定约束，约束可以规定相同优先级的任意两条连接路径之间不相交。
在一种可能的实现中，为了保证最终确定出的不同优先级的任意两条连接路径之间不相交，可以在确定连接路径时设定约束，约束可以规定不同优先级的任意两条连接路径之间不相交。例如，在确定出至少一条第一目标连接路径后，在从多个第二候选连接路径中选择第二目标连接路径时设定约束，约束可以规定第二目标连接路径的任意连接路径与至少一条第一目标连接路径之间不相交。
在一种可能的实现中，为了保证最终确定出的不同优先级的任意两条连接路径之间不相交，可以在候选连接路径的选择上就设定约束，约束可以规定不同优先级的候选连接路径之间不相交。
在一种可能的实现中，可以输出所述至少一个第二目标连接路径。
示例性的，参照图18，图18为本申请实施例的一个电路设计类应用程序的界面示意，其中，电路设计类应用程序在从所述多个第二候选连接路径中确定至少一个第二目标连接路径之后，可以通过电路图的形式来显示至少一个第二目标连接路径。
示例性的，参照图19，图19为本申请实施例的一个电路设计类应用程序的界面示意，其中，电路设计类应用程序在完成优先级3的连接路径的路径计算之后，可以通过电路图的形式来显示优先级3的连接路径。
示例性的，以端口为I/O单元，引脚为bump为例，参照图20，图20为本申请实施例的走线确定方法的流程示意。
其中，I/O单元的第一信息以及bump的第二信息可以用于构建I/O单元和bump之间的多个候选连接路径，并表示成二分图的形式输入至机器学习模型中，例如可以输入至机器学习模型的图嵌入网络中，图嵌入网络得到的特征表示可以输入到机器学习模型的策略网络中，以得到各个候选连接路径的代价值，根据代价值通过走线确定算法可以得到目标连接路径。
示例性的，以端口为I/O单元，引脚为bump为例，参照图21，图21为本申请实施例的基于优先权的走线确定方法的流程示意。
其中，I/O单元的第一信息以及bump的第二信息可以用于构建I/O单元和bump之间 的多个候选连接路径，并表示成二分图的形式输入至机器学习模型中，例如可以输入至机器学习模型的图嵌入网络中，图嵌入网络得到的特征表示可以输入到机器学习模型的策略网络中，以得到优先级1的各个候选连接路径的代价值，根据代价值通过走线确定算法可以得到第一目标连接路径，根据第一目标连接路径可以更新二分图，更新后的二分图可以被输入到机器学习模型中，以得到优先级2的各个候选连接路径的代价值，根据代价值通过走线确定算法可以得到第二目标连接路径。
本申请实施例提供了一种电路走线确定方法，所述方法包括：获取电路的多个输入输出端口的第一信息、以及多个转接单元引脚的第二信息；所述多个端口和所述多个引脚之间包括多个候选连接路径；所述候选连接路径为端口和引脚之间的连接路径；根据所述第一信息和所述第二信息，通过机器学习模型，得到每个所述候选连接路径的代价值，所述代价值用于指示候选连接路径对所述多个端口和所述多个引脚之间总连接路径的数量的影响；根据所述代价值，从所述多个候选连接路径中确定至少一个目标连接路径。本申请通过机器学习模型，有效评估候选连接路径的代价值，从而提高端口与引脚之间的连接数量。
参照图22，本申请实施例还提供了一种电路走线确定方法，所述方法包括：
2201、获取电路的多个输入输出端口的第一信息、以及多个转接单元引脚的第二信息；所述多个端口包括多个第一端口以及多个第二端口，所述多个引脚包括多个第一引脚以及多个第二引脚；所述多个第一端口和所述多个第一引脚之间形成多个第一候选连接路径，所述多个第二端口和所述多个第二引脚之间形成多个第二候选连接路径；
2202、基于所述第一信息和所述第二信息指示所述第一端口的重要性高于所述第二端口的重要性，根据所述多个第一候选连接路径的信息以及多个第二候选连接路径的信息，从所述多个第一候选连接路径中确定至少一个第一目标连接路径；根据所述至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，从所述多个第二候选连接路径中确定至少一个第二目标连接路径。
关于图22中所描述的一种电路走线确定方法的具体描述可以参照上述实施例中图7a对应的实施例的描述，相似之处不再赘述。
在一种可能的实现中，所述端口为输入输出I/O单元，所述引脚为转接单元bump。
在一种可能的实现中，所述多个第一候选连接路径中的至少两个第一候选连接路径之间相交；或者，
每个所述第二候选连接路径与所述多个第一候选连接路径之间不相交；或者，
至少一个第二候选连接路径与多个第一候选连接路径中的至少一个第一候选连接路径之间相交；或者，
所述多个第二候选连接路径中的至少两个第二候选连接路径之间相交。
在一种可能的实现中，方法还包括：
输出多个第一端口和多个第一引脚之间形成的多个第一初始候选连接路径，并基于对多个第一初始候选连接路径中至少一个第一初始候选连接路径的修改指令，得到多个第一候选连接路径。
在一种可能的实现中，方法还包括：
输出所述至少一个第一目标连接路径。
在一种可能的实现中，第一功能或第二功能为如下的一种：信号传输、接地、电能传输。
在一种可能的实现中，根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，包括：
根据至少一个第一连接路径的信息以及多个第二候选连接路径的信息、且不根据多个第一候选连接路径中除至少一个第一目标连接路径之外的其他第一候选连接路径。
在一种可能的实现中，方法还包括：
输出多个第二端口和多个第二引脚之间形成的多个第二初始候选连接路径，并基于对多个第二初始候选连接路径中至少一个第二初始候选连接路径的修改指令，得到多个第二候选连接路径。
在一种可能的实现中，方法还包括：
输出至少一个第二目标连接路径。
在一种可能的实现中，至少一个第一目标连接路径中的任意两个连接路径之间不相交，至少一个第二目标连接路径中的任意两个连接路径之间不相交，每个第一目标连接路径与至少一个第二目标连接路径中的任意第二目标连接路径之间不相交。
在一种可能的实现中，方法还包括：
基于对至少一个第一目标连接路径的修改信息，得到修改后的至少一个第一目标连接路径；
根据至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，包括：根据修改后的至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息。
参照图23，图23为本申请实施例提供的一种电路走线确定装置的结构示意，其中，所述装置2300，包括：
获取模块2301，用于获取电路的多个端口的第一信息、以及多个引脚的第二信息；所述多个端口和所述多个引脚之间包括多个候选连接路径；所述候选连接路径为端口和引脚之间的连接路径；
其中，关于获取模块2301的具体描述可以参照上述实施例中步骤701的描述，这里不再赘述。
代价值确定模块2302，用于根据所述第一信息和所述第二信息，通过机器学习模型，得到每个所述候选连接路径的代价值，所述代价值指示候选连接路径对所述多个端口和所述多个引脚之间总连接路径的数量的影响；所述代价值用于从所述多个候选连接路径中确定至少一个目标连接路径。
其中，关于代价值确定模块2302的具体描述可以参照上述实施例中步骤702的描述，这里不再赘述。
本申请通过机器学习模型，有效评估候选连接路径的代价值，通过代价值确定优选的 目标连接路径，从而提高芯片整体的端口与引脚之间的连接数量。
在一种可能的实现中，所述端口为输入输出I/O单元，所述引脚为转接单元bump。
在一种可能的实现中，所述装置还包括：
走线确定模块2303，用于根据所述代价值，从所述多个候选连接路径中确定至少一个目标连接路径；或者，
发送模块中继点的位置信息，用于向终端设备发送所述代价值，所述代价值用于指示所述终端设备从所述多个候选连接路径中确定至少一个目标连接路径。
在一种可能的实现中，所述代价值用于指示候选连接路径对所述多个端口和所述多个引脚之间总连接路径的数量的负向影响；所述多个候选连接路径包括多组候选连接路径，所述多组候选连接路径中的每组候选连接路径对应于一对端口和引脚；
所述走线确定模块2303，具体用于：
根据所述代价值，从所述每组候选连接路径中确定代价值最低的候选连接路径为所述目标连接路径。
在一种可能的实现中，所述第一信息还指示如下信息的至少一种：端口的功能或端口的优先级；
所述第二信息还指示如下信息的至少一种：引脚的功能或引脚的优先级。
在一种可能的实现中，所述候选连接路径包括两端的端口和引脚、以及所述候选连接路径所经过的至少一个中继点，所述中继点为相邻引脚之间的中间位置点；
所述根据所述第一信息和所述第二信息，包括：
根据所述候选连接路径所包括的端口的第一信息、所述候选连接路径所包括的引脚的第二信息、以及所述至少一个中继点的位置信息。
在一种可能的实现中，所述多个端口包括多个第一端口以及多个第二端口，所述多个引脚包括多个第一引脚以及多个第二引脚，所述多个第一端口和所述多个第一引脚用于实现第一功能；所述多个第二端口和所述多个第二引脚用于实现第二功能，所述第一功能和所述第二功能不同；
所述多个候选连接路径包括所述多个第一端口和所述多个第一引脚之间形成的多个第一候选连接路径，以及所述多个第二端口和所述多个第二引脚之间形成的多个第二候选连接路径；
所述代价值确定模块2302，具体用于：根据所述多个第一候选连接路径的信息以及所述多个第二候选连接路径的信息，通过机器学习模型，得到每个所述第一候选连接路径的代价值；
所述走线确定模块2303，具体用于：根据所述每个所述第一候选连接路径的代价值，从所述多个第一候选连接路径中确定至少一个第一目标连接路径。
在一种可能的实现中，所述多个第一候选连接路径中的至少两个第一候选连接路径之间相交；或者，
每个所述第二候选连接路径与所述多个第一候选连接路径之间不相交；或者，
至少一个第二候选连接路径与多个第一候选连接路径中的至少一个第一候选连接路径 之间相交；或者，
所述多个第二候选连接路径中的至少两个第二候选连接路径之间相交。
在一种可能的实现中，所述装置还包括：
输出模块，用于输出所述多个第一端口和所述多个第一引脚之间的多个第一初始候选连接路径，并基于对所述多个第一初始候选连接路径中至少一个第一初始候选连接路径的修改指令，得到所述多个第一候选连接路径。
在一种可能的实现中，所述装置还包括：
输出模块中继点的位置信息，用于输出所述至少一个第一目标连接路径。
在一种可能的实现中，所述第一功能或所述第二功能为如下的一种：信号传输、接地、电能传输。
在一种可能的实现中，所述代价值确定模块2302，还用于：根据所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息，通过所述机器学习模型，得到每个所述第二候选连接路径的代价值；
所述走线确定模块2303，还用于：根据所述每个所述第二候选连接路径的代价值，从所述多个第二候选连接路径中确定至少一个第二目标连接路径。
在一种可能的实现中，在所述通过所述机器学习模型，得到每个所述第二候选连接路径的代价值时，所述多个第一候选连接路径中除所述至少一个第一目标连接路径之外的其他第一候选连接路径不作为所述机器学习模型的输入。
在一种可能的实现中，所述多个候选连接路径还包括所述多个第二端口和所述多个第二引脚之间形成的至少一个第三候选连接路径，所述代价值确定模块2302，具体用于：
根据所述至少一个第一目标连接路径的信息、所述多个第二候选连接路径以及至少一个第三候选连接路径的信息。
在一种可能的实现中，所述输出模块，还用于：
输出所述多个第二端口和所述多个第二引脚之间形成的多个第二初始候选连接路径，并基于对所述多个第二初始候选连接路径的修改指令，得到所述多个第二候选连接路径。
在一种可能的实现中，所述输出模块，还用于：
输出所述至少一个第二目标连接路径。
在一种可能的实现中，所述至少一个目标连接路径中的任意两个目标连接路径之间不相交。
在一种可能的实现中，所述获取模块2301，还用于：
基于对所述至少一个第一目标连接路径的修改信息，得到修改后的所述至少一个第一目标连接路径；
所述根据所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息，包括：根据所述修改后的所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息。
在一种可能的实现中，所述第一信息指示所述第一端口的优先级高于所述第二端口的优先级；或者，所述第二信息指示所述第一引脚的优先级高于所述第二引脚的优先级。
在一种可能的实现中，所述走线确定模块2303，具体用于：
根据所述代价值，通过最小代价最大流算法，从所述多个候选连接路径中确定至少一个目标连接路径。
参照图24，图24为本申请实施例提供的一种电路走线确定装置的结构示意，其中，所述装置2400，包括：
获取模块2401，用于获取电路的多个输入输出端口的第一信息、以及多个转接单元引脚的第二信息；所述多个端口包括多个第一端口以及多个第二端口，所述多个引脚包括多个第一引脚以及多个第二引脚；所述多个第一端口和所述多个第一引脚之间形成多个第一候选连接路径，所述多个第二端口和所述多个第二引脚之间形成多个第二候选连接路径；
其中，关于获取模块2301的具体描述可以参照上述实施例中步骤2201的描述，这里不再赘述。
走线确定模块2402，用于基于所述第一信息和所述第二信息指示所述第一端口的重要性高于所述第二端口的重要性，根据所述多个第一候选连接路径的信息以及多个第二候选连接路径的信息，从所述多个第一候选连接路径中确定至少一个第一目标连接路径；根据所述至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，从所述多个第二候选连接路径中确定至少一个第二目标连接路径。
其中，关于走线确定模块2402的具体描述可以参照上述实施例中步骤2202的描述，这里不再赘述。
在一种可能的实现中，所述端口为输入输出I/O单元，所述引脚为转接单元bump。
在一种可能的实现中，所述多个第一候选连接路径中的至少两个第一候选连接路径之间相交；或者，
每个所述第二候选连接路径与所述多个第一候选连接路径之间不相交；或者，
至少一个第二候选连接路径与多个第一候选连接路径中的至少一个第一候选连接路径之间相交；或者，
所述多个第二候选连接路径中的至少两个第二候选连接路径之间相交。
在一种可能的实现中，所述装置还包括：
输出模块2403，用于输出所述多个第一端口和所述多个第一引脚之间形成的多个第一初始候选连接路径，并基于对所述多个第一初始候选连接路径的修改指令，得到所述多个第一候选连接路径。
在一种可能的实现中，所述装置还包括：
输出模块2403，用于输出所述至少一个第一目标连接路径。
在一种可能的实现中，所述第一功能或所述第二功能为如下的一种：信号传输、接地、电能传输。
在一种可能的实现中，所述根据所述至少一个第一目标连接路径的信息以及多个第二候选连接路径的信息，包括：
根据所述至少一个第一连接路径的信息以及多个第二候选连接路径的信息、且不根据所述多个第一候选连接路径中除所述至少一个第一目标连接路径之外的其他第一候选连接 路径。
在一种可能的实现中，所述输出模块2403，还用于：
输出所述多个第二端口和所述多个第二引脚之间形成的多个第二初始候选连接路径，并基于对所述多个第二初始候选连接路径的修改指令，得到所述多个第二候选连接路径。
在一种可能的实现中，所述输出模块2403，还用于：
输出所述至少一个第二目标连接路径。
在一种可能的实现中，所述至少一个第一目标连接路径中的任意两个连接路径之间不相交，所述至少一个第二目标连接路径中的任意两个连接路径之间不相交，每个所述第一目标连接路径与所述至少一个第二目标连接路径中的任意第二目标连接路径之间不相交。
在一种可能的实现中，所述获取模块2401，还用于：
基于对所述至少一个第一目标连接路径的修改信息，得到修改后的所述至少一个第一目标连接路径；
所述根据所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息，包括：根据所述修改后的所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息。
接下来介绍本申请实施例提供的一种执行设备，请参阅图25，图25为本申请实施例提供的执行设备的一种结构示意图，执行设备2500具体可以表现为手机、平板、笔记本电脑、智能穿戴设备等，此处不做限定。具体的，执行设备2500包括：接收器2501、发射器2502、处理器2503和存储器2504(其中执行设备2500中的处理器2503的数量可以一个或多个，图25中以一个处理器为例)，其中，处理器2503可以包括应用处理器25031和通信处理器25032。在本申请的一些实施例中，接收器2501、发射器2502、处理器2503和存储器2504可通过总线或其它方式连接。
存储器2504可以包括只读存储器和随机存取存储器，并向处理器2503提供指令和数据。存储器2504的一部分还可以包括非易失性随机存取存储器(non-volatile random access memory，NVRAM)。存储器2504存储有处理器和操作指令、可执行模块或者数据结构，或者它们的子集，或者它们的扩展集，其中，操作指令可包括各种操作指令，用于实现各种操作。
处理器2503控制执行设备的操作。具体的应用中，执行设备的各个组件通过总线系统耦合在一起，其中总线系统除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都称为总线系统。
上述本申请实施例揭示的方法可以应用于处理器2503中，或者由处理器2503实现。处理器2503可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器2503中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器2503可以是通用处理器、数字信号处理器(digital signal processing，DSP)、微处理器或微控制器，还可进一步包括专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。该处理器2503可以实现或者执行本申请实施例 中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器2504，处理器2503读取存储器2504中的信息，结合其硬件完成上述方法的步骤。
接收器2501可用于接收输入的数字或字符信息，以及产生与执行设备的相关设置以及功能控制有关的信号输入。发射器2502可用于输出数字或字符信息；发射器2502还可用于向磁盘组发送指令，以修改磁盘组中的数据。
本申请实施例中，在一种情况下，处理器2503，用于执行图7a以及图22对应实施例中的电路走线确定方法的步骤。
本申请实施例还提供了一种服务器，请参阅图26，图26是本申请实施例提供的服务器一种结构示意图，具体的，服务器2600由一个或多个服务器实现，服务器2600可因配置或性能不同而产生比较大的差异，可以包括一个或一个以上中央处理器(central processing units，CPU)2626(例如，一个或一个以上处理器)和存储器2632，一个或一个以上存储应用程序2642或数据2644的存储介质2630(例如一个或一个以上海量存储设备)。其中，存储器2632和存储介质2630可以是短暂存储或持久存储。存储在存储介质2630的程序可以包括一个或一个以上模块(图示没标出)，每个模块可以包括对服务器中的一系列指令操作。更进一步地，中央处理器2626可以设置为与存储介质2630通信，在服务器2600上执行存储介质2630中的一系列指令操作。
服务器2600还可以包括一个或一个以上电源2626，一个或一个以上有线或无线网络接口2650，一个或一个以上输入输出接口2658；或，一个或一个以上操作系统2641，例如Windows ServerTM，Mac OS XTM，UnixTM,LinuxTM，FreeBSDTM等等。
本申请实施例中，中央处理器2626，用于执行图7a以及图22对应实施例中的电路走线确定方法的步骤。
本申请实施例中还提供一种包括计算机可读指令的计算机程序产品，当其在计算机上运行时，使得计算机执行如前述执行设备所执行的步骤，或者，使得计算机执行如前述训练设备所执行的步骤。
本申请实施例中还提供一种计算机可读存储介质，该计算机可读存储介质中存储有用于进行信号处理的程序，当其在计算机上运行时，使得计算机执行如前述执行设备所执行的步骤，或者，使得计算机执行如前述训练设备所执行的步骤。
本申请实施例提供的执行设备、训练设备或终端设备具体可以为芯片，芯片包括：处理单元和通信单元，所述处理单元例如可以是处理器，所述通信单元例如可以是输入/输出接口、管脚或电路等。该处理单元可执行存储单元存储的计算机执行指令，以使执行设备内的芯片执行上述实施例描述的电路走线确定方法，或者，以使训练设备内的芯片执行上述实施例中与模型训练相关的步骤。可选地，所述存储单元为所述芯片内的存储单元，如寄存器、缓存等，所述存储单元还可以是所述无线接入设备端内的位于所述芯片外部的存 储单元，如只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)等。
具体的，请参阅图27，图27为本申请实施例提供的芯片的一种结构示意图，所述芯片可以表现为神经网络处理器NPU 2700，NPU 2700作为协处理器挂载到主CPU(Host CPU)上，由Host CPU分配任务。NPU的核心部分为运算电路2703，通过控制器2704控制运算电路2703提取存储器中的矩阵数据并进行乘法运算。
在一些实现中，运算电路2703内部包括多个处理单元(Process Engine,PE)。在一些实现中，运算电路2703是二维脉动阵列。运算电路2703还可以是一维脉动阵列或者能够执行例如乘法和加法这样的数学运算的其它电子线路。在一些实现中，运算电路2703是通用的矩阵处理器。
举例来说，假设有输入矩阵A，权重矩阵B，输出矩阵C。运算电路从权重存储器2702中取矩阵B相应的数据，并缓存在运算电路中每一个PE上。运算电路从输入存储器2701中取矩阵A数据与矩阵B进行矩阵运算，得到的矩阵的部分结果或最终结果，保存在累加器(accumulator)2708中。
统一存储器2706用于存放输入数据以及输出数据。权重数据直接通过存储单元访问控制器(Direct Memory Access Controller，DMAC)2705，DMAC被搬运到权重存储器2702中。输入数据也通过DMAC被搬运到统一存储器2706中。
BIU为Bus Interface Unit即，总线接口单元2710，用于AXI总线与DMAC和取指存储器(Instruction Fetch Buffer，IFB)2709的交互。
总线接口单元2710(Bus Interface Unit，简称BIU)，用于取指存储器2709从外部存储器获取指令，还用于存储单元访问控制器2705从外部存储器获取输入矩阵A或者权重矩阵B的原数据。
DMAC主要用于将外部存储器DDR中的输入数据搬运到统一存储器2706或将权重数据搬运到权重存储器2702中或将输入数据数据搬运到输入存储器2701中。
向量计算单元2707包括多个运算处理单元，在需要的情况下，对运算电路的输出做进一步处理，如向量乘，向量加，指数运算，对数运算，大小比较等等。主要用于神经网络中非卷积/全连接层网络计算，如Batch Normalization(批归一化)，像素级求和，对特征平面进行上采样等。
在一些实现中，向量计算单元2707能将经处理的输出的向量存储到统一存储器2706。例如，向量计算单元2707可以将线性函数；或，非线性函数应用到运算电路2703的输出，例如对卷积层提取的特征平面进行线性插值，再例如累加值的向量，用以生成激活值。在一些实现中，向量计算单元2707生成归一化的值、像素级求和的值，或二者均有。在一些实现中，处理过的输出的向量能够用作到运算电路2703的激活输入，例如用于在神经网络中的后续层中的使用。
控制器2704连接的取指存储器(instruction fetch buffer)2709，用于存储控制器2704使用的指令；
统一存储器2706，输入存储器2701，权重存储器2702以及取指存储器2709均为 On-Chip存储器。外部存储器私有于该NPU硬件架构。
其中，上述任一处提到的处理器，可以是一个通用中央处理器，微处理器，ASIC，或一个或多个用于控制上述程序执行的集成电路。
另外需说明的是，以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。另外，本申请提供的装置实施例附图中，模块之间的连接关系表示它们之间具有通信连接，具体可以实现为一条或多条通信总线或信号线。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本申请可借助软件加必需的通用硬件的方式来实现，当然也可以通过专用硬件包括专用集成电路、专用CPU、专用存储器、专用元器件等来实现。一般情况下，凡由计算机程序完成的功能都可以很容易地用相应的硬件来实现，而且，用来实现同一功能的具体硬件结构也可以是多种多样的，例如模拟电路、数字电路或专用电路等。但是，对本申请而言更多情况下软件程序实现是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在可读取的存储介质中，如计算机的软盘、U盘、移动硬盘、ROM、RAM、磁碟或者光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，训练设备，或者网络设备等)执行本申请各个实施例所述的方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。
所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、训练设备或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、训练设备或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的训练设备、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(Solid State Disk，SSD))等。

Claims (37)

  1. 一种电路走线确定方法，其特征在于，所述方法包括：
    获取电路的多个端口的第一信息、以及多个引脚的第二信息；所述多个端口和所述多个引脚之间包括多个候选连接路径；所述候选连接路径为端口和引脚之间的连接路径，所述第一信息指示端口的位置特征，所述第二信息指示引脚的位置特征；
    根据所述第一信息和所述第二信息，通过机器学习模型，得到每个所述候选连接路径的代价值，所述代价值指示候选连接路径对所述多个端口和所述多个引脚之间总连接路径的数量的影响；所述代价值用于从所述多个候选连接路径中确定至少一个目标连接路径。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    根据所述代价值，从所述多个候选连接路径中确定至少一个目标连接路径；或者，
    向终端设备发送所述代价值，所述代价值用于指示所述终端设备根据所述代价值，从所述多个候选连接路径中确定至少一个目标连接路径。
  3. 根据权利要求2所述的方法，其特征在于，所述多个端口包括多个第一端口以及多个第二端口，所述多个引脚包括多个第一引脚以及多个第二引脚，所述多个第一端口和所述多个第一引脚用于实现第一功能；所述多个第二端口和所述多个第二引脚用于实现第二功能，所述第一功能和所述第二功能不同；
    所述多个候选连接路径包括所述多个第一端口和所述多个第一引脚之间形成的多个第一候选连接路径，以及所述多个第二端口和所述多个第二引脚之间形成的多个第二候选连接路径；
    所述根据所述第一信息和所述第二信息，通过机器学习模型，得到每个所述候选连接路径的代价值，包括：根据所述多个第一候选连接路径的信息以及所述多个第二候选连接路径的信息，通过机器学习模型，得到每个所述第一候选连接路径的代价值；
    所述根据所述代价值，从所述多个候选连接路径中确定至少一个目标连接路径，包括：根据所述每个所述第一候选连接路径的代价值，从所述多个第一候选连接路径中确定至少一个第一目标连接路径。
  4. 根据权利要求3所述的方法，其特征在于，所述根据所述第一信息和所述第二信息，通过机器学习模型，得到每个所述候选连接路径的代价值，还包括：根据所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息，通过所述机器学习模型，得到每个所述第二候选连接路径的代价值；
    所述根据所述代价值，从所述多个候选连接路径中确定至少一个目标连接路径，还包括：根据所述每个所述第二候选连接路径的代价值，从所述多个第二候选连接路径中确定至少一个第二目标连接路径。
  5. 根据权利要求4所述的方法，其特征在于，
    每个所述第二候选连接路径与所述多个第一候选连接路径之间不相交。
  6. 根据权利要求5所述的方法，其特征在于，所述多个候选连接路径还包括所述多个第二端口和所述多个第二引脚之间形成的至少一个第三候选连接路径，所述至少一个第三候选连接路径与所述多个第一候选连接路径中除所述至少一个第一目标连接路径之外的其他第一候选连接路径之间相交，所述根据所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息，包括：
    根据所述至少一个第一目标连接路径的信息、所述多个第二候选连接路径以及至少一个第三候选连接路径的信息。
  7. 根据权利要求4至6任一所述的方法，其特征在于，
    每个所述第二目标连接路径与所述至少一个第一目标连接路径之间不相交。
  8. 根据权利要求4至7任一所述的方法，其特征在于，所述方法还包括：
    基于对所述至少一个第一目标连接路径的修改信息，得到修改后的所述至少一个第一目标连接路径；
    所述根据所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息，包括：根据所述修改后的所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息。
  9. 根据权利要求4至8任一所述的方法，其特征在于，所述方法还包括：
    输出所述至少一个第二目标连接路径。
  10. 根据权利要求3至9任一所述的方法，其特征在于，所述方法还包括：
    输出所述至少一个第一目标连接路径。
  11. 根据权利要求3至10任一所述的方法，其特征在于，所述第一功能或所述第二功能为如下的一种：信号传输、接地、电能传输。
  12. 根据权利要求3至11任一所述的方法，其特征在于，所述第一信息指示所述第一端口的优先级高于所述第二端口的优先级；或者，所述第二信息指示所述第一引脚的优先级高于所述第二引脚的优先级。
  13. 根据权利要求2至12任一所述的方法，其特征在于，所述代价值用于指示候选连接路径对所述多个端口和所述多个引脚之间总连接路径的数量的负向影响；所述多个候选连接路径包括多组候选连接路径，所述多组候选连接路径中的每组候选连接路径对应于一对端口和引脚；
    所述根据所述代价值，从所述多个候选连接路径中确定至少一个目标连接路径，包括：
    根据所述代价值，从所述每组候选连接路径中确定代价值最低的候选连接路径为所述目标连接路径。
  14. 根据权利要求2至13任一所述的方法，其特征在于，所述根据所述代价值，从所述多个候选连接路径中确定至少一个目标连接路径，包括：
    根据所述代价值，通过最小代价最大流算法，从所述多个候选连接路径中确定至少一个目标连接路径。
  15. 根据权利要求1至14任一所述的方法，其特征在于，所述第一信息还指示如下信息的至少一种：端口的功能或端口的优先级；
    所述第二信息还指示如下信息的至少一种：引脚的功能或引脚的优先级。
  16. 根据权利要求1至15任一所述的方法，其特征在于，所述候选连接路径包括两端的端口和引脚、以及所述候选连接路径所经过的至少一个中继点，所述中继点为相邻引脚之间的中间位置点；
    所述根据所述第一信息和所述第二信息，包括：
    根据所述候选连接路径所包括的端口的第一信息、所述候选连接路径所包括的引脚的第二信息、以及所述至少一个中继点的位置信息。
  17. 根据权利要求1至16任一所述的方法，其特征在于，所述端口为输入输出I/O单元，所述引脚为转接单元bump。
  18. 一种电路走线确定装置，其特征在于，所述装置包括：
    获取模块，用于获取电路的多个端口的第一信息、以及多个引脚的第二信息；所述多个端口和所述多个引脚之间包括多个候选连接路径；所述候选连接路径为端口和引脚之间的连接路径，所述第一信息指示端口的位置特征，所述第二信息指示引脚的位置特征；
    代价值确定模块，用于根据所述第一信息和所述第二信息，通过机器学习模型，得到每个所述候选连接路径的代价值，所述代价值指示候选连接路径对所述多个端口和所述多个引脚之间总连接路径的数量的影响；所述代价值用于从所述多个候选连接路径中确定至少一个目标连接路径。
  19. 根据权利要求18所述的装置，其特征在于，所述装置还包括：
    走线确定模块，用于根据所述代价值，从所述多个候选连接路径中确定至少一个目标连接路径；或者，
    发送模块，用于向终端设备发送所述代价值，所述代价值用于指示所述终端设备从所述多个候选连接路径中确定至少一个目标连接路径。
  20. 根据权利要求19所述的装置，其特征在于，所述多个端口包括多个第一端口以及多个第二端口，所述多个引脚包括多个第一引脚以及多个第二引脚，所述多个第一端口和所述多个第一引脚用于实现第一功能；所述多个第二端口和所述多个第二引脚用于实现第二功能，所述第一功能和所述第二功能不同；
    所述多个候选连接路径包括所述多个第一端口和所述多个第一引脚之间形成的多个第一候选连接路径，以及所述多个第二端口和所述多个第二引脚之间形成的多个第二候选连接路径；
    所述代价值确定模块，具体用于：根据所述多个第一候选连接路径的信息以及所述多个第二候选连接路径的信息，通过机器学习模型，得到每个所述第一候选连接路径的代价值；
    所述走线确定模块，具体用于：根据所述每个所述第一候选连接路径的代价值，从所述多个第一候选连接路径中确定至少一个第一目标连接路径。
  21. 根据权利要求20所述的装置，其特征在于，所述代价值确定模块，还用于：根据所述至少一个第一目标连接路径的信息以及所述多个第二候选连接路径的信息，通过所述机器学习模型，得到每个所述第二候选连接路径的代价值；
    所述走线确定模块，还用于：根据所述每个所述第二候选连接路径的代价值，从所述多个第二候选连接路径中确定至少一个第二目标连接路径。
  22. 根据权利要求21所述的装置，其特征在于，
    每个所述第二候选连接路径与所述多个第一候选连接路径之间不相交。
  23. 根据权利要求22所述的装置，其特征在于，所述多个候选连接路径还包括所述多个第二端口和所述多个第二引脚之间形成的至少一个第三候选连接路径，所述至少一个第三候选连接路径与所述多个第一候选连接路径中除所述至少一个第一目标连接路径之外的其他第一候选连接路径之间相交，所述代价值确定模块，具体用于：
    根据所述至少一个第一目标连接路径的信息、所述多个第二候选连接路径以及至少一个第三候选连接路径的信息。
  24. 根据权利要求21至23任一所述的装置，其特征在于，
    每个所述第二目标连接路径与所述至少一个第一目标连接路径之间不相交。
  25. 根据权利要求21至24任一所述的装置，其特征在于，所述获取模块，还用于：
    基于对所述至少一个第一目标连接路径的修改信息，得到修改后的所述至少一个第一目标连接路径；
    所述代价值确定模块，具体用于：根据所述修改后的所述至少一个第一目标连接路径 的信息以及所述多个第二候选连接路径的信息。
  26. 根据权利要求21至25任一所述的装置，其特征在于，所述装置还包括：
    输出模块，用于输出所述至少一个第二目标连接路径。
  27. 根据权利要求20至26任一所述的装置，其特征在于，所述输出模块，还用于：
    输出所述至少一个第一目标连接路径。
  28. 根据权利要求25至30任一所述的装置，其特征在于，所述第一功能或所述第二功能为如下的一种：信号传输、接地、电能传输。
  29. 根据权利要求20至28任一所述的装置，其特征在于，所述第一信息指示所述第一端口的优先级高于所述第二端口的优先级；或者，所述第二信息指示所述第一引脚的优先级高于所述第二引脚的优先级。
  30. 根据权利要求19至29任一所述的装置，其特征在于，所述代价值用于指示候选连接路径对所述多个端口和所述多个引脚之间总连接路径的数量的负向影响；所述多个候选连接路径包括多组候选连接路径，所述多组候选连接路径中的每组候选连接路径对应于一对端口和引脚；
    所述走线确定模块，具体用于：
    根据所述代价值，从所述每组候选连接路径中确定代价值最低的候选连接路径为所述目标连接路径。
  31. 根据权利要求19至30任一所述的装置，其特征在于，所述走线确定模块，具体用于：
    根据所述代价值，通过最小代价最大流算法，从所述多个候选连接路径中确定至少一个目标连接路径。
  32. 根据权利要求18至31任一所述的装置，其特征在于，所述第一信息还指示如下信息的至少一种：端口的功能或端口的优先级；
    所述第二信息还指示如下信息的至少一种：引脚的功能或引脚的优先级。
  33. 根据权利要求18至32任一所述的装置，其特征在于，所述候选连接路径包括两端的端口和引脚、以及所述候选连接路径所经过的至少一个中继点，所述中继点为相邻引脚之间的中间位置点；
    所述根据所述第一信息和所述第二信息，包括：
    根据所述候选连接路径所包括的端口的第一信息、所述候选连接路径所包括的引脚的 第二信息、以及所述至少一个中继点的位置信息。
  34. 根据权利要求18至33任一所述的装置，其特征在于，所述端口为输入输出I/O单元，所述引脚为转接单元bump。
  35. 一种电路走线确定装置，其特征在于，所述装置包括存储器和处理器；所述存储器存储有代码，所述处理器被配置为获取所述代码，并执行如权利要求1至17任一所述的方法。
  36. 一种计算机可读存储介质，其特征在于，包括计算机可读指令，当所述计算机可读指令在计算机设备上运行时，使得所述计算机设备执行权利要求1至17任一项所述的方法。
  37. 一种计算机程序产品，其特征在于，包括计算机可读指令，当所述计算机可读指令在计算机设备上运行时，使得所述计算机设备执行如权利要求1至17任一所述的方法。
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* Cited by examiner, † Cited by third party
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