WO2023207456A1 - Procédé et appareil de transmission de commande - Google Patents

Procédé et appareil de transmission de commande Download PDF

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Publication number
WO2023207456A1
WO2023207456A1 PCT/CN2023/083662 CN2023083662W WO2023207456A1 WO 2023207456 A1 WO2023207456 A1 WO 2023207456A1 CN 2023083662 W CN2023083662 W CN 2023083662W WO 2023207456 A1 WO2023207456 A1 WO 2023207456A1
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WIPO (PCT)
Prior art keywords
command
work queue
transmission mode
information
cache
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Application number
PCT/CN2023/083662
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English (en)
Chinese (zh)
Inventor
李瑛�
程中武
李力军
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华为技术有限公司
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Publication of WO2023207456A1 publication Critical patent/WO2023207456A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/542—Event management; Broadcasting; Multicasting; Notifications
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues

Definitions

  • the present application relates to the field of chip technology, and more specifically, to a command transmission method and device.
  • DSA domain special accelerate
  • DSA can offload typical data processing to reduce CPU usage, thereby improving the overall performance of the system.
  • the encryption and decryption engine can implement encryption and decryption operations
  • the hash engine can implement hash operations
  • the codec engine can implement video encoding and decoding.
  • DSA can obtain commands from the CPU and execute the commands to achieve the above various data processing.
  • the CPU can issue at least one command to the DSA through an asynchronous mode or a synchronous mode.
  • the asynchronous mode means that the at least one command and the notification message of the at least one command are respectively sent to the DSA.
  • the synchronous mode means that the at least one command is sent to the DSA.
  • the command is carried in the notification message of the at least one command and is sent to the DSA together.
  • This application provides a command transmission method, which can transmit commands in asynchronous mode or synchronous mode through a set of message interfaces, which can improve the flexibility of command transmission.
  • this application provides a command transmission method, which can be used for a central processor.
  • the method can include: generating a notification message, the notification message being used to notify the accelerator to execute the first command, the notification message including the first work
  • the first work queue cache is used to store the first command.
  • the first address information is used to indicate that the first command is stored in the first work queue cache.
  • the first transmission mode information is used to indicate the transmission mode of the first command.
  • the transmission mode includes a synchronous mode or an asynchronous mode. When the transmission mode of the first command is the synchronous mode, the notification The message also includes the first command; sending the notification message to the accelerator.
  • the central processor can indicate the transmission mode of the first command through the first transmission mode information in the notification message.
  • the central processor can use the identification information cached by the first work queue in the notification message and The first address information indicates the storage address of the first command in the memory.
  • the transmission mode of the first command is the synchronous mode
  • the first command can be carried through the notification message.
  • the accelerator may obtain the first command and execute the first command based on the notification message.
  • commands can be transmitted between the central processor and the accelerator through a set of message interfaces in asynchronous mode or synchronous mode. In this way, the central processor can select the command according to the characteristics of the command. By choosing an appropriate method for delivery, you can retain the flexibility of command delivery and gain the benefit of quickly processing short commands.
  • the notification message is also used to notify the accelerator to execute the second command.
  • the notification message also includes the identification information cached by the second work queue, the second address information and the second transmission mode information.
  • the second work queue cache is used to store the second command
  • the second address information is used to indicate the storage address of the second command in the second work queue cache
  • the second transmission mode information is used to indicate the storage address of the second command. Transmission mode.
  • the transmission mode of the first command is different from the transmission mode of the second command.
  • the notification message also includes the second command.
  • the central processor can transmit commands compatible with asynchronous mode and synchronous mode through a set of message interfaces. That is to say, synchronous mode and asynchronous mode can be operated in combination, thereby improving the flexibility of command transmission. .
  • the first work queue cache and the second work queue cache are the same, and the storage address of the first command in the first work queue cache is the same as the storage address of the second command in the first work queue.
  • the storage addresses in the cache are different; or, the first work queue cache and the second work queue cache are different.
  • the different commands can share the same work queue cache through the first address information in the notification message, thereby achieving collaborative work.
  • the first command includes multiple commands
  • the second command includes multiple commands
  • the central processor can issue multiple commands in batches in asynchronous mode through a set of message interfaces, and/or, issue multiple commands in batches in synchronous mode, which can improve the flexibility of command transmission. sex and efficiency.
  • the notification message also includes a first identification field, a first address field, a first transmission mode field, and a first command field.
  • the first identification field is used to carry the first work queue cache.
  • the identification information and the first address field are used to carry the first address information
  • the first transmission mode field is used to carry the first transmission mode information
  • the first command field is used to carry the first command.
  • the central processor can distinguish the transmission mode adopted by each command as a synchronous mode or an asynchronous mode through a unified format notification message, without modifying the central processor or requiring additional instructions.
  • the method may further include: writing the first command based on the first target address information. into the memory, and the first target address information is used to indicate the storage address of the first command in the memory.
  • this application also provides a command transmission method, which can be used for an accelerator.
  • the method can include: receiving a notification message from the processor, the notification message being used to notify the accelerator to execute the first command, the notification message including The first work queue buffers the identification information, the first address information and the first transmission mode information.
  • the first work queue buffer is used to store the first command.
  • the first address information is used to indicate that the first command is in the first The storage address in the work queue cache.
  • the first transmission mode information is used to indicate the transmission mode of the first command.
  • the transmission mode includes a synchronous mode or an asynchronous mode. When the transmission mode of the first command is the synchronous mode, , the notification message also includes the first command; based on the notification message, the first command is obtained; and the first command is executed.
  • the central processor can indicate the transmission mode of the first command through the first transmission mode information in the notification message.
  • the central processor can use the identification information cached by the first work queue in the notification message and The first address information indicates the storage address of the first command in the memory.
  • the transmission mode of the first command is the synchronous mode
  • the first command can be carried through the notification message.
  • the accelerator may obtain the first command and execute the first command based on the notification message.
  • commands can be transmitted between the central processor and the accelerator through a set of message interfaces in asynchronous mode or synchronous mode. In this way, the central processor can choose the appropriate method to issue the command according to the characteristics of the command, and can retain the command issuance. The flexibility can gain the benefit of fast processing of short commands.
  • the notification message is also used to notify the accelerator to execute the second command.
  • the notification message also includes the identification information cached by the second work queue, the second address information and the second transmission mode information.
  • the second work queue cache is used to store the second command
  • the second address information is used to indicate the storage address of the second command in the second work queue cache
  • the second transmission mode information is used to indicate the storage address of the second command.
  • Transmission mode, the transmission mode of the first command is different from the transmission mode of the second command, wherein when the transmission mode of the second command is the synchronization mode, the notification message also includes the second command, and the method further includes : Based on the notification message, obtain the second command; execute the second command.
  • the central processor can transmit commands compatible with asynchronous mode and synchronous mode through a set of message interfaces. That is to say, synchronous mode and asynchronous mode can be operated in combination, thereby improving the flexibility of command transmission. .
  • the first work queue cache is the same as the second work queue cache, but the storage address of the first command in the first work queue cache is the same as the storage address of the second command in the first work queue cache.
  • the storage addresses in the queue cache are different; or, the first work queue cache and the second work queue cache are different.
  • the different commands can share the same work queue cache through the first address information in the notification message, thereby achieving collaborative work.
  • the first command includes multiple commands
  • the second command includes multiple commands
  • the central processor can issue multiple commands in batches in asynchronous mode through a set of message interfaces, and/or, issue multiple commands in batches in synchronous mode, which can improve the flexibility of command transmission. sex and efficiency.
  • the notification message also includes a first identification field, a first address field, a first transmission mode field, and a first command field.
  • the first identification field is used to carry the first work queue cache.
  • the identification information and the first address field are used to carry the first address information
  • the first transmission mode field is used to carry the first transmission mode information
  • the first command field is used to carry the first command.
  • obtaining the first command based on the notification message includes: based on the identification information cached in the first work queue, the first address information and the first transmission mode information, from the memory Read the first command in .
  • the central processor can distinguish the transmission mode adopted by each command as a synchronous mode or an asynchronous mode through a unified format notification message, without modifying the central processor or requiring additional instructions.
  • reading the first command from the memory based on the identification information cached by the first work queue, the first address information and the first transmission mode information includes: when the first A transmission mode information is used to indicate that the transmission mode of the first command is the synchronous mode, but when the first command cannot be written to the command cache queue of the accelerator, based on the identification information cached in the first work queue and the first address Information, the first command is read from this memory.
  • the asynchronous mode can be further used to read the first command from the memory.
  • the asynchronous mode can be used to solve the problem of command transmission failure caused by the storage space size of the command queue cache in the accelerator or the processing speed of the accelerator in the synchronous mode, thereby improving the performance of the central processor.
  • reading the first command from the memory based on the identification information cached by the first work queue and the first address information includes: based on the identification information cached by the first work queue , the first address information and the preset mapping relationship determine the first target address information.
  • the mapping relationship is used to indicate the identification information cached by the first work queue and the storage address cached by the first work queue in the memory.
  • the first target address information is used to indicate the storage address of the first command in the memory; based on the first target address information, the first command is read from the memory.
  • mapping relationship may be pre-configured in the accelerator, or the accelerator may obtain the mapping relationship from other devices in advance, which is not limited in the embodiments of the present application.
  • the accelerator obtains the mapping relationship in advance, that is, the notification message does not need to carry the mapping relationship, which can reduce the amount of transmitted data and thereby improve transmission efficiency.
  • the method before reading the first command from the memory based on the first target address information, the method further includes: writing the first command based on the first target address information. into this memory.
  • the accelerator writes the first command into the memory, Then the first command is read from the memory, so that the asynchronous mode can be used to handle scenarios that the synchronous mode cannot handle.
  • reading the first command from the memory based on the identification information cached by the first work queue, the first address information and the first transmission mode information includes: when the first When a transmission mode information is used to indicate that the transmission mode of the first command is the asynchronous mode, the first command is read from the memory based on the identification information cached in the first work queue and the first address information.
  • the accelerator can cache based on the identification information of the first work queue and the third Using address information and reading the first command from the memory can reduce the storage space requirements of the accelerator and reduce the processing complexity of the accelerator.
  • obtaining the first command based on the notification message includes: when the first transmission mode information is used to indicate that the transmission mode of the first command is the synchronization mode, and the first command When the command cache queue of the accelerator can be written, the first command is read from the command cache queue.
  • the first transmission mode information is used to indicate that the transmission mode of the first command is the synchronous mode
  • the first command can be written into the command cache queue of the accelerator, from Reading the first command from the command cache queue can reduce interaction overhead, thereby improving command transmission efficiency.
  • the method before reading the first command from the command cache queue, the method further includes: writing the first command into the command cache queue.
  • this application also provides a command transmission device.
  • the device may include: a processor and a communication interface.
  • the processor is coupled to the communication interface.
  • the processor is used to: generate a notification message, and the notification message is used to notify the accelerator.
  • the notification message includes identification information, first address information and first transmission mode information of the first work queue cache.
  • the first work queue cache is used to store the first command.
  • the first address information is used to store the first command.
  • the transmission mode includes a synchronous mode or an asynchronous mode, wherein when the first When the command transmission mode is the synchronous mode, the notification message also includes the first command; the notification message is sent to the accelerator through the communication interface.
  • the notification message is also used to notify the accelerator to execute the second command.
  • the notification message also includes the identification information cached by the second work queue, the second address information and the second transmission mode information.
  • the second work queue cache is used to store the second command
  • the second address information is used to indicate the storage address of the second command in the second work queue cache
  • the second transmission mode information is used to indicate the storage address of the second command. Transmission mode.
  • the transmission mode of the first command is different from the transmission mode of the second command.
  • the notification message also includes the second command.
  • the first work queue cache and the second work queue cache are the same, and the storage address of the first command in the first work queue cache is the same as the storage address of the second command in the first work queue.
  • the storage addresses in the cache are different; or, the first work queue cache and the second work queue cache are different.
  • the first command includes multiple commands
  • the second command includes multiple commands
  • the notification message also includes a first identification field, a first address field, a first transmission mode field, and a first command field.
  • the first identification field is used to carry the first work queue cache.
  • the identification information and the first address field are used to carry the first address information
  • the first transmission mode field is used to carry the first transmission mode information
  • the first command field is used to carry the first command.
  • the processor is further configured to: when the first transmission mode information is used to indicate that the transmission mode of the first command is an asynchronous mode, based on the first target address information, transfer the first command to Written into the memory, the first target address information is used to indicate the storage address of the first command in the memory.
  • this application also provides a command transmission device.
  • the device may include: a processor and a communication interface.
  • the processor is coupled to the communication interface.
  • the processor is configured to: receive a notification message from the processor through the communication interface.
  • the notification message is used to notify the accelerator to execute the first command.
  • the notification message includes the identification information, the first address information and the first transmission mode information of the first work queue cache.
  • the first work queue cache is used to store the first command.
  • the first address information is used to indicate the storage address of the first command in the first work queue cache
  • the first transmission mode information is used to indicate the transmission mode of the first command.
  • the transmission mode includes synchronous mode or asynchronous mode. mode, wherein when the transmission mode of the first command is the synchronous mode, the notification message also includes the first command; based on the notification message, the first command is obtained; and the first command is executed.
  • the notification message is also used to notify the accelerator to execute the second command.
  • the notification message also includes the identification information cached by the second work queue, the second address information and the second transmission mode information.
  • the second work queue cache is used to store the second command
  • the second address information is used to indicate the storage address of the second command in the second work queue cache
  • the second transmission mode information is used to indicate the storage address of the second command.
  • transmission mode the transmission of the first command
  • the transmission mode is different from the transmission mode of the second command, wherein when the transmission mode of the second command is the synchronous mode, the notification message also includes the second command, and the processor is further configured to: based on the notification message, Obtain the second command; execute the second command.
  • the first work queue cache is the same as the second work queue cache, but the storage address of the first command in the first work queue cache is the same as the storage address of the second command in the first work queue cache.
  • the storage addresses in the queue cache are different; or, the first work queue cache and the second work queue cache are different.
  • the first command includes multiple commands
  • the second command includes multiple commands
  • the notification message also includes a first identification field, a first address field, a first transmission mode field, and a first command field.
  • the first identification field is used to carry the first work queue cache.
  • the identification information and the first address field are used to carry the first address information
  • the first transmission mode field is used to carry the first transmission mode information
  • the first command field is used to carry the first command.
  • the processor is specifically configured to: read the first command from the memory based on the identification information cached in the first work queue, the first address information and the first transmission mode information. .
  • the processor is specifically configured to: when the first transmission mode information is used to indicate that the transmission mode of the first command is the synchronous mode, but the first command cannot write a command of the accelerator When caching the queue, the first command is read from the memory based on the cached identification information of the first work queue and the first address information.
  • the processor is specifically configured to: determine the first target address information based on the identification information cached by the first work queue, the first address information and a preset mapping relationship, where the mapping relationship is In order to indicate the correspondence between the identification information cached by the first work queue and the storage address of the first work queue cache in the memory, the first target address information is used to indicate the storage of the first command in the memory. address; based on the first target address information, read the first command from the memory.
  • the processor is further configured to: before reading the first command from the memory based on the first target address information, read the first command based on the first target address information. The command is written to this memory.
  • the processor is specifically configured to: when the first transmission mode information is used to indicate that the transmission mode of the first command is the asynchronous mode, based on the identification information cached in the first work queue and The first address information reads the first command from the memory.
  • the processor is specifically configured to: when the first transmission mode information is used to indicate that the transmission mode of the first command is the synchronous mode, and the first command can write a command of the accelerator When the queue is cached, the first command is read from the command cache queue.
  • the processor is further configured to write the first command into the command cache queue before reading the first command from the command cache queue.
  • the present application also provides a command transmission device, which may include units for implementing the methods described in the above aspects or various possible implementations thereof.
  • the present application also provides a computer-readable storage medium, which stores a computer program.
  • the computer program When executed by at least one processor, the computer program is used to implement the above aspects or any possible implementation thereof. The method described in the method.
  • the present application also provides a computer program product, which when executed by at least one processor is used to implement the methods described in the above aspects or any possible implementation manner thereof.
  • the command transmission device, computer storage medium and computer program product provided by this application are all used to execute the command transmission method provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects of the command transmission method provided above. The effect will not be described here.
  • Figure 1 is a schematic block diagram of a command transmission system 100 provided by an embodiment of the present application.
  • Figure 2 is a schematic flow chart of the command transmission method 200 provided by the embodiment of the present application.
  • FIG. 3 is a schematic diagram of the format of the notification message provided by the embodiment of the present application.
  • Figure 4 is a schematic flow chart of the command transmission method 300 provided by the embodiment of the present application.
  • Figure 5 is a schematic flow chart of the command transmission method 400 provided by the embodiment of the present application.
  • Figure 6 is a schematic block diagram of the command transmission device 500 provided by the embodiment of the present application.
  • Figure 7 is a schematic block diagram of the command transmission device 600 provided by the embodiment of the present application.
  • Figure 8 is a schematic block diagram of the command transmission device 700 provided by the embodiment of the present application.
  • FIG. 9 is a schematic block diagram of a command transmission device 800 provided by an embodiment of the present application.
  • At least one (item) refers to one or more, and “plurality” refers to two or more.
  • “And/or” is used to describe the relationship between associated objects, indicating that there can be three relationships. For example, “A and/or B” can mean: only A exists, only B exists, and A and B exist simultaneously. , where A and B can be singular or plural. The character “/” generally indicates that the related objects are in an "or” relationship. “At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • At least one of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c” ”, where a, b, c can be single or multiple.
  • the command transmission method in asynchronous mode may include the following steps (1) to (5):
  • the CPU writes command 1 into the work queue cache 1 in the DDR.
  • the DDR may include at least one work queue cache, and the at least one work queue cache includes the work queue cache 1.
  • the CPU sends a notification message to the DSA, and the notification message includes the index of the work queue cache 1; accordingly, the DSA receives the notification message from the CPU.
  • the DSA determines the address information based on the index of the work queue cache 1 and the preset mapping relationship.
  • the address information is used to indicate the storage address of the work queue cache 1 in the DDR.
  • the mapping relationship is used to indicate the Correspondence between the index of work queue cache 1 and the storage address of work queue cache 1 in the DDR.
  • the DSA reads the command 1 from the work queue cache 1 based on the address information.
  • the CPU can carry the index of the work queue cache corresponding to the batch command through the notification message, and write the batch command into the corresponding work queue cache in the memory; accordingly, the DSA reads the batch command from the memory based on the notification message. Reading the batch command and executing it is not limited in this application.
  • commands and notification messages are transmitted asynchronously, providing greater flexibility.
  • DSA needs to first receive the notification message sent by the CPU, and then read the command from the DDR based on the notification message. There is a lot of interaction and high overhead. Especially when the data volume of the command is small, the overhead accounts for a larger proportion, which will cause the command to The transmission efficiency is poor.
  • the command transmission method in synchronous mode may include the following steps (a) to (f):
  • the CPU sends a command enqueuing instruction to the DSA.
  • the command enqueuing instruction is used to instruct command 2 to be saved to the command queue cache in the DSA.
  • the command enqueuing instruction includes the command 2; accordingly, the DSA receives from This command is queued to the instruction for this CPU.
  • the DSA determines the reception result of the command 2 based on the data amount of the command 2 and the storage space of the command queue cache, and the reception result includes reception success or reception failure.
  • the DSA continues to perform steps (d) to (e); if the reception result is a reception failure, the DSA waits for further instructions from the CPU to reacquire the command 2.
  • the DSA reads the command 2 from the command queue cache.
  • the CPU can carry batch commands through the command queue cache; accordingly, if the batch commands are received successfully, the DSA can read the batch commands from the command queue cache and execute them, which is not limited in this application.
  • the interaction is simple and the overhead is small. Especially when the data volume of the command is small, the overhead is relatively small, which can improve the efficiency of command transmission.
  • using synchronous mode to transmit commands will be limited by the storage space of the command queue cache in the DSA and the processing speed of the DSA. That is to say, the storage space of the command queue cache is small or the processing speed of the DSA is slow. Scenarios that may cause command reception to fail.
  • Figure 1 shows a schematic block diagram of a command transmission system 100 provided by an embodiment of the present application.
  • the system 100 may include: a central processing unit (CPU) 110 and an accelerator 120, wherein the CPU 110 may include an interface a1, the accelerator 120 may include an interface b1, the CPU 110 and the accelerator 120. Commands can be transmitted between accelerators 120 through the interface a1 and the interface b1.
  • CPU central processing unit
  • accelerator 120 may include an interface b1
  • the CPU 110 and the accelerator 120 can be transmitted between accelerators 120 through the interface a1 and the interface b1.
  • the accelerator 120 may be a DSA, such as an encryption and decryption engine, a hash engine, a codec engine, etc.
  • the system 100 may also include a memory 130.
  • the memory 130 may include an interface c1 and an interface c2.
  • the central processor 110 may also include an interface a2.
  • the accelerator 120 may also include an interface b2.
  • the central processor 110 and Commands can be transmitted between the memory 130 through the interface a2 and the interface c1, and commands can be transmitted between the accelerator 120 and the memory 130 through the interface b2 and the interface c2.
  • the memory 130 may be DDR.
  • system 100 can be used on a chip.
  • the command transmission system provided by the embodiment of the present application is introduced above with reference to Figure 1.
  • the command transmission method provided by the embodiment of the present application will be further introduced below.
  • FIG. 2 shows a schematic flow chart of the message transmission method 200 provided by the embodiment of the present application.
  • the method 200 can be applied to the system 100 shown in FIG. 1 .
  • the method 200 may include the following steps. It should be noted that the steps listed below may be executed in various orders and/or occur simultaneously, and are not limited to the execution order shown in FIG. 2 .
  • the central processor generates a notification message.
  • the notification message is used to notify the accelerator to execute the first command.
  • the notification message includes the identification information cached by the first work queue, the first address information and the first transmission mode information.
  • the first work queue The cache is used to store the first command, the first address information is used to indicate the storage address of the first command in the first work queue cache, and the first transmission mode information is used to indicate the transmission mode of the first command,
  • the transmission mode includes a synchronous mode or an asynchronous mode, wherein when the transmission mode of the first command is the synchronous mode, the notification message also includes the first command.
  • this application does not limit the format of the notification message.
  • the notification message may also include a first identification field, a first address field and a first transmission mode field, where the first identification field is used to carry identification information cached by the first work queue. .
  • the first address field is used to carry the first address information
  • the first transmission mode field is used to carry the first transmission mode information.
  • the notification message may also include a first command field.
  • the first transmission mode information is used to indicate that the transmission mode of the first command is the synchronization mode
  • the first command field is used to carry the first command.
  • the first transmission mode information is used to indicate that the transmission mode of the first command is the asynchronous mode
  • the first command field is an invalid field.
  • Figure 3 shows a schematic format diagram of the notification message provided by the embodiment of the present application.
  • the notification message may include: a first identification field, a first address field, a first transmission mode field and a first command field.
  • the length of the first identification field is 16 bits
  • the length of the first address field is 16 bits.
  • the length is 32 bits
  • the length of the first transmission mode field is 1 bit
  • the length of the first command field is 463 bits.
  • the central processor can distinguish the transmission mode adopted by each command as a synchronous mode or an asynchronous mode through a unified format notification message, without modifying the central processor or requiring additional instructions.
  • the identification information can identify the first work queue cache in various ways, which is not limited in this application.
  • the identification information may include the number, name or index of the first work queue cache.
  • the memory includes work queue cache 1, work queue cache 2, ..., and work queue cache 5.
  • the first work queue cache is work queue cache 2.
  • the storage address of work queue cache 1 is: Add 0 ⁇ Add 1G.
  • the storage address of work queue cache 2 is: Add(1G+1k) ⁇ Add(2G+1k),...
  • the storage address of work queue cache 5 is: Add(4G+4k) ⁇ Add(5G+4k), where , work queue cache 1, work queue cache 2...work queue cache
  • the indexes of storage 5 are N1, N2,..., and N5.
  • the identification information can be "N2".
  • the first address information may indicate the storage address of the first command in the first work queue cache in various ways.
  • the first address information may include a storage address of the first command cached in the first work queue.
  • the first address information may be: Add(1G+3k) ⁇ Add(1G+5k).
  • the first work queue cache includes at least one storage area
  • the first address information may include an index of a storage area used to store the first command in the at least one storage area.
  • the storage addresses of the first work queue cache are: Add(1G+1k) ⁇ Add(2G+1k), and the first work queue cache is divided into storage area 1, storage area 2,..., storage areas. 5.
  • Storage area 2 is used to store the first command.
  • the indexes of storage area 1, storage area 2,..., and storage area 5 are respectively N2-Sub1, N2-Sub2,..., N2-Sub5.
  • the first command One address information can be "N2-Sub2".
  • this application does not limit the format of the command (such as the first command).
  • the format of existing commands please refer to the format of existing commands.
  • the command may include type information, address information, length information and command parameters.
  • the type information is used to indicate the command type of the command (such as read command, write command, encryption command, etc.)
  • the address information is used to indicate the storage address of the data to be processed
  • the length information is used to indicate the length of the data to be processed
  • the command parameters include parameters required during the execution of the command (such as the encryption algorithm used in encryption processing).
  • the notification message is also used to notify the accelerator to execute the second command.
  • the notification message also includes the identification information, the second address information and the second transmission mode information of the second work queue cache.
  • the second work queue cache uses When storing the second command, the second address information is used to indicate the storage address of the second command in the second work queue cache, the second transmission mode information is used to indicate the transmission mode of the second command, and the second transmission mode information is used to indicate the transmission mode of the second command.
  • the transmission mode of a command is different from the transmission mode of the second command, wherein when the transmission mode of the second command is the synchronization mode, the notification message also includes the second command.
  • the central processor can transmit commands compatible with asynchronous mode and synchronous mode through a set of message interfaces. That is to say, synchronous mode and asynchronous mode can be operated in combination, thereby improving the flexibility of command transmission. .
  • this application does not limit the storage locations of the first command and the second command.
  • the first work queue cache and the second work queue cache are the same, and the storage address of the first command in the first work queue cache is the same as the storage address of the second command in the first work queue.
  • the storage addresses in the cache are different.
  • the first work queue cache is different from the second work queue cache.
  • this application does not limit the number of commands included in the first command or the number of commands included in the second command.
  • the first command includes multiple commands.
  • the second command includes multiple commands.
  • the first command includes multiple commands
  • the second command includes multiple commands
  • the central processor can issue multiple commands in batches in asynchronous mode through a set of message interfaces, and/or, issue multiple commands in batches in synchronous mode, which can improve the flexibility of command transmission. sex and efficiency.
  • the central processor sends the notification message to the accelerator; accordingly, the accelerator receives the notification message from the central processor.
  • the method 200 may also include: the processor writes the first command based on the first target address information.
  • the first target address information is used to indicate the storage address of the first command in the memory, wherein the memory may include at least one work queue cache, and the at least one work queue cache includes the first work queue cache.
  • the central processor can indicate the transmission mode of the first command through the first transmission mode information in the notification message.
  • the central processor can use the identification information cached by the first work queue in the notification message and The first address information indicates the storage address of the first command in the memory.
  • the transmission mode of the first command is the synchronous mode
  • the first command can be carried through the notification message.
  • the accelerator may obtain the first command and execute the first command based on the notification message.
  • commands can be transmitted between the central processor and the accelerator through a set of message interfaces in asynchronous mode or synchronous mode. In this way, the central processor can choose the appropriate method to issue the command according to the characteristics of the command, and can retain the command issuance. The flexibility can gain the benefit of fast processing of short commands.
  • the accelerator obtains the first command based on the notification message.
  • S203 may include: reading the first command from the memory based on the identification information cached in the first work queue, the first address information, and the first transmission mode information.
  • reading the first command from the memory based on the identification information cached by the first work queue, the first address information and the first transmission mode information may include: when the When the first transmission mode information is used to indicate that the transmission mode of the first command is the asynchronous mode, the first command is read from the memory based on the identification information cached in the first work queue and the first address information.
  • the accelerator can cache based on the identification information of the first work queue and the third Using address information and reading the first command from the memory can reduce the storage space requirements of the accelerator and reduce the processing complexity of the accelerator.
  • reading the first command from the memory based on the identification information cached by the first work queue, the first address information and the first transmission mode information may include: The first transmission mode information is used to indicate that the transmission mode of the first command is the synchronous mode, but when the first command cannot be written to the command cache queue of the accelerator, based on the identification information cached in the first work queue and the third An address information is used to read the first command from the memory.
  • the asynchronous mode can be further used to read the first command from the memory.
  • the asynchronous mode can be used to solve the problem of command transmission failure caused by the storage space size of the command queue cache in the accelerator or the processing speed of the accelerator in the synchronous mode, thereby improving central processing. performance of the device.
  • the accelerator can read the first command from the memory based on the identification information cached in the first work queue and the first address information in various ways, which is not limited in this application.
  • the accelerator may determine the first target address information based on the identification information cached by the first work queue, the first address information and a preset mapping relationship, the mapping relationship being used to indicate the first A corresponding relationship between the identification information cached by the work queue and the storage address cached by the first work queue in the memory.
  • the first target address information is used to indicate the storage address of the first command in the memory; based on the The first target address information is read from the memory and the first command is read.
  • the accelerator may write the first command into the memory based on the first target address information.
  • S203 may include: when the first transmission mode information is used to indicate that the transmission mode of the first command is the synchronous mode, and the first command can be written to the command cache queue of the accelerator, from the command cache The first command is read from the queue.
  • the method before reading the first command from the command cache queue, the method further includes: writing the first command into the command cache queue.
  • the first transmission mode information is used to indicate that the transmission mode of the first command is the synchronous mode
  • the first command can be written into the command cache queue of the accelerator, from Reading the first command from the command cache queue can reduce interaction overhead, thereby improving command transmission efficiency.
  • the accelerator executes the first command.
  • Figure 4 shows a schematic flow chart of the command transmission method 300 provided by the embodiment of the present application.
  • the method 300 may be applied to the system 100 as shown in FIG. 1 .
  • the method 300 may include the following steps. It should be noted that the steps listed below may be executed in various orders and/or occur simultaneously, and are not limited to the execution order shown in FIG. 4 .
  • the central processor generates a notification message.
  • the notification message is used to notify the accelerator to execute the first command.
  • the notification message includes the identification information cached by the first work queue, the first address information and the first transmission mode information.
  • the first work queue The cache is used to store the first command, the first address information is used to indicate the storage address of the first command in the first work queue cache, and the first transmission mode information is used to indicate that the transmission mode of the first command is Asynchronous mode.
  • the central processor sends the notification message to the accelerator; accordingly, the accelerator receives the notification message from the processor.
  • the processor writes the first command into the memory based on the first target address information.
  • the first target address information is used to indicate the storage address of the first command in the memory.
  • the memory includes at least one work queue cache, The at least one work queue cache includes the first work queue cache.
  • the accelerator determines the first target address information based on the identification information cached in the first work queue, the preset mapping relationship and the first address information.
  • the mapping relationship is used The corresponding relationship between the identification information indicating the first work queue cache and the storage address of the first work queue cache in the memory.
  • the accelerator reads the first command from the memory based on the first target address information.
  • the accelerator executes the first command.
  • Figure 5 shows a schematic flow chart of the command transmission method 400 provided by the embodiment of the present application.
  • the method 400 may be applied to the system 100 as shown in FIG. 1 .
  • the method 400 may include the following steps. It should be noted that the steps listed below may be executed in various orders and/or occur simultaneously, and are not limited to the execution order shown in FIG. 5 .
  • the central processor generates a notification message, which is used to notify the accelerator to execute the first command.
  • the notification message includes the identification information cached by the first work queue, the first address information, the first transmission mode information and the first command,
  • the first work queue cache is used to store the first command, the first address information is used to indicate the storage address of the first command in the first work queue cache, and the first transmission mode information is used to indicate the first
  • the transmission mode of the command is synchronous mode.
  • the central processor sends the notification message to the accelerator; accordingly, the accelerator receives the notification message from the central processor.
  • the accelerator determines whether the first command can be written into the command queue cache of the accelerator based on the transmission mode of the first command being the synchronous mode. If the first command cannot be written into the command queue buffer, continue to execute S404-S406; if the first command can be written into the command queue buffer, continue to execute S407-S408.
  • the accelerator determines the first target address information based on the identification information cached in the first work queue, the preset mapping relationship and the first address information.
  • the first target address information is used to indicate the location of the first command in the memory.
  • Storage address, the mapping relationship is used to indicate the correspondence between the identification information of the first work queue cache and the storage address of the first work queue cache in the memory, wherein the memory includes at least one work queue cache, the at least A work queue cache includes the first work queue cache.
  • the accelerator writes the first command into the memory based on the first target address information.
  • the accelerator reads the command from the memory based on the first target address information.
  • the accelerator writes the first command into the command queue cache.
  • the accelerator reads the first command from the command queue cache.
  • the accelerator executes the first command.
  • the command transmission method provided by the embodiment of the present application is introduced above with reference to Figures 2 to 5.
  • the command transmission device provided by the embodiment of the present application will be further introduced below.
  • FIG. 6 shows a schematic block diagram of the command transmission device 500 provided by the embodiment of the present application.
  • the device 500 may include: a generating module 501 and a sending module 502.
  • the device 500 can be used in the above-mentioned system 100. Further, the device 500 can be the central processor 110 in the above-mentioned system 100.
  • the generation module 501 is used to generate a notification message.
  • the notification message is used to notify the accelerator to execute the first command.
  • the notification message includes the identification information cached by the first work queue, the first address information and the first transmission mode information.
  • the first work queue cache is used to store the first command
  • the first address information is used to indicate the storage address of the first command in the first work queue cache
  • the first transmission mode information is used to Indicates the transmission mode of the first command.
  • the transmission mode includes a synchronous mode or an asynchronous mode. When the transmission mode of the first command is the synchronous mode, the notification message also includes the first command. .
  • the sending module 502 is used to send the notification message to the accelerator.
  • the notification message is also used to notify the accelerator to execute the second command, and the notification message also includes the identification information cached by the second work queue, the second address information and the second transmission mode information.
  • the second work queue cache is used to store the second command, and the second address information is used to indicate where the second command is located.
  • the storage address in the second work queue cache, the second transmission mode information is used to indicate the transmission mode of the second command, the transmission mode of the first command is different from the transmission mode of the second command, wherein , when the transmission mode of the second command is the synchronization mode, the notification message further includes the second command.
  • the first work queue cache and the second work queue cache are the same, and the storage address of the first command in the first work queue cache is the same as the storage address of the second command in the first work queue.
  • the storage addresses in the cache are different; or, the first work queue cache and the second work queue cache are different.
  • the first command includes multiple commands
  • the second command includes multiple commands
  • the notification message also includes a first identification field, a first address field, a first transmission mode field, and a first command field.
  • the first identification field is used to carry the first work queue cache.
  • the identification information and the first address field are used to carry the first address information
  • the first transmission mode field is used to carry the first transmission mode information
  • the first command field is used to carry the first command.
  • the device 500 also includes a writing module 503.
  • the writing module 503 is configured to write the first command based on the first target address information when the first transmission mode information is used to indicate that the transmission mode of the first command is an asynchronous mode.
  • the command is written into the memory, and the first target address information is used to indicate the storage address of the first command in the memory.
  • the device 500 may be specifically a central processing unit in the above-mentioned method 200, method 300 or method 400 embodiments, and the device 500 may be used to perform the above-mentioned method 200, method 300 or method 400 embodiments with the central processing unit. To avoid duplication, the various processes and/or steps corresponding to the processor will not be described again here.
  • One or more of the various modules in the embodiment shown in Figure 6 may be implemented through software, hardware, firmware, or a combination thereof.
  • the software or firmware includes, but is not limited to, computer program instructions or code, and may be executed by a hardware processor.
  • the hardware includes but is not limited to various types of integrated circuits, such as central processing unit (CPU), digital signal processor (DSP), field programmable gate array (FPGA) or field programmable gate array (FPGA).
  • ASIC Application Specific Integrated Circuit
  • Figure 7 shows a schematic block diagram of a command transmission device 600 provided by an embodiment of the present application.
  • the device 600 may include a processor 601 and a communication interface 602.
  • the processor 601 is coupled to the communication interface 602.
  • the communication interface 602 is used to output data, such as notification messages, from the processor 601; the processor 601 is used to run computer programs or instructions, so that the device 600 implements the method described in the above method 200, method 300 or method 400 embodiment. .
  • the processor 601 in the embodiment of this application includes but is not limited to a central processing unit (Central Processing Unit, CPU), a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC). ), off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA), discrete gate or transistor logic devices or discrete hardware components, etc.
  • a general-purpose processor can be a microprocessor, a microcontroller, or any conventional processor.
  • the processor 601 is used to generate a notification message.
  • the notification message is used to notify the accelerator to execute the first command.
  • the notification message includes the identification information cached by the first work queue, the first address information and the first transmission mode information.
  • a work queue cache is used to store the first command, and the first address information is used to indicate that the first command is in the first work queue.
  • the first transmission mode information is used to indicate the transmission mode of the first command.
  • the transmission mode includes a synchronous mode or an asynchronous mode. When the transmission mode of the first command is the synchronous mode,
  • the notification message also includes the first command; the notification message is sent to the accelerator through the communication interface 602.
  • the device 600 can be specifically a central processing unit in the above method 200, method 300 or method 400 embodiment, and the device 600 can be used to execute the above method 200, method 300. Or the various processes and/or steps corresponding to the central processor in the method 400 embodiment will not be described again in order to avoid duplication.
  • the device 600 may also include a memory 603.
  • the memory 603 may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically removable memory.
  • Erase programmable read-only memory Electrode EPROM, EEPROM
  • Volatile memory may be Random Access Memory (RAM), which is used as an external cache.
  • RAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM DDR SDRAM
  • ESDRAM enhanced synchronous dynamic random access memory
  • Synchlink DRAM SLDRAM
  • Direct Rambus RAM Direct Rambus RAM
  • the memory 603 is used to store program codes and instructions of the device 600 .
  • the memory 603 is also used to store data obtained when the processor 601 executes the above-mentioned method 200, method 300 or method 400 embodiments, such as notification messages or commands.
  • the memory 603 may be a separate device or integrated in the processor 601.
  • FIG. 7 only shows a simplified design of the device 600.
  • the device 600 may also include other necessary components, including but not limited to any number of communication interfaces, processors, controllers, memories, etc., and all devices 600 that can implement the present application are included in the present application. within the scope of protection.
  • the device 600 may be a chip device.
  • the chip device can also include one or more memories for storing computer execution instructions.
  • the processor can execute the computer execution instructions stored in the memory, so that the chip device executes the above command transmission method. .
  • the chip device can be a field programmable gate array, a dedicated integrated chip, a system chip, a central processing unit, a network processor, a digital signal processing circuit, a microcontroller, or a programmable controller that implements related functions. or other integrated chips.
  • Figure 8 shows a schematic block diagram of the command transmission device 700 provided by the embodiment of the present application.
  • the device 700 may include: a receiving module 701, a reading module 702, and an execution module 703.
  • the device 700 can be used in the above-mentioned system 100. Further, the device 700 can be the accelerator 120 in the above-mentioned system 100.
  • the receiving module 701 is used to receive a notification message from the processor.
  • the notification message is used to notify the accelerator to execute the first command.
  • the notification message includes the identification information cached by the first work queue, the first address information and the first transmission mode information.
  • the first work queue cache is used to store the first command, and the first address information is used to indicate that the first command is in the The storage address in the first work queue cache.
  • the first transmission mode information is used to indicate the transmission mode of the first command.
  • the transmission mode includes a synchronous mode or an asynchronous mode. When the transmission mode of the first command is the synchronous mode, mode, the notification message also includes the first command.
  • the reading module 702 is used to obtain the first command based on the notification message.
  • the execution module 703 is used to execute the first command.
  • the notification message is also used to notify the accelerator to execute the second command.
  • the notification message also includes the identification information cached by the second work queue, the second address information and the second transmission mode information.
  • the second work queue cache is used to store the second command
  • the second address information is used to indicate the storage address of the second command in the second work queue cache
  • the second transmission mode information is used to indicate the storage address of the second command. Transmission mode.
  • the transmission mode of the first command is different from the transmission mode of the second command.
  • the notification message also includes the second command; the reading module 702 It is also used to obtain the second command based on the notification message; the execution module 703 is also used to execute the second command.
  • the first work queue cache is the same as the second work queue cache, but the storage address of the first command in the first work queue cache is the same as the storage address of the second command in the first work queue cache.
  • the storage addresses in the queue cache are different; or, the first work queue cache and the second work queue cache are different.
  • the first command includes multiple commands
  • the second command includes multiple commands
  • the notification message also includes a first identification field, a first address field, a first transmission mode field, and a first command field.
  • the first identification field is used to carry the first work queue cache.
  • the identification information and the first address field are used to carry the first address information
  • the first transmission mode field is used to carry the first transmission mode information
  • the first command field is used to carry the first command.
  • the reading module 702 is specifically configured to read the first work queue cached identification information, the first address information and the first transmission mode information from the memory. One command.
  • the reading module 702 is specifically used to: when the first transmission mode information is used to indicate that the transmission mode of the first command is the synchronous mode, but the first command cannot be written to the accelerator When the command cache queue is cached, the first command is read from the memory based on the identification information cached in the first work queue and the first address information.
  • the device 700 further includes: a determining module 704.
  • the determining module 704 is configured to determine the first target address information based on the identification information cached by the first work queue, the first address information and a preset mapping relationship, and the mapping relationship is used for Indicates the correspondence between the identification information cached by the first work queue and the storage address cached by the first work queue in the memory.
  • the first target address information is used to indicate the storage address of the first command in the memory.
  • the reading module 702 is specifically configured to read the first command from the memory based on the first target address information.
  • the device 700 also includes: a writing module 705.
  • the writing module 705 is configured to write the first command based on the first target address information before reading the first command from the memory based on the first target address information. Write to this memory.
  • the reading module 702 is also configured to: when the first transmission mode information is used to indicate that the transmission mode of the first command is the asynchronous mode, based on the identification information cached in the first work queue and the first address information, and reads the first command from the memory.
  • the reading module 702 is also used to: when the first transmission mode information is used to indicate the When the transmission mode of the first command is the synchronous mode, and the first command can be written into the command cache queue of the accelerator, the first command is read from the command cache queue.
  • the writing module 705 is also configured to write the first command into the command cache queue before reading the first command from the command cache queue.
  • the device 700 may be specifically an accelerator in the above-mentioned method 200, method 300 or method 400 embodiments, and the device 700 may be used to execute the accelerator corresponding to the above-mentioned method 200, method 300 or method 400 embodiments. To avoid repetition, various processes and/or steps will not be described again here.
  • One or more of the various modules in the embodiment shown in Figure 8 may be implemented through software, hardware, firmware, or a combination thereof.
  • the software or firmware includes, but is not limited to, computer program instructions or code, and may be executed by a hardware processor.
  • the hardware includes but is not limited to various types of integrated circuits, such as central processing unit (CPU), digital signal processor (DSP), field programmable gate array (FPGA) or field programmable gate array (FPGA).
  • ASIC Application Specific Integrated Circuit
  • Figure 9 shows a schematic block diagram of a command transmission device 800 provided by an embodiment of the present application.
  • the device 800 may include a processor 801 and a communication interface 802.
  • the processor 801 is coupled to the communication interface 802.
  • the communication interface 802 is used to provide data, such as notification messages, to the processor 801; the processor 801 is used to run computer programs or instructions, so that the device 800 implements the method described in the above method 200, method 300 or method 400 embodiment. .
  • the processor 801 in the embodiment of this application includes but is not limited to a central processing unit (Central Processing Unit, CPU), a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC ), off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA), discrete gate or transistor logic devices or discrete hardware components, etc.
  • a general-purpose processor can be a microprocessor, a microcontroller, or any conventional processor.
  • the processor 801 is configured to receive a notification message from the processor through the communication interface 802.
  • the notification message is used to notify the accelerator to execute the first command.
  • the notification message includes the identification information and the first address information cached by the first work queue. and first transmission mode information, the first work queue cache is used to store the first command, the first address information is used to indicate the storage address of the first command in the first work queue cache, the first transmission mode The information is used to indicate the transmission mode of the first command.
  • the transmission mode includes a synchronous mode or an asynchronous mode. When the transmission mode of the first command is the synchronous mode, the notification message also includes the first command; based on the Notify the message to obtain the first command; execute the first command.
  • the device 800 can be specifically an accelerator in the above method 200, method 300 or method 400 embodiment, and the device 800 can be used to execute the above method 200, method 300 or method.
  • various processes and/or steps corresponding to the accelerator in the embodiment 400 will not be described again here.
  • the device 800 may also include a memory 803.
  • the memory 803 may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically removable memory. Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • Volatile The permanent memory may be Random Access Memory (RAM), which is used as an external cache.
  • RAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • Enhanced SDRAM, ESDRAM enhanced synchronous dynamic random access memory
  • Synchlink DRAM, SLDRAM synchronous link dynamic random access memory
  • Direct Rambus RAM Direct Rambus RAM
  • the memory 803 is used to store program codes and instructions of the device 800 .
  • the memory 803 is also used to store data obtained when the processor 801 executes the above-mentioned method 200, method 300 or method 400 embodiments, such as notification messages or commands.
  • the memory 803 may be a separate device or integrated in the processor 801.
  • FIG. 9 only shows a simplified design of the device 800.
  • the device 800 may also include other necessary components, including but not limited to any number of communication interfaces, processors, controllers, memories, etc., and all devices 800 that can implement the present application are included in the present application. within the scope of protection.
  • the device 800 may be a chip device.
  • the chip device can also include one or more memories for storing computer execution instructions.
  • the processor can execute the computer execution instructions stored in the memory, so that the chip device executes the above command transmission method. .
  • the chip device can be a field programmable gate array, a dedicated integrated chip, a system chip, a central processing unit, a network processor, a digital signal processing circuit, a microcontroller, or a programmable controller that implements related functions. or other integrated chips.
  • the size of the sequence numbers of the above-mentioned processes does not mean the order of execution.
  • the execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application.
  • the aforementioned storage media include: U disk, mobile hard disk, Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk or optical disk and other media that can store program code.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Multimedia (AREA)
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  • Mobile Radio Communication Systems (AREA)

Abstract

La présente demande concerne un procédé et un appareil de transmission de commande. Une commande peut être transmise dans un mode asynchrone ou un mode synchrone au moyen d'un ensemble d'interfaces de message de telle sorte que la flexibilité de transmission de commande puisse être améliorée. Le procédé peut consister : à générer un message de notification, le message de notification étant utilisé pour notifier à un accélérateur d'exécuter une première commande, le message de notification comportant des informations d'identification d'un premier cache de file d'attente de travail, des premières informations d'adresse et des premières informations de mode de transmission, le premier cache de file d'attente de travail étant utilisé pour stocker la première commande, les premières informations d'adresse étant utilisées pour indiquer une adresse de stockage de la première commande dans le premier cache de file d'attente de travail, les premières informations de mode de transmission étant utilisées pour indiquer un mode de transmission de la première commande, le mode de transmission comprenant un mode synchrone ou un mode asynchrone, et, lorsque le mode de transmission de la première commande est le mode synchrone, le message de notification comprenant en outre la première commande ; et à envoyer le message de notification à l'accélérateur.
PCT/CN2023/083662 2022-04-28 2023-03-24 Procédé et appareil de transmission de commande WO2023207456A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090006657A1 (en) * 2007-06-26 2009-01-01 Asad Azam Enabling consecutive command message transmission to different devices
CN107454634A (zh) * 2016-06-01 2017-12-08 中兴通讯股份有限公司 一种快速切换的方法、快速切换的装置、终端及基站
CN110569653A (zh) * 2019-08-28 2019-12-13 华为技术有限公司 数据处理方法、相关设备及计算机存储介质
CN111930678A (zh) * 2020-08-14 2020-11-13 山东云海国创云计算装备产业创新中心有限公司 一种数据传输方法、装置及电子设备和存储介质

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090006657A1 (en) * 2007-06-26 2009-01-01 Asad Azam Enabling consecutive command message transmission to different devices
CN107454634A (zh) * 2016-06-01 2017-12-08 中兴通讯股份有限公司 一种快速切换的方法、快速切换的装置、终端及基站
CN110569653A (zh) * 2019-08-28 2019-12-13 华为技术有限公司 数据处理方法、相关设备及计算机存储介质
CN111930678A (zh) * 2020-08-14 2020-11-13 山东云海国创云计算装备产业创新中心有限公司 一种数据传输方法、装置及电子设备和存储介质

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