WO2023207328A1

WO2023207328A1 - Semiconductor structure and preparation method therefor, and electronic device

Info

Publication number: WO2023207328A1
Application number: PCT/CN2023/079419
Authority: WO
Inventors: 杨荣华; 刘少鹏; 张敏; 张恒; 赵杰; 宋俊存; 余剑
Original assignee: 华为技术有限公司
Priority date: 2022-04-28
Filing date: 2023-03-02
Publication date: 2023-11-02
Also published as: CN117038571A

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Disclosed are a semiconductor structure and a preparation method therefor, and an electronic device, which are used for alleviating the narrow width effect and reducing the area of a bit cell, thereby achieving higher-density and higher-performance applications. The preparation method for a semiconductor structure comprises: providing a substrate, which has a preset shallow trench region; etching the part of the substrate that is located in the preset shallow trench region, so as to form a first sub-shallow trench; performing ion implantation on a side wall of the first sub-shallow trench, so as to form a doped region in the substrate; etching a bottom wall of the first sub-shallow trench, and forming a second sub-shallow trench below the first sub-shallow trench, so as to obtain a shallow trench comprising the first sub-shallow trench and the second sub-shallow trench; and forming a filling portion in the shallow trench.

Description

Semiconductor structure and preparation method thereof, electronic equipment

This application claims priority to the Chinese patent application submitted to the State Intellectual Property Office on April 28, 2022, with application number 202210471432.5 and the application name "Semiconductor Structure and Preparation Methods and Electronic Equipment", the entire content of which is incorporated by reference. in this application.

Technical field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and its preparation method, and electronic equipment.

Background technique

As a new type of memory, ferroelectric memory is more and more widely used than traditional dynamic random access memory (DRAM) because it has the advantages of non-volatility, high speed, and low power consumption. .

The bit cell of ferroelectric memory is generally composed of a gate tube and a ferroelectric capacitor. At advanced process nodes, ferroelectric memory uses input and output devices (IO devices) as strobes. However, the size of the input and output devices is usually relatively large. Therefore, the area of the bit cell of the ferroelectric memory using the input and output devices is also relatively large, which is not conducive to high-density and high-performance applications. At present, transistors with a complementary metal oxide semiconductor (CMOS) structure (the transistors can be referred to as CMOS transistors for short) are usually used to replace the above input and output devices as gate transistors to achieve high-density and high-performance applications.

As the semiconductor manufacturing process enters the deep sub-micron stage, in order to achieve higher density and higher performance applications, the size of CMOS transistors needs to be greatly reduced. Therefore, the isolation process between CMOS transistors becomes more and more important. The current semiconductor manufacturing process uses shallow trench isolation (STI) technology to isolate different CMOS transistors. However, as the size of CMOS transistors decreases, the channel width of the CMOS transistors will gradually shrink, which will The narrow width effect (NWE) occurs, causing the threshold voltage of the CMOS transistor to become lower and the leakage current to increase, which in turn causes the performance of the CMOS transistor to seriously degrade. In addition, due to the restriction of the narrow channel effect, it is difficult to further reduce the channel width of CMOS transistors, which in turn makes it difficult to reduce the area of the bit cells of ferroelectric memories using CMOS transistors, making it difficult to achieve higher density and higher performance. Applications.

Contents of the invention

Embodiments of the present application provide a semiconductor structure, a preparation method thereof, and electronic equipment, which are used to improve the narrow channel effect and reduce the area of bit cells to achieve higher density and higher performance applications.

In order to achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

In a first aspect, a method for preparing a semiconductor structure is provided. The preparation method includes: providing a substrate with a preset shallow trench area; etching a portion of the substrate located in the preset shallow trench area to form a third A sub-shallow trench; ion implantation is performed on the sidewall of the first sub-shallow trench to form a doped region in the substrate; the bottom wall of the first sub-shallow trench is etched, and the bottom wall of the first sub-shallow trench is etched. A second sub-shallow trench is formed below to obtain a shallow trench including a first sub-shallow trench and a second sub-shallow trench; a filling portion is formed in the shallow trench.

The above-mentioned shallow trench, the filling portion located in the shallow trench, and the doped region located in the substrate can be called a shallow trench isolation structure, for example. On the one hand, this application can utilize the doping region in the shallow trench isolation structure to adjust the transistor to be formed. The threshold voltage reduces the leakage current of the transistor to be formed and improves the performance of the transistor to be formed, thereby improving the narrow channel effect. This is conducive to compressing the channel size of the transistor to be formed, which in turn is conducive to reducing the area of the bit cell to be formed, and achieving higher density and higher performance applications.

Moreover, this application decomposes the formation process of shallow trenches, using two etching processes to form the first sub-shallow trench and the second sub-shallow trench respectively, and before etching to form the second sub-shallow trench, Then, ions are implanted into the exposed sidewalls of the first sub-shallow trench ST1, and after etching to form the second sub-shallow trench, a filling portion that at least fills the shallow trench is formed at once. In this way, on the one hand, it is possible to avoid etching back the filling part, avoid the filling part being bombarded by plasma, and ensure the insulation performance and reliability of the filling part. On the other hand, it is possible to avoid breaking the vacuum during the formation of the filling part, thereby preventing The filling part contacts the air and forms defects. On the other hand, it can avoid increasing the process of engraving back and reduce the process cost. In addition, since this application first performs ion implantation on the exposed sidewalls of the first sub-shallow trench and then forms the filling part, this can avoid implanting ions into the filling part, so that the filling part can be free from the influence of additional ion implantation. , which can further ensure the insulation performance and reliability of the filling part.

In a possible implementation of the first aspect, etching the portion of the substrate located in the preset shallow trench area includes: sequentially forming a liner layer, a hard mask layer and a photoresist layer on the substrate; etching Etch the portion of the photoresist layer located in the preset shallow trench area, and form a first opening in the photoresist layer; through the first opening, etch the hard mask layer, liner layer and substrate located in the preset shallow trench area. In the portion of the trench area, a second opening is formed in the hard mask layer and the liner layer, and a first sub-shallow trench is formed in the substrate.

In this application, after forming the first sub-shallow trench, ions can be implanted into the sidewalls of the first sub-shallow trench, and then the bottom wall of the first sub-shallow trench can be etched to form the second sub-shallow trench. . That is to say, this application mainly uses the hard mask layer to define the first sub-shallow trench, and then defines the shallow trench. The method of defining shallow trenches is relatively simple and does not require additional processes. It can not only reduce process costs, but also avoid modifying the photolithography dimensions of the active area in advance, reducing process risks.

In a possible implementation of the first aspect, performing ion implantation on the sidewall of the first sub-shallow trench includes: removing the photoresist layer; using the hard mask layer and the liner layer as masks, through the second opening, Ion implantation is performed on the sidewall of the first sub-shallow trench; there is an angle between the direction of the ion implantation and the direction perpendicular to the substrate. In this application, the hard mask layer and the liner layer can be used as masks to block and shield the first surface of the substrate, ensuring that ions can be injected into the sidewalls of the first shallow trench and preventing ions from being injected into the substrate. first surface to avoid affecting the performance of the transistor to be formed. In addition, by making an angle between the direction of ion implantation and the direction perpendicular to the substrate, it can be ensured that ions can be implanted into the sidewalls of the first sub-shallow trench, and thus the threshold voltage of the transistor to be formed can be adjusted and improved. Narrow channel effect.

In a possible implementation manner of the first aspect, the angle between the direction of ion implantation and the direction perpendicular to the substrate ranges from 5° to 45°. This can ensure that most of the ions can be injected into the sidewalls of the first sub-shallow trench, and reduce the amount of ions injected into the bottom wall of the first sub-shallow trench, so as to facilitate the adjustment of the threshold voltage of the transistor to be formed. , while improving the narrow channel effect, reducing the usage (or waste) of ions and reducing process costs.

In a possible implementation of the first aspect, forming the filling part in the shallow trench includes: forming a filling film on the hard mask layer, with a part of the filling film located in the shallow trench; and removing the part of the filling film covering the hard mask layer. and a hard mask layer, retaining the portion of the filling film located in the shallow trench to form a filling portion. This can not only avoid the formation of defects in the filling part, avoid the filling part from being affected by additional ion implantation, and ensure the insulation performance and reliability of the filling part. It can also simplify the preparation process of the filling part and reduce the process cost.

In a possible implementation manner of the first aspect, the preparation method further includes: annealing the doped region. This can repair the lattice damage of the material caused by ion implantation and activate the implanted ions.

In a possible implementation manner of the first aspect, the preparation method further includes: annealing the filling film; wherein, during the annealing treatment of the filling film, the doping region is also annealed. In other words, this application can integrate the annealing process of the doped region into the existing annealing process in the preparation method of the semiconductor structure, and simultaneously perform the annealing process on the filling film and the doped region in one annealing process. , which can avoid the introduction of additional annealing processes, simplify the preparation process of semiconductor structures, and reduce process costs.

In a possible implementation of the first aspect, the preparation method further includes: performing ion implantation on a portion of the substrate surrounded by the shallow trench to form an active region; forming a gate dielectric layer and a gate electrode on the active region; The portion of the source region that is not covered by the gate dielectric layer and the gate electrode is ion implanted to form the source and drain electrodes of the transistor. Using this preparation method, a transistor can be prepared. In addition, after the transistor is prepared and formed, the channel of the transistor will still be in contact with the doped region, so additional channel implantation will be formed in the area where the two are in contact. This additional channel injection will have an impact on the channel of the transistor, which can adjust and stabilize the threshold voltage of the transistor, reduce the leakage of the transistor, improve and suppress the narrow channel effect, and improve the performance of the transistor. This will help reduce the channel width of the transistor, reduce the area of the transistor, and facilitate the formation of more transistors in the substrate.

In a possible implementation of the first aspect, ion implantation is performed on the portion of the substrate surrounded by the shallow trench, including: removing the photoresist layer and the hard mask layer; using the liner layer as a protective layer, through the liner The layer implants ions into the portion of the substrate surrounded by the shallow trenches. In this way, the liner layer can protect the surface of the substrate and prevent the surface of the substrate from being damaged.

In a possible implementation of the first aspect, before sequentially forming the gate dielectric layer and the gate electrode on the active area, the preparation method further includes: removing the liner layer. This can avoid affecting the formation of the gate dielectric layer and gate electrode.

In a possible implementation of the first aspect, the transistor is an N-type transistor, and the ions injected into the sidewall of the first sub-shallow trench are P-type ions. Alternatively, the transistor is a P-type transistor, and the ions injected into the sidewall of the first sub-shallow trench are N-type ions. That is to say, the type of transistor is opposite to the type of ions injected into the sidewall of the first sub-shallow trench. This can form an inversion layer, thereby adjusting the threshold voltage of the transistor, reducing the leakage of the transistor, and improving and suppressing the leakage of the transistor. Narrow channel effect improves transistor performance.

In a possible implementation manner of the first aspect, the transistor is an N-type transistor, and the ions injected into the sidewall of the first sub-shallow trench are boron ions.

In a possible implementation of the first aspect, the preparation method further includes: forming a storage structure on the first electrode, the storage structure being electrically connected to the first electrode; and the first electrode being the source electrode or the drain electrode. Transistors and the memory structures electrically connected to them can constitute bit cells, and bit cell arrays can constitute memories. By improving and suppressing the narrow channel effect, this application can easily reduce the channel width of the transistor, reduce the area of the transistor, and reduce the area of the bit unit, thereby enabling more transistors T and more bit units to be set up to achieve Higher density, higher performance applications.

In a possible implementation of the first aspect, the depth range of the first sub-shallow trench is By limiting the depth of the first shallow trench, the amount of ions injected into the sidewalls of the first sub-shallow trench can be ensured, the threshold voltage of the transistor to be formed can be effectively adjusted, and the narrow channel effect can be effectively improved. .

In a second aspect, a semiconductor structure is provided. The semiconductor structure includes: a substrate and a filling part. The substrate has a doped region, and a shallow trench is opened on the first surface of the substrate. The filling part is located in the shallow groove and has an integrated structure. in, The shallow trench includes a first sub-shallow trench close to the first surface of the substrate, and a second sub-shallow trench located below the first sub-shallow trench, and the doped region is located on the sidewall of the first sub-shallow trench; Compared with the second sub-shallow trench, the first sub-shallow trench and the doped region are formed first.

The semiconductor structure provided by this application can, on the one hand, use the doping region to adjust the threshold voltage of the transistor, reduce the leakage current of the transistor, and improve the performance of the transistor, thereby improving the narrow channel effect, so as to compress the channel size of the transistor and reduce the The area of the bit cell can achieve higher density and higher performance applications. On the other hand, it can avoid damaging the filling part and avoid doping ions in the filling part, which will affect the insulation performance and reliability of the filling part.

In a possible implementation of the second aspect, the semiconductor structure further includes: an active region, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode. The active area extends from the first surface of the substrate to the interior of the substrate, and the active area is surrounded by shallow trenches. The source and drain are located in the active area. The gate dielectric layer is located on the first surface of the substrate and between the source electrode and the drain electrode. The gate electrode is located on the gate dielectric layer. Here, the active area, source, drain, gate dielectric layer and gate can constitute a transistor. The above-mentioned doped area can adjust and stabilize the threshold voltage of the transistor, reduce the leakage of the transistor, improve and suppress the narrow channel effect, and improve Transistor performance.

In a possible implementation manner of the second aspect, the semiconductor structure further includes: a storage structure. The storage structure is located on the first pole and is electrically connected to the first pole. The first pole is the source or drain. The memory structure 10 allows the semiconductor structure to constitute a memory. Since this application can improve and suppress the narrow channel effect, reduce the channel width of the transistor, and reduce the area of the transistor, it can further reduce the area of the bit unit, and can provide more transistors and more bit units to achieve Higher density, higher performance applications.

A third aspect provides an electronic device, which includes the semiconductor structure according to any one of the above second aspects.

Among them, the technical effects brought by the design method in the second aspect can be found in the technical effects brought by the different design methods in the first aspect and the second aspect, and will not be described again here.

Description of drawings

Figure 1 is a structural diagram of a ferroelectric random access memory provided by an embodiment of the present application;

Figure 2 is a circuit diagram of a ferroelectric random access memory provided by an embodiment of the present application;

Figures 3a to 3g are structural diagrams corresponding to each step of a method for preparing a semiconductor structure provided in an implementation manner;

Figures 4a to 4i are structural diagrams corresponding to each step of a method for preparing a semiconductor structure provided in another implementation mode;

Figure 5 is a flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present application;

Figure 6 is a structural diagram corresponding to a step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

7a to 7b are structural diagrams corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

8a to 8b are structural diagrams corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

9a to 9c are structural diagrams corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

Figures 10a to 10b are structural diagrams corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

Figures 11a to 11b are structural diagrams corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

Figures 12a to 12b are structural diagrams corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

Figures 13a to 13d are structural diagrams corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

Figures 14a to 14b are structural diagrams corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

Figures 15a to 15b are structural diagrams corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

Figures 16a to 16b are structural diagrams corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

Figure 17 is a structural diagram corresponding to another step of a method for preparing a semiconductor structure provided by an embodiment of the present application;

Figure 18 is a structural diagram of a semiconductor structure provided by an embodiment of the present application;

Figure 19 is a structural diagram of another semiconductor structure provided by an embodiment of the present application;

Figure 20 is a structural diagram of another semiconductor structure provided by an embodiment of the present application;

Figure 21 is a structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments.

Among them, in the description of this application, unless otherwise stated, "plurality" means two or more than two. “At least one item (item)” or similar expressions thereof refers to any combination of these items, including any combination of single item (items) or plural items (items). For example, at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .

In addition, in order to facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as “first” and “second” are used to distinguish identical or similar items with basically the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the number and execution order, and words such as "first" and "second" do not limit the number and execution order. At the same time, in the embodiments of this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "such as" in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner that is easier to understand.

In the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to being defined relative to the schematically placed directions of the components in the drawings. It should be understood that these directional terms may be relative. Concepts, which are used for relative description and clarification, may change accordingly depending on the orientation in which components are placed in the drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity, and the dimensional proportions between the various parts in the illustrations do not reflect actual dimensional proportions.

Example embodiments are described herein with reference to cross-sectional illustrations and/or plan illustrations that are idealized illustrations. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated. Therefore, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.

In addition, the architecture and scenarios described in the embodiments of the present application are for the purpose of explaining the technical solutions of the embodiments of the present application more clearly, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art will know that as the architecture With the evolution of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

It should be noted that ferroelectric memory mainly includes ferroelectric random access memory (ferroelectric random access memory, FeRAM) and ferroelectric field effect transistor (ferroelectric field-effect-transistor, FeFET) memory. Each bit cell (or memory cell) of a ferroelectric memory includes a CMOS transistor and at least one ferroelectric capacitor electrically connected to the CMOS transistor. Where the bit cell includes multiple ferroelectric capacitors, the ferroelectric memory may be a 3D memory. Among them, the difference between FeRAM and FeFET lies in the location of the ferroelectric capacitor.

This application takes FeRAM as an example. Figure 1 is a structural diagram of FeRAM, and Figure 1 is a circuit diagram of FeRAM. In Figures 1 and 2, forty bit cells BC in FeRAM are exemplified respectively. Each bit cell BC includes a CMOS transistor Tr and a ferroelectric capacitor C. In each bit cell BC, the gate of the CMOS transistor Tr is electrically connected to the word line WL, the second electrode of the CMOS transistor Tr is electrically connected to the bit line BL, and the first electrode of the CMOS transistor Tr is electrically connected to the first terminal of the ferroelectric capacitor C. connection, the second end of the ferroelectric capacitor C is electrically connected to the plate line PL.

In this application, the above-mentioned COMS transistor Tr may be a transistor with an N-channel metal oxide semiconductor (N-channel metal oxide semiconductor, NMOS) structure (the transistor may be referred to as an NMOS transistor for short), or may be a P-type metal oxide semiconductor ( P-channel metal oxide semiconductor, PMOS) structure transistor (this transistor can be referred to as PMOS transistor for short). One of the drain or the source of the CMOS transistor Tr is the first electrode, and the other is the second electrode.

Illustratively, the ferroelectric capacitor C includes a ferroelectric material between a first end and a second end thereof. FeRAM can store data by taking advantage of the fact that ferroelectric materials can undergo spontaneous polarization and the polarization state can be reoriented with the action of an external electric field.

Specifically, when an electric field is applied to a ferroelectric material, its central atom stays in a low-energy state along the electric field. Conversely, when an electric field flip is applied to the same ferroelectric material, its central atom follows the direction of the electric field. Move within the crystal and stay in another lower energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains. The ferroelectric domains form polarization charges (also called flip charges) under the action of an electric field. The flipping charge formed by the flipping of ferroelectric domains under the action of electric field is high, and the flipping charge formed by ferroelectric domains not flipping under the action of electric field is low. This binary stable state of ferroelectric materials allows ferroelectric materials to be used as The memory uses the difference in the direction of the residual polarization intensity and applies an electric field in the same direction to generate different flip charges, which can be used to store data "0" and "1".

For example, each ferroelectric capacitor C can be used to store 1 bit of data.

It can be understood that as the area of the bit cells in the ferroelectric memory decreases, the number of bit cells that can be set for storing data becomes larger, and accordingly, higher density and higher performance applications can be achieved. . However, the reduction in the area of the bit cell will inevitably compress the size of the CMOS transistor in the bit cell. After the size of a CMOS transistor is compressed and reduced to a certain extent, a narrow channel effect will occur, causing the threshold voltage of the CMOS transistor to become lower and the leakage current to increase, resulting in serious degradation of the performance of the CMOS transistor. At the same time, after the narrow channel effect occurs, it is difficult to further compress and reduce the size of the CMOS transistor, and it is difficult to further reduce the area of the bit cell.

In one implementation, a method for preparing a semiconductor structure is provided for improving the narrow channel effect so as to further compress and reduce the size of the CMOS transistor and reduce the area of the bit cell. The flow chart of this preparation method is shown in Figures 3a to 3g.

In some examples, the preparation method of the above-mentioned semiconductor structure includes: S10a to S60a.

S10a, as shown in Figure 3a, a liner layer 2 and a hard mask layer 3 are sequentially formed on the substrate 1, and then the hard mask layer 3 is patterned to form an opening in the hard mask layer 3. Corresponds to the location of the shallow trench to be formed. The liner layer 2 and the substrate 1 are then sequentially patterned through the opening to form a shallow trench ST in the substrate 1 .

S20a, as shown in FIG. 3b and FIG. 3c, the shallow trench ST is filled with oxide, and the oxide at least fills the shallow trench ST. Then, the oxide is etched back to remove part of the oxide, thereby obtaining the first filled portion 41 . The thickness of the first filling portion 41 is smaller than the depth of the shallow trench ST so as to expose the top of the sidewall of the shallow trench ST.

S30a, as shown in FIG. 3d, perform ion implantation on the top of the sidewall of the shallow trench ST through the opening in the hard mask layer 3, corresponding to the top of the sidewall of the shallow trench ST in the substrate 1. A doped region DR is formed at the position. The implanted ions may be fluorine ions.

S40a, as shown in FIG. 3e, the first filling portion 41 is filled with oxide again through the opening in the hard mask layer 3. The oxide not only fills the shallow trench ST and the opening in the hard mask layer 3, will also be located on hard mask layer 3. The oxide located on the hard mask layer 3 is then polished until the surface of the hard mask layer 3 is exposed, and a portion of the oxide located in the shallow trench ST and the opening in the hard mask layer 3 is retained. At this time, the second filling part 42 including the first filling part 41 is obtained.

S50a, as shown in FIG. 3f, wet etching is used to sequentially remove the hard mask layer 3 and the liner layer 2, and simultaneously remove a part of the second filling portion 42 to obtain the final filling portion 4. Wherein, a recess is formed at the interface between the top of the filling part 4 and the substrate 1, and this recess exposes a part of the doped region DR.

S60a, as shown in Figure 3g, ion implantation is performed on the substrate 1 to form N-type and P-type doped active regions 5, and a gate dielectric is grown on the surface of the portion of the substrate 1 corresponding to the active region 5. Layer 6. Then, CMOS transistors (such as PMOS transistors and NMOS transistors) can be formed in the area surrounded by the shallow trench ST.

Among them, due to the influence of the doped region DR in the recess, the thickness of the partial gate dielectric layer 6 grown in the recess is greater than the thickness of the partial gate dielectric layer 6 grown in other locations. That is to say, by forming the doped region DR, the growth rate of the gate dielectric layer 6 at different positions can be affected. By forming the gate dielectric layer 6 with different thicknesses, the formation of parasitic transistors at the position of the shallow trench ST can be avoided, and thus It can effectively improve the narrow channel effect. This is beneficial to reducing the size of the subsequently formed CMOS transistor, which in turn is beneficial to reducing the area of the bit cell.

It should be noted that in the above-mentioned S20a, since the oxide filled into the shallow trench ST needs to be etched back, this will cause the first filling portion 41 formed after the etching back to be bombarded by plasma, reducing the first The insulation performance of the filling part 41 reduces the reliability of the first filling part 41 . Moreover, in filling the oxide into the shallow trench ST After the object is re-engraved, it is necessary to confirm whether the size of the re-engraving is as expected. This will expose the first filling part 41 to the air, causing the surface of the first filling part 41 to contact the air and form defects.

In the above S30a, during the process of ion implantation into the top of the sidewall of the shallow trench ST, fluorine ions will be implanted into the first filling portion 41, which will change the doping concentration of the first filling portion 41 and further reduce the doping concentration of the first filling portion 41. The insulation performance of the first filling part 41 further reduces the reliability of the first filling part 41 .

In addition, the preparation method of the semiconductor structure provided by the above-mentioned implementation requires an additional etching-back process, which will increase the complexity of the process flow of the above-mentioned preparation method and increase the process cost.

In another implementation, a method for preparing a semiconductor structure is provided to improve the narrow channel effect so as to further compress and reduce the size of the CMOS transistor and reduce the area of the bit cell. The flow chart of this preparation method is shown in Figures 4a to 4i.

In some examples, the preparation method of the above-mentioned semiconductor structure includes: S10b to S60b.

S10b, as shown in Figure 4a, a liner layer 2 and a hard mask layer 3 are sequentially formed on the substrate 1, and then the liner layer 2 and the hard mask layer 3 are patterned. An opening K is formed in the mask layer 3 , the opening K corresponds to the position of the shallow trench to be formed, and includes a portion of the surface of the substrate 1 .

S20b, as shown in FIG. 4b, ions are implanted into the exposed part of the surface of the substrate 1 through the above-mentioned opening K, and then the substrate 1 is annealed to form a doped region DR in the substrate 1. The implanted ions may be boron ions.

S30b, as shown in FIG. 4c and FIG. 4d, an insulating film 7a is formed on the hard mask layer 3, and the insulating film 7a also covers the sidewall of the opening K. Then, the insulating film 7a is patterned, and the portion of the insulating film 7a covering the sidewalls of the opening K is retained to form the sidewalls 7.

S40b, as shown in FIG. 4e and FIG. 4f , using the sidewall 7 as a mask, the substrate 1 is patterned to form a shallow trench ST in the substrate 1 . Then, the spacers 7 are removed, leaving the doped region DR in the substrate 1 . The doped region DR is located on the top of the sidewall of the shallow trench ST.

S50b, as shown in FIG. 4g and FIG. 4h, fill the shallow trench ST with oxide through the above-mentioned opening K to form a filling film 4a. The filling film 4a not only fills the shallow trench ST and the above-mentioned opening K, but also is located in the shallow trench ST. on hard mask layer 3. Then, the portion of the filling film 4a located on the hard mask layer 3 is removed, and the hard mask layer 3 is removed, leaving the portion of the filling film 4a located in the shallow trench ST to obtain the filling portion 4.

S60b, as shown in FIG. 4i, remove the liner layer 2, and perform ion implantation on the substrate 1 to form the active region 5. After that, a CMOS transistor can be formed in the area surrounded by the shallow trench ST.

By using the sidewall 7 as a mask to define the shallow trench ST, the doping region DR formed by ion implantation can be used to adjust the threshold voltage of the subsequently formed CMOS transistor and improve the narrow channel effect. This is beneficial to reducing the size of the subsequently formed CMOS transistor, which in turn is beneficial to reducing the area of the bit cell.

It should be noted that the above-mentioned another implementation method uses the sidewall 7 as a mask to define the shallow trench ST, which requires additional formation processes and etching processes of the insulating film 7a, which will increase the process flow of the above-mentioned preparation method. The complexity increases the process cost. Moreover, the width of the shallow trench ST is generally fixed, and the sidewalls 7 have a certain width. This will cause the size of the active area 5 to be affected by the sidewalls 7, and further requires photolithography of the active area 5 in advance. The dimensions are corrected to make up for the width of the side wall 7 in advance and increase the width of the opening K, which increases the process risk of the above preparation method.

Some embodiments of the present application provide a method of manufacturing a semiconductor structure. As shown in Figure 5, the preparation method The method includes S100~S500.

S100, as shown in Figure 6, a substrate 1 is provided. The substrate 1 has a preset shallow trench area A.

For example, the above-mentioned substrate 1 is a wafer substrate, which can provide support for subsequent semiconductor manufacturing process steps. For example, the material of the substrate 1 can be single crystal silicon, polycrystalline silicon, single crystal germanium, silicon germanium or silicon carbide; it can also be silicon on insulator or germanium on insulator; it can also be other materials, such as gallium arsenide. etc. III-V compounds.

The shape of the above-mentioned preset shallow trench region A can be set according to the position of the transistor to be formed (eg, CMOS transistor), which is not limited in this application.

For example, the spacing between the transistors to be formed is relatively large. The preset shallow trench areas A may be in an annular shape and surround different transistors to be formed.

For another example, the spacing between the transistors to be formed is small. The preset shallow trench area A can be in a grid shape (as shown in Figure 1) to separate the transistors to be formed.

S200, as shown in FIGS. 9a to 9c, the portion of the substrate 1 located in the preset shallow trench area A is etched to form a first sub-shallow trench ST1.

For example, this application can use a dry etching process or a wet etching process to etch the substrate 1 to remove a part of the substrate 1 located in the preset shallow trench area A. For example, the substrate 1 has a first surface 1a and a second surface 1b arranged opposite each other. In this application, the first surface 1a of the substrate 1 can be etched to form a first sub-shallow trench ST1.

The depth of the first sub-shallow trench ST1 is less than the thickness of the substrate 1 . That is to say, as shown in FIG. 9c, during the process of forming the first sub-shallow trench ST1, the bottom wall W1 of the first sub-shallow trench ST1 is located inside the substrate 1, and the first sub-shallow trench ST1 does not penetrate the substrate. Bottom 1.

The shape of the orthographic projection (or plan view shape) of the first sub-shallow trench ST1 on the plane of the substrate 1 is the same as the shape of the preset shallow trench area A. The cross-sectional shape of the first sub-shallow trench ST1 is, for example, rectangular (as shown in FIG. 9c) or an inverted trapezoid.

S300, as shown in FIG. 10a and FIG. 10b, perform ion implantation on the sidewall of the first sub-shallow trench ST1 to form a doped region DR in the substrate 1.

For example, this application may use an ion implantation process to implant ions into the sidewalls of the first sub-shallow trench ST1. The implanted ions can enter the interior of the substrate 1 , so that a doped region DR can be formed in the substrate 1 . The doped region DR may surround the sidewall of the first sub-shallow trench ST1.

In the process of ion implantation into the sidewall of the first sub-shallow trench ST1, for example, ion implantation may be performed only at the top position of the sidewall; for example, ion implantation may be performed at the entire sidewall position.

Here, the depth of implantation of ions into the interior of the substrate 1 can be selected and set as needed, and is not limited in this application.

For example, in the cross-sectional view shown in FIG. 10b, the first sub-shallow trench ST1 has two sidewalls W2 and W3. The two sidewalls W2 and W3 are respectively located on both sides of the bottom wall W1 and are respectively connected with the to-be-formed corresponding to the transistor.

During the process of ion implantation into the sidewalls of the first sub-shallow trench ST1, for example, the two sidewalls W2 and W3 of the first sub-shallow trench ST1 may be ion-implanted at the same time; for another example, the ion implantation may be performed first into the sidewalls W2 and W3 of the first sub-shallow trench ST1. One of the two side walls W2 and W3 of the first sub-shallow trench ST1 is ion implanted, and then the other of the two side walls W2 and W3 of the first sub-shallow trench ST1 is ion implanted.

It can be understood that, as shown in Figure 10b, during the ion implantation into the sidewall of the first sub-shallow trench ST1 During the process, ions may also be implanted into the bottom wall W1 of the first sub-shallow trench ST1, so that the doping region DR may be in a grid shape and surround the bottom wall W1 of the first sub-shallow trench ST1.

It should be noted that the above doped region DR can be used to adjust the threshold voltage of the transistor to be formed, for example, can be used to increase the threshold voltage of the transistor to be formed.

S400, as shown in Figures 11a and 11b, etch the bottom wall W1 of the first sub-shallow trench ST1, and form a second sub-shallow trench ST2 below the first sub-shallow trench ST1, to obtain a structure including the first sub-shallow trench ST1. The trench ST1 and the shallow trench ST of the second sub-shallow trench ST2.

For example, this application can use a dry etching process or a wet etching process to etch the bottom wall W1 of the first sub-shallow trench ST1, and further remove the substrate 1 located in the preset shallow trench area A. part to form a second sub-shallow trench ST2 below the first sub-shallow trench ST1. The first sub-shallow trench ST1 and the second sub-shallow trench ST2 are connected.

As shown in FIG. 11a , after the second sub-shallow trench ST2 is formed, only a portion of the doped region DR surrounding the sidewall of the first sub-shallow trench ST1 remains.

The sum of the depths of the first sub-shallow trench ST1 and the second sub-shallow trench ST2 is less than the thickness of the substrate 1 . That is to say, as shown in FIG. 11b , after the second sub-shallow trench ST2 is formed, the bottom wall of the second sub-shallow trench ST2 is located inside the substrate 1 , and the second sub-shallow trench ST2 does not penetrate the substrate 1 . Since the shallow trench ST includes the first sub-shallow trench ST1 and the second sub-shallow trench ST2, the sum of the depths of the first sub-shallow trench ST1 and the depth of the second sub-shallow trench ST2 is shallow trench ST. The depth of the second sub-shallow trench ST2 is the bottom wall of the shallow trench ST. That is to say, the shallow trench ST does not penetrate the substrate 1 , and there is a certain distance between the bottom wall of the shallow trench ST and the second surface 1 b of the substrate 1 . This is beneficial to ensuring the structural stability of the substrate 1 .

Exemplarily, the depth of the shallow trench ST ranges from

For example, the depth of shallow trench ST is or wait.

The shape of the orthographic projection (or plan view shape) of the second sub-shallow trench ST2 on the plane of the substrate 1 is the same as the shape of the preset shallow trench area A. The cross-sectional shape of the second sub-shallow trench ST2 is, for example, rectangular or inverted trapezoid (as shown in Figure 11b).

S500, as shown in FIGS. 13a to 13d , the filling portion 4 is formed in the shallow trench ST.

For example, the material of the filling portion 4 is an insulating material, and the insulating material includes, for example, insulating oxide. For example, the material of the filling portion 4 includes silicon dioxide. The filling portion 4 fills at least the shallow trench ST.

The above-mentioned shallow trench ST, the filling portion 4 located in the shallow trench ST, and the doped region DR located in the substrate 1 can be called a shallow trench isolation structure, for example. On the one hand, this application can use the shallow trench ST in the shallow trench isolation structure to isolate the transistors to be formed. On the other hand, the application can use the filling portion 4 in the shallow trench isolation structure to improve the structural stability of the substrate 1. And isolate the transistor to be formed to improve the performance of the transistor to be formed. On the other hand, the doping region DR with injected ions can also be used to adjust the threshold voltage of the transistor to be formed, reduce the leakage current of the transistor to be formed, and improve the performance of the transistor to be formed. The performance of the transistor is improved thereby improving the narrow channel effect. This is conducive to compressing the channel size of the transistor to be formed, which in turn is conducive to reducing the area of the bit cell to be formed, and achieving higher density and higher performance applications.

It should be noted that this application decomposes the formation process of the shallow trench ST, using two etching processes to form the first sub-shallow trench ST1 and the second sub-shallow trench ST2 respectively, and then etching to form the second sub-shallow trench ST1. Sub-shallow trench ST2 Before that, ion implantation is performed on the exposed sidewalls of the first sub-shallow trench ST1. After the second sub-shallow trench ST2 is formed by etching, the filling portion 4 that at least fills the shallow trench ST is formed in one go.

Compared with the preparation method provided by one of the above implementations, since this application forms the shallow trench ST and then forms the filling portion 4 in the shallow trench ST that at least fills the shallow trench ST, on the one hand, it can avoid filling The filling part 4 is etched back to prevent the filling part 4 from being bombarded by plasma, ensuring the insulation performance and reliability of the filling part 4. On the other hand, it is possible to avoid breaking the vacuum during the formation of the filling part 4, thereby preventing the filling part 4 from contacting Defects are formed due to air. On the other hand, it can avoid increasing the engraving process and reduce process costs. In addition, since this application first performs ion implantation on the exposed sidewalls of the first sub-shallow trench ST1 and then forms the filling part 4, this can avoid implanting ions into the filling part 4, so that the filling part 4 can be without additional The influence of ion implantation can further ensure the insulation performance and reliability of the filling part 4 .

In some examples, in the above S200, the portion of the substrate 1 located in the preset shallow trench area A is etched, including: S210 to S230.

S210, as shown in FIG. 7a and FIG. 7b, a liner layer 2, a hard mask layer 3 and a photoresist layer 8 are sequentially formed on the substrate 1.

For example, this application may use chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination of thin film deposition processes. A liner layer 2 is formed on the first surface 1a of the substrate 1, and then a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to form a hard mask layer 3 on the liner layer 2, and then a coating process is used (For example, spin coating or dot coating, etc.) A photoresist layer 8 is formed on the hard mask layer 3 .

For example, the material of the liner layer 2 includes silicon dioxide, the material of the hard mask layer 3 includes silicon nitride, and the material of the photoresist layer 8 includes negative photoresist.

By disposing the liner layer 2 between the substrate 1 and the hard mask layer 3, the liner layer 2 can be used as a transition to relieve the stress between the substrate 1 and the hard mask layer 3.

S220, as shown in FIGS. 8a to 8b, the portion of the photoresist layer 8 located in the preset shallow trench area A is etched, and a first opening K1 is formed in the photoresist layer 8.

For example, this application may use a photolithography process to etch the portion of the photoresist layer 8 located in the preset shallow trench area A. Optionally, this application can set a mask on the photoresist layer 8, which blocks the portion of the photoresist layer 8 located in the preset shallow trench area A, and exposes the portion of the photoresist layer 8 located in the preset shallow trench area A. The portion outside the preset shallow trench area A is exposed to the photoresist layer 8 through a mask, so that the portion of the photoresist layer 8 outside the preset shallow trench area A is cured, and then the photoresist layer 8 is exposed. The layer 8 is developed, retaining the portion of the photoresist layer 8 located outside the preset shallow trench area A, and removing the portion of the photoresist layer 8 located in the preset shallow trench area A, so that in the photoresist layer 8 A first opening K1 is formed.

Among them, the photoresist layer 8 can protect the parts of the hard mask layer 3, the liner layer 2 and the substrate 1 that are blocked and shielded by the photoresist layer 8.

S230, as shown in Figures 9a to 9c, etch the hard mask layer 3, the liner layer 2 and the portion of the substrate 1 located in the preset shallow trench area A through the first opening K1. A second opening K2 is formed in layer 3 and liner layer 2 , and a first sub-shallow trench ST1 is formed in substrate 1 .

For example, this application can use a dry etching process or a wet etching process to etch the hard mask layer 3, the liner layer 2 and the portion of the substrate 1 located in the preset shallow trench area A.

This application can complete the etching of the hard mask layer 3, the liner layer 2 and the portion of the substrate 1 located in the preset shallow trench area A in one etching process, or this application can use multiple etching processes. An etching process is performed to complete the etching of the hard mask layer 3, the liner layer 2 and the portion of the substrate 1 located in the preset shallow trench area A.

In the case where multiple etching processes are used to complete the etching of the hard mask layer 3 , the liner layer 2 and the portion of the substrate 1 located in the preset shallow trench area A, the etching process includes, for example, but is not limited to : As shown in Figure 9b, the hard mask layer 3 and the liner layer 2 are etched through the first opening K1 in the photoresist layer 8, and a second opening K1 is formed in the hard mask layer 3 and the liner layer 2. Opening K2; as shown in Figure 9c, through the above-mentioned first opening K1 and the second opening K2, the portion of the substrate 1 located in the preset shallow trench area A is etched, and a first sub-shallow trench is formed in the substrate 1. Trench ST1.

It can be understood that the hard mask layer 3 has a high etching selectivity ratio. Therefore, the sidewall morphology and bottom wall morphology of the first sub-shallow trench ST1 are relatively regular, and the morphology of the first sub-shallow trench ST1 is relatively regular. The width is relatively uniform, and the width of the first sub-shallow trench ST1 is basically the same as the width of the second opening K2.

It should be noted that in this application, after forming the first sub-shallow trench ST1, ion implantation can be performed on the sidewalls of the first sub-shallow trench ST1, and then the bottom wall of the first sub-shallow trench ST1 can be etched. , forming the second sub-shallow trench ST2, and obtaining the shallow trench ST. That is to say, this application mainly uses the hard mask layer 3 to define the first sub-shallow trench ST1 and then define the shallow trench ST.

Compared with the preparation method provided by the other implementation method mentioned above, the method of forming the shallow trench ST1 in this application is simpler. On the one hand, it can reduce the process of forming the insulating film 7a and etching the insulating film 7a to form the sidewalls 7 process to reduce process costs. On the other hand, the width of the second opening K1 and the width of the second opening K2 can be made consistent with the width of the shallow trench ST, thereby avoiding the need to pre-set the active area 5 due to the provision of sidewalls 7 The photolithography dimensions are modified to reduce the process risk of the preparation method provided by this application.

In some examples, the depth range of the above-mentioned first sub-shallow trench ST1 is (angstrom)

For example, the depth of the first shallow trench ST1 may be or wait.

By limiting the depth of the first shallow trench ST1, the amount of ions injected into the sidewalls of the first sub-shallow trench ST1 can be ensured, the threshold voltage of the transistor to be formed can be effectively adjusted, and the narrow trench can be effectively improved. Tao effect. This can avoid the situation that it is difficult to adjust the threshold voltage of the transistor to be formed and improve the narrow channel effect due to the small amount of ion implantation due to the small depth of the first sub-shallow trench ST1. Alternatively, it can avoid the situation that the first sub-shallow trench ST1 has a small depth. The depth of the sub-shallow trench ST1 is relatively large, resulting in a large amount of ion implantation, thereby reducing the adjustment effect of the threshold voltage of the transistor to be formed and the improvement effect of the narrow channel effect.

In some examples, in the above-mentioned S300, ion implantation is performed on the sidewall of the first sub-shallow trench ST1, including: S310˜S320.

S310, as shown in Figure 10a and Figure 10b, remove the above photoresist layer 8.

For example, this application can use a plasma font etching process, a wet etching process or any other etching process to remove the photoresist layer 8 and expose the hard mask layer 3 .

S320, as shown in FIG. 10a and FIG. 10b, using the hard mask layer 3 and the liner layer 2 as masks, ion implantation is performed into the sidewall of the first sub-shallow trench ST1 through the second opening K2. There is an included angle between the direction of ion implantation and the direction perpendicular to the substrate 1, and the included angle is, for example, α.

It can be understood that during the process of ion implantation into the sidewall of the first sub-shallow trench ST1, the hard mask layer 3 and the liner layer 2 can be used as masks to shield the first surface of the substrate 1. Shielding ensures ion energy It can be implanted into the sidewall of the first shallow trench ST1 to prevent ions from being implanted into the first surface of the substrate 1 and thus avoid affecting the performance of the transistor to be formed.

For example, there is an angle α between the direction of ion implantation and the direction perpendicular to the substrate 1, which means that the direction of ion implantation is not parallel to the direction perpendicular to the substrate 1, and the direction of ion implantation is not parallel to the direction where the substrate 1 is located. The angle between the directions of the planes is less than 90°.

This ensures that ions can be implanted into the sidewall of the first sub-shallow trench ST1, thereby adjusting the threshold voltage of the transistor to be formed and improving the narrow channel effect.

In some examples, the angle α between the direction of the ion implantation and the direction perpendicular to the substrate 1 ranges from 5° to 45°.

For example, the above-mentioned included angle α may be 5°, 10°, 15°, 20°, 25°, 29°, 33°, or 45°, etc.

This can ensure that most of the ions can be injected into the sidewalls of the first sub-shallow trench ST1 and reduce the amount of ions injected into the bottom wall of the first sub-shallow trench ST1, so as to achieve the threshold voltage of the transistor to be formed. While adjusting and improving the narrow channel effect, it also reduces the usage (or waste) of ions and reduces process costs.

It can be understood that, as shown in Figure 11a and Figure 11b, after ion implantation is performed on the sidewall of the first sub-shallow trench ST1, the present application can still use the hard mask layer 3 and the liner layer 2 as masks, through The second opening K2 is used to etch the bottom wall of the first sub-shallow trench ST1 to form the second sub-shallow trench ST2, so as to ensure the uniformity of the second sub-shallow trench ST2.

In some examples, in the above S500, the filling portion 4 is formed in the shallow trench ST, including: S510 to S520.

S510, as shown in FIG. 12a and FIG. 12b, a filling film 4a is formed on the hard mask layer 3, and a part of the filling film 4a is located in the shallow trench ST.

For example, this application can use a film deposition process such as CVD, PVD, ALD or any combination thereof to form the filling film 4a. Among them, a part of the filling film 4a is located in the shallow trench ST and fills the shallow trench ST; the other part of the filling film 4a is located on the hard mask layer 3 and covers the hard mask layer 3.

S520, as shown in FIGS. 13a and 13b, remove the portion of the filling film 4a covering the hard mask layer 3 and the hard mask layer 3, leaving the portion of the filling film 4a located in the shallow trench ST to form the filling portion 4.

For example, this application can use a chemical mechanical polish (CMP) process to polish the filling film 4a to planarize it, and expose the hard mask layer 3, and then use a wet etching process to polish the hard mask layer. 3 is etched to remove the hard mask layer 3 and expose the liner layer 2. The side surface of the filling portion 4 away from the substrate 1 may be higher than the side surface of the liner layer 2 away from the substrate 1 .

It can be understood that the filling film 4a and the hard mask layer 3 have different polishing rates. In this way, during the process of grinding and removing the filling film 4a, part of the hard mask layer 3 may be removed.

It can be seen from the above that the filling part 4 in this application has an integrated structure and is formed at one time through a semiconductor process (that is, a CMP process). This not only avoids the formation of defects in the filling part 4, prevents the filling part 4 from being affected by additional ion implantation, ensures the insulation performance and reliability of the filling part 4, but also simplifies the preparation process of the filling part 4 and reduces the process cost.

In some examples, the preparation method provided by this application also includes: annealing the filling film 4a formed in the above S510.

For example, this application may use an annealing process such as a thermal annealing process or a laser annealing process to anneal the filling film 4a.

In some examples, the preparation method provided by this application further includes: annealing the doped region DR.

For example, this application may use an annealing process such as a thermal annealing process or a laser annealing process to anneal the doped region DR.

This can repair the lattice damage of the material caused by ion implantation and activate the implanted ions.

For example, in this application, during the annealing process of the above-mentioned filling film 4a, the doping region DR can also be annealed.

In other words, this application can integrate the annealing process of the doped region DR into the existing annealing process in the preparation method of the semiconductor structure, and simultaneously perform the annealing process on the filling film 4a and the doped region DR in one annealing process. The annealing process can avoid the introduction of additional annealing processes, simplify the preparation process of semiconductor structures, and reduce process costs.

In some embodiments, the preparation method provided by this application also includes: S600 to S800.

S600, as shown in FIG. 13c, ion implantation is performed on the portion of the substrate 1 surrounded by the shallow trench ST to form the active region 5.

For example, this application may use multiple ion implantation processes to form the active region 5 .

For example, this application can use three ion implantation processes to form the active region 5 .

Optionally, in the first ion implantation process, ions can be implanted into the interior of the substrate 1 to form the well region 51 in the substrate 1; wherein, the depth of the first ion implantation is greater than the first sub-shallow trench. The depth of trench ST1 is smaller than the depth of shallow trench ST. Depending on the type of implanted ions, the formed well region 51 may be a P well (P well) or an N well (N well).

In the second ion implantation process, ions can be implanted into the well region 51 and deep into the interior of the substrate 1 to form an anti-penetration layer in the substrate 1; wherein, the depth of the second ion implantation is smaller than the depth of the second ion implantation process. The depth of one ion implantation.

In the third ion implantation process, ions may be implanted into the well region 51 and substantially close to or located at the first surface 1 a of the substrate 1 to form a trench substantially close to or located at the first surface 1 a of the substrate 1 Road District 52.

In some examples, in the above-mentioned S600, ion implantation is performed on the portion of the substrate 1 surrounded by the shallow trench ST, including: S610˜S620.

S610, remove the photoresist layer 8 and the hard mask layer 3.

Here, for the process of removing the photoresist layer 8 and the hard mask layer 3, reference can be made to the descriptions in S310 and S320 above, which will not be described again here.

S620, as shown in FIG. 13c, using the liner layer 2 as a protective layer, ions are implanted through the liner layer 2 into the portion of the substrate 1 surrounded by the shallow trench ST.

It can be understood that during the ion implantation process into the portion of the substrate 1 surrounded by the shallow trench ST, the liner layer 2 can protect the surface of the substrate 1 (that is, the first surface 1a) to prevent the liner from forming. The surface of bottom 1 is damaged.

S700, as shown in FIGS. 14a to 15b, the gate dielectric layer 6 and the gate electrode 9 are formed on the active area 5.

In some examples, as shown in Figure 13d, before the above-mentioned S700, the preparation method provided by this application further includes: removing the liner layer 2. This can avoid affecting the formation of the gate dielectric layer 6 and the gate electrode 9 .

For example, this application may use a wet etching process or a dry etching process to remove the liner layer 2 .

After removing the liner layer 2, as shown in Figure 14a and Figure 14b, this application uses a thermal oxidation process to A gate dielectric film 6 a is formed on the source region 5 , and the gate dielectric film 6 a is located on the first surface 1 a of the substrate 1 . Then, a deposition process or a sputtering process is used to form a gate conductive film on the gate dielectric film 6a, and then a photolithography process or the like can be used to etch the gate dielectric film 6a and the gate conductive film to form the gate dielectric layer 6 and the gate electrode 9. Among them, the gate dielectric layer 6 and the gate electrode 9 are strip-shaped, covering a part of the active area 5 and dividing the uncovered part of the active area 5 into two parts.

For example, the material of the gate dielectric layer 6 includes an oxide material, and the oxide material includes, for example, silicon oxide.

Using a thermal oxidation process to form the gate dielectric film 6a is beneficial to improving the quality of the subsequently formed gate dielectric layer 6.

S800, as shown in FIG. 16a and FIG. 16b, ion implantation is performed in the portion of the active region 5 that is not covered by the gate dielectric layer 6 and the gate electrode 9 to form the source S and drain D of the transistor T.

For example, during the ion implantation process, the portion of the active region 5 covered by the gate dielectric layer 6 and the gate electrode 9 is blocked, and ions are basically not implanted into this portion, but are injected into the portion that is not covered by the gate dielectric layer 6 and the gate electrode 9 . The portion covered by the gate electrode 9 , that is, the gate dielectric layer 6 and both sides of the gate electrode 9 .

It can be understood that, after ion implantation, the portion of the active region 5 that is not covered by the gate dielectric layer 6 and the gate electrode 9 will form two conductors located on both sides of the gate dielectric layer 6 and the gate electrode 9 respectively. The two conductors form the source S and drain D of the transistor T respectively. The part of the channel region 52 located between the source electrode S and the drain electrode D and covered by the gate dielectric layer 6 and the gate electrode 9 constitutes a channel that only provides T.

Using the above preparation method, the transistor T can be prepared and formed. The transistor T can be a PMOS transistor or an NMOS transistor. A semiconductor structure in which a plurality of transistors T is formed in the substrate 1 may constitute, for example, an integrated circuit or a control circuit.

It can be understood that after the active region 5 is formed, the channel region 52 in the active region 5 and the doping region DR (for example, called a local channel) are in contact. After the transistor T is fabricated and formed, the channel of the transistor T will still be in contact with the doped region DR. Therefore, additional channel implantation will be formed in the contact area between the two. This additional channel injection will have an impact on the channel of the transistor T, which can adjust and stabilize the threshold voltage of the transistor T, reduce the leakage of the transistor T, improve and suppress the narrow channel effect, and improve the performance of the transistor T. This is beneficial to reducing the channel width of the transistor T, reducing the area of the transistor T, and facilitating the formation of more transistors T in the substrate 1 .

It is worth mentioning that the channel width of the transistor T formed using the preparation method provided by this application can reach the minimum design value required by the design rule manual, or even be smaller than the minimum design value required by the design rule manual. That is to say, using the preparation method provided by this application can greatly increase the number of transistors T formed in the substrate 1, increase the density of the transistors T, and achieve high-performance and high-density applications.

In some examples, the type of the above-mentioned transistor T is related to the type of ions implanted into the sidewall of the first sub-shallow trench ST1.

For example, the transistor T is an N-type transistor (that is, an NMOS transistor), and the ions injected into the sidewall of the first sub-shallow trench ST1 are P-type ions.

For example, the transistor is a P-type transistor (that is, a PMOS transistor), and the ions injected into the sidewall of the first sub-shallow trench ST1 are N-type ions.

That is to say, the type of transistor T and the type of ions injected into the sidewall of the first sub-shallow trench ST1 are opposite. Since the doping region DR is located at the position of the channel region 52 in the active region 5, this can make The channel region 52 is in contact with the doped region DR to form an inversion layer. The doped region DR can then be used to adjust the threshold voltage of the transistor T, reduce the leakage of the transistor T, improve and suppress the narrow channel effect, and improve the performance of the transistor T. .

It can be understood that in the above S800, the number of transistors T formed is multiple. The plurality of transistors T can be of the same type, for example, they are all N-type transistors (that is, NMOS transistors) or all are P-type transistors (that is, PMOS transistors); or the types of the plurality of transistors T can also be different, for example, At least one transistor T is an N-type transistor (that is, an NMOS transistor), and at least one transistor T is a P-type transistor (that is, a PMOS transistor).

When two adjacent transistors T are of different types, the types of ions implanted in the two sidewalls of the first sub-shallow trench ST1 between the two adjacent transistors T are different.

Optionally, in the above S600, the formed well regions 51 are all P-wells, and accordingly, the formed transistors are all N-type transistors (that is, NMOS transistors). At this time, the ions injected into the sidewall of the first sub-shallow trench ST1 are all boron ions.

For example, the implantation energy range of boron ions includes but is not limited to 1Kev～100KeV, and the dose range includes but is not limited to 1e ¹¹ /cm ² to 1e ¹⁴ /cm ² .

For example, the implantation energy of boron ions is 1Kev, 15Kev, 30Kev, 35Kev, 70Kev or 100KeV, etc. The dosage is 1e ¹¹ /cm ² , 2e ¹¹ /cm ² , 1e ¹² /cm ² , 5e ¹² /cm ² or 1e ¹⁴ /cm ² etc.

It should be noted that the dose of boron ions can be determined according to the amount of ion implantation in the channel. The two cooperate with each other to effectively adjust the threshold voltage of the transistor T, reduce the leakage of the transistor T, and improve and suppress the narrow channel effect. Improve the performance of transistor T.

In some embodiments, the preparation method provided by this application further includes: S900.

S900, as shown in FIG. 17, the memory structure 10 is formed on the first pole of the transistor T. The memory structure 10 is electrically connected to the first pole. The first electrode is source S or drain D.

In some examples, as shown in FIG. 17 , the present application can also form a first interconnection line between the first pole of the transistor T and the memory structure 10 , and one end of the first interconnection line is electrically connected to the first pole of the transistor T. , the other end is electrically connected to the storage structure 10 .

In some examples, as shown in FIG. 17 , the present application can also form a second interconnection line on the storage structure 10 , one end of the second interconnection line is electrically connected to the storage structure 10 , and the other end is connected to other signal lines (such as board lines). ) electrical connection.

For example, as shown in FIG. 17 , the above-mentioned memory structure 10 includes but is not limited to a first electrode layer 101 , a memory function layer 102 and a second electrode layer 103 . Among them, the storage function layer 102 is used to store data.

It can be understood that the transistor T and the memory structure 10 electrically connected thereto can constitute a bit cell, and the bit cell array can constitute a memory. By improving the method of forming the shallow trench ST, the doped region DR and the filling portion 4, this application can effectively use the doped region DR to adjust the threshold voltage of the transistor T, reduce the leakage of the transistor T, and improve and suppress the narrow channel effect. So that the width of the channel 52 of the transistor T can be reduced, the area of the transistor T can be reduced, the spacing between different active areas 5 can be reduced, and the area of the bit cell can be reduced, so that more transistors T can be provided and more transistors T can be provided. More bit cells enable higher-density, higher-performance applications.

There are many types of the above-mentioned storage function layer 102, which can be selected and set according to actual needs.

For example, the above-mentioned storage functional layer 102 includes but is not limited to a ferroelectric layer, a resistive layer, a phase change layer, or a magnetic tunnel junction (MTJ).

Here, in the case where the storage function layer 102 includes a ferroelectric layer, the type of memory may be a random access memory (FeRAM). In the case where the storage function layer 102 includes a resistive switching layer, the type of memory may be resistive random access memory (RRAM). in storage function When the layer 102 includes a phase change layer, the type of memory may be a phase change memory (PCM). In the case where the storage function layer 102 includes a magnetic tunnel junction, the type of memory may be magnetoresistive random access memory (MRAM).

As shown in Figures 18 to 20, some embodiments of the present application provide a semiconductor structure 100. The semiconductor structure 100 can be prepared and formed, for example, using the preparation methods provided in some of the above embodiments.

In some examples, as shown in FIG. 18 , semiconductor structure 100 includes substrate 1 and fill 4 .

For example, as shown in FIG. 18 , a shallow trench ST is formed on the first surface 1 a of the substrate 1 . The shallow trench ST includes a first sub-shallow trench ST1 close to the first surface 1a of the substrate 1, and a second sub-shallow trench ST2 located below the first sub-shallow trench ST1. The second sub-shallow trench ST2 is deeper into the interior of the substrate 1 than the first sub-shallow trench ST1. The sidewalls of the first sub-shallow trench ST1 are, for example, perpendicular to the plane where the substrate 1 is located, and the sidewalls of the second sub-shallow trench ST2 are, for example, arranged at an obtuse angle to the plane where the substrate 1 is located, so that the first sub-shallow trench ST1 The side wall of the second sub-shallow trench ST2 may be arranged at an obtuse angle.

The substrate 1 has a doping region DR, and ions are doped in the doping region DR. The doping region DR is located on the sidewall of the first sub-shallow trench ST1 and surrounds the sidewall of the first sub-shallow trench ST1.

The filling portion 4 is located in the shallow trench ST. The filling portion 4 fills at least the shallow trench ST, for example.

For example, the above-mentioned filling part 4 has an integrated structure, that is, the structure of the filling part 4 is continuous and not divided. In the process of preparing the filling part 4, the filling part 4 is formed at once.

For example, compared with the second sub-shallow trench ST2, the first sub-shallow trench ST1 and the doping region DR are formed earlier.

That is to say, the above-mentioned shallow trench ST is formed in two times, one time to form the first sub-shallow trench ST1, and the other time to form the second sub-shallow trench ST2. Moreover, before forming the second sub-shallow trench ST2, ion implantation is performed on the sidewall of the first sub-shallow trench ST1 to form a doped region DR. After the second sub-shallow trench ST2 is formed, the filling portion 4 that at least fills the shallow trench ST is formed at once.

The semiconductor structure 100 provided by this application can, on the one hand, use the doping region DR to adjust the threshold voltage of the transistor, reduce the leakage current of the transistor, and improve the performance of the transistor, thereby improving the narrow channel effect and compressing the channel size of the transistor. Reduce the area of the bit cell to achieve higher density and higher performance applications. On the other hand, it can avoid damaging the filling part 4 and avoid doping ions in the filling part 4, which will affect the insulation performance and reliability of the filling part 4.

In some embodiments, as shown in FIG. 19 , the above-mentioned semiconductor structure 100 further includes a transistor T. The transistor T includes an active region 5 , a source S, a drain D, a gate dielectric layer 6 and a gate 9 .

In some examples, as shown in FIG. 19 , the active region 5 extends from the first surface 1 a of the substrate 1 to the interior of the substrate 1 . The active region 5 also includes a channel region 52 (or channel) located close to the first surface 1 a of the substrate 1 . The gate dielectric layer 6 is located on the first surface 1 a of the substrate 1 and covers the channel region 52 . The gate electrode 9 is located on the gate dielectric layer 6 . The source electrode S and the drain electrode D are located in the active region 5 , wherein the channel region 52 , the gate dielectric layer 6 and the gate electrode 9 are all located between the source electrode S and the drain electrode D.

Exemplarily, the active area 5 is surrounded by shallow trenches ST.

Since the doped region DR surrounds the sidewall of the first sub-shallow trench ST1 in the shallow trench ST, the doped region DR also surrounds the active region 5 and is in contact with the channel region 52 in the active region 5 . The area where the doped region DR and the channel region 52 are in contact will form an additional channel injection. This additional channel injection will have an impact on the channel of the transistor T, and can adjust and stabilize the threshold voltage of the transistor T, and reduce the threshold voltage of the transistor T. leakage, improve and suppress the narrow channel effect, Improve the performance of transistor T. This is beneficial to reducing the channel width of the transistor T, reducing the area of the transistor T, and facilitating the formation of more transistors T in the substrate 1 .

In some embodiments, as shown in FIG. 20 , the above-mentioned semiconductor structure 100 further includes: a memory structure 10 . The memory structure 10 is located on the first pole and is electrically connected to the first pole. The first pole is the source S or the drain D of the transistor T. The storage structure 10 is used to store data, and the storage structure 10 and the transistor T electrically connected thereto may be called a bit cell.

By arranging the memory structure 10 in the above-mentioned semiconductor structure 100, the semiconductor structure 100 can constitute a memory. By electrically connecting the storage structure 10 to the transistor T, the storage structure 10 can be controlled, thereby enabling data storage or reading.

It can be understood that since the present application can improve and suppress the narrow channel effect, reduce the channel width of the transistor T, and reduce the area of the transistor T, it can further reduce the area of the bit cell and enable more transistors T to be provided. Configure more bit cells to enable higher density, higher performance applications.

Here, in the case where the storage function layer 102 includes a ferroelectric layer, the type of memory may be a random access memory (FeRAM). In the case where the storage function layer 102 includes a resistive switching layer, the type of memory may be resistive random access memory (RRAM). In the case where the storage function layer 102 includes a phase change layer, the type of memory may be a phase change memory (PCM). In the case where the storage function layer 102 includes a magnetic tunnel junction, the type of memory may be magnetoresistive random access memory (MRAM).

Some embodiments of the present application provide an electronic device. The electronic device can be a mobile phone (mobile phone), tablet computer (pad), television, desktop computer, laptop computer, handheld computer, notebook computer, ultra-mobile personal computer (UMPC), netbook, As well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, smart wearable devices (such as , smart watches, smart bracelets), vehicle-mounted equipment, smart home equipment and/or smart city equipment. The embodiments of this application do not place special restrictions on the specific types of electronic equipment.

FIG. 21 is an architectural schematic diagram of an electronic device provided by an exemplary embodiment of the present application. As shown in Figure 21, the electronic device 1000 includes: a memory 100, a processor 200, an input device 300, an output device 400 and other components. Those skilled in the art can understand that the structure of the electronic device shown in Figure 21 does not constitute a limitation on the electronic device 100, and the electronic device 100 may include more or less components than those shown in Figure 21. Alternatively, some of the components shown in FIG. 1 may be combined, or may be arranged differently than those shown in FIG. 21 .

The memory 100 is used to store software programs and modules. The memory 100 mainly includes a storage program area and a storage data area, wherein the storage program area can store the operating system, at least one application program required for a function (such as a sound playback function, an image playback function, etc.), etc.; the storage data area can store an electronic program according to the electronic program. Data created by the use of the device (such as audio data, image data, phone book, etc.), etc. In addition, the memory 100 includes an external memory 110 and an internal memory 120 . Data stored in the external memory 110 and the internal memory 120 can be transferred to each other. The external memory 110 includes, for example, a hard disk, a USB disk, a floppy disk, etc. The internal memory 120 includes, for example, static random access memory (static random access memory). random access memory (SRAM), dynamic random access memory (dynamic random access memory (DRAM)), read-only memory, etc.

The processor 200 is the control center of the above-mentioned electronic device 1000. It uses various interfaces and lines to connect various parts of the entire electronic device 1000, by running or executing software programs and/or modules stored in the memory 100, and by calling the software programs and/or modules stored in the memory 100. The electronic device 1000 performs various functions and processes data based on the data in the electronic device 1000, thereby overall monitoring the electronic device 1000. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (artificial intelligence, AI) processor, a digital signal processor (DSP), a neural network processor, or other processors. Application specific integrated circuit (ASIC), etc. In FIG. 21 , the processor 200 is a CPU as an example. The CPU may include a calculator 210 and a controller 220 . The arithmetic unit 210 obtains the data stored in the internal memory 120 and processes the data stored in the internal memory 120. The processed result is usually sent back to the internal memory 120. The controller 220 can control the arithmetic unit 210 to process data, and the controller 220 can also control the external memory 110 and the internal memory 120 to store data or read data.

The input device 300 is used to receive input numeric or character information and generate key signal input related to user settings and function control of the electronic device 1000 . By way of example, the input device 300 may include a touch screen and other input devices. The touch screen, also known as the touch panel, can collect the user's touch operations on or near the touch screen (such as the user's operations on or near the touch screen using fingers, stylus, or any suitable objects or accessories), and perform operations based on preset settings. The program drives the corresponding connection device. Optionally, the touch screen may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact point coordinates, and then sends it to the touch controller. to the processor 200, and can receive commands sent by the processor 200 and execute them. In addition, touch screens can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. Other input devices may include, but are not limited to, one or more of physical keyboards, function keys (such as volume control keys, power switch keys, etc.), trackballs, mice, joysticks, etc. The controller 220 in the above-mentioned processor 200 can also control the input device 300 to receive the input signal or not to receive the input signal. In addition, the input numeric or character information received by the input device 300 and the key signal input generated related to user settings and function control of the electronic device may be stored in the internal memory 120 .

The output device 400 is used to output signals corresponding to data input by the input device 300 and stored in the internal memory 120 . For example, the output device 400 outputs a sound signal or a video signal. The controller 220 in the above-mentioned processor 200 can also control the output device 400 to output a signal or not to output a signal.

It should be noted that the thick arrows in Figure 21 are used to indicate data transmission, and the direction of the thick arrow indicates the direction of data transmission. For example, a one-way arrow between the input device 300 and the internal memory 120 indicates that data received by the input device 300 is transmitted to the internal memory 120 . For another example, the bidirectional arrow between the operator 210 and the internal memory 120 indicates that the data stored in the internal memory 120 can be transferred to the operator 210 , and the data processed by the operator 210 can be transferred to the internal memory 120 . The thin arrows in Figure 21 indicate components that controller 220 can control. For example, the controller 220 can control the external memory 110, the internal memory 120, the operator 210, the input device 300, the output device 400, etc.

Optionally, the electronic device 1000 shown in FIG. 21 may also include various sensors. For example, gyroscope sensor, hygrometer sensor, infrared sensor, magnetometer sensor, etc., which will not be described in detail here. Optionally, the power The sub-device 1000 may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which will not be described again here.

It can be understood that the semiconductor structure provided by the embodiment of the present application can be used as the memory 100 in the above-mentioned electronic device 1000. For example, the semiconductor structure provided by the embodiment of the present application can be used as the external memory 110 in the above-mentioned memory 100, or can be used as the internal memory 120 in the above-mentioned memory 100. In addition, the semiconductor structure provided by this application can be used in independent memory chip particles.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that come to mind within the technical scope disclosed by the present disclosure by any person familiar with the technical field should be covered. within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A method for preparing a semiconductor structure, characterized in that the preparation method includes:

providing a substrate having a preset shallow trench area;

Etching the portion of the substrate located in the preset shallow trench area to form a first sub-shallow trench;

Perform ion implantation on the sidewall of the first sub-shallow trench to form a doped region in the substrate;

Etch the bottom wall of the first sub-shallow trench and form a second sub-shallow trench below the first sub-shallow trench to obtain the first sub-shallow trench and the second sub-shallow trench. Shallow trenches of trenches;

A filling portion is formed in the shallow trench.
The preparation method according to claim 1, wherein etching the portion of the substrate located in the preset shallow trench region includes:

sequentially forming a liner layer, a hard mask layer and a photoresist layer on the substrate;

Etching the portion of the photoresist layer located in the preset shallow trench area to form a first opening in the photoresist layer;

Through the first opening, the hard mask layer, the liner layer and the portion of the substrate located in the preset shallow trench area are etched. A second opening is formed in the pad layer, and the first sub-shallow trench is formed in the substrate.
The preparation method according to claim 2, wherein the ion implantation into the sidewall of the first sub-shallow trench includes:

Remove the photoresist layer;

Using the hard mask layer and the liner layer as masks, ion implantation is performed on the sidewall of the first sub-shallow trench through the second opening; the direction of the ion implantation is perpendicular to the There is an angle between the directions of the substrates.
The preparation method according to claim 3, characterized in that the angle between the direction of the ion implantation and the direction perpendicular to the substrate ranges from 5° to 45°.
The preparation method according to claim 2, wherein forming a filling portion in the shallow trench includes:

forming a filling film on the hard mask layer, with a portion of the filling film located in the shallow trench;

The part of the filling film covering the hard mask layer and the hard mask layer is removed, and the part of the filling film located in the shallow trench is retained to form the filling part.
The preparation method according to claim 5, characterized in that the preparation method further includes:

The doped region is annealed.
The preparation method according to claim 6, characterized in that the preparation method further includes:

annealing the filled film;

In the process of annealing the filling film, the doped region is also annealed.
The preparation method according to claim 2, characterized in that the preparation method further includes:

Perform ion implantation on the portion of the substrate surrounded by the shallow trench to form an active region;

forming a gate dielectric layer and a gate electrode on the active area;

Ions are implanted into the portion of the active area that is not covered by the gate dielectric layer and the gate electrode to form the source and drain of the transistor.
The preparation method according to claim 8, characterized in that the pair of substrates is covered by the shallow trench. The part surrounding the groove is ion implanted, including:

Remove the photoresist layer and the hard mask layer;

Using the liner layer as a protective layer, ions are implanted through the liner layer into the portion of the substrate surrounded by the shallow trench.
The preparation method according to claim 9, characterized in that, before sequentially forming a gate dielectric layer and a gate electrode on the active region, the preparation method further includes:

Remove the backing layer.
The preparation method according to claim 8, wherein the transistor is an N-type transistor, and the ions injected into the sidewall of the first sub-shallow trench are P-type ions; or,

The transistor is a P-type transistor, and the ions injected into the sidewall of the first sub-shallow trench are N-type ions.
The preparation method according to claim 11, wherein the transistor is an N-type transistor, and the ions injected into the sidewall of the first sub-shallow trench are boron ions.
The preparation method according to claim 8, characterized in that the preparation method further includes:

A storage structure is formed on the first electrode, and the storage structure is electrically connected to the first electrode; the first electrode is the source electrode or the drain electrode.
The preparation method according to any one of claims 1 to 13, characterized in that the depth range of the first sub-shallow trench is
A semiconductor structure, characterized in that the semiconductor structure includes:

A substrate has a doped region; a shallow trench is provided on the first surface of the substrate;

The filling part is located in the shallow groove and has an integrated structure;

Wherein, the shallow trench includes a first sub-shallow trench close to the first surface of the substrate, and a second sub-shallow trench located below the first sub-shallow trench, and the doped region is located at The sidewalls of the first sub-shallow trench; compared to the second sub-shallow trench, the first sub-shallow trench and the doped region are formed earlier.
The semiconductor structure according to claim 15, characterized in that the semiconductor structure further includes:

An active area extends from the first surface of the substrate to the interior of the substrate; the active area is surrounded by the shallow trench;

Source and drain electrodes located in the active area;

A gate dielectric layer located on the first surface of the substrate and between the source electrode and the drain electrode;

A gate electrode is located on the gate dielectric layer.
The semiconductor structure according to claim 16, wherein the semiconductor structure further comprises: a memory structure;

The memory structure is located on the first pole and is electrically connected to the first pole; the first pole is the source electrode or the drain electrode.
An electronic device, characterized in that the electronic device includes the semiconductor structure according to any one of claims 15 to 17.