WO2023206706A1

WO2023206706A1 - Design rule check method and device

Info

Publication number: WO2023206706A1
Application number: PCT/CN2022/096467
Authority: WO
Inventors: 范亚茹
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-04-24
Filing date: 2022-05-31
Publication date: 2023-11-02
Also published as: CN116976274A

Abstract

A design rule check method and device, relating to the technical field of semiconductors. The method comprises: determining the position of a target node in a circuit schematic diagram; according to the position of the target node in the circuit schematic diagram, determining a target position of the target node in a circuit layout corresponding to the circuit schematic diagram; and obtaining a layout design rule corresponding to the target node, and checking whether design parameters of a device arranged at the target position in the circuit layout satisfy the layout design rule. The method can effectively improve the performance and yield of a semiconductor device.

Description

Design rule checking methods and equipment

This disclosure claims priority to the Chinese patent application filed with the China Patent Office on April 24, 2022, with application number 202210434358. middle.

Technical field

Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a design rule checking method and device.

Background technique

At present, general chip design uses a sign-off process, that is, when the design is completed, a design rule check (DRC) is used to check whether the current design violates the design rules.

However, in order to improve the performance and yield of semiconductor devices, layout design will have some special requirements. For example, there will be high-voltage nodes in the circuit. These high-voltage nodes will have special rule requirements during layout design. Therefore, there is an urgent need to provide a new Design rule checking method to deal with some special needs in layout design, thereby improving the performance and yield of semiconductor devices.

Contents of the invention

Embodiments of the present disclosure provide a design rule checking method and device, which can improve the performance and yield of semiconductor devices.

In a first aspect, embodiments of the present disclosure provide a design rule checking method, which method includes:

Determine the position of the target node in the circuit schematic diagram, where the nodes in the circuit schematic diagram are the connection points between the devices in the circuit schematic diagram;

Determine the target position of the target node in the circuit layout corresponding to the circuit schematic diagram according to the position of the target node in the circuit schematic diagram;

Obtain the layout design rule corresponding to the target node, and check whether the design parameters of the device arranged at the target position in the circuit layout satisfy the layout design rule.

In a second aspect, embodiments of the present disclosure provide a design rule checking device, which includes:

A determination module, used to determine the position of the target node in the circuit schematic diagram, where the nodes in the circuit schematic diagram are the connection points between the devices in the circuit schematic diagram;

A positioning module, configured to determine the target position of the target node in the circuit layout corresponding to the circuit schematic diagram according to the position of the target node in the circuit schematic diagram;

The first checking module is used to obtain the layout design rules corresponding to the target node, and check whether the design parameters of the devices arranged at the target position in the circuit layout satisfy the layout design rules.

In a third aspect, embodiments of the present disclosure provide an electronic device, including: at least one processor and a memory;

The memory stores computer execution instructions;

The at least one processor executes the computer execution instructions stored in the memory, so that the at least one processor executes the design rule checking method provided in the first aspect.

In a fourth aspect, embodiments of the present disclosure provide a computer-readable storage medium that stores computer-executable instructions. When a processor executes the computer-executable instructions, the design provided in the first aspect is implemented. Rule checking method.

In a fifth aspect, an embodiment of the present disclosure provides a computer program product, including a computer program. When the computer program is executed by a processor, the design rule checking method as provided in the first aspect is implemented.

The design rule checking method and device provided by the embodiments of the present disclosure determine the position of the target node in the circuit schematic diagram and determine the target position of the target node in the circuit layout corresponding to the circuit schematic diagram based on the position of the target node in the circuit schematic diagram. ; Obtain the layout design rules corresponding to the target node, and check whether the design parameters of the devices arranged at the target position in the circuit layout meet the layout design rules, which can cope with some special needs in layout design, thereby effectively improving the performance of semiconductor devices performance and yield.

Description of the drawings

Figure 1 is a schematic flowchart of steps of a design rule checking method provided in an embodiment of the present disclosure;

Figure 2 is a schematic diagram of two circuit schematic diagrams provided in embodiments of the present disclosure;

Figure 3 is a circuit layout of a semiconductor device provided in an embodiment of the present disclosure;

Figure 4 is a schematic flowchart of steps of another design rule checking method provided in an embodiment of the present disclosure;

Figure 5 is a schematic diagram of a program module of a design rule checking device provided in an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments These are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this disclosure. In addition, although the disclosure in this disclosure is introduced in terms of one or several exemplary examples, it should be understood that each aspect of the disclosure may also individually constitute a complete embodiment.

It should be noted that the brief description of terms in this disclosure is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of the disclosure. Unless otherwise stated, these terms should be understood according to their ordinary and usual meaning.

The terms "first", "second", etc. in the description and claims of this disclosure and the above-mentioned drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence. Unless otherwise noted. It is to be understood that the terms so used are interchangeable under appropriate circumstances and, for example, the embodiments of the present disclosure can be implemented in an order other than that illustrated or described.

In addition, the terms "including" and "having" and any variations thereof are intended to cover but not exclusively include, for example, a product or device that includes a range of components need not be limited to those components explicitly listed, but may include There are other components not expressly listed or inherent to these products or devices.

The term "module" as used in embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic or combination of hardware or/and software code capable of performing the functions associated with that element .

The embodiments of the present disclosure can be applied in the semiconductor field, for example, in the semiconductor layout design process.

In the semiconductor field, general chip design uses a sign-off process. That is, after the chip design is completed, it will go through a design rule check (DRC) to check whether the current design violates the design rules.

Ordinary layout design through LVS and general DRC can ensure that the designed circuit diagram and layout are consistent, thereby ensuring that the functions of the semiconductor device can be realized normally. However, in order to improve the performance and yield of semiconductor devices, layout design will have some special requirements. For example, there will be high-voltage nodes in the circuit. These high-voltage nodes will have special rule requirements during layout design. Therefore, there is an urgent need to provide a new Design rule checking method to deal with some special needs in layout design, thereby improving the performance and yield of semiconductor devices.

Faced with the above technical problems, embodiments of the present disclosure provide a design rule checking method, which determines the target position of the target node in the circuit layout corresponding to the circuit schematic diagram according to the position of the target node in the circuit schematic diagram; obtains the target node corresponding layout design rules, and check whether the design parameters of the devices laid out at the target positions in the circuit layout meet the layout design rules. This can respond to some special needs in layout design, ensure the accuracy of layout design, and improve Semiconductor device performance and yield.

Referring to FIG. 1 , FIG. 1 is a schematic flow chart of a design rule checking method provided in an embodiment of the present disclosure. In some embodiments of the present disclosure, the above design rule checking method includes:

S101. Determine the position of the target node in the circuit schematic diagram.

Among them, the above-mentioned circuit schematic diagram can also be called an electronic circuit diagram or circuit diagram. It is a diagram drawn with agreed symbols to represent the circuit structure. It can reflect the electrical connection and working principle of each component in the electronic product. It is usually applied In designing and analyzing circuits. When analyzing a circuit, you can understand the working principle of the circuit by identifying the various circuit component symbols drawn on the circuit schematic diagram and the connections between them.

In some embodiments, the circuit schematic diagram may be composed of component symbols, connections, nodes, etc. The component symbol represents the component in the actual circuit. Its shape is not necessarily similar to the actual component, or even completely different, but it generally indicates the characteristics of the component, and the number of pins is consistent with the actual component. The connection represents the wire in the actual circuit. Although it is a wire in the schematic diagram, in commonly used chips or printed circuit boards, it is often not a wire but a metal wire of various shapes. Nodes represent the mutual connection relationships between several component pins or several wires. All component pins and wires connected to the node, regardless of the number, are conductive.

In a feasible implementation manner, when performing the design rule check, the positions of each target node in the circuit schematic diagram that need to be checked by the design rule are first determined. Optionally, the above circuit schematic diagram may have one target node or multiple target nodes, which is not limited in the embodiments of the present disclosure.

S102. According to the position of the target node in the circuit schematic diagram, determine the target position of the target node in the circuit layout corresponding to the circuit schematic diagram.

Among them, the above-mentioned circuit layout can also be called an integrated circuit layout. Circuit layout design is to map the circuit schematic or circuit description language to the physical description level, so that the designed circuit can be mapped to the wafer for production.

Among them, the circuit layout usually contains relevant physical information such as device type, device size, relative position between devices, and connection relationship between each device of the integrated circuit.

In some embodiments of the present disclosure, after the above circuit schematic diagram is designed, its corresponding circuit layout can be generated based on the circuit schematic diagram.

After determining the position of the target node in the circuit schematic diagram, the target node's target position in the circuit layout corresponding to the circuit schematic diagram is determined based on the position of the target node in the circuit schematic diagram.

S103. Obtain the layout design rules corresponding to the target node, and check whether the design parameters of the devices arranged at the target positions in the circuit layout meet the layout design rules.

In some embodiments of the present disclosure, layout design rules corresponding to each target node can be obtained in advance. The layout design rules can include design parameters such as device size, relative positions between devices, and connection relationships between devices.

After determining the target position of the target node in the circuit layout, it can be checked whether the design parameters of the device arranged at the target position satisfy the layout design rules corresponding to the target node.

For example, when the relative position spacing between devices arranged at the target location is less than the minimum spacing specified in the layout design rules corresponding to the target node, it can be determined that the design parameters of the devices arranged at the target location do not satisfy the layout design rules corresponding to the target node. .

In some embodiments of the present disclosure, when it is checked that the design parameters of the device arranged at the target position do not meet the layout design rules corresponding to the target node, the layout design rules corresponding to the target node can also be modified based on the layout design rules corresponding to the target node. The design parameters of the device enable the design parameters of the device arranged at the target position to meet the layout design rules corresponding to the target node, thereby improving the accuracy of the layout design.

The design rule checking method provided by the embodiment of the present disclosure determines the target position of the target node in the circuit layout corresponding to the circuit schematic diagram according to the position of the target node in the circuit schematic diagram; obtains the layout design rule corresponding to the target node, and checks the circuit Whether the design parameters of the device arranged at the target position in the layout meet the layout design rules can cope with some special needs in the layout design, thereby effectively improving the performance and yield of the semiconductor device.

Based on the content described in the above embodiments, in some embodiments of the present disclosure, corresponding marks can also be added to each node in the circuit schematic diagram in advance. For example, according to the voltage characteristics of each node in the circuit schematic diagram, voltage marks can be added to each node, such as ultra-high voltage marks, high voltage marks, low voltage marks, etc.

In some embodiments of the present disclosure, after adding corresponding marks to each node in the circuit schematic diagram, you can also check whether the marks corresponding to each node satisfy the preset node design rules, that is, check whether the marks added to each node are correct.

In some embodiments of the present disclosure, the above-mentioned node design rules may be codes written according to circuit principles. This code will traverse the marks in the circuit schematic diagram and check the correctness of the position of each mark.

Assume that the following three markers can be added to the circuit schematic:

Mark 1: Indicates ultra-high voltage and is positive voltage; Mark 2: Indicates high voltage and is positive voltage; Mark 3: Indicates low voltage and is negative voltage.

And it is assumed that the node design rules include: a node cannot add two positive voltage marks or two negative voltage marks at the same time; a node can add a positive voltage mark and a negative voltage mark at the same time.

Referring to FIG. 2 , FIG. 2 is a schematic diagram of two circuit schematic diagrams provided in embodiments of the present disclosure.

For example, both the circuit schematic diagram (a) and the circuit schematic diagram (b) shown in FIG. 2 include multiple MOS transistors.

Among them, in the circuit schematic diagram (a), since node Q has both markers 2 and 3 added, it can be determined that the node Q in the circuit schematic diagram (a) does not meet the above node design rules; while the circuit schematic diagram (b) ) has both markers 3 and 1 added to the node Q, then it can be determined that each node in the circuit schematic diagram (b) satisfies the above node design rules.

In some embodiments of the present disclosure, when there is a node whose mark does not meet the node design rules, the mark corresponding to the node is modified according to the node design rules, and the mark corresponding to each node is rechecked to see whether it satisfies the above node design rules until each node Until the corresponding markers meet the above node design rules.

In some embodiments of the present disclosure, when it is determined that the marks added to each node in the circuit schematic diagram meet the node design rules, the location of the target node in the circuit can be determined based on the position of the mark corresponding to the target node in the circuit schematic diagram. location in the schematic.

For example, the position of the high-voltage node in the circuit schematic diagram can be determined based on the position of "Mark 2" in the circuit schematic diagram.

The design rule checking method provided by the embodiment of the present disclosure adds corresponding marks to each node in the circuit schematic diagram, and checks whether the marks corresponding to each node satisfy the preset node design rules. When there is a mark that does not satisfy the node design rules, When a node is selected, the mark corresponding to the node is modified according to the node design rules, thereby ensuring that the marks added to each node meet the node design rules, and the target can be accurately determined based on the position of the mark corresponding to the target node in the circuit schematic diagram. The location of a node in a circuit schematic.

Based on what is described in the above embodiments, in some embodiments of the present disclosure, after generating the corresponding circuit layout based on the above circuit schematic diagram, the LVS tool can also be used to perform a consistency check on the above circuit schematic diagram and circuit layout.

Among them, the LVS (Layout Versus Schematics) tool is a tool used to verify whether the circuit layout and circuit schematic are consistent.

Among them, the error types that LVS can verify can be roughly divided into two categories: inconsistent points and mismatched devices. Among them, the inconsistencies can be divided into node inconsistencies and device inconsistencies. Node inconsistency means that there is a node in the circuit layout and the circuit schematic diagram. The devices connected to the two nodes are similar, but not exactly the same. Device inconsistency means that there is a device in the circuit layout and the circuit schematic. The two devices are the same and the nodes connected are very similar, but not exactly the same. Among them, mismatched devices refer to all devices that are present in the circuit schematic diagram but not in the circuit layout, or are present in the circuit layout but not in the circuit schematic diagram.

In addition, LVS can also verify the substrate type of the device (such as NMOS and PMOS in CMOS circuits) and some device parameters, which are not limited in the embodiments of the present disclosure.

In some embodiments of the present disclosure, when the above-mentioned circuit schematic diagram and circuit layout fail the consistency check of the LVS tool, the above-mentioned circuit layout can be modified according to the circuit schematic diagram, and the LVS tool can be reused to check the circuit schematic diagram and the modified The circuit layout is checked for consistency until the above-mentioned circuit schematic diagram and circuit layout pass the consistency check of the LVS tool.

In some embodiments of the present disclosure, after the above-mentioned circuit schematic diagram and circuit layout pass the consistency check of the LVS tool, the LVS tool can be used to determine the position of the target node in the circuit layout based on the position of the target node in the circuit schematic diagram. target location.

The design rule checking method provided by the embodiment of the present disclosure, after generating the corresponding circuit layout based on the above-mentioned circuit schematic diagram, uses the LVS tool to perform a consistency check on the above-mentioned circuit schematic diagram and circuit layout, which can ensure that the above-mentioned circuit schematic diagram is consistent with the above-mentioned circuit schematic diagram. The consistency of the circuit layout, and then based on the position of the target node in the circuit schematic diagram, the target position of the target node in the circuit layout can be accurately determined.

Based on the content described in the above embodiments, in some embodiments of the present disclosure, it is assumed that the above target node is a high voltage node, and the high voltage node is equipped with a semiconductor device at a target position in the circuit layout.

Wherein, the above-mentioned high-voltage node is a node whose operating voltage is close to the power supply voltage or higher than the power supply voltage.

Before checking the design parameters of the devices arranged at the above target positions, the layout design rules corresponding to the high-voltage nodes can be obtained in advance. The layout design rules can include the device width and device area of the above-mentioned semiconductor devices, as well as the different components of the above-mentioned semiconductor devices. The distance, inclusion relationship, extension relationship, etc. between semiconductor structures are not limited in the embodiments of the present disclosure.

In some embodiments of the present disclosure, the layout design rules corresponding to the high-voltage nodes are more stringent than the layout design rules corresponding to the general nodes.

Illustratively, refer to FIG. 3 , which is a circuit layout of a semiconductor device provided in an embodiment of the present disclosure.

As shown in Figure 3, Figure 3 is a circuit layout of a MOS device. The MOS device includes an N+ doped region, a gate (GATE), a contact structure 1 and a contact structure 2, where the contact structure 1 and the contact structure 2 are to form the source and drain.

Among them, under normal circumstances, the minimum value of d1 that conforms to the layout design rules is 0.024 length units, and the minimum value of d2 that conforms to the layout design rules is 0.027 length units. In the case of high voltage, the minimum values of d1 and d2 that comply with the layout design rules are both 0.04 length units.

Among them, d1 and d2 are the distances between the edge of the contact structure and the edge of the adjacent N+ doped region.

In addition, under normal circumstances, the distance between the gate and the contact structure 1 and the contact structure 2 is the same, but under high voltage conditions, the distance between the gate and the contact structure 1 needs to be greater than the distance from the contact structure 2.

In some embodiments of the present disclosure, after obtaining the layout design rules corresponding to the high-voltage node, it is checked whether the design parameters of the semiconductor devices arranged at the above-mentioned target positions in the circuit layout satisfy the layout design rules corresponding to the high-voltage node; if not, then according to the above The layout design rules corresponding to the high-voltage nodes modify the design parameters of the above-mentioned semiconductor devices in the circuit layout; if satisfied, the above-mentioned circuit layout can be output.

The design rule checking method provided by the embodiment of the present disclosure can better cope with the design of high-voltage nodes in layout design by using the layout design rules corresponding to high-voltage nodes to check the design parameters of devices arranged at target positions in the circuit layout. demand, thereby improving the performance and yield of semiconductor devices.

Based on the contents described in the above embodiments, refer to FIG. 4 , which is a schematic step flow diagram of another design rule checking method provided in an embodiment of the present disclosure. In some embodiments of the present disclosure, the above design rule checking method includes:

S401. Add corresponding marks to each node in the circuit schematic diagram.

For example, according to the voltage characteristics of each node in the circuit schematic diagram, a voltage mark can be added to each node, such as an ultra-high voltage mark, a high voltage mark, a low voltage mark, etc.

Among them, the above-mentioned nodes represent the mutual connection relationships between several component pins or several wires. All component pins and wires connected to the node, regardless of the number, are conductive.

S402. Check whether the position of each mark is correct.

In some embodiments of the present disclosure, after adding corresponding marks to each node in the circuit schematic diagram, preset node design rules are obtained, and based on the node design rules, it is checked whether the marks corresponding to each node are correct.

When there is a node with an incorrect mark, modify the mark corresponding to the node according to the node design rules, and recheck whether the mark corresponding to each node is correct, until the mark corresponding to each node satisfies the above node design rules, continue to execute S403.

In some embodiments of the present disclosure, the above-mentioned node design rule may be a check code written according to the circuit principle. The check code will traverse the marks in the circuit schematic diagram and check the correctness of the position of each mark.

For example, the above node design rules may include: a node cannot add two positive voltage marks or two negative voltage marks at the same time; a node can add a positive voltage mark and a negative voltage mark at the same time, etc.

S403. Determine whether the LVS check reports an error.

In some embodiments of the present disclosure, the LVS tool can be used to check the consistency of the above-mentioned circuit schematic diagram and circuit layout. When the above-mentioned circuit schematic diagram and circuit layout fail the consistency check of the LVS tool, the above-mentioned circuit layout can be modified according to the circuit schematic diagram, and the LVS tool can be reused to check the consistency of the circuit schematic diagram and the modified circuit layout until When the above circuit schematic diagram and circuit layout pass the consistency check of the LVS tool, continue to execute S404.

S404. Determine the position of the target node in the circuit schematic diagram.

In some embodiments of the present disclosure, the position of the target node in the circuit schematic diagram can be determined based on the position of the mark corresponding to the target node in the circuit schematic diagram.

Optionally, the above circuit schematic diagram may have one target node or multiple target nodes, which is not limited in the embodiments of the present disclosure.

S405. Determine the target position of the target node in the circuit layout according to the position of the target node in the circuit schematic diagram.

In some embodiments of the present disclosure, the LVS tool can be used to determine the target position of the target node in the circuit layout based on the position of the target node in the circuit schematic diagram.

In some embodiments of the present disclosure, the position of the mark corresponding to the target node in the circuit schematic diagram can be first determined, and then the LVS tool is used to determine the target position corresponding to the position in the circuit layout.

S406. Check whether the design parameters of the device arranged at the target position are correct.

In some embodiments of the present disclosure, the layout design rules corresponding to the target node can be obtained, and it is checked whether the design parameters of the devices arranged at the target position in the circuit layout meet the above layout design rules; if the design parameters of the devices arranged at the target position are satisfied If the above layout design rules are met, the above circuit layout will be output; if the design parameters of the devices laid out at the above target positions do not meet the above layout design rules, then the design parameters of the devices laid out at the above target positions in the circuit layout will be modified according to the above layout design rules. Finally, recheck whether the design parameters of the device placed at the target location are correct.

In some embodiments of the present disclosure, the target node may be a high-voltage node, and the high-voltage node is a node with an operating voltage close to or higher than the power supply voltage.

Optionally, the layout design rules may include the device width and device area of the above-mentioned semiconductor device, as well as the distance, inclusion relationship and extension relationship between different semiconductor structures in the above-mentioned semiconductor device, etc., which are not limited in the embodiments of the present disclosure.

In some embodiments of the present disclosure, the layout design rules corresponding to the high-voltage nodes are more stringent than the layout design rules corresponding to the nodes.

It is understandable that after adding corresponding marks to each node in the circuit schematic diagram, the marks will not be reflected in the circuit layout, so ordinary DRC checks cannot guarantee the correctness of the layout.

In the embodiment of the present disclosure, node design rules can be used to ensure that the positions of all marks added in the circuit schematic diagram are correct. When designing the layout, the layout design engineer will design according to the corresponding marks and different layout design rules. Circuit layout. After the circuit layout is designed, use LVS to find the corresponding position in the circuit layout based on the position of the mark added in the circuit schematic diagram, and check whether the layout design at that position complies with the layout design rules.

The design rule checking method provided by the embodiment of the present disclosure can accurately determine the location of the target node in the circuit schematic diagram based on the position of the mark corresponding to the target node in the circuit schematic diagram by adding marks to each node in the circuit schematic diagram. at the same time, use the LVS tool to check the consistency of the above-mentioned circuit schematic diagram and circuit layout, which can ensure the consistency between the above-mentioned circuit schematic diagram and the above-mentioned circuit layout, and then according to the position of the target node in the circuit schematic diagram, you can Accurately determine the target position of the target node in the circuit layout; use the layout design rules corresponding to the target node to check the design parameters of the devices placed at the target position in the circuit layout, which can better deal with the special nodes in the layout design. design requirements, thereby improving the performance and yield of semiconductor devices.

Based on the contents described in the above embodiments, embodiments of the present disclosure also provide a design rule checking device. Referring to Figure 5, Figure 5 is a schematic diagram of a program module of a design rule checking device provided in an embodiment of the present disclosure. The design rule checking device includes:

The determination module 501 is used to determine the position of the target node in the circuit schematic diagram. The nodes in the circuit schematic diagram are the connection points between the devices in the circuit schematic diagram.

The positioning module 502 is configured to determine the target position of the target node in the circuit layout corresponding to the circuit schematic diagram according to the position of the target node in the circuit schematic diagram.

The first checking module 503 is used to obtain the layout design rules corresponding to the target node, and check whether the design parameters of the devices arranged at the target position in the circuit layout satisfy the layout design rules.

In some embodiments of the present disclosure, the above design rule checking device further includes a marking module and a second checking module.

The marking module is used to:

Add corresponding labels to each node in the circuit schematic diagram.

The second inspection module is used for:

Check whether the mark corresponding to each node satisfies the preset node design rule; when there is a first node whose mark does not meet the node design rule, modify the mark corresponding to the first node according to the node design rule, And recheck whether the tags corresponding to each node satisfy the node design rules, until the tags corresponding to each node satisfy the node design rules.

In some embodiments of the present disclosure, the determining module 501 is specifically used to:

The position of the target node in the circuit schematic diagram is determined according to the position of the mark corresponding to the target node in the circuit schematic diagram.

In some embodiments of the present disclosure, the above-mentioned design rule checking device further includes a third checking module, used for:

Use the LVS tool to check the consistency of the circuit schematic diagram and the circuit layout;

When the circuit schematic diagram and the circuit layout fail the consistency check, modify the circuit layout according to the circuit schematic diagram, and reuse the LVS tool to check the circuit schematic diagram and the circuit Check the layout for consistency;

When the circuit schematic diagram and the circuit layout pass the consistency check, continue to perform the step of determining the position of the target node in the circuit schematic diagram according to the position of the target node in the circuit schematic diagram. target location in the circuit layout.

In some embodiments of the present disclosure, the positioning module 502 is used to:

The LVS tool is used to determine the target position of the target node in the circuit layout according to the position of the target node in the circuit schematic diagram.

In some embodiments of the present disclosure, the target node is a high-voltage node, and the high-voltage node is equipped with a semiconductor device at a target position in the circuit layout;

The first inspection module 503 is also specifically used for:

Obtain the layout design rules corresponding to the high-voltage node. The layout design rules corresponding to the high-voltage node include the value range of at least one of the following design parameters of the semiconductor device: device width, device area, and the The distance, inclusion relationship and extension relationship between different semiconductor structures in semiconductor devices.

In some embodiments of the present disclosure, the first inspection module 503 is specifically used to:

Check whether the design parameters of the semiconductor device in the circuit layout meet the layout design rules corresponding to the high-voltage node;

When the design parameters of the semiconductor device in the circuit layout do not meet the layout design rules corresponding to the high-voltage node, modify the design parameters of the semiconductor device in the circuit layout according to the layout design rules corresponding to the high-voltage node;

When the design parameters of the semiconductor device in the circuit layout satisfy the layout design rules corresponding to the high-voltage node, the circuit layout is output.

The design rule checking device provided by the embodiment of the present disclosure determines the target position of the target node in the circuit layout corresponding to the circuit schematic diagram according to the position of the target node in the circuit schematic diagram; obtains the layout design rule corresponding to the target node, and checks the circuit Whether the design parameters of the device arranged at the target position in the layout meet the layout design rules can cope with some special needs in the layout design, thereby effectively improving the performance and yield of the semiconductor device.

It should be noted that, for the specific execution content of the determination module 501, the positioning module 502 and the first inspection module 503 in the embodiment of the present disclosure, please refer to the relevant content in the embodiment shown in Figures 1 to 4, and will not be described again here.

Further, based on the content described in the above embodiments, embodiments of the present disclosure also provide an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor The computer execution instructions stored in the memory are executed to implement each step in the design rule checking method as described in the above embodiment, which will not be described again in this embodiment.

In order to better understand the embodiment of the present disclosure, refer to FIG. 6 , which is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present disclosure.

As shown in Figure 6, the electronic device 60 of this embodiment includes: a processor 601 and a memory 602; wherein:

Memory 602, used to store computer execution instructions;

The processor 601 is configured to execute computer execution instructions stored in the memory to implement various steps in the design rule checking method described in the above embodiments. For details, please refer to the relevant descriptions in the foregoing method embodiments.

Optionally, the memory 602 can be independent or integrated with the processor 601 .

When the memory 602 is provided independently, the device also includes a bus 603 for connecting the memory 602 and the processor 601 .

Further, based on the content described in the above embodiments, embodiments of the present disclosure also provide a computer-readable storage medium, which stores computer-executable instructions. When the processor executes the computer-executed instructions, Instructions are issued to implement each step in the design rule checking method as described in the above embodiment, which will not be described again in this embodiment.

Further, based on the content described in the above embodiments, embodiments of the present disclosure also provide a computer program product, including a computer program. When the computer program is executed by a processor, the design rules as described in the above embodiments are implemented. Each step in the inspection method will not be described again in this embodiment.

In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods, for example, multiple modules may be combined or integrated. to another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or modules, and may be in electrical, mechanical or other forms.

The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in various embodiments of the present disclosure can be integrated into a processing unit, or each module can exist physically alone, or two or more modules can be integrated into one unit. The units integrated by the above modules can be implemented in the form of hardware or in the form of hardware plus software functional units.

The above integrated modules implemented in the form of software function modules can be stored in a computer-readable storage medium. The above-mentioned software function modules are stored in a storage medium and include a number of instructions to cause a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to execute the various embodiments of the present disclosure. Some steps of the method.

It should be understood that the above-mentioned processor may be a central processing unit (English: Central Processing Unit, referred to as: CPU), or other general-purpose processor, digital signal processor (English: Digital Signal Processor, referred to as: DSP), or an application-specific integrated circuit (English: Application Specific Integrated Circuit, abbreviation: ASIC), etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the method disclosed in conjunction with the present disclosure can be directly embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

The memory may include high-speed RAM memory, and may also include non-volatile storage NVM, such as at least one disk memory, which may also be a USB flash drive, a mobile hard disk, a read-only memory, a magnetic disk, or an optical disk.

The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, the bus in the drawings of this disclosure is not limited to only one bus or one type of bus.

The above storage medium can be implemented by any type of volatile or non-volatile storage device or their combination, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable Except programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. Storage media can be any available media that can be accessed by a general purpose or special purpose computer.

An exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in Application Specific Integrated Circuits (ASICs for short). Of course, the processor and the storage medium can also exist as discrete components in the electronic device or the main control device.

Persons of ordinary skill in the art can understand that all or part of the steps to implement the above method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps including the above-mentioned method embodiments are executed; and the aforementioned storage media include: ROM, RAM, magnetic disks, optical disks and other media that can store program codes.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present disclosure, but not to limit it; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present disclosure. scope.

Claims

A design rule checking method, the method includes:

Determine the position of the target node in the circuit schematic diagram, where the nodes in the circuit schematic diagram are the connection points between the devices in the circuit schematic diagram;

Determine the target position of the target node in the circuit layout corresponding to the circuit schematic diagram according to the position of the target node in the circuit schematic diagram;

Obtain the layout design rule corresponding to the target node, and check whether the design parameters of the device arranged at the target position in the circuit layout satisfy the layout design rule.
The method according to claim 1, wherein before determining the position of the target node in the circuit schematic diagram, it further includes:

Add corresponding marks to each node in the circuit schematic diagram;

Check whether the tags corresponding to each node meet the preset node design rules;

When there is a first node whose mark does not satisfy the node design rule, modify the mark corresponding to the first node according to the node design rule, and recheck whether the mark corresponding to each node satisfies the node design rule. , until the marks corresponding to each node satisfy the node design rules.
The method according to claim 2, wherein determining the position of the target node in the circuit schematic diagram includes:

The position of the target node in the circuit schematic diagram is determined according to the position of the mark corresponding to the target node in the circuit schematic diagram.
The method according to claim 2, wherein before determining the target position of the target node in the circuit layout corresponding to the circuit schematic diagram according to the position of the target node in the circuit schematic diagram, include:

Use the LVS tool to check the consistency of the circuit schematic diagram and the circuit layout;

When the circuit schematic diagram and the circuit layout fail the consistency check, modify the circuit layout according to the circuit schematic diagram, and reuse the LVS tool to check the circuit schematic diagram and the circuit Check the layout for consistency;

When the circuit schematic diagram and the circuit layout pass the consistency check, continue to perform the step of determining the position of the target node in the circuit schematic diagram according to the position of the target node in the circuit schematic diagram. target location in the circuit layout.
The method according to claim 4, wherein determining the target position of the target node in the circuit layout corresponding to the circuit schematic diagram according to the position of the target node in the circuit schematic diagram includes:

The LVS tool is used to determine the target position of the target node in the circuit layout according to the position of the target node in the circuit schematic diagram.
The method according to any one of claims 1 to 5, wherein the target node is a high-voltage node, and the high-voltage node is equipped with a semiconductor device at a target position in the circuit layout;

The obtaining the layout design rules corresponding to the target node includes:

Obtain the layout design rules corresponding to the high-voltage node. The layout design rules corresponding to the high-voltage node include the value range of at least one of the following design parameters of the semiconductor device: device width, device area, and the The distance, inclusion relationship and extension relationship between different semiconductor structures in semiconductor devices.
The method according to claim 6, wherein the checking whether the design parameters of the devices arranged at the target position in the circuit layout satisfy the layout design rules includes:

Check whether the design parameters of the semiconductor device in the circuit layout meet the layout design rules corresponding to the high-voltage node;

When the design parameters of the semiconductor device in the circuit layout do not meet the layout design rules corresponding to the high-voltage node, modify the design parameters of the semiconductor device in the circuit layout according to the layout design rules corresponding to the high-voltage node;

When the design parameters of the semiconductor device in the circuit layout satisfy the layout design rules corresponding to the high-voltage node, the circuit layout is output.
A design rule checking device, the device includes:

A determination module, used to determine the position of the target node in the circuit schematic diagram, where the nodes in the circuit schematic diagram are the connection points between the devices in the circuit schematic diagram;

A positioning module, configured to determine the target position of the target node in the circuit layout corresponding to the circuit schematic diagram according to the position of the target node in the circuit schematic diagram;

The first checking module is used to obtain the layout design rules corresponding to the target node, and check whether the design parameters of the devices arranged at the target position in the circuit layout satisfy the layout design rules.
The device according to claim 8, further comprising a marking module and a second inspection module; the marking module is used for:

Add corresponding marks to each node in the circuit schematic diagram;

The second inspection module is used for:

Check whether the tags corresponding to each node meet the preset node design rules;

When there is a first node whose mark does not satisfy the node design rule, modify the mark corresponding to the first node according to the node design rule, and recheck whether the mark corresponding to each node satisfies the node design rule. , until the marks corresponding to each node satisfy the node design rules.
The device according to claim 9, wherein the determining module is specifically configured to:

The position of the target node in the circuit schematic diagram is determined according to the position of the mark corresponding to the target node in the circuit schematic diagram.
The device according to claim 9, further comprising a third inspection module for:

Use the LVS tool to check the consistency of the circuit schematic diagram and the circuit layout;

When the circuit schematic diagram and the circuit layout fail the consistency check, modify the circuit layout according to the circuit schematic diagram, and reuse the LVS tool to check the circuit schematic diagram and the circuit Check the layout for consistency;

When the circuit schematic diagram and the circuit layout pass the consistency check, continue to perform the step of determining the position of the target node in the circuit schematic diagram according to the position of the target node in the circuit schematic diagram. target location in the circuit layout.
The device according to claim 11, wherein the positioning module is used for:

The LVS tool is used to determine the target position of the target node in the circuit layout according to the position of the target node in the circuit schematic diagram.
The device according to any one of claims 8 to 12, wherein the target node is a high-voltage node, and the high-voltage node is equipped with a semiconductor device at a target position in the circuit layout;

The first inspection module is also specifically used for:

Obtain the layout design rules corresponding to the high-voltage node. The layout design rules corresponding to the high-voltage node include the value range of at least one of the following design parameters of the semiconductor device: device width, device area, and the The distance, inclusion relationship and extension relationship between different semiconductor structures in semiconductor devices.
The device according to claim 13, wherein the first inspection module is specifically used for:

Check whether the design parameters of the semiconductor device in the circuit layout meet the layout design rules corresponding to the high-voltage node;

When the design parameters of the semiconductor device in the circuit layout do not meet the layout design rules corresponding to the high-voltage node, modify the design parameters of the semiconductor device in the circuit layout according to the layout design rules corresponding to the high-voltage node;

When the design parameters of the semiconductor device in the circuit layout satisfy the layout design rules corresponding to the high-voltage node, the circuit layout is output.
An electronic device including: at least one processor and memory;

The memory stores computer execution instructions;

The at least one processor executes the computer execution instructions stored in the memory, so that the at least one processor executes the design rule checking method according to any one of claims 1 to 7.
A computer-readable storage medium in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the design rule checking method as described in any one of claims 1 to 7 is implemented. .
A computer program product includes a computer program that, when executed by a processor, implements the design rule checking method described in any one of claims 1 to 7.