WO2023202366A1

WO2023202366A1 - Graphics processing unit and system, electronic apparatus and device, and graphics processing method

Info

Publication number: WO2023202366A1
Application number: PCT/CN2023/085937
Authority: WO
Inventors: 唐志敏; 王海洋; 姜莹
Original assignee: 象帝先计算技术(重庆)有限公司
Priority date: 2022-04-20
Filing date: 2023-04-03
Publication date: 2023-10-26
Also published as: CN116957900A

Abstract

The present invention provides a graphics processing unit, system and method and an electronic apparatus and device. The graphics processing unit comprises a tile division module, configured to: perform tile division processing on primitives in an image frame according to a basic tile size and a VRS pixel group size, the size of the divided tiles being a product of the basic tile size and the VRS pixel group size; a depth test module, configured to: perform a depth test tile by tile, and for each tile, perform a depth test in multiple sub-tiles, the size of each sub-tile being the basic tile size; and a fragment shader module, configured to: perform fragment calculation tile by tile, wherein the fragment shader module is called after the depth test of each sub-tile in each tile is completed.

Description

Graphics processor, system, electronic device, equipment and graphics processing method

Cross-references to related applications

This application is filed based on a Chinese patent application with application number 202210414535.8 and a filing date of April 20, 2022, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated by reference into this application.

Technical field

This application relates to the technical field of GPU (Graphics Processing Unit, graphics processor), and in particular to a graphics processor, a graphics processing system, an electronic device, an electronic device and a graphics processing method.

Background technique

With the adoption of a tile-based GPU architecture, memory bandwidth requirements during rendering can be reduced. For tile-based GPU architectures, rasterization and pixel processing of the rendering process are performed at tile granularity. During rasterization and pixel processing, on-chip buffers (On-Chip Buffers) are used to store pixel depth buffer information, geometry buffer information and other information in a tile. Among them, the storage space on the on-chip buffer that saves the depth buffer information is called the depth buffer (Depth Buffer), and the storage space on the on-chip buffer that saves the geometry buffer information is called the geometry buffer (G Buffer). The size of the depth buffer determines the number of samples or pixels that can be used for depth testing on the chip, and the size of the geometry buffer determines the number of samples or pixels that can be used for fragment calculation on the chip. . The size of the depth buffer and the size of the geometry buffer together determine the size of the tiles that can be divided. For example, if the tile size is 16×16 pixels, then both the depth buffer and the geometry buffer need to provide on-chip processing capabilities for 16×16 pixels.

In traditional tile-based GPU architectures, the choice of tile size is limited by both the depth buffer and the geometry buffer. When VRS (Variable Rate Shading) is enabled, the granularity of fragment calculations is reduced, which means that the geometry buffer requirements become smaller. Larger sized tiles can be divided if the size of the geometry buffer matches the tile size. But depth testing limits tile division to larger sizes. For example, both the depth buffer and the geometry buffer support on-chip processing capabilities of 16×16 pixels. After VRS is enabled, the geometry buffer supports dividing tiles larger than 16×16 pixels, but the depth buffer limits the number of tiles. The maximum size is 16×16 pixels. It can be seen that after enabling VRS, the traditional tile-based GPU architecture limits the choice of tile size.

Contents of the invention

The purpose of this disclosure is to provide a graphics processor, a graphics processing system, a graphics processing method, an electronic device and an electronic device so that when VRS is enabled, tiles can be divided according to the size of the geometry buffer.

According to one aspect of the present disclosure, a graphics processor is provided. The graphics processor adopts a tile-based rendering architecture, and the graphics processor at least includes:

The tile division module is configured to: perform tile division processing on the primitives in the image frame according to the basic tile size and the VRS pixel group size. The divided tile size is larger than the basic tile size, but not larger than the basic tile size. The product of the VRS pixel group size;

The depth test module is configured to: perform depth testing one by one, and perform depth testing on multiple sub-tiles for each tile, and the size of each sub-tile is limited to the size of the depth buffer;

The fragment shader module is configured to perform fragment calculations tile by tile, where the fragment shader module is called after the depth test of each sub-tile within each tile is completed.

Optionally, the divided tile size is the product of the basic tile size and the VRS pixel group size.

Optionally, the subtile size is the base tile size.

Based on any of the above graphics processor embodiments, the depth testing module may be configured to: divide each tile into multiple sub-tiles. Alternatively, the tile dividing module is further configured to divide each tile into multiple sub-tiles.

If the depth testing module divides sub-tiles, further, the depth testing module can be configured to: mark the sub-tile division results in the block division results of each tile.

If the block division module divides sub-blocks, further, the block division module is further configured to: save the block division results of each block separately, and mark the sub-blocks in the block division results of each block. Block division results.

Based on any of the above graphics processor embodiments, the fragment shader module may be configured to perform a fragment calculation on pixels in the same VRS pixel group.

On this basis, optionally, only one fragment calculation result is saved for the same VRS pixel group in the geometry buffer corresponding to the fragment shader.

According to another aspect of the present disclosure, a graphics processing system is also provided. The graphics processing system includes the graphics processor described in any of the above embodiments.

According to another aspect of the present disclosure, an electronic device is also provided. The electronic device includes the graphics processing system described in any of the above embodiments. In some usage scenarios, the product form of the electronic device is a graphics card; in other usage scenarios, the product form of the electronic device is a CPU motherboard.

According to another aspect of the present disclosure, an electronic device is also provided, which includes the above-mentioned electronic device. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smartphone, tablet computer, VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, game console, etc.

According to another aspect of the present disclosure, a graphics processing method is also provided. The graphics processing method adopts a tile-based rendering architecture. The graphics processing method at least includes the following operations:

The graphics elements in the image frame are divided into blocks according to the basic block size and the VRS pixel group size. The divided block size is larger than the basic block size, but not larger than the basic block size and the VRS pixel group size. the product of;

Depth testing is performed tile by tile, and for each tile, depth testing is performed in multiple sub-tiles. The size of each sub-tile is limited to the size of the depth buffer;

Fragment calculations are done on a tile-by-tile basis, where the fragment shader module is called after depth testing of individual sub-tiles within each tile.

Optionally, the subtile size is the base tile size.

Based on any of the above embodiments of the graphics processing method, each tile may also be divided into multiple sub-tiles before being divided into multiple sub-tiles for depth testing.

Further, the sub-tile division results can be marked in the tile division results of each tile.

Based on any of the above graphics processing method embodiments, a fragment calculation is performed on pixels in the same VRS pixel group.

Description of the drawings

The drawings described here are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the attached picture:

Figure 1 is a schematic diagram of block division according to an embodiment of the present disclosure;

Figure 2 is a schematic structural diagram of a graphics processing system according to an embodiment of the present disclosure;

Figure 3 is a schematic flowchart of a graphics processing method according to an embodiment of the present disclosure.

Detailed ways

Before introducing the embodiments of the present disclosure, it should be noted that:

Some embodiments of the present disclosure are described as processing flows. Although various operation steps of the flow may be labeled with sequential step numbers, the operation steps therein may be implemented in parallel, concurrently, or simultaneously.

In embodiments of the present disclosure, the terms “first”, “second”, etc. may be used to describe various features, but these features should not be limited by these terms. These terms are used solely to distinguish one characteristic from another.

The term "and/or" may be used in embodiments of the present disclosure, and "and/or" includes any and all combinations of one or more of the associated listed features.

It should be understood that when describing the connection relationship or communication relationship between two components, unless a direct connection or direct communication between the two components is clearly stated, otherwise, the connection or communication between the two components may be understood as a direct connection or communication, or a direct connection or communication between the two components. It can be understood as indirect connection or communication through intermediate components.

In order to make the technical solutions and advantages in the embodiments of the present disclosure more clear, the exemplary embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure. This is not an exhaustive list of all embodiments. It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

After the VRS function is enabled, in the depth test phase, the depth test is performed at the granularity of pixels or samples, but in the fragment calculation phase, the fragment calculation is performed at the granularity of the VRS pixel group (pixel group), that is, one pixel group performs one fragment calculation. Therefore, with the VRS function enabled, the geometry buffer can support greater processing power than without the VRS function. For example, when the VRS function is not enabled, the size of the geometry buffer is 16×16, and the supported tile size is 16×16; when the VRS function is enabled, and the VRS pixel group is set to 1×2 Below, the geometry buffer can support a tile size of 16×32. In view of this, the present disclosure provides a graphics processor that adopts a tile-based rendering architecture, and the graphics processor can adjust the tile size. Specifically, when VRS is enabled, the tile size can be adjusted according to the size of the geometry buffer, thereby effectively utilizing the geometry buffer. Not only that, by increasing the tile size, the data interaction with memory caused by tile switching during the fragment calculation phase can be reduced. In addition, due to the use of larger tiles, it is possible to reduce the situation where primitives cover multiple tiles, which is more conducive to reducing the situation of tile switching and reuse of primitive information. After increasing the tile size, the tile size may exceed the size of the depth buffer. Therefore, the graphics processor provided by the present disclosure performs a depth test on each tile according to the granularity of sub-tiles in the depth testing stage to match the depth buffer. area size. Here, the depth test is performed according to the granularity of the sub-tiles, which means that the tile is divided into multiple sub-tiles. The depth test for the tile is converted into reading the data of one sub-tile at a time, and is performed for one sub-tile. Depth testing until all sub-tiles of the tile are depth-tested.

Among them, GPU refers to a processor with computing functions implemented through hardware, which includes computing units, caches and other components. So GPGPU (general-purpose graphics processing unit, general-purpose graphics processor) can also be a GPU.

The graphics processor provided by the embodiment of the present disclosure is suitable for any tile-based rendering architecture, such as TBR (Tile Based Render, tile-based rendering), TBDR (Tile Based Deferred Rendering, tile-based deferred rendering), etc.

One embodiment of the present disclosure provides a graphics processor that adopts a tile-based rendering architecture, which at least includes a tile partitioning module, a depth testing module, and a fragment shader module.

In the present disclosure, the block division module is configured to perform block division processing on the primitives in the image frame according to the basic block size and the VRS pixel group size. The divided block size is larger than the basic block size, but not larger than the basic block size. The product of the tile size and the VRS pixel group size.

In the embodiment of the present disclosure, the basic tile size refers to the tile size used for tile division when the VRS function is not enabled. The base tile size is determined based on the size of the on-chip buffers such as the size of the geometry buffer and the size of the depth buffer.

In the embodiment of the present disclosure, as shown in Figure 1, assuming that the basic block size is 4×4, two horizontally adjacent pixels are set to form a pixel group (that is, the VRS pixel group size is 1×2, and the ellipse in Figure 1 is actually (shown in wireframe), then the product of the basic tile size and the VRS pixel group size is 4*1*4*2=4*8. In the embodiment shown in FIG. 1 , the divided tile size is the product of the basic tile size and the VRS pixel group size. Therefore, the size of a tile is shown using a rectangular solid line frame in FIG. 1 .

According to the requirements of Direct3D12, the pixel group sizes supported by VRS include: 1×2, 2×1, 2×2, 2×4, 4×2 and 4×4. For different VRS pixel group sizes, the rules for tile size adjustment by the tile division module are shown in Table 1. In Table 1, a×b represents the set basic tile size.

Table 1 tile size allocation

In this disclosure, the depth testing module is configured to perform depth testing tile by tile, and perform depth testing in multiple subtiles (subtiles) for each tile, and the size of each subtile is no larger than the size of the depth buffer.

In some embodiments, the sub-tile size is the base tile size. Still taking the block division method shown in Figure 1 as an example, the dotted rectangular box in Figure 1 shows the sub-block size.

Specifically, the depth test is performed on the pixels within the tile. The embodiment of the present disclosure does not limit which pixels are depth tested. In some embodiments, the depth test is performed on all pixels covered by the primitive. In other embodiments, the depth test is performed on the visible pixels of the screen covered by the primitive. This disclosure does not limit the granularity of depth testing. Depth testing can be performed based on pixel granularity, or depth testing can be performed based on sample granularity.

The depth testing module performs depth testing on pixels in each tile according to a predetermined processing sequence. Among them, the depth test for the pixels of each tile is performed at the sub-tile granularity. In this disclosure, each tile is divided into multiple sub-tiles according to the same sub-tile division rules. tiles. Taking the i-th tile as an example, the data in one sub-tile is read each time for depth testing. After completing the depth test of one sub-tile, the data in the next sub-tile is read in a predetermined order. Depth testing is performed until all sub-tiles in the i-th tile complete the depth test. After all sub-tiles in the i-th tile complete the depth test, the fragment shader module can be called to perform fragment calculations for the i-th tile. In the embodiment of the present disclosure, the fragment shader module can be called by the depth testing module or by other hardware modules in the graphics processor.

Among them, the fragment shader module is configured to perform fragment calculations block by block, wherein the fragment shader module is called after the depth test of each sub-block within each block is completed.

In the embodiment of the present disclosure, when VRS is enabled, the block size divided by the block dividing module can not only be the product of the basic block size and the VRS pixel group size, but can also be other choices under the above constraints. The present disclosure There is no limit to this.

In the embodiment of the present disclosure, the sub-tile size can be not only the basic block size, but also other choices under the above constraints, which is not limited by the present disclosure.

In the embodiment of the present disclosure, the function of dividing sub-tiles can be implemented by the depth testing module, or can be implemented by the tile dividing module. Of course, it can also be implemented by other modules, and the present disclosure does not limit this.

If the sub-tiles are divided by the depth testing module, then the depth testing module may be configured to: divide each tile into multiple sub-tiles.

Dividing each tile into multiple sub-tiles specifically refers to determining the primitives covering each sub-tile among the primitives covering the tile. The specific implementation method can refer to the implementation method of tile division, and will not be described again here.

The division result of sub-tiles can be saved in a separate data structure, and its data structure can refer to the data structure of the division result of the tile. However, the data structure of the tile division result may be different in the following ways: the association between the sub-tile and the tile is marked in the sub-tile division result. This disclosure does not limit the specific marking method of association relationships. For example, the division result of each sub-block includes a sub-block identification, and the sub-block identification uses at least one identification bit to mark the block to which the sub-block belongs. As another example, the end of the tile is marked in the division result of the last sub-tile of each tile. Of course, the above-mentioned correlation relationship does not need to be marked in the data structure of the sub-tile division results. Then, the depth testing module can confirm the end of the depth test of a tile by comparing the tile division results with the sub-tile division results, or The end of the depth test of a tile is confirmed based on the number of reads, which is not limited by this disclosure.

The division results of sub-tiles can also be saved in the tile division results. That is, the sub-tile division results are marked in the tile division results of each tile. This disclosure does not limit the marking method of the sub-tile division results. The tile division result of each tile includes a tile identifier and a primitive index of the covering tile. As an example but not a limitation, identification information corresponding to the primitive index of each tile may be added, and the identification information includes the tile index used by the tile. The subtile marker for the meta overridden subtile.

If the tile dividing module divides the sub-tiles, then the tile dividing module is further configured to: divide each tile into multiple sub-tiles. For its specific implementation, reference may be made to the description of the above embodiments, which will not be described again here.

As mentioned above, the division results of sub-tiles can be stored in a separate data structure or in the division results of tiles. For specific implementation methods, reference can be made to the description of the above embodiments and will not be described again here.

If the sub-tiles are divided by the tile division module, the tile division and the sub-tile division can be completed in the same process. As an example but not a limitation: the tile division module determines the primitives covering each sub-tile. This process actually realizes the division of sub-tiles and tiles.

In the above embodiment of any sub-block division, if the size of the block is the product of the basic block size and the VRS pixel group size, as By way of example but not limitation, the blocking rule is to divide sub-blocks using the basic block size as the granularity. If the size of the tile is smaller than the product of the basic tile size and the VRS pixel group size, as an example but not a limitation, the blocking rule is to divide the tile into N sub-tiles.

An embodiment of the present disclosure also provides a graphics processing system, which includes the graphics processor described in any of the above embodiments.

In this disclosed embodiment, the product form of the graphics processing system may be a SOC (System on Chip) chip.

The graphics processor system in the embodiment of the present disclosure may be a single-die (wafer) SOC chip or a multi-die interconnected SOC chip.

The following uses a die as an example to explain the architecture and working principle of the graphics processing system provided by the present disclosure.

In one embodiment shown in FIG. 2 , a single-die graphics processing system includes a GPU core, which is the above-mentioned graphics processor.

The GPU core is used to process drawing instructions. According to the drawing instructions, it executes the pipeline of image rendering and can also be used to execute other computing instructions. The GPU core further includes: a computing unit, which is used to execute compiled instructions of the shader. It is a programmable module and consists of a large number of ALUs; a cache (Cache), which is used to cache GPU core data to reduce access to memory; Rasterization module, a fixed stage of the 3D rendering pipeline; Tilling module, which divides a frame into tiles in the TBR and TBDR GPU architecture; Cropping module, a fixed stage of the 3D rendering pipeline, crops out Graph elements that are outside the observation range or are not displayed on the back; the post-processing module is used to perform operations such as scaling, cropping, rotating, etc. on the finished drawing; the Micro core is used between various pipeline hardware modules on the GPU core Scheduling, or task scheduling for multiple GPU cores.

The GPU cores are connected to the on-chip network. Among them, the on-chip network is used for data exchange between masters and slaves on the graphics processing system. In this embodiment, the on-chip network includes a configuration bus, a data communication network, a communication bus, and so on.

As shown in Figure 2, the graphics processing system can also include:

Universal DMA (Direct Memory Access) is used to perform data movement between the host and the graphics processing system memory (such as graphics card memory). For example, DMA is used to move the vertex data of 3D drawings from the host. to graphics processing system memory;

PCIe controller, an interface used to communicate with the host, implements the PCIe protocol, so that the graphics processing system is connected to the host through the PCIe interface, and the graphics API and graphics card driver and other programs are run on the host;

The application processor is used to schedule the tasks of each module on the graphics processing system. For example, after the GPU has finished rendering a frame, it notifies the application processor, and the application processor then starts the display controller to display the picture drawn by the GPU on the screen;

Memory controller, used to connect memory devices and save data on the SOC;

The display controller controls the output of the frame buffer in the memory to the display through the display interface (HDMI, DP, etc.);

Video decoding can decode the encoded video on the host hard disk into a displayable picture;

Video encoding can encode the original video stream on the host hard disk into a specified format and return it to the host.

Based on the graphics processing system architecture shown in Figure 2, in one embodiment, the graphics rendering process is as follows:

The graphics API of the host computer (in actual applications, for mobile graphics processing systems, it can also be used by software on the application processor) sends drawing instructions to the SOC chip, requiring the rendering of image frames.

Wherein, the image frame includes at least one object.

General DMA transfers the vertex coordinate information of each object in the image frame from the host to the memory of the graphics processing system.

After obtaining the above drawing instruction, the computing unit of the GPU core decodes the drawing instruction.

The vertex shader of the GPU core (its function is implemented by the computing unit) obtains the vertex coordinate information of each object in the image frame from the system memory, and transmits the vertex coordinate information of the object to the geometry shader (its function is implemented by the computing unit), The geometry shader converts the 3D coordinates of the object's vertices into unwrapped texture coordinates (i.e. (u,v) coordinates). In addition, the computing unit also assembles primitives based on the vertex coordinate information of the object to determine the vertex coordinates of each primitive. Among them, the value at the texture coordinate corresponding to the vertex coordinate in the texture map is the vertex color information.

The vertex coordinate information and vertex texture coordinates of the primitive are saved to the primitive's data structure in system memory.

After the geometry processing is completed, the block division module in the GPU core identifies whether VRS is enabled. If VRS is not enabled, the primitives in the image frame are divided into blocks according to the basic block size. If VRS is enabled, the primitives in the image frame are divided into blocks according to the extended size. Tile size performs tile division processing on the primitives in the image frame. Among them, the extended tile size is the product of the basic tile size and the VRS pixel group size. The tile division module saves the tile division result to the tile buffer, and the tile division result of each tile includes the tile identification and the primitive index of the primitive covering the tile.

After the tile division is completed, the rasterization module performs rasterization processing. The rasterization module processes tiles one by one, reading the primitive index of the primitive covering the current tile from the tile buffer each time; the rasterization module reads the primitive information of the primitive through the primitive index, and uses the primitive index to The primitive information of the primitive is subjected to a pixel coverage test to determine the pixels covered by the primitive, and then the texture coordinates corresponding to the pixels covered by the primitive are determined through interpolation calculation, and then at least one pixel test is performed to determine the visibility of the pixel (As an example and not a limitation, pixel testing may include depth testing, template testing, etc.).

Among them, before the rasterization module performs the depth test, each tile is divided into multiple sub-tiles according to the basic tile size, and the sub-tile division result is marked in the tile division result of each tile. Then, the rasterization module divides the results into sub-tiles and loads the data of one sub-tile from the memory into the depth buffer at a time for depth testing.

As an example and not a limitation, the rasterization module identifies the tile currently to be processed from the tile buffer according to the tile identifier, and searches for the corresponding sub-tile from the primitive index corresponding to the current tile in the tile buffer. Graph element index; and then search the graph element information of the graph element according to the found graph element index. The graph element information includes the depth information of the graph element, and load the depth information of the graph element corresponding to the current sub-tile.

After the depth test is completed on one sub-tile, the data of another sub-tile is loaded. After the depth test of all sub-tiles in a tile is completed, the fragment shader is called to perform shading calculations on the frame (i.e. fragment calculation).

In this disclosed embodiment, the depth information of all pixels in a sub-tile is stored in the depth buffer, which can be read and updated repeatedly during the depth test until the depth test of all pixels in a sub-tile is completed.

The fragment shader of the GPU core (which is implemented by the computing unit) performs shading calculations (such as lighting calculations) on the pixels within the tile.

Among them, the fragment shader is called once for the pixels in a pixel group according to the shading rate set by VRS. The results of fragment shading calculations are saved in a geometry buffer.

The geometry buffer does not copy the fragment shading result to each pixel in the pixel group, but only stores the result of one fragment shading for a pixel group. The fragment shader can also read data from the geometry buffer and perform calculations until all pixels in a tile are rendered.

An embodiment of the present disclosure also provides an electronic device, which includes the graphics processing system described in any of the above embodiments. In some usage scenarios, the product form of the electronic device is a graphics card; in other usage scenarios, the product form of the electronic device is a graphics card. For the CPU motherboard.

An embodiment of the present disclosure also provides an electronic device, which includes the above-mentioned electronic device. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smartphone, tablet, VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, game console, workstation, server wait.

Based on the same inventive concept, embodiments of the present disclosure also provide a graphics processing method using a tile-based rendering architecture, as shown in Figure 3. The method at least includes the following steps:

Step 301: Perform tile division processing on the picture elements in the image frame according to the basic tile size and the VRS pixel group size. The divided tile size is larger than the basic tile size, but not larger than the basic tile size and the VRS pixel group size. The product of the pixel group dimensions;

Step 302: Perform depth testing one by one, and perform depth testing on multiple sub-tiles for each tile. The size of each sub-tile is limited to the size of the depth buffer;

Step 303: Perform fragment calculations tile by tile. After the depth test of each sub-tile in each tile is completed, the fragment shader module is called.

Optionally, the subtile size is the base tile size.

Further, the sub-tile division results are marked in the tile division results of each tile.

Although the preferred embodiments of the present disclosure have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once the basic inventive concepts are apparent. Therefore, it is intended that the appended claims be construed to include the preferred embodiments and all changes and modifications that fall within the scope of this disclosure.

Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

A graphics processor using a tile-based rendering architecture, the graphics processor including:

A block dividing module is configured to: perform block dividing processing on the picture elements in the image frame according to the basic block size and the VRS pixel group size, and the divided block size is the basic block size and the VRS pixel group size. product of dimensions;

The depth testing module is configured to: perform depth testing one by one, and perform depth testing on each tile in multiple sub-tiles, the size of each sub-tile being the basic tile size;

The fragment shader module is configured to perform fragment calculations block by block, wherein the fragment shader module is called after the depth test of each sub-block within each block is completed.
The graphics processor of claim 1, the depth testing module is configured to divide each tile into a plurality of sub-tiles.
The graphics processor according to claim 2, the depth testing module is further configured to: mark the sub-tile division result in the tile division result of each tile.
According to the graphics processor of claim 1, the tile dividing module is further configured to divide each tile into a plurality of sub-tiles.
The graphics processor according to claim 4, the tile division module is further configured to: respectively save the tile division results of each tile, and mark sub-tiles in the tile division results of each tile. Divide the results.
According to the graphics processor according to any one of claims 1 to 5, the fragment shader module is configured to perform a fragment calculation on pixels in the same VRS pixel group.
According to the graphics processor of claim 6, the geometry buffer corresponding to the fragment shader only stores one fragment calculation result for the same VRS pixel group.
A graphics processing system, including the graphics processing system according to any one of claims 1 to 7.
An electronic device comprising the system of claim 8.
An electronic device including the electronic device according to claim 9.
A graphics processing method using a tile-based rendering architecture, the graphics processing method includes:

Perform block division processing on the primitives in the image frame according to the basic block size and the VRS pixel group size, and the divided block size is the product of the basic block size and the VRS pixel group size;

Conduct depth testing one by one, and perform depth testing on multiple sub-tiles for each tile, and the size of each sub-tile is the basic tile size;

Fragment calculations are performed tile by tile, where the fragment shader module is called after the depth test of each sub-tile within each tile is completed.
The method according to claim 11, before dividing into multiple sub-tiles for depth testing, the method further includes:

Divide each tile into sub-tiles.
The method of claim 12, further comprising:

Mark sub-tile partitioning results in the tile partitioning results for each tile.
According to the method of any one of claims 11 to 13, a fragment calculation is performed on pixels in the same VRS pixel group.
According to the method of claim 14, only one fragment calculation result is stored for the same VRS pixel group in the geometry buffer corresponding to the fragment calculation.