WO2023201842A1 - 高带宽信号处理系统、设备、方法和存储介质 - Google Patents
高带宽信号处理系统、设备、方法和存储介质 Download PDFInfo
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Definitions
- the present invention relates to the field of signal processing technology, and in particular, to a high-bandwidth signal processing system, equipment, method and storage medium.
- the present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a high-bandwidth signal processing system, equipment, method and storage medium, which can improve the speed and accuracy of signal processing.
- a high-bandwidth signal processing system includes: a camera used to capture images and generate corresponding two-dimensional image information; and an image blocking module used to block the two-dimensional image information. , forming multi-channel serial data; a motion sensor, used to obtain the position information and motion status information of the high-bandwidth signal processing system; an image processing accelerator, used to obtain the image block module and the motion sensor sent The data is processed in a parallel multi-stage pipeline to realize the identification and positioning of target objects; a multi-core task processor is used to allocate and schedule tasks for the data processing process of the image processing accelerator, and Obtain the data processing result of the image processing accelerator; a storage module is used to provide a data caching function for the image processing accelerator and provide a training set for the image processing accelerator.
- a communication interface is further included, and the communication interface is electrically connected to the multi-core task processor.
- the image processing accelerator includes: a data interface used to restore the multi-channel serial data into the two-dimensional image information; an image segmentation module used to process the two-dimensional image The information is image segmented to obtain image blocks containing the target object; a target data processing module is used to perform first preprocessing on the image blocks to obtain first image data; an image resolution truncation module is used to The two-dimensional image information is subjected to resolution truncation to obtain image information containing only background data; a background data processing module is used to perform a second preprocessing on the image information to obtain second image data; an image encoding and compression module , used to encode and compress the first image data and the second image data to obtain third image data; a visual processing module, used to perform processing according to the third image data in a parallel multi-stage pipeline. Perform data processing to realize the identification and positioning of target objects; a feedback module is used to send the data processing results of the visual processing module as feedback information to the image segmentation module and the image resolution
- the image processing accelerator and the storage module are directly connected on a PCB.
- the image processing accelerator and the multi-core task processor have a heterogeneous structure.
- an electronic device includes the high-bandwidth signal processing system as described above.
- a signal processing method includes: acquiring two-dimensional image information containing a target object; acquiring position information and motion state information of a high-bandwidth signal processing system; and according to the two-dimensional image information, the The position information and the motion status information are processed in a parallel multi-stage pipeline to realize the identification and positioning of the target object.
- the following steps are also included: dividing the two-dimensional image information into blocks to form multi-channel serial data; Serial-to-parallel conversion to restore the two-dimensional image information.
- data processing is performed in a parallel multi-stage pipeline based on the two-dimensional image information, the position information and the motion state information to realize the identification and positioning of the target object. , including the following steps: performing image segmentation on the two-dimensional image information to obtain image blocks containing the target object; performing first preprocessing on the image blocks to obtain first image data; performing image segmentation on the two-dimensional image information.
- the image information is subjected to resolution truncation to obtain image information containing only background data; a second preprocessing is performed on the image information to obtain second image data; the first image data and the second image data are subjected to Encoding and compression to obtain the third image data; performing data processing on the third image data, the position information and the motion state information in a parallel multi-stage pipeline to realize the recognition of the target object and positioning.
- the storage medium stores a program, and when the program is executed by a processor, the signal processing method as described above is implemented.
- the high-bandwidth signal processing system, equipment, method and storage medium according to the embodiments of the present invention have at least the following beneficial effects: through the cooperation of the camera and the motion sensor, the signal processing results can be appropriately processed from different dimensions in the signal processing. Calibration to improve detection accuracy; through the cooperation of the image processing accelerator and the multi-core task processor, data processing can be completed in the form of a parallel multi-stage pipeline, which improves the speed of signal processing and enables accurate identification of target objects. and positioning.
- Figure 1 is a schematic structural diagram of a high-bandwidth signal processing system according to an embodiment of the present invention
- Figure 2 is a schematic structural diagram of an image processing accelerator according to an embodiment of the present invention.
- FIG. 3 is a schematic diagram of the working principle of the image segmentation module according to the embodiment of the present invention.
- Figure 4 is a schematic diagram of the pipeline processing structure of the image processing accelerator according to an embodiment of the present invention.
- Figure 5 is a step flow chart of the signal processing method according to the embodiment of the present invention.
- Camera 100 image blocking module 200, motion sensor 300, image processing accelerator 400, data interface 410, image segmentation module 420, target data processing module 430, image resolution truncation module 440, background data processing module 450, image encoding and compression module 460.
- a high-bandwidth signal processing system includes a camera 100, an image blocking module 200, a motion sensor 300, an image processing accelerator 400, a multi-core task processor 500 and a storage module 600;
- the image blocking module 200 is electrically connected to the camera 100
- the image processing accelerator 400 is electrically connected to the image blocking module 200 and the motion sensor 300 respectively
- the multi-core task processor 500 and the storage module 600 are electrically connected to the image processing accelerator 400 respectively.
- the camera 100 is used to capture images and generate corresponding two-dimensional image information; the image blocking module 200 is used to block the two-dimensional image information to form multi-channel serial data and send it to the image processing accelerator 400;
- the motion sensor 300 is used to obtain the position information and motion status information of the high-bandwidth signal processing system and send it to the image processing accelerator 400; the multi-core task processor 500 performs task allocation and scheduling on the image processing accelerator 400, so that the image processing accelerator 400 operates in parallel.
- Data processing is performed in a multi-stage pipeline to realize the identification, tracking and positioning of target objects, and the data processing results are sent to the multi-core task processor 500; the storage module 600 is used to provide a data caching function for the image processing accelerator 400, and The image processing accelerator 400 is provided with a training set.
- the camera 100 adopts a high-precision, high-resolution high-speed camera with a resolution of 1080p or above; after the camera 100 captures the image, it uses a two-dimensional image information storage format and a high-speed serial method.
- the data is output to the image tiling module 200.
- the image blocking module 200 blocks the two-dimensional image information sent by the camera 100 and sends the serial data to the image processing accelerator 400 in a multi-channel parallel transmission mode, thereby reducing the amount of one-time data transmission in a single channel.
- the image processing accelerator 400 is based on the parallel processing capabilities of the FPGA (Field Programmable Gate Array) architecture and is adapted to the multi-core task processor 500 so that the data is processed in the form of a parallel multi-core multi-stage pipeline. Processing is performed in the image processing accelerator 400 to complete the identification, tracking and positioning of the target object.
- the multi-core task processor 500 may adopt an ARM architecture to schedule and allocate pipeline tasks of the image processing accelerator 400, thereby realizing high-speed data transmission and processing and avoiding data congestion.
- the storage module 600 includes multiple high-bandwidth memories and has the functions of data caching and PINGPONG data interaction; at the same time, the storage module 600 is also used to provide a basic image training set for the image processing accelerator 400 for training. Form an accurate operational parameter model.
- the signal processing results can be appropriately calibrated from different dimensions in the signal processing to improve the detection accuracy; through image processing
- the cooperation of the accelerator 400 and the multi-core task processor 500 can complete data processing in the form of a parallel multi-stage pipeline, improve the speed of signal processing, and achieve accurate identification and positioning of target objects.
- the high-bandwidth signal processing system further includes a communication interface 700 , and the communication interface 700 is electrically connected to the multi-core task processor 500 .
- the communication interface 700 is a wireless communication interface, used to complete the frame packaging function of data and transmit data content. After the multi-core task processor 500 obtains the real-time processing results of the data, the results can be sent to the server or client through the communication interface 700 .
- the image processing accelerator 400 includes a data interface 410, an image segmentation module 420, a target data processing module 430, an image resolution truncation module 440, a background data processing module 450, and an image encoding and compression module 460. , visual processing module 470 and feedback module 480.
- the data interface 410 is used to restore multi-channel serial data into two-dimensional image information; the image segmentation module 420 is used to perform image segmentation on the two-dimensional image information to obtain image blocks containing the target object; the target data processing module 430 is used to Perform first preprocessing on the image block to obtain first image data; the image resolution truncation module 440 is used to perform resolution truncation on the two-dimensional image information to obtain image information containing only background data; the background data processing module 450 uses The image encoding and compression module 460 is used for performing a second preprocessing on the image information to obtain the second image data; the image encoding and compression module 460 is used for encoding and compressing the first image data and the second image data to obtain the third image data; the visual processing module 470 is used for According to the third image data, data processing is performed in a parallel multi-stage pipeline to realize the identification and positioning of the target object; the feedback module 480 is used to send the data processing results of the visual processing module 470 as feedback information to the image
- the data interface 410 restores the multi-channel serial data sent from the image blocking module 200 into the original two-dimensional image information, and sends it to the image segmentation module 420 and image resolution truncation respectively.
- Module 440 restores the multi-channel serial data sent from the image blocking module 200 into the original two-dimensional image information, and sends it to the image segmentation module 420 and image resolution truncation respectively.
- the image segmentation module 420 converts the actual position of the target object into the corresponding block address in the two-dimensional image information, and segments the image, retaining only the image block 800 containing the target object.
- Image segmentation module 420 performs segmentation at high resolution. As shown in FIG. 3 , the image block 800 containing the target object only occupies a small part of the real-shot image acquired by the camera 100 . Therefore, this part of the image needs to be segmented by the image segmentation module 420 to reduce the amount of data for image processing.
- the image segmentation module 420 sends the image block 800 to the target data processing module 430 for first preprocessing.
- the first preprocessing includes but is not limited to filtering, scaling, translation, rotation and other linear corresponding operations on the image; the image segmentation module 420
- the first image data obtained after the first preprocessing is sent to the image encoding and compression module 460 .
- the image resolution truncation module 440 After obtaining the two-dimensional image information, the image resolution truncation module 440 only retains the image information containing background data (that is, excluding the target object), and performs resolution truncation on the image information, using only 8 bits of the original RGB image as the background
- the image information is input to the background data processing module 450 as a low-resolution image, thereby reducing the amount of data that actually needs to be transmitted by reducing the resolution.
- the background data processing module 450 performs a second preprocessing on the image information.
- the second preprocessing includes but is not limited to filtering, scaling, translation, rotation and other linear corresponding operations on the image, and uses the second preprocessing obtained after the second preprocessing.
- the image data is sent to image encoding and compression module 460.
- the image encoding and compression module 460 uses an image compression algorithm to compress the image data from a bit stream into a format such as JPEG in a parallel manner, thereby reducing the amount of data calculation and compressing the compressed data.
- the image is input to the visual processing module 470 to complete image processing.
- the visual processing module 470 processes data in a parallel multi-stage pipeline manner under the control of the multi-core task processor 500.
- the input data is a compressed JPEG image, and after completing the training locally, a suitable operation parameter model is obtained.
- the output information includes the position information of the target object, the spatial position information of the current system, motion status information, etc.
- Figure 4 shows the pipeline processing structure of the visual processing module 470. Taking three processing tasks as an example, the advantages of multi-core are used to complete the tasks that need to be cached in the pipeline tasks; in the pipeline processing, through the CPU in the multi-core task processor 500 Carry out storage scheduling to meet the caching requirements in pipeline tasks and ensure that data processing does not get stuck.
- the data processing results of the visual processing module 470 are also used as feedback information and are input to the image segmentation module 420 and the image resolution truncation module 430 through the feedback module 480.
- the position of the target is completed and used as a parameter. Provided to the image segmentation module 420 and the image resolution truncation module 430 to improve the accuracy of the operation.
- the multi-core task processor 500 and the image processing accelerator 400 have a heterogeneous structure, which can reduce hardware interconnections between chips and effectively reduce the difficulty of design development.
- the image processing accelerator 400 and the storage module 600 are directly connected on a PCB, thereby providing a high-speed connection method at the system PCB level and effectively increasing the computing speed.
- the camera 100 serves as an image sensor to generate a high-resolution data stream, and the data stream generated by the motion sensor 300 is input into the image processing accelerator 400 as a frame signal.
- the image data is transmitted to the image encoding and compression module 460 after image segmentation preprocessing and image resolution and truncation preprocessing to complete data compression, and then passes through the visual processing module 470 with a pipeline structure to complete data calculation and processing.
- a heterogeneous system using FPGA+AMR is used to reduce the interconnection structure, and a multi-core scheduling task mechanism is used to complete pipeline tasks in segments and tasks, thereby improving the computing speed.
- the present invention also provides an electronic device, which includes the above-mentioned high-bandwidth signal processing system.
- the electronic device may be a flight recorder or other common electronic devices.
- the present invention also proposes a signal processing method that is adapted to the above-mentioned high-bandwidth signal processing system and includes the following steps:
- Step S100 Obtain two-dimensional image information containing the target object.
- a high-precision, high-resolution high-speed camera can be used to capture images to generate corresponding two-dimensional image information.
- the camera 100 has a resolution of 1080p or above; after the camera 100 captures the image, the two-dimensional image information is stored. Format and high-speed serial mode, the data is output to the image blocking module 200.
- the image blocking module 200 blocks the two-dimensional image information sent by the camera 100, and sends the serial data to the image processing accelerator 400 in a multi-channel parallel transmission mode.
- the image processing accelerator 400 uses the data interface 410 to convert the multi-channel Serial data is restored to the original two-dimensional image information.
- Step S200 Obtain position information and motion status information of the high-bandwidth signal processing system.
- the motion sensor 300 is used to obtain the position information and motion status information of the high-bandwidth signal processing system, and sends it to the image processing accelerator 400 .
- Step S300 Perform data processing in a parallel multi-stage pipeline based on the two-dimensional image information, position information and motion status information to realize the identification and positioning of the target object.
- the image processing accelerator 400 After acquiring the two-dimensional image information sent by the image blocking module 200 and the position information and motion status information sent by the motion sensor 300, the image processing accelerator 400, with the assistance of the multi-core task processor 500 and the storage module 600, Data processing is carried out in a multi-core and multi-stage pipeline to complete the identification and positioning of target objects.
- the specific data processing process of the image processing accelerator 400 includes the following steps:
- Step S401 Perform image segmentation on the two-dimensional image information to obtain image blocks containing the target object;
- Step S402 Perform first preprocessing on the image block to obtain first image data
- Step S403 Perform resolution truncation on the two-dimensional image information to obtain image information containing only background data;
- Step S404 Perform second preprocessing on the image information to obtain second image data
- Step S405 Encode and compress the first image data and the second image data to obtain third image data
- Step S406 Perform data processing on the third image data, position information and motion state information in a parallel multi-stage pipeline to achieve identification and positioning of the target object.
- the data interface 410 restores the multi-channel serial data sent from the image blocking module 200 into the original two-dimensional image information, and sends it to the image segmentation module 420 and image resolution truncation respectively.
- Module 440 restores the multi-channel serial data sent from the image blocking module 200 into the original two-dimensional image information, and sends it to the image segmentation module 420 and image resolution truncation respectively.
- the image segmentation module 420 converts the actual position of the target object into the corresponding block address in the two-dimensional image information, and segments the image, retaining only the image block 800 containing the target object.
- the image segmentation module 420 performs segmentation with high resolution, and the segmentation size is generally more than 8 times. As shown in FIG. 3 , the image block 800 containing the target object only occupies a small part of the real-shot image acquired by the camera 100 . Therefore, this part of the image needs to be segmented by the image segmentation module 420 to reduce the amount of data for image processing.
- the image segmentation module 420 sends the image block 800 to the target data processing module 430 for first preprocessing.
- the first preprocessing includes but is not limited to filtering, scaling, translation, rotation and other linear corresponding operations on the image; the image segmentation module 420
- the first image data obtained after the first preprocessing is sent to the image encoding and compression module 460 .
- the image resolution truncation module 440 After obtaining the two-dimensional image information, the image resolution truncation module 440 only retains the image information containing background data (that is, excluding the target object), and performs resolution truncation on the image information, using only 8 bits of the original RGB image as the background
- the image information is input to the background data processing module 450 as a low-resolution image, thereby reducing the amount of data that actually needs to be transmitted by reducing the resolution.
- the background data processing module 450 performs a second preprocessing on the image information.
- the second preprocessing includes but is not limited to filtering, scaling, translation, rotation and other linear corresponding operations on the image, and uses the second preprocessing obtained after the second preprocessing.
- the image data is sent to image encoding and compression module 460.
- the image encoding and compression module 460 uses an image compression algorithm to compress the image data from a bit stream into a format such as JPEG in a parallel manner, thereby reducing the amount of data calculation and compressing the compressed data.
- the image is input to the visual processing module 470 to complete image processing.
- the visual processing module 470 processes data in a parallel multi-stage pipeline manner under the control of the multi-core task processor 500.
- the input data is a compressed JPEG image, and after completing the training locally, a suitable operation parameter model is obtained.
- the output information includes the position information of the target object, the spatial position information of the current system, motion status information, etc.
- Figure 4 shows the pipeline processing structure of the visual processing module 470. Taking three processing tasks as an example, the advantages of multi-core are used to complete the tasks that need to be cached in the pipeline tasks; in the pipeline processing, through the CPU in the multi-core task processor 500 Carry out storage scheduling to meet the caching requirements in pipeline tasks and ensure that data processing does not get stuck.
- the data processing results of the visual processing module 470 are also used as feedback information and are input to the image segmentation module 420 and the image resolution truncation module 430 through the feedback module 480.
- the position of the target is completed and used as a parameter. Provided to the image segmentation module 420 and the image resolution truncation module 430 to improve the accuracy of the operation.
- the signal processing results can be appropriately calibrated from different dimensions in the signal processing to improve the detection accuracy;
- the image processing accelerator 400 Cooperating with the multi-core task processor 500, data processing can be completed in the form of a parallel multi-stage pipeline, improving the speed of signal processing, and enabling accurate identification and positioning of target objects.
- the present invention also provides a computer-readable storage medium, which stores a program.
- the program is executed by a processor, the above-mentioned signal processing method is implemented.
- blocks in the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions, and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware computer systems that perform the specified functions, elements or steps, or combinations of special purpose hardware and computer instructions.
- Program modules, applications, and the like described herein may include one or more software components, including, for example, software objects, methods, data structures, and the like. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) be executed.
- Software components can be coded in any of a variety of programming languages.
- One exemplary programming language may be a low-level programming language, such as assembly language associated with a particular hardware architecture and/or operating system platform.
- Software components that include assembly language instructions may need to be converted to executable machine code by an assembler before being executed by the hardware architecture and/or platform.
- Another exemplary programming language may be a higher level programming language that is portable across multiple architectures.
- Software components including higher-level programming languages may need to be converted to an intermediate representation by an interpreter or compiler before execution.
- Other examples of programming languages include, but are not limited to, macro languages, shell or command languages, job control languages, scripting languages, database query or search languages, or report writing languages.
- a software component containing instructions from one of the above programming language examples can be executed directly by an operating system or other software component without first being converted to another form.
- Software components may be stored as files or other data storage structures. Software components of similar types or related functionality may be stored together, such as in specific directories, folders or libraries. Software components may be static (eg, preset or fixed) or dynamic (eg, created or modified at execution time).
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Abstract
一种高带宽信号处理系统、设备、方法和存储介质，涉及信号处理领域。高带宽信号处理系统包括摄像头（100）、图像分块模块（200）、运动传感器（300）、图像处理加速器（400）、多核任务处理器（500）和存储模块（600）；摄像头（100）用于拍摄图像，并产生相应的二维图像信息；图像分块模块（200）用于对二维图像信息进行分块，形成多通道的串行数据；运动传感器（300）用于获取高带宽信号处理系统的位置信息和运动状态信息；多核任务处理器（500）对图像处理加速器（400）进行任务分配和调度，使得图像处理加速器（400）以并行的多级流水线的方式进行数据处理，以实现对目标物体的识别追踪和定位。能够提升对信号处理的速度和准确性。
Description
本发明涉及信号处理技术领域，尤其是涉及一种高带宽信号处理系统、设备、方法和存储介质。
随着飞行记录仪的快速发展，高分辨率摄像的需求也逐渐增大，因此对图像处理的能力也提出了新的需求。高分辨率摄像头在实时检测中传输的数据量非常大，因此需要设计能与高分辨率摄像头相适配、实现实时数据处理的高带宽信号处理系统，既保证信号处理的准确性，又尽可能地提高处理速度。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一。为此，本发明提出了一种高带宽信号处理系统、设备、方法和存储介质，能够提升对信号处理的速度和准确性。
一方面，根据本发明实施例的高带宽信号处理系统，包括：摄像头，用于拍摄图像，并产生相应的二维图像信息；图像分块模块，用于对所述二维图像信息进行分块，形成多通道的串行数据；运动传感器，用于获取所述高带宽信号处理系统的位置信息和运动状态信息；图像处理加速器，用于获取所述图像分块模块和所述运动传感器所发送的数据，并以并行的多级流水线的方式进行数据处理，以实现对目标物体的识别和定位；多核任务处理器，用于对所述图像处理加速器的数据处理过程进行任务分配和调度，以及获取所述图像处理加速器的数据处理结果；存储模块，用于为所述图像处理加速器提供数据缓存功能，以及为所述图像处理加速器提供训练集。
根据本发明的一些实施例，还包括通信接口，所述通信接口与所述多核任务处理器电连接。
根据本发明的一些实施例，所述图像处理加速器包括：数据接口，用于将所述多通道的串行数据还原成所述二维图像信息；图像分割模块，用于对所述二维图像信息进行图像分割，以获取包含所述目标物体的图像块；目标数据处理模块，用于对所述图像块进行第一预处理， 以获得第一图像数据；图像分辨率截断模块，用于对所述二维图像信息进行分辨率截断，以获取仅包含背景数据的图像信息；背景数据处理模块，用于对所述图像信息进行第二预处理，以获得第二图像数据；图像编码压缩模块，用于对所述第一图像数据和所述第二图像数据进行编码压缩，以获得第三图像数据；视觉处理模块，用于根据所述第三图像数据，以并行的多级流水线的方式进行数据处理，以实现对目标物体的识别和定位；反馈模块，用于将所述视觉处理模块的数据处理结果作为反馈信息，发送至所述图像分割模块和所述图像分辨率截断模块。
根据本发明的一些实施例，所述图像处理加速器与所述存储模块在一块PCB上直连。
根据本发明的一些实施例，所述图像处理加速器和所述多核任务处理器为异构体结构。
另一方面，根据本发明实施例的电子设备，包括如上所述的高带宽信号处理系统。
另一方面，根据本发明实施例的信号处理方法，包括：获取包含目标物体的二维图像信息；获取高带宽信号处理系统的位置信息和运动状态信息；根据所述二维图像信息、所述位置信息和所述运动状态信息，以并行的多级流水线的方式进行数据处理，以实现对所述目标物体的识别和定位。
根据本发明的一些实施例，所述获取二维图像信息的步骤之后，还包括以下步骤：对所述二维图像信息进行分块，形成多通道的串行数据；对所述串行数据进行串并转换，以还原所述二维图像信息。
根据本发明的一些实施例，所述根据所述二维图像信息、所述位置信息和所述运动状态信息，以并行的多级流水线的方式进行数据处理，以实现对目标物体的识别和定位，包括以下步骤：对所述二维图像信息进行图像分割，以获取包含所述目标物体的图像块；对所述图像块进行第一预处理，以获得第一图像数据；对所述二维图像信息进行分辨率截断，以获取仅包含背景数据的图像信息；对所述图像信息进行第二预处理，以获得第二图像数据；对所述第一图像数据和所述第二图像数据进行编码压缩，以获得第三图像数据；以并行的多级流水线的方式，对所述第三图像数据、所述位置信息和所述运动状态信息进行数据处理，以实现对所述目标物体的识别和定位。
另一方面，根据本发明实施例的计算机可读存储介质，所述存储介质存储有程序，所述程序被处理器执行时实现如上所述的信号处理方法。
根据本发明实施例的高带宽信号处理系统、设备、方法和存储介质，至少具有以下有益效果：通过摄像头和运动传感器的配合，在信号处理中能够从不同维度上对信号处理的结果进行适当的校准，以提高检测准确度；通过图像处理加速器与多核任务处理器的相互配合，能够以并行的多级流水线的形式完成数据处理，提高了信号处理的速度，并能够实现对目标物体的准确识别和定位。
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1为本发明实施例的高带宽信号处理系统的结构示意图；
图2为本发明实施例的图像处理加速器的结构示意图；
图3为本发明实施例的图像分割模块的工作原理示意图；
图4为本发明实施例的图像处理加速器的流水线处理结构的示意图；
图5为本发明实施例的信号处理方法的步骤流程图；
附图标记：
摄像头100、图像分块模块200、运动传感器300、图像处理加速器400、数据接口410、图像分割模块420、目标数据处理模块430、图像分辨率截断模块440、背景数据处理模块450、图像编码压缩模块460、视觉处理模块470、反馈模块480、多核任务处理器500、存储模块600、通信接口700、图像块800。
本部分将详细描述本发明的具体实施例，本发明之较佳实施例在附图中示出，附图的作用在于用图形补充说明书文字部分的描述，使人能够直观地、形象地理解本发明的每个技术特征和整体技术方案，但其不能理解为对本发明保护范围的限制。
在本发明的描述中，若干的含义是一个或者多个，多个的含义是两个以上，大于、小于、超过等理解为不包括本数，以上、以下、以内等理解为包括本数。如果有描述到第一、第二只是用于区分技术特征为目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的 技术特征的数量或者隐含指明所指示的技术特征的先后关系。
本发明的描述中，除非另有明确的限定，设置、安装、连接等词语应做广义理解，所属技术领域技术人员可以结合技术方案的具体内容合理确定上述词语在本发明中的具体含义。
一方面，如图1所示，根据本发明实施例的高带宽信号处理系统，包括摄像头100、图像分块模块200、运动传感器300、图像处理加速器400、多核任务处理器500和存储模块600；图像分块模块200与摄像头100电连接，图像处理加速器400分别与图像分块模块200和运动传感器300电连接，多核任务处理器500和存储模块600分别与图像处理加速器400电连接。其中，摄像头100用于拍摄图像，并产生相应的二维图像信息；图像分块模块200用于对二维图像信息进行分块，形成多通道的串行数据，并发送至图像处理加速器400；运动传感器300用于获取高带宽信号处理系统的位置信息和运动状态信息，并发送至图像处理加速器400；多核任务处理器500对图像处理加速器400进行任务分配和调度，使得图像处理加速器400以并行的多级流水线的方式进行数据处理，以实现对目标物体的识别追踪和定位，并将数据处理结果发送至多核任务处理器500；存储模块600用于为图像处理加速器400提供数据缓存功能，以及为图像处理加速器400提供训练集。
具体的，在一些实施例中，摄像头100采用高精度、高分辨率的高速摄像头，具备1080p以上的分辨率；摄像头100拍摄图像后，以二维图像信息的存储格式和高速串行的方式，将数据输出至图像分块模块200。图像分块模块200对摄像头100发送的二维图像信息进行分块，并以多通道并行的传输模式发送串行数据至图像处理加速器400，从而降低单通道一次性的数据传输量。图像处理加速器400以FPGA(Field Programmable Gate Array，现场可编程门阵列)架构的并行处理运算能力为基础，与多核任务处理器500相适配，使得数据以并行的多核多级流水线的形式，在图像处理加速器400内进行处理，从而完成对目标物体的识别追踪和定位。多核任务处理器500可以采用ARM架构，用于对图像处理加速器400的流水线任务进行调度和分配，从而实现数据的高速传输和处理，避免发生数据堵塞的情况。存储模块600包括多片高带宽的存储器，具备数据缓存和PINGPONG数据交互的功能；同时，存储模块600还用于为图像处理加速器400提供基础的图像训练集，供图像处理加速器400进行训练，以形成准确的运算参数模型。
根据本发明实施例的高带宽信号处理系统，通过摄像头100和运动传感器300的配合， 在信号处理中能够从不同维度上对信号处理的结果进行适当的校准，以提高检测准确度；通过图像处理加速器400与多核任务处理器500的相互配合，能够以并行的多级流水线的形式完成数据处理，提高了信号处理的速度，并能够实现对目标物体的准确识别和定位。
如图1所示，在一些实施例中，高带宽信号处理系统还包括通信接口700，通信接口700与多核任务处理器500电连接。其中，通信接口700为无线通信接口，用于完成数据的帧打包功能和传输数据内容。在多核任务处理器500得到数据的实时处理结果后，可以通过通信接口700发送结果至服务器或者客户端。
如图2所示，在一些实施例中，图像处理加速器400包括数据接口410、图像分割模块420、目标数据处理模块430、图像分辨率截断模块440、背景数据处理模块450、图像编码压缩模块460、视觉处理模块470和反馈模块480。数据接口410用于将多通道的串行数据还原成二维图像信息；图像分割模块420用于对二维图像信息进行图像分割，以获取包含目标物体的图像块；目标数据处理模块430用于对图像块进行第一预处理，以获得第一图像数据；图像分辨率截断模块440用于对二维图像信息进行分辨率截断，以获取仅包含背景数据的图像信息；背景数据处理模块450用于对图像信息进行第二预处理，以获得第二图像数据；图像编码压缩模块460用于对第一图像数据和第二图像数据进行编码压缩，以获得第三图像数据；视觉处理模块470用于根据第三图像数据，以并行的多级流水线的方式进行数据处理，以实现对目标物体的识别和定位；反馈模块480用于将视觉处理模块470的数据处理结果作为反馈信息，发送至图像分割模块420和图像分辨率截断模块440。
具体的，数据接口410基于串并转换结构，将图像分块模块200发送过来的多通道的串行数据，还原成原始的二维图像信息，并分别发送至图像分割模块420和图像分辨率截断模块440。
图像分割模块420根据目标物体的实际位置，将其转换成二维图像信息中对应的块地址，并对图像进行分割，只保留包含目标物体的图像块800。图像分割模块420以高分辨率进行分割。如图3所示，包含目标物体的图像块800仅占据摄像头100获取的实拍图像的一小部分，因此需要通过图像分割模块420将这部分图像分割出来，降低图像处理的数据量。随后，图像分割模块420将图像块800发送至目标数据处理模块430进行第一预处理，第一预处理包括但不限于对图像进行滤波、缩放、平移、旋转等线性相应操作；图像分割模块420将经 过第一预处理后所获得的第一图像数据发送至图像编码压缩模块460。
图像分辨率截断模块440在获得二维图像信息后，仅保留包含背景数据(即不包括目标物体)的图像信息，并对该图像信息进行分辨率截断，将原始的RGB图像只取8bit作为背景图像信息，从而以低分辨率的图像输入至背景数据处理模块450，通过降低分辨率的方式来降低实际所需传输的数据量。背景数据处理模块450对图像信息进行第二预处理，第二预处理包括但不限于对图像进行滤波、缩放、平移、旋转等线性相应操作，并将经过第二预处理后所获得的第二图像数据发送至图像编码压缩模块460。
图像编码压缩模块460在获得第一图像数据和第二图像数据后，采用图像压缩算法，以并行的方式将图像数据由比特流形式压缩成JPEG等格式，从而降低数据运算量，并将压缩后的图像输入到视觉处理模块470完成图像的处理。
视觉处理模块470在多核任务处理器500的控制下，以并行的多级流水线方式处理数据，其输入数据为经过压缩后的JPEG图像，并在本地完成训练之后，得到合适的运算参数模型，其输出信息包括目标物体的位置信息和当前系统的空间位置信息、运动状态信息等。如图4所示为视觉处理模块470的流水线处理结构，以3项处理任务为例，利用多核的优势完成流水线任务中需要缓存的任务；在流水线处理中，通过多核任务处理器500中的CPU进行存储调度，满足流水线任务中的缓存需求，确保数据处理的不卡顿。同时，视觉处理模块470的数据处理结果还作为反馈信息，并通过反馈模块480输入到图像分割模块420和图像分辨率截断模块430，在下次数据信息获取时，完成目标的位置定位，并作为参数提供给图像分割模块420和图像分辨率截断模块430，提高运算的准确度。
在一些实施例中，多核任务处理器500与图像处理加速器400为异构体结构，能够减少芯片之间的硬件互联，有效降低设计的开发难度。
在一些实施例中，图像处理加速器400与存储模块600在一块PCB上直连，从而在系统PCB级提供了高速连接的方式，有效提高运算速率。
根据本发明实施例的高带宽信号处理系统，摄像头100作为图像传感器，生成高分辨率的数据流，并与运动传感器300生成的数据流作为一帧信号输入到图像处理加速器400中。图像数据经过图像分割预处理和图像分辨截断预处理传输到图像编码压缩模块460完成数据量的压缩，再经过流水线结构的视觉处理模块470，完成数据的运算和处理。在本发明实施 例中，采用FPGA+AMR的异构系统，降低了互联结构，并采用多核调度的任务机制，分段分任务的完成流水线任务，提高了运算速度。
另一方面，本发明还提出了一种电子设备，该电子设备包括上述的高带宽信号处理系统。其中，电子设备可以是飞行记录仪或是其它常见的电子设备。
另一方面，如图5所示，本发明还提出了一种信号处理方法，该信号处理方法与上述的高带宽信号处理系统相适配，包括以下几个步骤：
步骤S100：获取包含目标物体的二维图像信息。
具体的，可以采用高精度、高分辨率的高速摄像头来拍摄图像，从而产生相应的二维图像信息，该摄像头100具备1080p以上的分辨率；摄像头100拍摄图像后，以二维图像信息的存储格式和高速串行的方式，将数据输出至图像分块模块200。图像分块模块200对摄像头100发送的二维图像信息进行分块，并以多通道并行的传输模式发送串行数据至图像处理加速器400，由图像处理加速器400借助数据接口410，将多通道的串行数据还原成原始的二维图像信息。
步骤S200：获取高带宽信号处理系统的位置信息和运动状态信息。
具体的，采用运动传感器300来获取高带宽信号处理系统的位置信息和运动状态信息，并将其发送至图像处理加速器400。
步骤S300：根据二维图像信息、位置信息和运动状态信息，以并行的多级流水线的方式进行数据处理，以实现对目标物体的识别和定位。
具体的，图像处理加速器400在获取到图像分块模块200发送的二维图像信息和运动传感器300发送的位置信息和运动状态信息后，在多核任务处理器500和存储模块600的辅助下，以多核多级流水线的方式进行数据处理，完成对目标物体的识别和定位。
图像处理加速器400的具体数据处理过程包括以下步骤：
步骤S401：对二维图像信息进行图像分割，以获取包含目标物体的图像块；
步骤S402：对图像块进行第一预处理，以获得第一图像数据；
步骤S403：对二维图像信息进行分辨率截断，以获取仅包含背景数据的图像信息；
步骤S404：对图像信息进行第二预处理，以获得第二图像数据；
步骤S405：对第一图像数据和第二图像数据进行编码压缩，以获得第三图像数据；
步骤S406：以并行的多级流水线的方式，对第三图像数据、位置信息和运动状态信息进行数据处理，以实现对目标物体的识别和定位。
具体的，数据接口410基于串并转换结构，将图像分块模块200发送过来的多通道的串行数据，还原成原始的二维图像信息，并分别发送至图像分割模块420和图像分辨率截断模块440。
图像分割模块420根据目标物体的实际位置，将其转换成二维图像信息中对应的块地址，并对图像进行分割，只保留包含目标物体的图像块800。图像分割模块420以高分辨率进行分割，分割大小一般为8倍以上。如图3所示，包含目标物体的图像块800仅占据摄像头100获取的实拍图像的一小部分，因此需要通过图像分割模块420将这部分图像分割出来，降低图像处理的数据量。随后，图像分割模块420将图像块800发送至目标数据处理模块430进行第一预处理，第一预处理包括但不限于对图像进行滤波、缩放、平移、旋转等线性相应操作；图像分割模块420将经过第一预处理后所获得的第一图像数据发送至图像编码压缩模块460。
图像分辨率截断模块440在获得二维图像信息后，仅保留包含背景数据(即不包括目标物体)的图像信息，并对该图像信息进行分辨率截断，将原始的RGB图像只取8bit作为背景图像信息，从而以低分辨率的图像输入至背景数据处理模块450，通过降低分辨率的方式来降低实际所需传输的数据量。背景数据处理模块450对图像信息进行第二预处理，第二预处理包括但不限于对图像进行滤波、缩放、平移、旋转等线性相应操作，并将经过第二预处理后所获得的第二图像数据发送至图像编码压缩模块460。
图像编码压缩模块460在获得第一图像数据和第二图像数据后，采用图像压缩算法，以并行的方式将图像数据由比特流形式压缩成JPEG等格式，从而降低数据运算量，并将压缩后的图像输入到视觉处理模块470完成图像的处理。
视觉处理模块470在多核任务处理器500的控制下，以并行的多级流水线方式处理数据，其输入数据为经过压缩后的JPEG图像，并在本地完成训练之后，得到合适的运算参数模型，其输出信息包括目标物体的位置信息和当前系统的空间位置信息、运动状态信息等。如图4所示为视觉处理模块470的流水线处理结构，以3项处理任务为例，利用多核的优势完成流水线任务中需要缓存的任务；在流水线处理中，通过多核任务处理器500中的CPU进行存储 调度，满足流水线任务中的缓存需求，确保数据处理的不卡顿。同时，视觉处理模块470的数据处理结果还作为反馈信息，并通过反馈模块480输入到图像分割模块420和图像分辨率截断模块430，在下次数据信息获取时，完成目标的位置定位，并作为参数提供给图像分割模块420和图像分辨率截断模块430，提高运算的准确度。
根据本发明实施例的信号处理方法，通过摄像头100和运动传感器300的配合，在信号处理中能够从不同维度上对信号处理的结果进行适当的校准，以提高检测准确度；通过图像处理加速器400与多核任务处理器500的相互配合，能够以并行的多级流水线的形式完成数据处理，提高了信号处理的速度，并能够实现对目标物体的准确识别和定位。
另一方面，本发明还提供了一种计算机可读存储介质，该存储介质存储有程序，程序被处理器执行时实现上述的信号处理方法。
尽管本文描述了具体实施方案，但是本领域中的普通技术人员将认识到，许多其它修改或另选的实施方案同样处于本公开的范围内。例如，结合特定设备或组件描述的功能和/或处理能力中的任一项可以由任何其它设备或部件来执行。另外，虽然已根据本公开的实施方案描述了各种示例性具体实施和架构，但是本领域中的普通技术人员将认识到，对本文所述的示例性具体实施和架构的许多其它修改也处于本公开的范围内。
上文参考根据示例性实施方案所述的系统、方法、系统和/或计算机程序产品的框图和流程图描述了本公开的某些方面。应当理解，框图和流程图中的一个或多个块以及框图和流程图中的块的组合可分别通过执行计算机可执行程序指令来实现。同样，根据一些实施方案，框图和流程图中的一些块可能无需按示出的顺序执行，或者可以无需全部执行。另外，超出框图和流程图中的块所示的那些部件和/或操作以外的附加部件和/或操作可存在于某些实施方案中。
因此，框图和流程图中的块支持用于执行指定功能的装置的组合、用于执行指定功能的元件或步骤的组合以及用于执行指定功能的程序指令装置。还应当理解，框图和流程图中的每个块以及框图和流程图中的块的组合可以由执行特定功能、元件或步骤的专用硬件计算机系统或者专用硬件和计算机指令的组合来实现。
本文所述的程序模块、应用程序等可包括一个或多个软件组件，包括例如软件对象、方法、数据结构等。每个此类软件组件可包括计算机可执行指令，所述计算机可执行指令响应 于执行而使本文所述的功能的至少一部分(例如，本文所述的例示性方法的一种或多种操作)被执行。
软件组件可以用各种编程语言中的任一种来编码。一种例示性编程语言可以为低级编程语言，诸如与特定硬件体系结构和/或操作系统平台相关联的汇编语言。包括汇编语言指令的软件组件可能需要在由硬件架构和/或平台执行之前由汇编程序转换为可执行的机器代码。另一种示例性编程语言可以为更高级的编程语言，其可以跨多种架构移植。包括更高级编程语言的软件组件在执行之前可能需要由解释器或编译器转换为中间表示。编程语言的其它示例包括但不限于宏语言、外壳或命令语言、作业控制语言、脚本语言、数据库查询或搜索语言、或报告编写语言。在一个或多个示例性实施方案中，包含上述编程语言示例中的一者的指令的软件组件可直接由操作系统或其它软件组件执行，而无需首先转换成另一种形式。
软件组件可存储为文件或其它数据存储构造。具有相似类型或相关功能的软件组件可一起存储在诸如特定的目录、文件夹或库中。软件组件可为静态的(例如，预设的或固定的)或动态的(例如，在执行时创建或修改的)。
上面结合附图对本发明实施例作了详细说明，但是本发明不限于上述实施例，在所属技术领域普通技术人员所具备的知识范围内，还可以在不脱离本发明宗旨的前提下作出各种变化。
Claims (10)
- 一种高带宽信号处理系统，其特征在于，包括：摄像头，用于拍摄图像，并产生相应的二维图像信息；图像分块模块，用于对所述二维图像信息进行分块，形成多通道的串行数据；运动传感器，用于获取所述高带宽信号处理系统的位置信息和运动状态信息；图像处理加速器，用于获取所述图像分块模块和所述运动传感器所发送的数据，并以并行的多级流水线的方式进行数据处理，以实现对目标物体的识别和定位；多核任务处理器，用于对所述图像处理加速器的数据处理过程进行任务分配和调度，以及获取所述图像处理加速器的数据处理结果；存储模块，用于为所述图像处理加速器提供数据缓存功能，以及为所述图像处理加速器提供训练集。
- 根据权利要求1所述的高带宽信号处理系统，其特征在于，还包括通信接口，所述通信接口与所述多核任务处理器电连接。
- 根据权利要求1所述的高带宽信号处理系统，其特征在于，所述图像处理加速器包括：数据接口，用于将所述多通道的串行数据还原成所述二维图像信息；图像分割模块，用于对所述二维图像信息进行图像分割，以获取包含所述目标物体的图像块；目标数据处理模块，用于对所述图像块进行第一预处理，以获得第一图像数据；图像分辨率截断模块，用于对所述二维图像信息进行分辨率截断，以获取仅包含背景数据的图像信息；背景数据处理模块，用于对所述图像信息进行第二预处理，以获得第二图像数据；图像编码压缩模块，用于对所述第一图像数据和所述第二图像数据进行编码压缩，以获得第三图像数据；视觉处理模块，用于根据所述第三图像数据，以并行的多级流水线的方式进行数据处理，以实现对目标物体的识别和定位；反馈模块，用于将所述视觉处理模块的数据处理结果作为反馈信息，发送至所述图像分割模块和所述图像分辨率截断模块。
- 根据权利要求1所述的高带宽信号处理系统，其特征在于，所述图像处理加速器与所述存储模块在一块PCB上直连。
- 根据权利要求1所述的高带宽信号处理系统，其特征在于，所述图像处理加速器和所 述多核任务处理器为异构体结构。
- 一种电子设备，其特征在于，包括如权利要求1至5任一项所述的高带宽信号处理系统。
- 一种信号处理方法，其特征在于，包括：获取包含目标物体的二维图像信息；获取高带宽信号处理系统的位置信息和运动状态信息；根据所述二维图像信息、所述位置信息和所述运动状态信息，以并行的多级流水线的方式进行数据处理，以实现对所述目标物体的识别和定位。
- 根据权利要求7所述的信号处理方法，其特征在于，所述获取包含目标物体的二维图像信息的步骤之后，还包括以下步骤：对所述二维图像信息进行分块，形成多通道的串行数据；对所述串行数据进行串并转换，以还原所述二维图像信息。
- 根据权利要求7所述的信号处理方法，其特征在于，所述根据所述二维图像信息、所述位置信息和所述运动状态信息，以并行的多级流水线的方式进行数据处理，以实现对所述目标物体的识别和定位，包括以下步骤：对所述二维图像信息进行图像分割，以获取包含所述目标物体的图像块；对所述图像块进行第一预处理，以获得第一图像数据；对所述二维图像信息进行分辨率截断，以获取仅包含背景数据的图像信息；对所述图像信息进行第二预处理，以获得第二图像数据；对所述第一图像数据和所述第二图像数据进行编码压缩，以获得第三图像数据；以并行的多级流水线的方式，对所述第三图像数据、所述位置信息和所述运动状态信息进行数据处理，以实现对所述目标物体的识别和定位。
- 一种计算机可读存储介质，所述存储介质存储有程序，其特征在于，所述程序被处理器执行时实现权利要求7至9任一项所述的信号处理方法。
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