WO2023201797A1 - 频域特性测量方法、装置、系统及存储介质 - Google Patents

频域特性测量方法、装置、系统及存储介质 Download PDF

Info

Publication number
WO2023201797A1
WO2023201797A1 PCT/CN2022/092923 CN2022092923W WO2023201797A1 WO 2023201797 A1 WO2023201797 A1 WO 2023201797A1 CN 2022092923 W CN2022092923 W CN 2022092923W WO 2023201797 A1 WO2023201797 A1 WO 2023201797A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency point
power supply
output
supply network
output interface
Prior art date
Application number
PCT/CN2022/092923
Other languages
English (en)
French (fr)
Inventor
马茂松
方雅祺
刘建斌
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US18/164,095 priority Critical patent/US20230341447A1/en
Publication of WO2023201797A1 publication Critical patent/WO2023201797A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G01R23/10—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into a train of pulses, which are then counted, i.e. converting the signal into a square wave
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a frequency domain characteristic measurement method, device, system and storage medium of a power supply network (PDN, Power Delivery Network).
  • PDN Power Supply Network
  • the normal operation of the chip requires power.
  • Some chips include a power network and functional circuits.
  • the functional circuits are powered by the power network.
  • the power network is crucial to the working stability of a chip, so it is necessary to measure the frequency domain characteristics of the power network.
  • the power network of a chip usually includes the entire path from the power supply circuit to the power input end of the functional circuit.
  • the circuits inside the chip are too delicate, there are few instruments that can truly measure the frequency domain characteristics of the power supply network.
  • embodiments of the present disclosure are expected to provide a method, device, system and storage medium for measuring frequency domain characteristics of a power supply network.
  • Embodiments of the present disclosure provide a method for measuring frequency domain characteristics of a power supply network.
  • the output end of the power supply network is connected to the power supply end of a functional circuit; the method includes:
  • the impedance characteristic of the power supply network at the first frequency point is determined.
  • the first level signal of the first preset pattern represents a level signal whose signal value is always the first level
  • the second level signal of the second preset pattern indicates that the signal value is the level signal formed by the first level and the second level according to the preset duty cycle
  • the first level is greater than the second level.
  • the voltage corresponding to the first level is substantially the same as the voltage provided by the power network to the functional circuit.
  • the preset duty cycle is 50%.
  • the preset duty cycle includes multiple duty cycles
  • the obtaining the voltage change value corresponding to the first frequency point output by the output interface under test includes:
  • the average value of multiple preliminary impedance characteristics corresponding to the first frequency point is determined as the impedance characteristic of the power supply network at the first frequency point.
  • determining the impedance characteristics of the power network at the first frequency point based on the voltage change value corresponding to the first frequency point includes:
  • the impedance characteristics of the power supply network at the first frequency point are determined.
  • the impedance characteristics of the power supply network at the first frequency point are determined, including:
  • the quotient of the power supply noise value corresponding to the first frequency point and the current value corresponding to the first frequency point is determined as the impedance characteristic at the first frequency point.
  • the first preset frequency point is a certain frequency point within the preset frequency range; the method further includes:
  • the frequency point set includes the preset frequency Multiple frequency points within the range
  • the impedance characteristics of the power supply network at each remaining frequency point are determined.
  • the preset frequency range at least includes 10 MHz to 1000 MHz.
  • the method also includes:
  • a frequency domain characteristic curve of the power supply network is determined.
  • the method also includes:
  • the accuracy of the simulated frequency domain characteristic curve is verified based on the simulated frequency domain characteristic curve and the frequency domain characteristic curve.
  • the power supply network at least includes a power management integrated circuit, a printed circuit board power supply layer, a packaged power supply layer, and a power processing subcircuit of the power supply end of the functional chip.
  • An embodiment of the present disclosure also provides a device for measuring frequency domain characteristics of a power supply network, the output end of the power supply network is connected to the power supply end of the functional circuit; the device includes:
  • a detection module configured to obtain the output interface to be tested of the chip
  • a control module configured to control the output interface under test to output a first level signal of a first preset pattern
  • the control module is also configured to control at least one other output interface of the chip except the output interface to be tested to output a second level signal of a second preset rule according to a first frequency point;
  • the detection module is also configured to obtain the voltage change value corresponding to the first frequency point output by the output interface under test;
  • An analysis module configured to determine the impedance characteristics of the power network at the first frequency point based on the voltage change value corresponding to the first frequency point.
  • An embodiment of the present disclosure also provides a frequency domain measurement system for a power supply network, including: a chip, a control circuit, a detection circuit and an analysis circuit; wherein,
  • the chip includes a power supply network and a functional circuit; the output end of the power supply network is connected to the power supply end of the functional circuit; the power supply network is used to: provide power for the functional circuit;
  • the detection circuit is used to: obtain the output interface to be tested of the functional circuit;
  • the control circuit is connected to the power supply network and the detection circuit respectively; the control circuit is used to control the output interface to be tested to output a first level signal of a first preset pattern; to control the functional circuit to remove all At least one other output interface other than the output interface to be tested outputs a second level signal with a second preset pattern according to the first frequency point;
  • the detection circuit is connected to the output interface to be tested of the functional circuit and the analysis circuit; the detection circuit is used to: detect the voltage change value corresponding to the first frequency point output by the output interface to be tested, and Pass the first voltage change value corresponding to the first frequency point to the analysis circuit;
  • the control circuit is also configured to determine the impedance characteristics of the power network at the first frequency point based on the voltage change value corresponding to the first frequency point.
  • An embodiment of the present disclosure also provides a computer-readable storage medium on which a computer program is stored.
  • the computer program is executed by a processor, the steps in the frequency domain characteristic measurement method of a power supply network provided by the embodiment of the present disclosure are implemented.
  • the impedance characteristics of the power network at a specific frequency point are determined by detecting the voltage change value output by the output interface to be tested of the chip at a specific frequency point.
  • the impedance characteristics at a specific frequency point are obtained based on real circuit measurements, which can more realistically reflect the frequency domain characteristics of the power supply network.
  • the power network in this disclosure is packaged inside the chip, and the level signal output by the chip output port is generated and controlled by the power network itself.
  • the focus of the test in this disclosure is to test the components located inside the memory or other packaged chips. Frequency domain characteristics of the power network.
  • Figure 1 is a schematic diagram of a basic resistance/inductance/capacitance (R/L/C) model of a power supply network provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of a frequency domain impedance curve corresponding to a model of each part of a power supply network provided by an embodiment of the present disclosure
  • Figure 3 is an example diagram of a frequency domain impedance curve of a power supply network obtained through simulation according to an embodiment of the present disclosure
  • Figure 4 is a schematic flow chart of the implementation of a method for measuring frequency domain characteristics of a power supply network provided by an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of the relationship between some output interfaces of the chip and the power supply network provided by the embodiment of the present disclosure
  • Figure 6 is a schematic diagram of level signals output by some output interfaces of the chip provided by an embodiment of the present disclosure
  • Figure 7 is an example diagram of a power supply noise curve corresponding to a specific frequency point of the power supply network provided by an embodiment of the present disclosure
  • Figure 8a is an example diagram of a power supply noise curve corresponding to 100MHz for the power supply network provided by the embodiment of the present disclosure
  • Figure 8b is an example diagram of a power supply noise curve corresponding to 150MHz for the power supply network provided by the embodiment of the present disclosure
  • Figure 9 is an example diagram of a frequency domain impedance curve of a power supply network obtained through real measurements provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a device for measuring frequency domain characteristics of a power supply network provided by an embodiment of the present disclosure.
  • Some chips include a power supply network and a functional circuit; among them, the functional circuit is powered by the power supply network.
  • the power supply network can be understood as the sum of the power supply parts in the chip. It is used to provide all the voltages required by the power circuit. It is generally believed that only There is a power network, because the power network itself is a collection of power supply paths.
  • a general power network can usually include: power management integrated circuit (PMIC), which is the power supply circuit, printed circuit board power planes (PCB Power Planes), package power planes (Package Power Planes), and power processing subcircuit at the power supply end of the functional circuit. Such as on-die Capacitance.
  • PMIC power management integrated circuit
  • PCB Power Planes printed circuit board power planes
  • Package Power Planes package power planes
  • Power Processing subcircuit at the power supply end of the functional circuit.
  • Each part can be abstracted into the most basic R/L/C model, thereby modeling the entire power network in terms of frequency domain characteristics.
  • the power network of the chip is equivalent to: the voltage reference and low-pass filter (LPF) formed by the power management integrated circuit, and the large-capacity capacitor (such as the equivalent formed by the power layer of the printed circuit board).
  • LPF voltage reference and low-pass filter
  • the large-capacity capacitor such as the equivalent formed by the power layer of the printed circuit board.
  • Electrolytic capacitors small-capacity high capacitors (such as ceramic capacitors)
  • the first inductance equivalently formed between each layer of the printed circuit board (PCB Plane) and each via hole (Via), via holes and solder balls in the package power layer
  • the second inductor is equivalently formed between (Ball)
  • the third inductor is equivalently formed by solder bumps (Bumps), and the decoupling capacitor (on-chip capacitor) of the power supply end of the functional circuit.
  • the impedance curve of the power supply network will have a peak value, such as the power supply network resonance point (PDN Resonance) shown in the dotted circle in Figure 2. ).
  • Zmax is the base impedance.
  • the base impedance can be calculated according to the following formula:
  • the impedance characteristics of the chip's power network are generally obtained through simulation. Specifically, the R/L/C models of the aforementioned power management integrated circuit, printed circuit board power layer, and package power layer are extracted through simulation, and Combined with the value of the on-chip capacitor, the frequency domain impedance curve of a power supply network is simulated. In practical applications, an example diagram of the frequency domain impedance curve of a power supply network obtained through simulation is shown in Figure 3. However, the frequency domain impedance curve of the power supply network obtained through simulation lacks consideration of the real circuit environment and cannot truly reflect the frequency domain characteristics of the power supply network.
  • embodiments of the present disclosure provide a method, device, system and storage medium for measuring frequency domain characteristics of a power supply network.
  • the impedance characteristics of the power supply network at a specific frequency point are determined by detecting the voltage change value output by the output interface under test of the chip at a specific frequency point.
  • the impedance characteristics at specific frequency points are obtained based on real circuit measurements, which can more realistically reflect the frequency domain characteristics of the power supply network.
  • FIG. 4 is a schematic flow chart of the implementation of the method for measuring frequency domain characteristics of a power supply network according to an embodiment of the present disclosure. As shown in Figure 4, the method includes the following steps:
  • Step 401 Obtain the output interface to be tested of the functional circuit
  • Step 402 Control the output interface to be tested to output a first level signal of a first preset pattern
  • Step 403 Control at least one other output interface of the functional circuit except the output interface to be tested to output a second level signal of the second preset pattern according to the first frequency point;
  • Step 404 Obtain the voltage change value corresponding to the first frequency point output by the output interface under test
  • Step 405 Determine the impedance characteristics of the power supply network at the first frequency point based on the voltage change value corresponding to the first frequency point.
  • a chip is equipped with a power supply network.
  • the power supply network can be understood as the sum of the power supply parts of the chip. It is used to provide all the voltages required by functional circuits.
  • a power network can provide one voltage or several different voltages. For example, if the functional circuit of a chip requires two different voltages, 3.3V and 1.8V, the power network of the chip can provide two different voltages, 3.3V and 1.8V.
  • the chip's power network usually includes the entire path from the power supply circuit to the power input terminal of the functional circuit.
  • the power network includes at least a power management integrated circuit, a printed circuit board power layer, a packaged power layer, and a power supply processing subcircuit of the functional circuit.
  • the power processing subcircuit of the power supply end of the functional circuit may include an on-chip capacitor provided in the chip at the power supply end of the functional circuit, etc.
  • the chip can include a power network and a functional circuit, and the output end of the power network is connected to the power supply end of the functional circuit.
  • the chip may include a dynamic random access device.
  • the embodiment of the present disclosure proposes a method for testing the frequency domain characteristics of the chip power network based on the characteristics of the chip's internal power network and output interface.
  • the functional circuit of the chip may include multiple output interfaces.
  • the output interface may be the input/output (I/O, Input/Output) pin of the chip, or a test solder joint connected to the input/output pin of the chip.
  • the power network provides power to multiple I/O pins of the chip at the same time.
  • Figure 5 is a schematic diagram of the relationship between some output interfaces of the chip provided by the embodiment of the present disclosure and the power network. As shown in Figure 5, the I/O pins consume power when there is a signal output and draw current from the power network.
  • the output interface to be tested includes any one of the multiple output interfaces that is powered by the power network.
  • the way to obtain the output interface under test of a functional circuit is to receive information.
  • the received information indicates that any output interface (any numbered I/O pin powered by the power network) is randomly selected as the output interface under test. , or specify and select a certain output interface (a specific number of I/O pins powered by the power network) as the output interface to be tested.
  • step 402 the controlled object is the aforementioned output interface to be tested.
  • the first preset rule may include constantly generating a certain level signal.
  • the first level signal of the first preset pattern represents a level signal whose signal value is always the first level.
  • the voltage corresponding to the first level is substantially the same as the voltage provided by the power network to the functional circuit, that is, a high level.
  • the I/O pin can be regarded as a short circuit with the power network, so that the I/O pin always outputs the voltage provided by the power network to the functional circuit.
  • the slight difference can be a slight voltage drop caused by the line or a measurement error, etc.
  • the control object is at least one other output interface of the chip except the output interface to be tested. Both the at least one output interface and the output interface to be tested are powered by the power network. It should be noted that at least one other output interface may include multiple, and as the number increases, the higher the spectrum assignment of a specific I/O pin, the more obvious the noise phenomenon of the power supply will be. In practical applications, among the N I/O pins powered by the same power supply network, the remaining N-1 I/O pins except those selected as the output interface to be tested can be used as control objects in step 403.
  • the second level signal of the second preset pattern represents a level signal formed by the first level and the second level according to the preset duty cycle; in other embodiments, the second preset level signal
  • the rules include randomly generating level signals, and the randomly generated level is the first level or the second level.
  • the first level is greater than the second level, the first level is a high level, and the second level is a low level; in addition, the above-mentioned "preset duty cycle" can be a fixed value or a random value.
  • the preset duty cycle is 50%. For example, output a changing clock signal of "010101.".
  • the preset duty cycle may be other stable values.
  • a clock signal that changes between "001001001" and "000100010001" is output.
  • the first frequency point is a fixed frequency value.
  • the output frequency of the second level signal can be adjusted according to the frequency of the clock pulse (CP, Clock Pulse) to achieve frequency adjustment.
  • control circuit that can realize the chip pin control function can be used to implement the control in steps 402 and 403.
  • the control circuit here includes but is not limited to a field programmable logic array (FPGA, Field Programmable Gate Array) test development board. .
  • step 404 the output value, that is, the voltage change value of the output interface under test within a period of time is measured to determine the influence of the output interface under test on other output interfaces.
  • an oscilloscope or spectrum analyzer can be used to obtain the voltage change value corresponding to the first frequency point output by the output interface under test.
  • step 405 the impedance characteristics of the power supply network at the first frequency point can be determined based on the voltage change value corresponding to the first frequency point.
  • the impedance characteristics of the power supply network at the first frequency point are determined based on the voltage change value corresponding to the first frequency point, including:
  • the impedance characteristics of the power supply network at the first frequency point are determined.
  • the power supply noise value may be the maximum value of the difference between the current voltage value and the current expected voltage value among the voltage change values corresponding to the first frequency point.
  • the current expected voltage value changes as the level changes.
  • the expected voltage value may It is considered to be the maximum voltage value of the corresponding level; or, the difference between the maximum voltage value and the minimum voltage value.
  • determining the impedance characteristics of the power supply network at the first frequency point includes:
  • the quotient of the power supply noise value corresponding to the first frequency point and the current value corresponding to the first frequency point is determined as the impedance characteristic at the first frequency point.
  • the current value refers to the operating current provided by the power network to at least one output interface (N-1 I/O pins) of the chip in addition to the output interface to be tested.
  • the current value is N-1 I/O tubes.
  • the current value can be obtained by measuring the current on the load of N-1 I/O pins.
  • the specific way to measure the current may be to measure the current by measuring the voltage and resistance at both ends of the load.
  • the impedance characteristics of the power network at the first frequency point are obtained.
  • the impedance characteristics of the power supply network at the first frequency point can reflect at least part of the frequency domain characteristics of the power supply network.
  • the second level signal can be a variety of clock signals with different duty cycles, so that each different duty cycle can be tested separately.
  • the preset duty cycle includes multiple duty cycles
  • the average value of multiple preliminary impedance characteristics corresponding to the first frequency point is determined as the impedance characteristic of the power supply network at the first frequency point.
  • the test for each duty cycle is the same as the method for determining the impedance characteristics corresponding to the aforementioned duty cycle of 50%.
  • the obtained multiple preliminary impedance characteristics of the power supply network at the first frequency point can be determined as the impedance characteristics of the power supply network at the first frequency point by averaging or other methods.
  • the output frequency range of the chip is wide. According to the aforementioned method of obtaining the impedance characteristics of the power supply network at the first frequency point, the impedance characteristics of the power supply network at other frequency points in the output frequency range can be obtained.
  • the first preset frequency point is a certain frequency point within the preset frequency range; the method further includes:
  • the frequency point set includes multiple frequency points within a preset frequency range;
  • the impedance characteristics of the power network at each remaining frequency point are determined.
  • the method for determining the impedance characteristics corresponding to each remaining frequency point in the frequency point set except the first frequency point is the same as the aforementioned first frequency point.
  • the general output frequency range of the chip is 50MHz ⁇ 200MHz
  • the preset range can be a range that covers the output frequency range.
  • the preset frequency range includes at least 10 MHz to 1000 MHz.
  • the method further includes:
  • the frequency domain characteristic curve of the power supply network is determined.
  • the frequency domain of the power supply network can be drawn using the characteristic impedance corresponding to the first frequency point and each remaining frequency point. characteristic curve. It can be understood that when the number of each remaining frequency point acquired is larger, the frequency domain characteristic curve of the power supply network drawn is more accurate and smoother.
  • the measured frequency domain characteristic curve of the power supply network can be compared with the simulated frequency domain characteristic curve of the power supply network obtained through modeling and simulation to evaluate The accuracy of the simulated frequency domain characteristic curve.
  • the method further includes:
  • the measured frequency domain characteristic curve of the power supply network can also be used to guide the model correction of the power supply network.
  • the impedance characteristics of the power network at a specific frequency point are determined by detecting the voltage change value output by the output interface to be tested of the chip at a specific frequency point.
  • the impedance characteristics at a specific frequency point are obtained based on real circuit measurements, which can more realistically reflect the frequency domain characteristics of the power supply network.
  • the embodiment of the present disclosure is implemented through a specific I/O combination method, specifically:
  • Step 1 Among the N I/O pins powered by the same power supply network, select any I/O pin (equivalent to the aforementioned output interface to be tested) and always output a high level, that is, output "111111" clock signal (equivalent to the aforementioned first level signal).
  • Step 2 Among the N I/O pins powered by the same power supply network, except the selected one I/O pin, connect the remaining N-1 pins (equivalent to the aforementioned chip except the output interface to be tested). At least one other output interface), and simultaneously outputs a clock signal that changes "010101" according to a fixed frequency (equivalent to the aforementioned second level signal).
  • the schematic diagram of the I/O pin output signal in steps 1 and 2 is shown in Figure 6. It should be noted that the number of I/O pins shown in Figure 6 does not represent the actual number used, and the N value can be adjusted according to the actual situation.
  • Step 3 Use an oscilloscope or spectrum analyzer to test the high-level signal output by the I/O pin selected in step 1 to calculate the power supply noise value at this time.
  • FIG. 7 is an example diagram of a power supply noise curve corresponding to a specific frequency point of the power supply network provided by an embodiment of the present disclosure.
  • the waveform in the upper part of Figure 7 is the "010101" switching signal output by N-1 I/O pins; the waveform in the lower part of Figure 7 is the waveform of power supply noise. From Figure 7 it can be This results in a power supply noise value of 105mV in this specific example.
  • Step 4 Repeat steps 2 and 3, switching the frequency of step 2 in each repetition.
  • the switching frequency range can be selected from 10MHz to 1000MHz.
  • Step 5 Record the power supply noise values at different frequency points, and divide the power supply noise value by the current consumed by N-1 I/O pin switching to obtain the impedance characteristics of the power supply network at different frequency points.
  • Figure 8a is an example diagram of a power supply noise curve corresponding to 100 MHz of the power supply network provided by an embodiment of the present disclosure
  • Figure 8b is an example diagram of a power supply noise curve corresponding to 150 MHz of the power supply network provided by an embodiment of the present disclosure.
  • FIG. 9 is an example diagram of a frequency domain impedance curve of a power supply network obtained through actual measurement provided by an embodiment of the present disclosure. Through this method, the frequency domain characteristics of the power supply network can be accurately measured and verified with the simulation results.
  • the embodiments of the present disclosure can be applied to various types of chips that require frequency domain characteristic testing.
  • it can be applied to the testing and verification of dynamic random access memory, such as synchronous dynamic random access memory SDRAM and double-rate synchronous dynamic random access memory DDR.
  • the FPGA memory test development board can be used to verify and test the frequency points of SSN (synchronous switching noise) generated inside the dynamic random access memory.
  • the embodiment of the present disclosure also provides a frequency domain characteristic measurement device 1000 for a power supply network.
  • Figure 10 is a structural diagram of the device according to the embodiment of the present disclosure. As shown in Figure 10, the device 1000 includes: Detection module 1001, control module 1002 and analysis module 1003; wherein,
  • the detection module 1001 is configured to obtain the output interface to be tested of the functional circuit
  • the control module 1002 is configured to control the output interface under test to output a first level signal of a first preset pattern
  • the control module 1002 is also configured to control at least one other output interface of the functional circuit except the output interface to be tested to output a second level signal of a second preset rule according to the first frequency point;
  • the detection module 1001 is also configured to obtain the voltage change value corresponding to the first frequency point output by the output interface to be tested;
  • the analysis module 1003 is configured to determine the impedance characteristics of the power supply network at the first frequency point based on the voltage change value corresponding to the first frequency point.
  • the output of the power network is connected to the power supply of the functional circuit.
  • the first level signal of the first preset pattern represents a level signal whose signal value is always the first level
  • the second level signal of the second preset pattern indicates that the signal value is a level signal formed by the first level and the second level according to the preset duty cycle;
  • the first level is greater than the second level.
  • the voltage corresponding to the first level is substantially the same as the voltage provided by the power network to the functional circuit.
  • the preset duty cycle is 50%.
  • the preset duty cycle includes multiple duty cycles
  • the detection module 1001 is specifically configured to obtain multiple sets of voltage change values corresponding to the first frequency point output by the output interface to be tested; the multiple sets of voltage change values correspond to multiple different duty cycles respectively;
  • the analysis module 1003 is specifically configured to determine multiple preliminary impedance characteristics of the power supply network at the first frequency point based on multiple sets of voltage change values corresponding to the first frequency point. Each preliminary impedance characteristic corresponds to a duty cycle; convert the first frequency The average value of multiple preliminary impedance characteristics corresponding to the points is determined as the impedance characteristics of the power network at the first frequency point.
  • the analysis module 1003 is specifically configured to determine the power supply noise value corresponding to the first frequency point based on the voltage change value corresponding to the first frequency point; based on the power supply noise value corresponding to the first frequency point, determine the power supply network in Impedance characteristics at the first frequency point.
  • the analysis module 1003 is specifically configured to obtain the current value corresponding to at least one other output interface at a first frequency point; and compare the power supply noise value corresponding to the first frequency point with the current value corresponding to the first frequency point. The quotient is determined as the impedance characteristic at the first frequency point.
  • the first preset frequency point is a certain frequency point within the preset frequency range
  • the control module 1002 is also configured to control at least one other output interface to output a second level signal according to each remaining frequency point in the frequency point set except the first frequency point; the frequency point set includes a preset frequency range. Multiple frequency points;
  • the detection module 1001 is also configured to obtain the voltage change value corresponding to each remaining frequency point output by the output terminal to be measured;
  • the analysis module 1003 is also configured to determine the impedance characteristics of the power network at each remaining frequency point based on the voltage change value corresponding to each remaining frequency point.
  • the preset frequency range includes at least 10 MHz to 1000 MHz.
  • the analysis module 1003 is further configured to determine the frequency domain characteristic curve of the power supply network based on the impedance characteristics of the power supply network at the first frequency point and the characteristic impedance of the power supply network at each remaining frequency point.
  • the detection module 1001 is configured to obtain the simulated frequency domain characteristic curve of the power supply network obtained by modeling and simulating the power supply network;
  • Device 1000 also includes:
  • a verification module configured to verify the accuracy of the simulated frequency domain characteristic curve based on the simulated frequency domain characteristic curve and the frequency domain characteristic curve.
  • the power network includes at least a power management integrated circuit, a printed circuit board power layer, a packaged power layer, and a power processing subcircuit on the power supply side of the functional circuit.
  • the detection module 1001, the control module 1002, the analysis module 1003 and the verification module are implemented by the processor in the frequency domain characteristic measurement device 1000 of the power supply network.
  • the embodiment of the present disclosure also provides a frequency domain measurement system for a power supply network, which is characterized in that it includes: a chip, a control circuit, a detection circuit and an analysis circuit;
  • the chip includes a power network and a functional circuit; the output end of the power network is connected to the power supply end of the functional circuit; the power network is used to: provide power for the functional circuit;
  • the detection circuit is used to: obtain the output interface to be tested of the functional circuit;
  • the control circuit is connected to the power supply network and the detection circuit respectively; the control circuit is used to: control the output interface to be tested to output a first level signal of a first preset pattern; to control at least one other output interface of the chip except the output interface to be tested according to The first frequency point outputs a second level signal with a second preset pattern; the output interface to be tested and at least one output interface are both powered by the power network;
  • the detection circuit is connected to the output interface to be tested and the analysis circuit of the chip; the detection circuit is used to: detect the voltage change value corresponding to the first frequency point output by the output interface to be tested, and transmit the first voltage change value corresponding to the first frequency point.
  • the detection circuit is used to: detect the voltage change value corresponding to the first frequency point output by the output interface to be tested, and transmit the first voltage change value corresponding to the first frequency point.
  • the analysis circuit is used to determine the impedance characteristics of the power network at the first frequency point based on the voltage change value corresponding to the first frequency point.
  • control circuit may include devices and device peripherals capable of realizing chip pin control functions.
  • Control circuits include but are not limited to FPGA, digital signal processing (DSP, Digital Signal Processing) micro control unit (MCU, Microcontroller Unit), etc.
  • the detection circuit can include a self-built test circuit or existing measurement equipment such as an oscilloscope or spectrum analyzer.
  • An embodiment of the present disclosure also provides a storage medium on which a computer program is stored.
  • the computer program is executed by a processor, the steps in the frequency domain characteristic measurement method of a power supply network provided by the embodiment of the present disclosure are implemented.
  • the storage medium may be Ferromagnetic Random Access Memory (FRAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM, Erasable Programmable Read-Only Memory), Electrically Erasable Programmable Read-Only Memory (EEPROM, Electrically Erasable Programmable Read-Only Memory), Flash Memory, Magnetic Surface Memory, optical disk, or CD-ROM (Compact Disc Read-Only Memory) and other memories; it can also be various devices including one of the above memories or any combination thereof.
  • FRAM Ferromagnetic Random Access Memory
  • ROM Read Only Memory
  • PROM Programmable Read-Only Memory
  • EPROM Erasable Programmable Read-Only Memory
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • Flash Memory Magnetic Surface Memory, optical disk, or CD-ROM (Compact Disc Read-Only Memory) and other memories; it can also be various devices including one of the above memories or any combination thereof.
  • executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and their May be deployed in any form, including deployed as a stand-alone program or deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.
  • executable instructions may, but do not necessarily correspond to, files in a file system and may be stored as part of a file holding other programs or data, for example, in a Hyper Text Markup Language (HTML) document. in one or more scripts, in a single file that is specific to the program in question, or in multiple collaborative files (e.g., files that store one or more modules, subroutines, or portions of code).
  • HTML Hyper Text Markup Language
  • executable instructions may be deployed to execute on one computing device, or on multiple computing devices located at one location, or alternatively, on multiple computing devices distributed across multiple locations and interconnected by a communications network execute on.
  • the impedance characteristics of the power network at a specific frequency point are determined by detecting the voltage change value output by the output interface to be tested of the chip at a specific frequency point.
  • the impedance characteristics at a specific frequency point are obtained based on real circuit measurements, which can more realistically reflect the frequency domain characteristics of the power supply network.
  • the power network in this disclosure is packaged inside the chip, and the level signal output by the chip output port is generated and controlled by the power network itself. The focus of the test in this disclosure is to test the components located inside the memory or other packaged chips. Frequency domain characteristics of the power network.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

一种电源网络的频域特性测量方法、装置、系统及存储介质。其中，所述电源网络的输出端连接功能电路的供电端；所述方法包括：获取所述功能电路的待测输出接口；控制所述待测输出接口输出第一预设规律的第一电平信号；控制所述功能电路除所述待测输出接口之外的其它至少一个输出接口按照第一频率点输出第二预设规律的第二电平信号；获取所述待测输出接口输出的所述第一频率点对应的电压变化值；基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第一频率点的阻抗特性。

Description

频域特性测量方法、装置、系统及存储介质
相关的交叉引用
本公开基于申请号为202210431068.X、申请日为2022年04月22日、发明名称为“频域特性测量方法、装置、系统及存储介质”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种电源网络(PDN，Power Delivery Network)的频域特性测量方法、装置、系统及存储介质。
背景技术
芯片的正常工作需要电源，一些芯片包括电源网络和功能电路，功能电路由电源网络进行供电。电源网络对一颗芯片的工作稳定性至关重要，因而电源网络的频域特性的测量十分有必要。实际应用中，一颗芯片的电源网络通常包含从电源供电电路到功能电路的电源输入端的整个通路。然而，由于芯片内部的电路太过于精细，几乎没有什么仪器可以真实测量到电源网络频域特性。
相关技术中，多采用建模与仿真的方式获得电源网络的频域特性，不能真实的反映电源网络的频域特性。因此，亟待提供一种能够比较真实的反映电源网络的频域特性的测量方法。
发明内容
有鉴于此，本公开实施例期望提供一种电源网络的频域特性测量方法、装置、系统及存储介质。
本公开实施例的技术方案是这样实现的：
本公开实施例提供一种电源网络的频域特性测量方法，所述电源网络的输出端连接功能电路的供电端；所述方法包括：
获取所述功能电路的待测输出接口；
控制所述待测输出接口输出第一预设规律的第一电平信号；
控制所述功能电路除所述待测输出接口之外的其它至少一个输出接口按照第一频率点输出第二预设规律的第二电平信号；
获取所述待测输出接口输出的所述第一频率点对应的电压变化值；
基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第 一频率点的阻抗特性。
上述方案中，所述第一预设规律的第一电平信号表示信号值恒为第一电平的电平信号；
所述第二预设规律的第二电平信号表示信号值为所述第一电平和第二电平按照预设占空比所形成的电平信号；
所述第一电平大于所述第二电平。
上述方案中，所述第一电平对应的电压与所述电源网络向所述功能电路提供的电压基本相同。
上述方案中，所述预设占空比为50％。
上述方案中，所述预设占空比包括多个占空比；
所述获取所述待测输出接口输出的所述第一频率点对应的电压变化值，包括：
获取所述待测输出接口输出的所述第一频率点对应的多组电压变化值；所述多组电压变化值分别对应所述多个不同的占空比；
所述基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第一频率点的阻抗特性，包括：
基于所述第一频率点对应的多组电压变化值，确定所述电源网络在所述第一频率点的多个初步阻抗特性，每个初步阻抗特性对应一占空比；
将所述第一频率点对应的多个初步阻抗特性的平均值，确定为所述电源网络在所述第一频率点的阻抗特性。
上述方案中，所述基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第一频率点的阻抗特性，包括：
基于所述第一频率点对应的电压变化值，确定所述第一频率点对应的电源噪声值；
基于所述第一频率点对应的电源噪声值，确定所述电源网络在所述第一频率点处的阻抗特性。
上述方案中，基于所述第一频率点对应的电源噪声值，确定所述电源网络在所述第一频率点的阻抗特性，包括：
获取所述其它至少一个输出端接口在所述第一频率点对应的电流值；
将所述第一频率点对应的电源噪声值与所述第一频率点对应的电流值的商确定为所述第一频率点处的阻抗特性。
上述方案中，所述第一预设频率点为预设频率范围内的某一频率点；所述方法还包括：
控制所述其它至少一个输出端接口分别按照频率点集合中除所述第一频率点之外的每一剩余频率点输出所述第二电平信号；所述频率点集合包括所述预设频率范围内的多个频率点；
获取所述待测输出端输出的对应每一剩余频率点的电压变化值；
基于所述对应每一剩余频率点的电压变化值，确定所述电源网络在所 述每一剩余频率点的阻抗特性。
上述方案中，所述预设频率范围至少包括10MHz到1000MHz。
上述方案中，所述方法还包括：
基于所述电源网络在所述第一频率点的阻抗特性和所述电源网络在每一所述剩余频率点的特性阻抗，确定所述电源网络的频域特性曲线。
上述方案中，所述方法还包括：
获取对所述电源网络进行建模仿真所得到的所述电源网络的仿真频域特性曲线；
基于所述仿真频域特性曲线和所述频域特性曲线验证所述仿真频域特性曲线的准确度。
上述方案中，所述电源网络至少包括电源管理集成电路、印制电路板电源层、封装电源层以及所述功能芯片的供电端的电源处理子电路。
本公开实施例还提供一种电源网络的频域特性测量装置，所述电源网络的输出端连接功能电路的供电端；所述装置包括：
检测模块，配置为获取所述芯片的待测输出接口；
控制模块，配置为控制所述待测输出接口输出第一预设规律的第一电平信号；
所述控制模块，还配置为控制所述芯片除所述待测输出接口之外的其它至少一个输出接口按照第一频率点输出第二预设规律的第二电平信号；
所述检测模块，还配置为获取所述待测输出接口输出的所述第一频率点对应的电压变化值；
分析模块，配置为基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第一频率点的阻抗特性。
本公开实施例又提供一种电源网络的频域测量系统，包括：芯片、控制电路、检测电路及分析电路；其中，
所述芯片包括电源网络及功能电路；所述电源网络的输出端连接所述功能电路的供电端；所述电源网络用于：为所述功能电路提供电源；
所述检测电路用于：获取所述功能电路的待测输出接口；
所述控制电路分别与所述电源网络、所述检测电路连接；所述控制电路用于控制所述待测输出接口输出第一预设规律的第一电平信号；控制所述功能电路除所述待测输出接口之外的其它至少一个输出接口按照第一频率点输出第二预设规律的第二电平信号；
所述检测电路与所述功能电路的待测输出接口及所述分析电路连接；所述检测电路用于：检测所述待测输出接口输出的所述第一频率点对应的电压变化值，并将所述第一频率点对应的第一电压变化值传递给所述分析电路；
所述控制电路还用于：基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第一频率点的阻抗特性。
本公开实施例还提供一种计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现本公开实施例提供的电源网络的频域特性测量方法中的步骤。
本公开实施例中，基于芯片的真实电路，通过检测芯片的待测输出接口在一特定频率点输出的电压变化值，确定电源网络在特定频率点的阻抗特性。本公开实施例中，在特定频率点的阻抗特性是基于真实的电路测量得到的，能够比较真实的反映电源网络的频域特性。
需要强调的是，本公开中的电源网络是被封装在芯片内部的，芯片输出端口输出的电平信号由电源网络自身生成和控制，本公开的测试重点在于测试位于存储器或者其他已封装芯片内部的电源网络的频域特性。
附图说明
图1为本公开实施例提供的一种电源网络的基本的电阻/电感/电容(R/L/C)模型示意图；
图2为本公开实施例提供的一种对应电源网络各部分模型的频域阻抗曲线示意图；
图3为本公开实施例提供的通过仿真得到的一种电源网络的频域阻抗曲线示例图；
图4为本公开实施例提供的一种电源网络的频域特性测量方法的实现流程示意图；
图5为本公开实施例提供的芯片的一些输出接口与电源网络的关系示意图；
图6为本公开实施例提供的芯片的一些输出接口输出的电平信号的示意图；
图7为本公开实施例提供的电源网络在一特定频率点对应的一种电源噪声曲线示例图；
图8a为本公开实施例提供的电源网络在100MHz对应的一种电源噪声曲线示例图；
图8b为本公开实施例提供的电源网络在150MHz对应的一种电源噪声曲线示例图；
图9为本公开实施例提供的通过真实测量得到的一种电源网络的频域阻抗曲线示例图；
图10为本公开实施例提供的电源网络的频域特性测量装置的组成结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本 公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。
一些芯片包括电源网络和功能电路；其中，功能电路由电源网络进行供电，电源网络可以理解为芯片中供电部分的总和，它用于提供用电电路所需要的所有电压，一般认为一个芯片中仅有一个电源网络，因为电源网络本身就是供电通路的集合。一般电源网络通常可以包括：电源管理集成电路(PMIC)即电源供电电路、印制电路板电源层(PCB Power Planes)、封装电源层(Package Power Planes)以及功能电路的供电端的电源处理子电路，如片上电容(On-die Capacitance)。每一部分都可以抽象成最基本的R/L/C模型，从而对整个电源网络从频域特性方面进行建模。
如图1所示，芯片的电源网络被等效为：电源管理集成电路等效形成的电压基准、低通滤波器(LPF)，印制电路板电源层等效形成的大容量的电容(如电解电容)、小容量高电容(如陶瓷电容)，印制电路板各层(PCB Plane)与各过孔(Via)之间等效形成的第一电感，封装电源层中过孔与锡球(Ball)之间等效形成的第二电感、焊料凸起(Bumps)等效形成的第三电感、功能电路的供电端的的去耦电容(片上电容)。
由于寄生电感(如前述的第一电感至第三电感)的影响，电源网络的阻抗特性在高频时通常比较大，去耦电容的设置可以在一定程度上消除寄生电感的影响，然而芯片的去耦电容的电容值比较有限，通常难以去除寄生电感的影响，所以从芯片端看出去，电源网络的阻抗曲线会有一个峰值，如图2中虚线圆圈所示的电源网络谐振点(PDN Resonance)。图2中Zmax为基准阻抗，在一些具体示例中，该基准阻抗可以根据如下公式计算得到：
Figure PCTCN2022092923-appb-000001
也就是说，图2中表示的为，理论上当不存在寄生电感时，电源网络在不同的工作频率下的阻抗恒为基准阻抗；但是，当实际应用中存在寄生电感时，不同工作频率下的阻抗会发生变化，在频率较低时，大容量的电容可以去除寄生电感的影响，之后随着频率的增长高频电容可以去除寄生电感的影响(表现为阻抗在基准阻抗附近)，之后片上的去耦电容的电容值比较有限，部分频率区域不能去除寄生电感的影响(表现为在部分频率区域的阻抗比基准阻抗大)。
实际应用中，由于芯片内部的电路太过于精细，几乎没有什么仪器可以真实测量到芯片的电源网络的频域特性。相关技术中，芯片的电源网络的阻抗特性一般是通过仿真来获得的，具体地，通过仿真提取前述电源管理集成电路、印制电路板电源层、封装电源层的R/L/C模型，并结合片上电容的值，仿真得到一个电源网络的频域阻抗曲线。实际应用中，通过仿真得到的一种电源网络的频域阻抗曲线示例图如图3所示。然而，利用仿真得到的电源网络的频域阻抗曲线缺少对真实电路环境的考量，不能真实 的反映电源网络的频域特性。
为了解决上述问题，本公开实施例提供了一种电源网络的频域特性测量方法、装置、系统及存储介质。本公开的各实施例中，基于电源网络和芯片的真实电路，通过检测芯片的待测输出接口在一特定频率点输出的电压变化值，确定电源网络在特定频率点的阻抗特性。本公开的各实施例中，在特定频率点的阻抗特性是基于真实的电路测量得到的，能够比较真实的反映电源网络的频域特性。
本公开实施例提供一种电源网络的频域特性测量方法，图4为本公开实施例电源网络的频域特性测量方法的实现流程示意图。如图4所示，方法包括以下步骤：
步骤401：获取功能电路的待测输出接口；
步骤402：控制待测输出接口输出第一预设规律的第一电平信号；
步骤403：控制功能电路除待测输出接口之外的其它至少一个输出接口按照第一频率点输出第二预设规律的第二电平信号；
步骤404：获取待测输出接口输出的第一频率点对应的电压变化值；
步骤405：基于第一频率点对应的电压变化值，确定电源网络在第一频率点的阻抗特性。
实际应用中，一个芯片中设置有一个电源网络，电源网络可以理解为芯片中供电部分的总和，它用于提供功能电路所需要的所有电压。一个电源网络可以提供一种电压或多种不同的电压。例如，一个芯片的功能电路需要3.3V和1.8V两种不同的电压，则该芯片的电源网络可以提供3.3V和1.8V两种不同的电压
芯片的电源网络通常包含从电源供电电路到功能电路的电源输入端的整个通路。在一些实施例中，电源网络至少包括电源管理集成电路、印制电路板电源层、封装电源层以及功能电路的供电端电源处理子电路。这里，功能电路的供电端的电源处理子电路可以包括芯片中设置在功能电路供电端的片上电容等。
这里，芯片可以包含电源网络和功能电路，电源网络的输出端连接功能电路的供电端。在一些具体示例中，芯片可以包括动态随机存取器。
本公开实施例是根据芯片内部电源网络及输出接口的特性，提出的一种测试芯片电源网络的频域特性的方法。
其中，在步骤401中，芯片的功能电路可以包括多个输出接口。实际应用中，输出接口可以是芯片的输入/输出(I/O，Input/Output)管脚，或者与芯片的输入/输出管脚连接的测试焊点。通常情况下，电源网络会给芯片的多个I/O管脚同时供电。
图5为本公开实施例提供的芯片的一些输出接口与电源网络的关系示意图如图5所示，I/O管脚在有信号输出的时候会耗电，从电源网络抽取电流。
这里，待测输出接口包括多个输出接口中由电源网络供电的任意一个输出接口。
实际应用中，获取功能电路的待测输出接口的方式为接收信息，该接收的信息指示随机选择任一个输出接口(该电源网络供电的任一编号的I/O管脚)作为待测输出接口，或者指定选择某一个输出接口(该电源网络供电的特定编号的I/O管脚)作为待测输出接口。
在步骤402中，控制的对象为前述的待测输出接口。
这里，第一预设规律可以包括恒定生成某一电平信号。在一些实施例中，第一预设规律的第一电平信号表示信号值恒为第一电平的电平信号。在一些实施例中，第一电平对应的电压与电源网络向功能电路提供的电压基本相同，即高电平。
也就是说，实际应用中，可以在同一个电源网络供电的N个I/O管脚中，选择任一个I/O管脚作为待测输出接口，并控制该I/O管脚一直输出高电平(“1”)。此时，可以将该I/O管脚看作与电源网络短路，从而该I/O管脚一直输出电源网络向功能电路提供的电压。
这里，基本相同可以理解为二者存在微小的差异，该微小的差异可以是线路带来的微小压降或者测量误差等。
在步骤403中，控制的对象为芯片除待测输出接口之外的其它至少一个输出接口，该至少一个输出接口与待测输出接口均由电源网络提供电源。需要说明的是，其它至少一个输出接口可以包括多个，并且随着数量的增大，特定I/O管脚频谱赋值越高，电源的噪声现象越明显。实际应用中，可以在同一个电源网络供电的N个I/O管脚中，除已选作待测输出接口的其余N-1个I/O管脚作为步骤403的控制的对象。
在一些实施例中，第二预设规律的第二电平信号表示第一电平和第二电平按照预设占空比所形成的电平信号；在另一些实施例中，第二预设规律包括随机生成电平信号，随机生成的电平为第一电平或第二电平。其中，第一电平大于第二电平，第一电平为高电平，第二电平为低电平；此外，上述“预设占空比”可以为固定值或随机值。
在一些实施例中，预设占空比为50％。例如，输出“010101…”变化的时钟信号。
在另一些实施例中，预设占空比可以是其它稳定的值。例如，输出“001001001…”、“000100010001…”变化的时钟信号。
需要说明的是，本公开实施例中只要是具有稳定占空比的均可，但是预设占空比为50％时，计算更方便简洁，电源的噪声现象体现更明显。实际应用中，可以采用多种不同占空比和幅值的时钟信号分别进行测试，该方案在后文中将会详细描述。
这里，第一频率点为一个固定的频率值。实际应用中，可以根据时钟脉冲(CP，Clock Pulse)的频率调整第二电平信号的输出频率从而实现频 率的调整。
实际应用中，可以利用能够实现芯片管脚控制功能的控制电路来实现步骤402、403中的控制，这里的控制电路包括但不限于现场可编程逻辑阵列(FPGA，Field Programmable Gate Array)测试开发板。
在步骤404中，测量待测输出接口的在一段时长内的输出值即电压变化值，从而测定该待测输出接口受其他输出接口的影响情况。
可以理解的是，当控制待测输出接口一直输出高电平时，若不考虑其它输出接口的影响，待测输出接口的在一段时长内的输出值即接近电源网络向芯片提供的电压。当此时同时控制其它至少一个输出接口输出高电平、低电平交替切换变化的时钟信号时，在电源网络上也会产生与高电平、低电平交替切换同频率的电源噪声，并且由于待测输出接口的输出信号持续为高电平(“1”)，待测输出接口到电源的通路此时是短路状态，因此，电源噪声的变化可以通过待测输出接口量测到。
实际应用中，可以利用示波器或频谱分析仪等获取待测输出接口输出的第一频率点对应的电压变化值。
在步骤405中：可以通过第一频率点对应的电压变化值，确定电源网络在第一频率点的阻抗特性。
在一些实施例中，基于第一频率点对应的电压变化值，确定电源网络在第一频率点的阻抗特性，包括：
基于第一频率点对应的电压变化值，确定第一频率点对应的电源噪声值；
基于第一频率点对应的电源噪声值，确定电源网络在第一频率点处的阻抗特性。
这里，电源噪声值可以是第一频率点对应的电压变化值中当前电压值与当前期望电压值的差值的最大值，当前期望电压值随着电平变化而变化，此外，期望电压值可以认为是对应电平的最大电压值；或者是，最大电压值与最小电压值之间的差值。
在一些实施例中，基于第一频率点对应的电源噪声值，确定电源网络在第一频率点的阻抗特性，包括：
获取其它至少一个输出端接口在第一频率点对应的电流值；
将第一频率点对应的电源噪声值与第一频率点对应的电流值的商确定为第一频率点处的阻抗特性。
这里，电流值是指电源网络提供给芯片除待测输出接口之外的其它至少一个输出接口(N-1个I/O管脚)的工作电流，电流值为N-1个I/O管脚的输出电流的总和。需要说明的是，电流值并不是一个定值，而是和输出电平有关，例如输出低电平时抽取的电流值较小，输出高电平时抽取的电流值较大。
实际应用中，电流值可以通过测量N-1个I/O管脚的负载上的电流来获 取。具体测量电流的方式可以是通过测量负载两端的电压和电阻来测量电流。
这里，获得了电源网络在第一频率点的阻抗特性。
实际应用中，电源网络在第一频率点的阻抗特性可以反映电源网络的至少部分频域特性。
实际应用中，第二电平信号可以为多种不同占空比的时钟信号，从而可以针对每种不同的占空比分别进行测试。
在一些实施例中，预设占空比包括多个占空比；
获取待测输出接口输出的第一频率点对应的电压变化值，包括：
获取待测输出接口输出的第一频率点对应的多组电压变化值；多组电压变化值分别对应多个不同的占空比；
基于第一频率点对应的电压变化值，确定电源网络在第一频率点的阻抗特性，包括：
基于第一频率点对应的多组电压变化值，确定电源网络在第一频率点的多个初步阻抗特性，每个初步阻抗特性对应一占空比；
将第一频率点对应的多个初步阻抗特性的平均值，确定为电源网络在第一频率点的阻抗特性。
这里，针对每一种占空比的情况的测试均与前述的占空比为50％时对应的阻抗特性确定方法是相同的。实际应用中，对于得到的电源网络在第一频率点的多个初步阻抗特性，可以通过求平均值或者其他方式，来确定为电源网络在第一频率点的阻抗特性。
实际应用中，芯片的输出频率范围较宽，可以根据前述获取电源网络在第一频率点的阻抗特性的方式，获得电源网络在输出频率范围中其它频率点的阻抗特性。
在一些实施例中，第一预设频率点为预设频率范围内的某一频率点；方法还包括：
控制其它至少一个输出接口分别按照频率点集合中除第一频率点之外的每一剩余频率点输出第二电平信号；频率点集合包括预设频率范围内的多个频率点；
获取待测输出端输出的对应每一剩余频率点的电压变化值；
基于对应每一剩余频率点的电压变化值，确定电源网络在每一剩余频率点的阻抗特性。
这里，针对频率点集合中除第一频率点之外的每一剩余频率点均与前述的第一频率点时对应的阻抗特性确定方法是相同的。实际应用中，芯片的一般输出频率范围为50MHz～200MHz，预设范围可以取一个覆盖该输出频率范围的范围。在一些实施例中，预设频率范围至少包括10MHz到1000MHz。
在一些实施例中，方法还包括：
基于电源网络在第一频率点的阻抗特性和电源网络在每一剩余频率点的特性阻抗，确定电源网络的频域特性曲线。
这里，在获取电源网络在第一频率点的阻抗特性和电源网络在每一剩余频率点的特性阻抗后，可以第一频率点和每一剩余频率点对应的特性阻抗描绘出电源网络的频域特性曲线。可以理解的是，当获取的每一剩余频率点的数量越多时，描绘出的电源网络的频域特性曲线越精确、越平滑。
实际应用中，在获取到电源网络的频域特性曲线后，可以将该测量得到的电源网络的频域特性曲线与通过建模仿真所得到的电源网络的仿真频域特性曲线进行比较，以评估仿真频域特性曲线的准确性。
在一些实施例中，方法还包括：
获取对电源网络进行建模仿真所得到的电源网络的仿真频域特性曲线；
基于仿真频域特性曲线和频域特性曲线验证仿真频域特性曲线的准确度。
实际应用中，还可以利用测量得到的电源网络的频域特性曲线指导电源网络的模型修正。
本公开实施例中，基于芯片的真实电路，通过检测芯片的待测输出接口在一特定频率点输出的电压变化值，确定电源网络在特定频率点的阻抗特性。本公开实施例中，在特定频率点的阻抗特性是基于真实的电路测量得到的，能够比较真实的反映电源网络的频域特性。
下面结合应用实施例对本公开再作进一步详细的描述。
为了测试电源网络的频域阻抗特性，本公开实施例通过一个特定的I/O组合方法来实现，具体地：
步骤1：在同一个电源网络供电的N个I/O管脚中，选择任一个I/O管脚(相当于前述的待测输出接口)，一直输出高电平，即输出“111111…”的时钟信号(相当于前述的第一电平信号)。
步骤2：在同一个电源网络供电的N个I/O管脚中，除已选的一个I/O管脚将其余N-1个管脚(相当于前述的芯片除待测输出接口之外的其它至少一个输出接口)，按照一个固定的频率同时输出“010101…”变化的时钟信号(相当于前述的第二电平信号)。
这里，步骤1和步骤2中I/O管脚输出信号的示意图如图6所示。需要说明的是图6中示出的I/O管脚的数量并不代表实际采用的数量，N值可以根据实际情况进行调整。
步骤3：用示波器或频谱分析仪测试步骤1中所选择的I/O管脚输出的高电平的信号，以计算此时的电源噪声值。
可以理解的是，上述步骤2中N-1个I/O管脚同时进行“010101…”的切换时，在电源网络上也会产生与信号切换同频率的电源噪声。上述步骤1中所选取的I/O管脚，其输出信号持续为“1”，信号输出管脚到电源网络的 通路此时是短路状态，因此电源噪声的变化可以通过信号输出量测到。
图7为本公开实施例提供的电源网络在一特定频率点对应的一种电源噪声曲线示例图。图7中上半部分的波形图为N-1个I/O管脚输出的“010101…”的切换信号；图7中下半部分的波形图为电源噪声的波形图，从图7中可以得到在该具体示例中，电源噪声值为105mV。
步骤4：重复步骤2、步骤3，在每一次重复中切换步骤2的频率，切换的频率范围可以从10MHz到1000MHz中选取。
步骤5：记录不同频点的电源噪声值，并将电源噪声值除以N-1个I/O管脚切换所需消耗的电流，即可得到这个电源网络在不同频点的阻抗特性。
可以理解的是，每次重复步骤2，3切换不同频率的‘010101…’信号，也就得到了不同频点的电源噪声值；而电源噪声值等于N-1个I/O管脚的输出电流乘以电源网络在每一频率下的阻抗值。通过测量上述步骤1中所选取的I/O管脚的输出，就可以得到不同频点的电源噪声值。
图8a为本公开实施例提供的电源网络在100MHz对应的一种电源噪声曲线示例图；图8b为本公开实施例提供的电源网络在150MHz对应的一种电源噪声曲线示例图。
需要说明的是，图8a、图8b中每一幅图的频率都有跨度，是因为即便输入的频率是特定的，但因为器件间的相互作用，会产生其他的频段及对应的噪声，但依旧是输入频率的噪声值最大。
图9为本公开实施例提供的通过真实测量得到的一种电源网络的频域阻抗曲线示例图。通过这种方法，可以准确地测量到电源网络的频域特性，与仿真结果进行验证。
需要说明的是，本公开实施例可以应用于需要进行频域特性测试的各类芯片。在一些具体实施例中，可以应用于动态随机存取内存，如同步动态随机存取内存SDRAM的、双倍速率的同步动态随机存取内存DDR的测试验证。实际应用中，可以利用FPGA内存测试开发板，对动态随机存取内存内部产生SSN(同步开关噪声)的频点进行验证测试。
为了实现本公开实施例的方法，本公开实施例还提供一种电源网络的频域特性测量装置1000，图10为本公开实施例装置的结构示图，如图10所示，装置1000包括：检测模块1001、控制模块1002以及分析模块1003；其中，
检测模块1001，配置为获取功能电路的待测输出接口；
控制模块1002，配置为控制待测输出接口输出第一预设规律的第一电平信号；
控制模块1002，还配置为控制功能电路除待测输出接口之外的其它至少一个输出接口按照第一频率点输出第二预设规律的第二电平信号；
检测模块1001，还配置为获取待测输出接口输出的第一频率点对应的电压变化值；
分析模块1003，配置为基于第一频率点对应的电压变化值，确定电源网络在第一频率点的阻抗特性。
这里，电源网络的输出端连接功能电路的供电端。
其中，在一些实施例中，第一预设规律的第一电平信号表示信号值恒为第一电平的电平信号；
第二预设规律的第二电平信号表示信号值为第一电平和第二电平按照预设占空比所形成的电平信号；
第一电平大于第二电平。
在一些实施例中，第一电平对应的电压与电源网络向功能电路提供的电压基本相同。
在一些实施例中，预设占空比为50％。
在一些实施例中，预设占空比包括多个占空比；
检测模块1001，具体配置为获取待测输出接口输出的第一频率点对应的多组电压变化值；多组电压变化值分别对应多个不同的占空比；
分析模块1003，具体配置为基于第一频率点对应的多组电压变化值，确定电源网络在第一频率点的多个初步阻抗特性，每个初步阻抗特性对应一占空比；将第一频率点对应的多个初步阻抗特性的平均值，确定为电源网络在第一频率点的阻抗特性。
在一些实施例中，分析模块1003，具体配置为基于第一频率点对应的电压变化值，确定第一频率点对应的电源噪声值；基于第一频率点对应的电源噪声值，确定电源网络在第一频率点处的阻抗特性。
在一些实施例中，分析模块1003，具体配置为获取其它至少一个输出端接口在第一频率点对应的电流值；将第一频率点对应的电源噪声值与第一频率点对应的电流值的商确定为第一频率点处的阻抗特性。
在一些实施例中，第一预设频率点为预设频率范围内的某一频率点；
控制模块1002，还配置为控制其它至少一个输出端接口分别按照频率点集合中除第一频率点之外的每一剩余频率点输出第二电平信号；频率点集合包括预设频率范围内的多个频率点；
检测模块1001，还配置为获取待测输出端输出的对应每一剩余频率点的电压变化值；
分析模块1003，还配置为基于对应每一剩余频率点的电压变化值，确定电源网络在每一剩余频率点的阻抗特性。
在一些实施例中，预设频率范围至少包括10MHz到1000MHz。
在一些实施例中，分析模块1003，还配置为基于电源网络在第一频率点的阻抗特性和电源网络在每一剩余频率点的特性阻抗，确定电源网络的频域特性曲线。
在一些实施例中，检测模块1001，配置为获取对电源网络进行建模仿真所得到的电源网络的仿真频域特性曲线；
装置1000还包括：
验证模块，配置为基于仿真频域特性曲线和频域特性曲线验证仿真频域特性曲线的准确度。
在一些实施例中，电源网络至少包括电源管理集成电路、印制电路板电源层、封装电源层以及功能电路的供电端的电源处理子电路。
实际应用时，检测模块1001、控制模块1002、分析模块1003及验证模块由电源网络的频域特性测量装置1000中的处理器实现。
需要说明的是：上述实施例提供的电源网络的频域特性测量方法在进行频域特性测量时，仅以上述各程序模块的划分进行举例说明，实际应用中，可以根据需要而将上述处理分配由不同的程序模块完成，即将装置的内部结构划分成不同的程序模块，以完成以上描述的全部或者部分处理。另外，上述实施例提供的电源网络的频域特性测量装置与电源网络的频域特性测量方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
为了实现本公开实施例的方法，本公开实施例还提供一种电源网络的频域测量系统，其特征在于，包括：芯片、控制电路、检测电路及分析电路；
芯片包括电源网络及功能电路；电源网络的输出端连接功能电路的供电端；电源网络用于：为功能电路提供电源；
检测电路用于：获取功能电路的待测输出接口；
控制电路分别与电源网络、检测电路连接；控制电路用于：控制待测输出接口输出第一预设规律的第一电平信号；控制芯片除待测输出接口之外的其它至少一个输出接口按照第一频率点输出第二预设规律的第二电平信号；待测输出接口与至少一个输出接口均由电源网络提供电源；
检测电路与芯片的待测输出接口及分析电路连接；检测电路用于：检测待测输出接口输出的第一频率点对应的电压变化值，并将第一频率点对应的第一电压变化值传递给分析电路；
分析电路用于：基于第一频率点对应的电压变化值，确定电源网络在第一频率点的阻抗特性。
这里，控制电路可以包括能够实现芯片管脚控制功能的器件及器件外围。控制电路包括但不限于FPGA、数字信号处理(DSP，Digital Signal Processing)微控制单元(MCU，Microcontroller Unit)等。
检测电路可以包括自行搭建的测试电路，也可以包括示波器或频谱分析仪等已有的测量设备。
需要说明的是：上述实施例提供的电源网络的频域特性测量系统与电源网络的频域特性测量方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
本公开实施例还提供一种存储介质，其上存储有计算机程序，该计算 机程序被处理器执行时实现本公开实施例提供的电源网络的频域特性测量方法中的步骤。
在一些实施例中，存储介质可以是磁性随机存取存储器(FRAM，Ferromagnetic Random Access Memory)、只读存储器(ROM，Read Only Memory)、可编程只读存储器(PROM，Programmable Read-Only Memory)、可擦除可编程只读存储器(EPROM，Erasable Programmable Read-Only Memory)、电可擦除可编程只读存储器(EEPROM，Electrically Erasable Programmable Read-Only Memory)、快闪存储器(Flash Memory)、磁表面存储器、光盘、或只读光盘(CD-ROM，Compact Disc Read-Only Memory)等存储器；也可以是包括上述存储器之一或任意组合的各种设备。
在一些实施例中，可执行指令可以采用程序、软件、软件模块、脚本或代码的形式，按任意形式的编程语言(包括编译或解释语言，或者声明性或过程性语言)来编写，并且其可按任意形式部署，包括被部署为独立的程序或者被部署为模块、组件、子例程或者适合在计算环境中使用的其它单元。
作为示例，可执行指令可以但不一定对应于文件系统中的文件，可以可被存储在保存其它程序或数据的文件的一部分，例如，存储在超文本标记语言(HTML，Hyper Text Markup Language)文档中的一个或多个脚本中，存储在专用于所讨论的程序的单个文件中，或者，存储在多个协同文件(例如，存储一个或多个模块、子程序或代码部分的文件)中。
作为示例，可执行指令可被部署为在一个计算设备上执行，或者在位于一个地点的多个计算设备上执行，又或者，在分布在多个地点且通过通信网络互连的多个计算设备上执行。
需要说明的是：“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
另外，本公开实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
工业实用性
本公开实施例中，基于芯片的真实电路，通过检测芯片的待测输出接口在一特定频率点输出的电压变化值，确定电源网络在特定频率点的阻抗特性。本公开实施例中，在特定频率点的阻抗特性是基于真实的电路测量得到的，能够比较真实的反映电源网络的频域特性。需要强调的是，本公开中的电源网络是被封装在芯片内部的，芯片输出端口输出的电平信号由电源网络自身生成和控制，本公开的测试重点在于测试位于存储器或者其他已封装芯片内部的电源网络的频域特性。

Claims (15)

  1. 一种电源网络的频域特性测量方法，所述电源网络的输出端连接功能电路的供电端；所述方法包括：
    获取所述功能电路的待测输出接口；
    控制所述待测输出接口输出第一预设规律的第一电平信号；
    控制所述功能电路除所述待测输出接口之外的其它至少一个输出接口按照第一频率点输出第二预设规律的第二电平信号；
    获取所述待测输出接口输出的所述第一频率点对应的电压变化值；
    基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第一频率点的阻抗特性。
  2. 根据权利要求1所述的方法，其中，所述第一预设规律的第一电平信号表示信号值恒为第一电平的电平信号；
    所述第二预设规律的第二电平信号表示信号值为所述第一电平和第二电平按照预设占空比所形成的电平信号；
    所述第一电平大于所述第二电平。
  3. 根据权利要求2所述的方法，其中，所述第一电平对应的电压与所述电源网络向所述功能电路提供的电压基本相同。
  4. 根据权利要求2所述的方法，其中，所述预设占空比为50％。
  5. 根据权利要求2所述的方法，其中，所述预设占空比包括多个占空比；
    所述获取所述待测输出接口输出的所述第一频率点对应的电压变化值，包括：
    获取所述待测输出接口输出的所述第一频率点对应的多组电压变化值；所述多组电压变化值分别对应所述多个不同的占空比；
    所述基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第一频率点的阻抗特性，包括：
    基于所述第一频率点对应的多组电压变化值，确定所述电源网络在所述第一频率点的多个初步阻抗特性，每个初步阻抗特性对应一占空比；
    将所述第一频率点对应的多个初步阻抗特性的平均值，确定为所述电源网络在所述第一频率点的阻抗特性。
  6. 根据权利要求1所述的方法，其中，所述基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第一频率点的阻抗特性，包括：
    基于所述第一频率点对应的电压变化值，确定所述第一频率点对应的电源噪声值；
    基于所述第一频率点对应的电源噪声值，确定所述电源网络在所述第一频率点处的阻抗特性。
  7. 根据权利要求6所述的方法，其中，基于所述第一频率点对应的电 源噪声值，确定所述电源网络在所述第一频率点的阻抗特性，包括：
    获取所述其它至少一个输出端接口在所述第一频率点对应的电流值；
    将所述第一频率点对应的电源噪声值与所述第一频率点对应的电流值的商确定为所述第一频率点处的阻抗特性。
  8. 根据权利要求1所述的方法，其中，所述第一预设频率点为预设频率范围内的某一频率点；所述方法还包括：
    控制所述其它至少一个输出接口分别按照频率点集合中除所述第一频率点之外的每一剩余频率点输出所述第二电平信号；所述频率点集合包括所述预设频率范围内的多个频率点；
    获取所述待测输出端输出的对应每一剩余频率点的电压变化值；
    基于所述对应每一剩余频率点的电压变化值，确定所述电源网络在所述每一剩余频率点的阻抗特性。
  9. 根据权利要求8所述的方法，其中，所述预设频率范围至少包括10MHz到1000MHz。
  10. 根据权利要求8所述的方法，其中，所述方法还包括：
    基于所述电源网络在所述第一频率点的阻抗特性和所述电源网络在每一所述剩余频率点的特性阻抗，确定所述电源网络的频域特性曲线。
  11. 根据权利要求10所述的方法，其中，所述方法还包括：
    获取对所述电源网络进行建模仿真所得到的所述电源网络的仿真频域特性曲线；
    基于所述仿真频域特性曲线和所述频域特性曲线验证所述仿真频域特性曲线的准确度。
  12. 根据权利要求1所述的方法，其中，所述电源网络至少包括电源管理集成电路、印制电路板电源层、封装电源层以及所述功能电路的供电端的电源处理子电路。
  13. 一种电源网络的频域特性测量装置，所述电源网络的输出端连接功能电路的供电端；所述装置包括：
    检测模块，配置为获取所述功能电路的待测输出接口；
    控制模块，配置为控制所述待测输出接口输出第一预设规律的第一电平信号；
    所述控制模块，还配置为控制所述功能电路除所述待测输出接口之外的其它至少一个输出接口按照第一频率点输出第二预设规律的第二电平信号；
    所述检测模块，还配置为获取所述待测输出接口输出的所述第一频率点对应的电压变化值；
    分析模块，配置为基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第一频率点的阻抗特性。
  14. 一种电源网络的频域测量系统，包括：芯片、控制电路、检测电 路及分析电路；其中，
    所述芯片包括电源网络及功能电路；所述电源网络的输出端连接功能电路的供电端；所述电源网络用于：为所述功能电路提供电源；
    所述检测电路用于：获取所述功能电路的待测输出接口；
    所述控制电路分别与所述电源网络、所述检测电路连接；所述控制电路用于：控制所述待测输出接口输出第一预设规律的第一电平信号；控制所述功能电路除所述待测输出接口之外的其它至少一个输出接口按照第一频率点输出第二预设规律的第二电平信号；
    所述检测电路与所述功能电路的待测输出接口及所述分析电路连接；所述检测电路用于：检测所述待测输出接口输出的所述第一频率点对应的电压变化值，并将所述第一频率点对应的第一电压变化值传递给所述分析电路；
    所述分析电路用于：基于所述第一频率点对应的电压变化值，确定所述电源网络在所述第一频率点的阻抗特性。
  15. 一种计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现权利要求1至12任一项所述的电源网络的频域特性测量方法中的步骤。
PCT/CN2022/092923 2022-04-22 2022-05-16 频域特性测量方法、装置、系统及存储介质 WO2023201797A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/164,095 US20230341447A1 (en) 2022-04-22 2023-02-03 Method, device and system for measuring frequency domain characteristics, and storage medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210431068.X 2022-04-22
CN202210431068.XA CN116973798A (zh) 2022-04-22 2022-04-22 频域特性测量方法、装置、系统及存储介质

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/164,095 Continuation US20230341447A1 (en) 2022-04-22 2023-02-03 Method, device and system for measuring frequency domain characteristics, and storage medium

Publications (1)

Publication Number Publication Date
WO2023201797A1 true WO2023201797A1 (zh) 2023-10-26

Family

ID=88418983

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/092923 WO2023201797A1 (zh) 2022-04-22 2022-05-16 频域特性测量方法、装置、系统及存储介质

Country Status (2)

Country Link
CN (1) CN116973798A (zh)
WO (1) WO2023201797A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101788604A (zh) * 2010-01-19 2010-07-28 河北省电力研究院 一种基于频域分析和序分量分析的电功率及电量测量方法
CN106093567A (zh) * 2016-06-01 2016-11-09 深圳先进技术研究院 一种高精度宽频域频率测量系统及频率测量方法
US10922940B1 (en) * 2018-12-05 2021-02-16 Amazon Technologies, Inc. Battery-powered radio frequency motion detector

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101788604A (zh) * 2010-01-19 2010-07-28 河北省电力研究院 一种基于频域分析和序分量分析的电功率及电量测量方法
CN106093567A (zh) * 2016-06-01 2016-11-09 深圳先进技术研究院 一种高精度宽频域频率测量系统及频率测量方法
US10922940B1 (en) * 2018-12-05 2021-02-16 Amazon Technologies, Inc. Battery-powered radio frequency motion detector

Also Published As

Publication number Publication date
CN116973798A (zh) 2023-10-31

Similar Documents

Publication Publication Date Title
US8521500B2 (en) Method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models
US20060195744A1 (en) Method and apparatus to simulate automatic test equipment
CN113157501B (zh) 一种基于ate测试机的微系统模块ac参数测试方法
CN113014339A (zh) PCIe外插卡接收通道的质量测试方法、装置及设备
TW200406587A (en) System and method of measuring low impedances
WO2023201797A1 (zh) 频域特性测量方法、装置、系统及存储介质
CN108897929B (zh) 一种电源平面频域阻抗仿真方法、系统及终端
CN111209654B (zh) 一种电源传输网络pdn频率阻抗测试系统及方法
US20230341447A1 (en) Method, device and system for measuring frequency domain characteristics, and storage medium
CN115906732A (zh) 建立场景化cpm模型的方法、装置和机器可读存储介质
CN115389923A (zh) 功率开关电路寄生参数测试方法、系统、电子设备及介质
Evans et al. Modeling and measurement of a high-performance computer power distribution system
Song et al. Optimal power distribution network design for high-performance solid-state-drive based on novel target-impedance extraction method
Stievano et al. Behavioral modeling of IC memories from measured data
Garben et al. Mid-frequency delta-I noise analysis of complex computer system boards with multiprocessor modules and verification by measurements
Cunha et al. Validation by measurements of an IC modeling approach for SiP applications
Hong et al. Extracting High Speed Refresh Current for DDR5 Module based on Network Parameter Theory
Su et al. DDR Debug Methodology for Board Design Quality and System Robustness
Määttä Verifying PDN in Time and in Frequency Domain
Chand et al. Power Delivery Measurement Correlation for Mixed Reality Rigid Flex Systems
WO2022262513A1 (zh) 检测输入信号对输出信号影响的方法、装置、设备和介质
Wu et al. Investigations on immunity of interfaces between intelligent media processor and DDR3 SDRAM memory
JP7125208B2 (ja) ノイズ解析装置及びノイズ解析方法
Chang et al. Board Level Probe-on-Pin Power Delivery Network Characterization
Luo et al. Calculation of the Worst-Case Voltage Noise for a Power Distribution Network Based on Ramp Current

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22938032

Country of ref document: EP

Kind code of ref document: A1