WO2023193441A1 - 多核电路、数据交换方法、电子设备及存储介质 - Google Patents

多核电路、数据交换方法、电子设备及存储介质 Download PDF

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WO2023193441A1
WO2023193441A1 PCT/CN2022/132418 CN2022132418W WO2023193441A1 WO 2023193441 A1 WO2023193441 A1 WO 2023193441A1 CN 2022132418 W CN2022132418 W CN 2022132418W WO 2023193441 A1 WO2023193441 A1 WO 2023193441A1
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data
computing core
status
queue
core
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PCT/CN2022/132418
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English (en)
French (fr)
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李贵鹏
贾磊
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北京百度网讯科技有限公司
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Publication of WO2023193441A1 publication Critical patent/WO2023193441A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/54—Indexing scheme relating to G06F9/54
    • G06F2209/548—Queue

Definitions

  • the present disclosure relates to the field of communication technology and the field of multi-core communication, for example, to a multi-core circuit, a data exchange method, an electronic device and a storage medium.
  • chips In order to speed up information processing, chips generally integrate multiple Central Processing Unit (CPU) cores, referred to as multi-cores. When processing data, multiple cores work at the same time, and when both parties need to exchange data, Inter-Process Communication (IPC) technology will be used.
  • CPU Central Processing Unit
  • IPC Inter-Process Communication
  • IPC is essentially a synchronization technology. Synchronization technology has a greater impact on the efficiency of multi-core communication, and different synchronization strategies have different impacts on hardware design.
  • chip design implements IPC, it mainly uses hardware to add centralized or distributed synchronization units to implement read-write locks and memory barriers. Although this method reduces the complexity of software design during IPC communication, it increases the complexity and cost of hardware.
  • the present disclosure provides a multi-core circuit, a data exchange method, an electronic device and a storage medium.
  • a multi-core circuit including:
  • each computing core is configured to: when the data exchange conditions are met, write the first data into the common storage area, and trigger the operation of the multiple computing cores except for each computing core.
  • the interrupt register corresponding to the computing core generates an interrupt signal; or, in the case where the interrupt register corresponding to each computing core generates an interrupt signal, read and write data in the common storage area recorded in the status register corresponding to each computing core. status, reading the second data written by the computing cores other than each computing core among the plurality of computing cores from the common storage area.
  • a data exchange method is provided, which is performed by a writing side computing core in a multi-core circuit, including:
  • the interrupt signal is used to instruct the reading computing core to obtain the data read and write status of the public storage area recorded in the corresponding status register, and read from the public storage area according to the data read and write status. the first data.
  • another data exchange method is provided, performed by a reader computing core in a multi-core circuit, including:
  • the interrupt register corresponding to the reading side computing core When the interrupt register corresponding to the reading side computing core generates an interrupt signal, obtain the data read and write status of the public storage area recorded in the status register corresponding to the reading side computing core; wherein the interrupt signal is a write When the input computing core meets the data exchange conditions, it writes the first data into the common storage area and triggers the interrupt register corresponding to the reading computing core;
  • the second data written by the writing side computing core is read from the public storage area.
  • a data exchange device including:
  • the first data writing module is configured to write the first data into the public storage area when the data exchange conditions are met;
  • the interrupt signal trigger module is configured to trigger the interrupt register corresponding to the reading side computing core to generate an interrupt signal
  • the interrupt signal is used to instruct the reading computing core to obtain the data read and write status of the public storage area recorded in the corresponding status register, and read from the public storage area according to the data read and write status. the first data.
  • a data exchange device including:
  • the data reading and writing status acquisition module is configured to acquire the data reading and writing status of the public storage area recorded in the status register corresponding to the reading side computing core when the interrupt register corresponding to the reading side computing core generates an interrupt signal; Wherein, the interrupt signal is generated by the writing side computing core triggering the interrupt register corresponding to the reading side computing core after writing the first data into the common storage area when the data exchange conditions are met;
  • the second data reading module is configured to read the second data written by the writing computing core from the public storage area according to the acquired data reading and writing status.
  • an electronic device including: the multi-core circuit according to any embodiment of the disclosure.
  • a memory communicatively connected to at least one computing core in the multi-core circuit; wherein,
  • the memory stores instructions that can be executed by the computing core, and the instructions are executed by the at least one computing core, so that the at least one computing core can perform the above-mentioned data exchange method.
  • a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to perform the above-mentioned data exchange method.
  • Figure 1 is a schematic diagram of a multi-core circuit provided by an embodiment of the present disclosure
  • Figure 2A is a flow chart of a data exchange method provided by an embodiment of the present disclosure
  • Figure 2B is a flow chart of another data exchange method provided by an embodiment of the present disclosure.
  • Figure 3A is a flow chart of another data exchange method provided by an embodiment of the present disclosure.
  • Figure 3B is a flow chart of another data exchange method provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of a processing function model provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of data exchange of a dual-core digital signal processing chip provided by an embodiment of the present disclosure
  • Figure 6 is a schematic diagram of the data processing process of a computing core 0 provided by an embodiment of the present disclosure
  • Figure 7 is a schematic diagram of the data processing process of a computing core 1 provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of the distribution results of a message structure in a ring queue provided by an embodiment of the present disclosure
  • Figure 9 is a schematic diagram of a data exchange device provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of another data exchange device provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic diagram of another data exchange device provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic diagram of another data exchange device provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic block diagram of an electronic device implementing a data exchange method provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a multi-core circuit provided by an embodiment of the present disclosure.
  • the multi-core circuit includes: a common storage area 110; multiple interrupt registers 120; multiple status registers 130; and There are multiple computing cores 140, each computing core 140 is configured to: when the data exchange conditions are met, write the first data into the common storage area 110, and trigger the corresponding interrupt registers 120 of other computing cores 140 to generate interrupt signals; Or, when the interrupt register 120 corresponding to the computing core 140 generates an interrupt signal, other calculations are read from the common storage area 110 according to the data read and write status of the common storage area 110 recorded in the status register 130 corresponding to the computing core 140. The second data written by core 140.
  • the multiple computing cores 140 may be of different types.
  • the computing core 140 may include an Advanced Reduced Instruction Set Computing Machine (ARM) core and a Digital Signal Processing (DSP) core.
  • Data exchange conditions can be used to indicate that there are new messages between multiple computing cores 140 that require interaction between multiple computing cores.
  • the first data may be data written by the computing core 140 itself into the public storage area 110 for other computing cores 140 to read.
  • the second data may be data that the computing core 140 that wrote the first data needs to read and that is written to the common storage area 110 by other computing cores 140 .
  • the common storage area 110 may be a data storage area shared by multiple computing cores 140 in a multi-core circuit, and is configured to realize data sharing among multiple cores.
  • the data read and write status can be used to characterize the data reading and data writing of the common storage area 110 by the computing core 140 .
  • each computing core 140 can serve as either a data writer or a data reader.
  • new messages need to be transmitted between multiple computing cores 140 (that is, data exchange conditions are met)
  • the current computing core If the current computing core writes the first data into the public storage area 110 as the data writer, the current computing core needs to configure the interrupt register 120 of the computing core (for example, computing core A) as the data reader, by triggering the The interrupt register 120 generates an interrupt signal to control the computing core A to perform the operation of reading the first data from the common storage area 110, thereby achieving the effect of exchanging the first data from the current computing core to the computing core A.
  • the current computing core serves as the data reader, after the current computing core is triggered based on the interrupt signal generated by the interrupt register 120, for example, the interrupt signal is triggered by the computing core B, it can be based on the status register corresponding to the current computing core.
  • the data reading and writing status of the common storage area 110 recorded in 130 is to read the second data written by the computing core B before triggering the generation of the interrupt signal from the common storage area 110 .
  • multiple computing cores 140 have a one-to-one correspondence with multiple interrupt registers 120 .
  • one computing core 140 corresponds to multiple status registers 130 .
  • the interrupt register 120 which corresponds one-to-one with the computing core (for example, computing core 1), can be configured by other computing cores (for example, computing core 2) to trigger the computing core 1 to perform the corresponding data reading operation; at the same time, with each A plurality of status registers 130 corresponding to each computing core are configured to store the data reading status and data writing status of the common storage area 110 of the computing core.
  • the technical solution of the embodiment of the present disclosure uses a common storage area, multiple interrupt registers, multiple status registers, and multiple computing cores to form a multi-core circuit, and then writes the first data to the common storage when the data exchange conditions are met. area, and trigger the interrupt register corresponding to other computing cores to generate an interrupt signal; or, when the interrupt register corresponding to the computing core generates an interrupt signal, the data read and write status of the public storage area recorded in the status register corresponding to the computing core , reading the second data written by other computing cores from the public storage area, without building a complex centralized or distributed synchronization unit, only by configuring a simple interrupt register and status register, complex data synchronization technology can be realized, reducing It reduces the complexity of hardware design, reduces the calculation delay of the chip, and ensures the improvement of the overall frequency of the chip. It can be widely used in the field of micro control units that are sensitive to power consumption and cost.
  • multiple interrupt registers 120 and multiple status registers 130 are visible to each computing core 140 .
  • the interrupt register 120 and the status register 130 of multiple computing cores 140 in the multi-core circuit are visible to each computing core 140, that is, one computing core 140 in the multi-core circuit can query or set the multi-core circuit. All the interrupt registers 120 and status registers 130 enable each computing core 140 to promptly sense the need for data exchange, trigger the execution of data exchange operations, and quickly locate the data that needs to be accessed.
  • the computing core 140 in the multi-core circuit that meets the data exchange conditions can set the interrupt register 120 of other computing cores 140 that exchange data with the core (itself), and query the interrupt registers 120 of other computing cores 140 that exchange data with the core. Status register 130.
  • the public storage area 110 may include a circular queue allocated to each computing core 140 to store data that needs to be exchanged.
  • a circular queue matching the number of computing cores can be allocated in the public storage area 110, so that each computing core 140 stores data that needs to be interacted with in a data structure connected end to end, thereby realizing the interaction between the computing cores 140. Fast access to data.
  • the public storage area 110 may include multiple ring queues allocated to each computing core 140.
  • Each ring queue may be configured to store a preset type of data, and different types of data correspond to different data processing priority.
  • the public storage area 110 may be configured according to the type of data that the computing core 140 needs to store in the common storage area 110 (that is, according to the processing priority of the data that the computing core 140 needs to store in the common storage area).
  • Multiple ring queues are allocated to each computing core 140, so that each ring queue of a computing core 140 stores a preset type of data, that is, different ring queues of a computing core 140 store different types of data, so that according to the data Different implementations of stored ring queues distinguish data with different processing priorities, thereby facilitating data classification and processing.
  • the preset type of data has a corresponding storage relationship with the circular queue. For example, assuming that alarm type data has a higher priority than parameter type data, the two ring queues can be divided into a high priority ring queue and a low priority ring queue, and then the alarm type data is stored in the high priority ring queue.
  • a high-level ring queue stores parameter type data in a low-priority ring queue.
  • ring queues can be configured for each computing core 140. Data of different priorities are put into ring queues of different priorities. The reader computing core 140 prioritizes those with high priority according to the priority of the ring queue. messages to ensure the real-time requirements of the system. The capacity of each ring queue can be resized based on the amount of data being transferred.
  • each ring queue may include a fixed-length ring sub-queue and a variable-length ring sub-queue; the fixed-length ring sub-queue is configured to store data at the storage location and data size of the variable-length ring sub-queue. ;Variable-length circular subqueue configured to store data.
  • a circular queue includes two sub-queues, one sub-queue is a fixed-length circular sub-queue configured to store fixed-length data description information, and the other sub-queue is a variable-length circular sub-queue configured to store variable-length actual data. subqueue.
  • the fixed-length circular subqueue is configured to store the storage location and data size of each data in the variable-length circular subqueue (that is, the above data description information), and the variable-length circular subqueue is configured To store actual variable-length data. Since the length of each storage space in the fixed-length circular subqueue is fixed, the corresponding storage space can be accurately located through the data count value. Furthermore, based on the data description information stored in each fixed-length circular subqueue, the variable can be Accurately locate the data of each item in the long circular subqueue.
  • each computing core 140 can package each data to be exchanged into a message.
  • the above-mentioned circular queue can be a message queue, wherein the fixed-length circular sub-queue can be configured to store message headers in the circular queue. , rather than the queue that stores the message body.
  • the variable-length ring subqueue may be a queue in the ring queue that is configured to store the message body.
  • the storage location and data size of the message body in the variable-length circular subqueue can be stored in the fixed-length circular subqueue of the circular queue, and the actual message body can be stored in the variable-length circular subqueue of the circular queue. in the subqueue.
  • the status register 130 may include a first-type status register or a second-type status register; each computing core 140 corresponds to at least one first-type status register and at least one second-type status register; first The first type of status register is configured to store the write count value of the corresponding computing core 140 to the preset type of data; the second type of status register is configured to store the belonging computing core 140 to the preset type of data in other computing cores 140. Read the count value.
  • the write count value may represent the number of data items written by the computing core 140 to the preset type of data in the common storage area 110 .
  • the read count value may represent the number of data items read by the computing core 140 for the preset type of data in the common storage area 110 .
  • each computing core 140 can configure the first type of status register according to the type of the preset type of data written, and configure the second type of status register according to the type of the set type of data read, Thus, at least one first-type status register and at least one second-type status register are obtained.
  • the at least one first-type status register stores the writing count value of the preset type of data by the corresponding computing core 140
  • at least one second-type status register stores the writing count value of the preset type of data by the corresponding computing core 140.
  • the status register stores the read count value of the preset type of data in the corresponding computing core 140 .
  • the status register 130 By distinguishing the functions of the status register 130, such as recording the count value of writing data of a preset type by the computing core 140 to which it belongs and the counting value of reading data of other computing cores 140, the status of data reading and writing by the computing core 140 can be realized. Effective management to quickly locate the data that needs to be read.
  • two first-type status registers can be configured: a high-priority first-type status register, and a high-priority first-type status register.
  • a low-priority first-type status register, two second-type status registers: a high-priority second-type status register, a low-priority second-type status register, and then a high-priority first-type status register The register stores the writing count value of high-priority data by the computing core 140 to which it belongs.
  • the low-priority first-type status register stores the writing count value of low-priority data by the computing core 140 to which it belongs.
  • the second type of status register stores the reading count value of high-priority data in the computing core 140 to which it belongs
  • the low-priority second type status register stores the reading count value of low-priority data in the computing core 140 to which it belongs.
  • the embodiments of the present disclosure do not limit the types of data that can be written by the computing core 140 and the types of data that can be read.
  • the number of first-type status registers corresponding to different computing cores may be the same or different, and the number of second-type status registers corresponding to different computing cores may be the same or different.
  • the multi-core circuit may be a dual-core digital signal processing chip.
  • the dual-core circuit can be configured to process audio data, video data, text data, etc.
  • the embodiments of the present disclosure do not limit the processing functions of the multi-core circuit, and can realize data interaction in heterogeneous computing core scenarios.
  • FIG. 2A is a flow chart of a data exchange method provided by an embodiment of the present disclosure. This embodiment can be applied to the situation of low-latency data exchange.
  • the method can be executed by a data exchange device.
  • the device can It is implemented by at least one of software and hardware, and generally can be integrated in the writing side computing core of the multi-core circuit as described in any embodiment of the present disclosure.
  • the method includes the following operations:
  • the computing core on the writing side may be the computing core on the data writing side in a multi-core circuit.
  • computing core A when computing core A in a multi-core circuit needs to send data generated by this core to other computing cores for data exchange, computing core A is the writing computing core that meets the data exchange conditions.
  • the first data to be transmitted can be written into the common storage area.
  • the interrupt signal may be used to instruct the reading computing core to obtain the data read and write status of the public storage area recorded in the corresponding status register, and read the first data from the public storage area according to the data read and write status.
  • the reading computing core may be determined by the writing computing core and is the computing core that needs to read the first data from the public storage area.
  • the interrupt register of the reading side computing core can be configured to trigger the corresponding interrupt register of the reading side computing core to generate an interrupt signal, so as to The reading side computing core is caused to read the first data written by the writing side computing core from the public storage area according to the instruction of the interrupt signal.
  • the writing side's computing core when the data exchange conditions are met, writes the first data into the public storage area, triggering the corresponding interrupt register of the reading side's computing core to generate an interrupt signal, thereby realizing reading.
  • the reading of the first data by Fang Calculation does not require complex circuits and bus structures.
  • Data interaction of the computing core can be completed only through the combined use of status registers and interrupt registers, reducing the complexity of hardware design and reducing the number of chips.
  • the calculation delay ensures the improvement of the overall frequency of the chip and can be widely used in the field of micro control units that are sensitive to power consumption and cost.
  • triggering the interrupt register corresponding to the reading side computing core to generate an interrupt signal may include: updating the data read and write status of the public storage area recorded in the status register corresponding to the writing side computing core, And trigger the interrupt register corresponding to the reading side computing core to generate an interrupt signal.
  • the writing side computing core after the writing side computing core writes the first data in the public storage area, it can record the status register corresponding to the writing side computing core according to the writing status of the first data in the public storage area.
  • the data writing status in the data reading and writing status is updated, thereby triggering the interrupt register corresponding to the reading side computing core to generate an interrupt signal.
  • the writer's computing core updates the data read and write status, and triggers the interrupt register corresponding to the reader's computing core to generate an interrupt signal. This allows the reader's computing core to accurately locate the first data that needs to be read, so as to better communicate with the reader.
  • the writing side computing core completes reliable cooperation.
  • updating the data read and write status of the public storage area recorded in the status register corresponding to the writing side computing core, and triggering the interrupt register corresponding to the reading side computing core to generate an interrupt signal may include : In the visible status register list, identify the status register corresponding to the writing side computing core, and update the data read and write status of the public storage area recorded in the status register; In the visible interrupt register list, identify the reading side computing core Core the corresponding interrupt register and trigger the interrupt register to generate an interrupt signal.
  • the visible status register list may be a list of status registers visible to the writing computing core in a multi-core circuit, that is, a list of status registers of each computing core included in the multi-core circuit.
  • the visible interrupt register list may be a list of interrupt registers visible to the writing computing core in a multi-core circuit, that is, a list of interrupt registers of all computing cores included in the multi-core circuit.
  • the status register corresponding to each computing core can be obtained in advance to establish a visible status register list, and then the writing side computing core can identify the status belonging to the writing side computing core based on the visible status register list register, thereby updating the data reading and writing status of the public storage area recorded in the identified status register according to the state of the writing side computing core writing the first data in the public storage area.
  • the interrupt register corresponding to each computing core can be obtained in advance and a list of visible interrupt registers can be established. Furthermore, the writing side computing core can identify the interrupt register belonging to the reading side computing core according to the visible interrupt register list, and trigger the identified interrupt register to generate an interrupt signal.
  • the visible status register list you can quickly determine the status register corresponding to the writing side computing core, so as to update the data writing status of the writing side computing core.
  • the visible interrupt register list you can quickly determine and read The interrupt register corresponding to the side computing core is used to accurately trigger the interrupt register of the reading side computing core to generate an interrupt signal.
  • writing the first data to the public storage area may include: obtaining the first circular queue allocated to the writing computing core in the public storage area; writing the first data to the first in a circular queue.
  • the first ring queue may be a storage area allocated to the writing side computing core in the public storage area, and is configured to store data written by the writing side computing core.
  • a first circular queue can be allocated to the writing side computing core in the public storage area, and then the writing side computing core writes the first data into the first ring queue.
  • the data is stored in the preconfigured first ring queue, which can facilitate the management of the first data.
  • obtaining the first circular queue allocated for the writing side computing core in the public storage area may include: according to the type of the first data, in the public storage area, obtaining the first ring queue allocated for the writing side computing core. Compute the first circular queue allocated by the core.
  • the number of first ring queues corresponding to the writing side computing core may be multiple, and different first ring queues are configured to store different types of data written by the writing side computing core. .
  • the writing computing core before writing the first data into the public storage area, the writing computing core first needs to determine the type of data in the first data, and then allocate data to the writing computing core in the public storage area based on the type of the first data. From all the first circular queues, obtain the first circular queue that matches the type of the first data.
  • the advantage of this setting is that by storing different types of data in different first ring queues, it can not only facilitate the writing side's computing core to manage different types of written data, but also prompt the reading side's computing core to manage different types of written data.
  • the priority order of data is used to read and process the data that needs to be read.
  • the first data may include multiple data items, and the types of the multiple data items are generally the same. However, in an extreme case, the types of multiple data items included in the first data are not exactly the same.
  • data items 1-3 are type a and data items 4-6 are type b.
  • data items 1-3 can be written to and into the first circular queue corresponding to type a, and write data items 4-6 into the second circular queue corresponding to type b.
  • writing the first data into the first circular queue may include: writing the first data into a variable-length circular sub-queue in the first circular queue, and writing the first data into the variable-length circular sub-queue. The size and the storage location of the first data in the variable-length circular subqueue are written to the fixed-length circular subqueue in the first circular queue.
  • the first circular queue includes two sub-queues: a variable-length circular sub-queue and a fixed-length circular sub-queue.
  • the fixed-length circular subqueue is configured to store the data size and the storage location of the data in the variable-length circular subqueue
  • the variable-length circular subqueue is configured to store the data itself.
  • each data item may be stored in the variable-length circular subqueue in turn.
  • the data size of each data item and the storage location in the variable-length circular sub-queue are stored in independent storage spaces in the fixed-length circular sub-queue.
  • updating the data read and write status of the public storage area recorded in the status register corresponding to the writing side computing core may include: in the status register corresponding to the writing side computing core, obtaining the The first type of status register corresponding to the type of the first data; according to the number of data items included in the first data, the writing count value of the preset type of data stored in the first type of status register in the first ring queue is calculated. renew.
  • the number of data items may be the total number of data items in the first data.
  • the status register corresponding to the writing side computing core can be obtained first, and then according to the data type of the first data, the third data corresponding to the type of the first data is determined from the status register corresponding to the writing side computing core.
  • a type of status register determines the data items included in the first data to write the preset type of data stored in the first type of status register in the first circular queue according to the number of data items included in the first data. The count value is updated.
  • the write count value of the type of written data in the first circular queue can be accurately updated according to the type of the first data and the number of data items of the first data.
  • the status register corresponding to the writing side computing core includes multiple first-type status registers, and each first-type status register is configured to store the writing count of the preset type of data of the writing side computing core. value.
  • the first data is written into the variable-length circular sub-queue in the first circular queue, and the data size of the first data and the storage location of the first data in the variable-length circular sub-queue are written
  • Writing to the fixed-length circular sub-queue in the first circular queue may include: sequentially obtaining the current data items in the first data, and obtaining the current write count value of the current data items in the first circular queue; according to the current write Enter the count value, locate the fixed-length storage area in the fixed-length circular subqueue; obtain the current variable-length storage location of the variable-length circular subqueue, and write the current variable-length storage location and the data size of the current data item into the fixed-length storage area; write the current data item into the variable-length circular subqueue according to the current variable-length storage location, and update the current variable-length storage location according to the data size of the current data item; return to the first data to obtain the current data item in sequence Operate until all data items are processed.
  • the current data item is the data item in the first data that currently needs to be written to the first circular queue.
  • the current write count value may be the current count value of data items written by the writing side computing core in the common storage area.
  • the fixed-length storage area may be an area configured to store message headers in the fixed-length circular subqueue.
  • the current variable-length storage location may be the starting location for storing the new message body.
  • the current data items can be obtained sequentially from the first data, and according to the write operation of the current data item, the current write count value of the first ring queue is updated by one, and then according to the updated current Write the count value and the total number of fixed-length storage areas of the fixed-length circular subqueue, locate the fixed-length storage area in the fixed-length circular subqueue, obtain the current variable-length storage location of the variable-length circular subqueue, and store the current variable-length storage location and the data size of the current data item are written into the fixed-length storage area.
  • the current variable-length storage location is used as the starting storage location of the current data item.
  • the current data item is written into the variable-length circular subqueue, and the current data item is written into the fixed-length storage area according to the data size of the current data item. , update the current variable-length storage location, that is, the next storage location of the last data of the current data item in the storage location of the variable-length circular subqueue is used as the current variable-length storage location, and then return to the first data to obtain the current data sequentially
  • the operation of items until the processing of all data items is completed, through the cooperation of the fixed-length circular subqueue and the variable-length circular subqueue, the writing status of the first data can be recorded, making it easier for the reader computing core to read the first data.
  • Figure 2B is a flow chart of another data exchange method provided by an embodiment of the present disclosure. As shown in Figure 2B, the method includes:
  • S2120 Obtain the current data items in the first data in sequence, and obtain the current write count value of the current data items in the first circular queue.
  • S2160 Check whether the processing of all the data items in the first data is completed. If the processing of all the data items in the first data is completed, execute S2170; if the processing of all the data items in the first data is not completed, return to S2120.
  • the technical solution of the embodiment of the present disclosure obtains the first data to be written to the public storage area when the data exchange conditions are met, and then obtains the calculation for the writing party in the public storage area according to the type of the first data.
  • the first circular queue allocated by the core and sequentially obtain the current data items in the first data, obtain the current write count value of the current data item in the first circular queue, and then based on the current write count value, in the fixed-length circular sub- In the queue, locate the fixed-length storage area. Get the current variable-length storage location of the variable-length ring subqueue, and write the current variable-length storage location and the data size of the current data item into the fixed-length storage area.
  • write the current data item into the variable-length ring Based on the current variable-length storage location, write the current data item into the variable-length ring. subqueue, and update the current variable length storage location according to the data size of the current data item, and detect whether the processing of all data items in the first data is completed. If the processing of all data items in the first data is completed, the system will display the data in the visible state In the register list, identify the status register corresponding to the writing computing core; if the processing of all data items in the first data is not completed, return to the execution to obtain the current data items in the first data in sequence, and obtain the current data items in the first data. The current write count in a ring queue.
  • the status register corresponding to the writing side computing core obtain the first type of status register corresponding to the type of the first data, and calculate the preset type stored in the first type of status register according to the number of data items included in the first data.
  • the write count value of the data in the first ring queue is updated, in the visible interrupt register list, the interrupt register corresponding to the reading side computing core is identified, and the interrupt register is triggered to generate an interrupt signal.
  • This disclosed solution does not require the construction of complex centralized or distributed synchronization units. It can implement complex data synchronization technology only by configuring simple interrupt registers and status registers, reducing the complexity of hardware design and reducing the calculation delay of the chip. This ensures an increase in the overall frequency of the chip and can be widely used in the field of micro control units that are sensitive to power consumption and cost.
  • FIG. 3A is a flow chart of another data exchange method provided by an embodiment of the present disclosure. This embodiment can be applied to the situation of low-latency data exchange.
  • the method can be executed by a data exchange device.
  • the device It can be implemented by at least one of software and hardware, and can generally be integrated in the reader computing core of the multi-core circuit as described in any embodiment of the present disclosure.
  • the method includes the following operations:
  • the interrupt signal is generated by the writing side computing core triggering the corresponding interrupt register of the reading side computing core after writing the second data into the common storage area when the data exchange conditions are met.
  • the current computing core when the current computing core serves as the reading computing core, after the writing computing core writes the second data into the public storage area, that is, when the writing computing core meets the data exchange conditions,
  • the interrupt register corresponding to the current computing core can be triggered to generate an interrupt signal.
  • the current computing core can read the data read and write status of the public storage area recorded in the status register of this core.
  • obtaining the data read and write status of the public storage area recorded in the status register corresponding to the reader computing core includes: identifying the first node corresponding to the reader computing core in the visible status register list. status register, and identify the second status register corresponding to the writing computing core; obtain the data reading and writing status respectively corresponding to the first status register and the second status register.
  • the first status register may be a status register that records the data reading and writing status of the reading side computing core.
  • the second status register may be a status register that records the data reading and writing status of the writing side computing core.
  • the first status register belonging to the current computing core (that is, the reading side computing core) can be identified according to the visible status register list, and the first status register belonging to the writing side can be identified.
  • Calculate the second status register of the core and then identify the data stored in the first status register and the second status register respectively to obtain the data read and write status corresponding to the first status register and the second status register respectively, that is, obtain the current calculation.
  • the data read and write status of the core and the data read and write status of the writing computing core can be accurately judged.
  • the reading side computing core can read the second data written by the writing side computing core from the public storage area according to the data reading and writing status stored in the status register.
  • the technical solution of the embodiment of the present disclosure is that when the interrupt register corresponding to the reading side computing core generates an interrupt signal, the reading side computing core obtains the data reading and writing of the public storage area recorded in the status register corresponding to the reading side computing core. status, and then read the second data written by the writing side computing core from the public storage area according to the obtained data reading and writing status, so as to realize the reading of the second data written by the writing side computing core by the reading side computing core.
  • the data interaction of the computing core can be completed only through the status register and interrupt register, which reduces the complexity of the hardware design, reduces the calculation delay of the chip, and ensures the improvement of the overall frequency of the chip. It is widely used in micro control unit fields that are sensitive to power consumption and cost.
  • reading the second data written by the writing side computing core from the public storage area according to the obtained data reading and writing status may include: in the public storage area, obtaining and writing side computing core The second circular queue corresponding to the core; according to the data reading and writing status, the second data written by the writing party calculation core is read from the second circular queue.
  • the second ring queue may be a storage area allocated for the writing computing core in the public storage area, and is configured for the writing computing core to write data that needs to be exchanged between cores.
  • the reader computing core needs to first determine the second circular queue allocated to the writer computing core in the public storage area, and then obtain the data reading status of this core (that is, the reader computing core) , and the writing status of the second data of the writing side computing core, read the second data written by the writing side computing core from the second circular queue, thereby accurately locating the second data that needs to be read.
  • reading the second data written by the writing side computing core from the second ring queue according to the data reading and writing status may include: data according to the data stored in multiple second ring queues Processing priority, in multiple second ring queues, obtain the current queue in sequence; in the data reading and writing status, obtain the target data reading status of the reader computing core for the current queue, and the writer computing core for the current queue The target data writing status; determine whether the second data is stored in the current queue according to the target data reading status and the target data writing status; if the second data is stored in the current queue, read the second data from the current queue ; If the second data is not stored in the current queue, return to the operation of obtaining the current queue in sequence.
  • the current queue may be a queue that stores data with the highest priority for data processing in the unprocessed second ring queue.
  • the target data read status may be the read status of the data item in the current queue calculated by the reader.
  • the target data writing status may be the writing status of the data item in the current queue by the writing computing core.
  • the reading side computing core can first determine the data processing priority of the data stored in the multiple second ring queues, and then according to the data processing priority of the data stored in the multiple second ring queues (for example, the priority is determined by (from high to low), in multiple second ring queues, obtain the current queue in sequence, and then determine the target data reading status of the core for the current queue based on the obtained data reading and writing status, and calculate the core pair for the writing side The target data writing status of the current queue.
  • the reading side computing core can analyze the target data reading status and the target data writing status to determine whether the writing side computing core stores the second data in the current queue, that is, whether the current queue writes new data, and if it writes If the incoming computing core stores the second data in the current queue, it reads the second data according to the target data reading status and the target data writing status. If the writing computing core does not store the second data in the current queue, it returns to perform the operation of obtaining the current queue in sequence, thereby accurately locating the second data that needs to be read.
  • obtaining the target data reading status of the reading side computing core for the current queue, and the target data writing status of the writing side computing core for the current queue may include : According to the type of data stored in the current queue, obtain the target second-type status register in the first status register corresponding to the reading side computing core, and obtain the target second type status register in the second status register corresponding to the writing side computing core.
  • Target first-type status register obtain the target read count value stored in the target second-type status register, calculate and check the target read count value of the current queue; obtain the target read count value of the writer stored in the target first-type status register, calculate and check the target of the current queue Write count value.
  • the target second-type status register may be a first status register corresponding to the reader computing core, and is configured to record the status of the read count value of the current queue storage data in the writer computing core against the reader computing core to which it belongs. register.
  • the target first-type status register may be a status register configured to store the write count value of the writing data of the writing side computing core in the current queue among the second status registers corresponding to the writing side computing core.
  • the target read count value may be the read count value calculated by the reader against the current queue data item.
  • the target write count value may be the write count value of the data item written by the writing side computing core in the current queue.
  • the reader computing core can obtain the target second type status register in the first status register corresponding to the reader computing core according to the type of data stored in the current queue, and write In the second status register corresponding to the square computing core, obtain the target first-type status register, read the target read count value stored in the target second-type status register, and check the target read count value of the current queue, as well as the target first-type status.
  • the write-side calculation stored in the register checks the target write count value of the current queue, thereby determining the data reading status of the core and the data writing status of the writing-side calculation core, making it easier for the core to accurately locate the first data that needs to be read. 2 data.
  • determining whether the second data is stored in the current queue according to the target data read status and the target data write status includes: if it is determined that the target read count value is less than the target write count value, then determining The second data is stored in the current queue.
  • the reader computing core may compare the obtained target read count value with the target write count value. If the target read count value is less than the target write count value, it indicates that the current queue stores the Second data, if the target read count value is equal to the target write count value, it indicates that the second data is not stored in the current queue. That is, only by comparing the target read count value and the target write count value, it can be determined that the second data in the current queue is Whether to store the second data without complex data analysis and simplify the algorithm complexity.
  • reading the second data from the current queue includes: updating the target read count value in the target second type status register by adding one; and based on the updated target read count value.
  • locate the historical storage area in the fixed-length circular sub-queue of the current queue in the historical storage area, obtain the historical variable-length storage location and target data size; according to the historical variable-length storage location and target data size, locate the historical variable-length storage location in the current queue
  • read a data item in the second data if it is determined that the updated target read count value is less than the target write count value, return to execute the target read count in the target second type status register
  • the value is updated by adding one until the complete reading of the second data is completed.
  • the historical storage area is determined by the read count value.
  • the reader computing core needs to read the relevant information of the previous data item in the storage area of the fixed-length circular subqueue.
  • the historical variable-length storage location may be a variable-length circular subqueue that stores the starting position of the previous data item that the reader computing core needs to read.
  • the target data may be data items written to the public storage area by the writing computing core that matches the historical storage area.
  • the reader computing core can update the target read count value in the target second type status register by one, based on the updated target read count value and the fixed length of the fixed-length ring subqueue.
  • the total number of storage areas In the fixed-length circular sub-queue of the current queue, locate the historical storage area, analyze the data in the historical storage area, obtain the historical variable-length storage location and the target data size for summing, and then add the summation result to the current queue. In the variable-length circular subqueue, read a data item in the second data. After reading a data item in the second data, the reader computing core may compare the updated target read count value with the target write count value.
  • target read count value is less than the target write count value. Then return to perform the operation of adding one and updating the target read count value in the target second type status register until the complete reading of the second data is completed, thereby realizing the data item in the second data that needs to be read. Read automatically.
  • the data exchange method is executed by the reader computing core in the multi-core circuit, and may also include: pre-registering different types of processing functions for processing different types of data; reading from the public storage area After the writing side calculates the second data written by the core, it also includes: calling a matching processing function for data processing according to the type of the second data.
  • the processing function may be a function that can perform data processing on the data in the public storage area.
  • the embodiment of the present disclosure does not limit the type of the processing function, as long as it can realize the required functions of the computing core.
  • different types of processing functions can be registered in advance according to the functions that the reader computing core needs to implement, so as to process different types of data in the public storage area based on different processing functions.
  • the reader computing core can Read the second data written by the writing side calculation core from the public storage area, determine the data type of the second data, and then call the processing function that matches the data type of the second data, so as to process the second data through the processing function , to realize the corresponding functions of the current computing core. Replacing traditional functional coding with processing functions can prevent the code from accurately processing data because the coder cannot know the global coding information.
  • the reader computing core registers the processing function to the message scheduler through registration.
  • the message scheduler can call the corresponding processing function according to the data type of the second data.
  • the message header stores the Cyclic Redundancy Check (CRC) value of the message body. The user can determine whether the message body in the current message body is overwritten based on the CRC value.
  • CRC Cyclic Redundancy Check
  • Figure 3B is a flow chart of another data exchange method provided by an embodiment of the present disclosure. As shown in Figure 3B, the method includes:
  • S3150 Obtain the target read count value stored in the second type status register of the target and check the target read count value of the current queue.
  • S3160 Obtain the write side stored in the first type status register of the target, calculate and check the target write count value of the current queue.
  • S3170 Determine whether the target read count value is less than the target write count value. If the target read count value is less than the target write count value, execute S3180; if the target read count value is not less than the target write count value, return to execute S3130. .
  • the technical solution of the embodiment of the present disclosure is to identify the first status register corresponding to the reading side computing core in the visible status register list when the interrupt register corresponding to the reading side computing core generates an interrupt signal, and identify the first status register corresponding to the reading side computing core.
  • the second status register corresponding to the writing side computing core and then obtains the data read and write status respectively corresponding to the first status register and the second status register, thereby obtaining the second status register corresponding to the writing side computing core in the public storage area.
  • Ring queue and according to the data processing priority of the data stored in multiple second ring queues, the current queue is obtained in sequence in the multiple second ring queues, so as to calculate with the reader based on the type of data stored in the current queue.
  • the target second-type status register is obtained from the first status register corresponding to the core, and the target first-type status register is obtained from the second status register corresponding to the writing computing core.
  • Whether the target read count value is less than the target write count value if the target read count value is less than the target write count value, read the second data from the current queue; if the target read count value is not less than the target write count Value, returns the operation performed according to the data processing priority of the data stored in multiple second ring queues.
  • This disclosed solution does not require the construction of complex centralized or distributed synchronization units. It can implement complex data synchronization technology only by configuring simple interrupt registers and status registers, reducing the complexity of hardware design and reducing the calculation delay of the chip. This ensures an increase in the overall frequency of the chip and can be widely used in the field of micro control units that are sensitive to power consumption and cost.
  • a dual-core digital signal processing chip can be designed with 2 interrupt registers and 8 status registers, and all registers are visible to the dual-core, which facilitates software to set the communication mode. If computing core 0 (CORE0) needs to notify computing core 1 (CORE1), then set IPC interrupt register 1 to trigger CORE1 to generate an IPC interrupt; CORE1 needs to notify CORE0, then set IPC interrupt register 0 to trigger CORE0 to generate an IPC interrupt. Before triggering the IPC interrupt, the dual-core will write the data that needs to be transferred into the public static random access register (Static Random Access Memory, SRAM) area, which is the public storage area.
  • SRAM Static Random Access Memory
  • the dual-core digital signal processing chip When the dual-core digital signal processing chip needs to synchronize data, it can package the data into a message and put it into a ring queue.
  • the uplink and downlink each hold their own message queues.
  • the message queue is a circular queue with the function of caching messages to coordinate the different data processing capabilities of the dual-core.
  • the data exchange diagram of the dual-core digital signal processing chip is shown in Figure 5.
  • Dual-core digital signal processing chip communication is duplex. Both parties act as producers and consumers of messages at the same time, each holding their own and the other party's first written count value and read count value.
  • computing core 0 When computing core 0 generates new data and sends it to computing core 1 (the uplink in the figure), the first written count value of computing core 0 will increase by 1, and the value of the first written count value will be increased.
  • Fill in the IPC status register 0, then trigger the IPC interrupt, exit the data processing program, and then notify the computing core 1 that there is a new message that needs to be processed.
  • computing core 1 After computing core 1 enters the IPC interrupt service program, it reads the first written count value generated by computing core 0 from IPC status register 0, exits the IPC interrupt service program, and then judges the first written count value and the read count Whether the values (saved by computing core 1) are equal, if the first written count value is not equal to the read count value, computing core 1 will continue to process unprocessed data, and the read count value will be increased by 1 until all After all the data has been processed, see Figure 6 for the data processing process of computing core 0, and see Figure 7 for the data processing process of computing core 1.
  • a message When transmitting a message, the length of the data will occupy memory space of varying lengths depending on the data.
  • data is stored through a ring queue to support the message structure of variable-length data.
  • a message consists of a message header and a message body. The structure of the message header is fixed and the length of the message body is variable. The message header stores the variable-length storage location and data size of the message body in the variable-length ring subqueue.
  • processors In order to coordinate the huge gap between CPU running speed and peripheral input/output (I/O) speed, processors often design multi-level caches. In view of the cacheline length factor, in order to facilitate cache write-back and refresh, the message body The length is designed to be 64B*N.
  • the message header and message body are stored in SRAM respectively and maintained by one of the DSP cores.
  • the number of message headers and the total length of the message body are configurable.
  • Both the message header and message body are ring queues.
  • the distribution of message structures in the ring queue is shown in Figure 8.
  • the 10th piece of data in the fixed-length ring subqueue stores the starting position of the 10th message body stored in the variable-length ring subqueue. (0x60050000) and the size of the message body (40B, 24B needs to be added).
  • the 11th piece of data in the fixed-length ring subqueue stores the beginning of the storage of the 11th message body stored in the variable-length ring subqueue.
  • the 12th data of the fixed-length ring subqueue stores the beginning of the storage of the 12th message body stored in the variable-length ring subqueue.
  • the reading side computing core can obtain the message header information based on the first written count value of the writing side computing core, and then read the message body information from the message header information, such as the message body location (variable length storage location) , data body size, etc.
  • Embodiments of the present disclosure also provide a data exchange device, which is executed by a writing side computing core in a multi-core circuit and is configured to perform the above-mentioned data exchange method.
  • Figure 9 is a schematic diagram of a data exchange device provided by an embodiment of the present disclosure. As shown in Figure 9, the device includes: a first data writing module 410 and an interrupt signal triggering module 420, wherein:
  • the first data writing module 410 is configured to write the first data into the public storage area when the data exchange conditions are met; the interrupt signal triggering module 420 is configured to trigger the interrupt register corresponding to the reading side computing core to generate Interrupt signal; wherein, the interrupt signal is used to instruct the reading computing core to obtain the data read and write status of the public storage area recorded in the corresponding status register, and read the first data from the public storage area according to the data read and write status.
  • the interrupt signal is used to instruct the reading computing core to obtain the data read and write status of the public storage area recorded in the corresponding status register, and read the first data from the public storage area according to the data read and write status.
  • the writing side's computing core when the data exchange conditions are met, writes the first data into the public storage area, triggering the corresponding interrupt register of the reading side's computing core to generate an interrupt signal, thereby realizing reading.
  • Fang Calculation checks the reading of the first data without the need for complex circuits and bus structures.
  • the data interaction of the computing core can be completed only through the status register and interrupt register, which reduces the complexity of the hardware design and reduces the calculation delay of the chip. This ensures an increase in the overall frequency of the chip and can be widely used in the field of micro control units that are sensitive to power consumption and cost.
  • the interrupt signal trigger module 420 is configured to update the data read and write status of the public storage area recorded in the status register corresponding to the writing side computing core, and trigger the interrupt register corresponding to the reading side computing core to generate interrupt signal.
  • the interrupt signal triggering module 420 is configured to identify the status register corresponding to the writing computing core in the visible status register list, and perform the data reading and writing status of the public storage area recorded in the status register. Update: In the visible interrupt register list, identify the interrupt register corresponding to the reader computing core, and trigger the interrupt register to generate an interrupt signal.
  • the first data writing module 410 is configured to obtain the first circular queue allocated to the writing computing core in the public storage area; write the first data to the third in a circular queue.
  • the first data writing module 410 is configured to obtain the first circular queue allocated to the writing computing core in the public storage area according to the type of the first data.
  • the first data writing module 410 is configured to write the first data into a variable-length circular sub-queue in the first circular queue, and write the data size of the first data and the The storage location of the first data in the variable-length circular sub-queue is written to the fixed-length circular sub-queue in the first circular queue.
  • the interrupt signal triggering module 420 is configured to obtain the first type of status register corresponding to the type of the first data in the status register corresponding to the writing side computing core; according to the first data The number of data items included updates the write count value of the preset type of data stored in the first type status register in the first circular queue.
  • the first data writing module 410 is configured to sequentially obtain current data items in the first data, and obtain the current write count value of the current data items in the first circular queue. ; According to the current write count value, locate the fixed-length storage area in the fixed-length circular subqueue; obtain the current variable-length storage location of the variable-length circular subqueue, and store the current variable-length storage location and the data size of the current data item are written into the fixed-length storage area; according to the current variable-length storage location, the current data item is written into the variable-length circular subqueue, and according to the data size of the current data item, Update the current variable-length storage location; return to perform the operation of sequentially acquiring the current data items in the first data until all data items are processed.
  • Embodiments of the present disclosure also provide a data exchange device, which is executed by a reader computing core in a multi-core circuit and is configured to perform the above data exchange method.
  • Figure 10 is a schematic diagram of another data exchange device provided by an embodiment of the present disclosure. As shown in Figure 10, the device includes: a data reading and writing status acquisition module 510 and a second data reading module 520, wherein:
  • the data read and write status acquisition module 510 is configured to obtain the data read and write status of the public storage area recorded in the status register corresponding to the reader computing core when the interrupt register corresponding to the reader computing core generates an interrupt signal; wherein , the interrupt signal is generated by the writing side computing core triggering the interrupt register corresponding to the reading side computing core after writing the second data into the common storage area when the data exchange conditions are met; the second data reading module 520 , configured to read the second data written by the writing side computing core from the public storage area according to the obtained data reading and writing status.
  • the technical solution of the embodiment of the present disclosure is to use the reading side computing core to obtain the data reading and writing of the public storage area recorded in the status register corresponding to the reading side computing core when the interrupt register corresponding to the reading side computing core generates an interrupt signal. status, and then read the second data written by the writing side computing core from the public storage area according to the obtained data reading and writing status, so as to realize the reading of the second data written by the writing side computing core by the reading side computing core.
  • the data interaction of the computing core can be completed only through the status register and interrupt register, which reduces the complexity of the hardware design, reduces the calculation delay of the chip, and ensures the improvement of the overall frequency of the chip. It is widely used in micro control unit fields that are sensitive to power consumption and cost.
  • the data read and write status acquisition module 510 is configured to identify the first status register corresponding to the reading side computing core in the visible status register list, and identify the second status corresponding to the writing side computing core. Register; obtain the data read and write status respectively corresponding to the first status register and the second status register.
  • the second data reading module 520 is configured to obtain the second circular queue corresponding to the writing side computing core in the public storage area; according to the data reading and writing status, from the third The second data written by the writing side computing core is read from the second circular queue.
  • the second data reading module 520 is configured to sequentially obtain the current queue in the plurality of second ring queues according to the data processing priority of the data stored in the plurality of second ring queues; in the data In the read and write state, obtain the target data reading status of the reading side computing core for the current queue, and the target data writing status of the writing side computing core for the current queue; according to the target data reading status and The target data writing status determines whether the second data is stored in the current queue; if the second data is stored in the current queue, the second data is read from the current queue. ; If the second data is not stored in the current queue, return to the operation of obtaining the current queue in sequence.
  • the second data reading module 520 is configured to obtain the target second type status register in the first status register corresponding to the reading side computing core according to the type of data stored in the current queue, and in Obtain the target first-type status register in the second status register corresponding to the write-side calculation core; obtain the target read count value of the current queue for the reader-side calculation and verification stored in the target second-type status register; Obtain the target write count value stored in the first type status register of the target and calculate and check the target write count value of the current queue.
  • the second data reading module 520 is configured to determine that the second data is stored in the current queue if it is determined that the target read count value is less than the target write count value.
  • the second data reading module 520 is configured to update the target read count value in the target second type status register by one; according to the updated target read count value, in the current queue In the fixed-length circular sub-queue of , read a data item in the second data; if it is determined that the updated target read count value is smaller than the target write count value, then return to execute the target read in the target second type status register. Get the count value and perform an update operation of adding one until the complete reading of the second data is completed.
  • the data exchange device further includes a processing function registration module 530, which is configured to pre-register different types of processing functions for processing different types of data.
  • the data exchange device further includes a data processing module 540, which is configured to call a matching processing function for data processing according to the type of the second data.
  • the present disclosure also provides an electronic device, a readable storage medium, and a computer program product to implement the above data exchange method.
  • FIG. 13 is a schematic block diagram of an electronic device implementing a data exchange method provided by an embodiment of the present disclosure.
  • Electronic devices are intended to refer to various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers.
  • Electronic devices may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices.
  • the components shown herein, their connections and relationships, and their functions are examples only and are not intended to limit implementations of the disclosure described and/or claimed herein.
  • the electronic device 600 includes a multi-core circuit 601, which can be loaded into a random access memory (Random Access Memory) according to a computer program stored in a read-only memory (Read-Only Memory, ROM) 602 or from a storage unit 608.
  • Computer program in RAM 603 to perform various appropriate actions and processes.
  • various programs and data required for the operation of the electronic device 600 can also be stored.
  • the multi-core circuit 601, ROM 602 and RAM 603 are connected to each other through a bus 604.
  • I/O interface 605 is also connected to bus 604.
  • the ROM 602 and the storage unit 608 may store data exchange methods executed by the multi-core circuit 601.
  • the computing cores in the multi-core circuit 601 are configured to: when the data exchange conditions are met, write the first data into the common storage area and trigger the corresponding interrupt registers of other computing cores to generate interrupt signals; or, when the computing core corresponds to When the interrupt register generates an interrupt signal, the second data written by other computing cores is read from the common storage area according to the data read and write status of the common storage area recorded in the status register corresponding to the computing core.
  • the I/O interface 605 includes: an input unit 606, such as a keyboard, a mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a magnetic disk, an optical disk, etc. etc.; and a communication unit 609, such as a network card, modem, wireless communication transceiver, etc.
  • the communication unit 609 allows the electronic device 600 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunications networks.
  • Multi-core circuit 601 may be a variety of general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of the multi-core circuit 601 include, but are not limited to, a CPU, a graphics processing unit (GPU), a variety of dedicated artificial intelligence (Artificial Intelligence, AI) computing chips, a variety of computing cores running machine learning model algorithms, and a DSP. , and any appropriate processor, controller, microcontroller, etc.
  • the multi-core circuit 601 performs a plurality of methods and processes described above, such as data exchange methods. For example, in some embodiments, the data exchange method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 608.
  • part or all of the computer program may be loaded and/or installed onto the electronic device 600 via the ROM 602 and/or the communication unit 609.
  • the computer program When the computer program is loaded into RAM 603 and executed by multi-core circuit 601, one or more steps of the data exchange method described above may be performed.
  • the multi-core circuit 601 may be configured to perform the data exchange method in any other suitable manner (eg, by means of firmware).
  • Various implementations of the systems and techniques described above may be implemented in digital electronic circuit systems, integrated circuit systems, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Parts (ASSP), System on Chip (SOC), Complex Programmable Logic Device (CPLD), computer hardware, firmware, software, and/or their realized in combination.
  • Various implementations may include implementation in one or more computer programs that may be executed and/or interpreted on a programmable system including at least one programmable processor that may is a special-purpose or general-purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
  • Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that the program codes, when executed by the processor or controller, cause the functions specified in the flowcharts and/or block diagrams/ The operation is implemented.
  • the program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
  • a machine-readable medium may be a tangible medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.
  • the machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any suitable combination of the foregoing.
  • machine-readable storage media examples include one or more wire-based electrical connections, laptop disks, hard drives, RAM, ROM, Erasable Programmable Read-Only Memory (EPROM), or flash memory ), optical fiber, portable compact disk read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • the systems and techniques described herein may be implemented on a computer having a display device (e.g., a cathode ray tube (CRT), CRT) or a liquid crystal display configured to display information to the user. (Liquid Crystal Display, LCD) monitor); and a keyboard and pointing device (such as a mouse or trackball) through which a user can provide input to the computer.
  • a display device e.g., a cathode ray tube (CRT), CRT) or a liquid crystal display configured to display information to the user. (Liquid Crystal Display, LCD) monitor); and a keyboard and pointing device (such as a mouse or trackball) through which a user can provide input to the computer.
  • a keyboard and pointing device such as a mouse or trackball
  • Other kinds of devices may also be configured to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and may be provided in any
  • the systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., A user's computer having a graphical user interface or web browser through which the user can interact with implementations of the systems and technologies described herein), or including such backend components, middleware components, or any combination of front-end components in a computing system.
  • the components of the system may be interconnected by any form or medium of digital data communication (eg, a communications network). Examples of communication networks include: Local Area Network (LAN), Wide Area Network (Wide Area Network, WAN), and the Internet.
  • Computer systems may include clients and servers. Clients and servers are generally remote from each other and typically interact over a communications network. The relationship of client and server is created by computer programs running on corresponding computers and having a client-server relationship with each other.
  • the server can be a cloud server, also known as cloud computing server or cloud host. It is a host product in the cloud computing service system to solve the problems that exist in traditional physical host and virtual private server (VPS) services. It has the disadvantages of difficult management and weak business scalability.
  • the server can also be a distributed system server or a server combined with a blockchain.
  • Steps can be reordered, added, or removed using various forms of the process shown above.
  • multiple steps described in the present disclosure can be executed in parallel, sequentially, or in different orders.
  • the desired results of the technical solution disclosed in the present disclosure can be achieved, there is no limitation here.

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Abstract

本公开提供了一种多核电路、数据交换方法、电子设备及存储介质。多核电路，包括：公共存储区；多个中断寄存器；多个状态寄存器；以及多个计算核，每个计算核被配置为：在满足数据交换条件的情况下，将第一数据写入公共存储区，并触发所述多个计算核中除所述每个计算核外的计算核对应的中断寄存器产生中断信号；或者，在所示每个计算核对应的中断寄存器产生中断信号的情况下，根据所述每个计算核对应的状态寄存器记录的公共存储区的数据读写状态，从所述公共存储区读取所述多个计算核中除所述每个计算核外的计算核写入的第二数据。

Description

多核电路、数据交换方法、电子设备及存储介质
本申请要求在2022年04月06日提交中国专利局、申请号为202210358411.2的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及通信技术领域，多核通信领域，例如涉及一种多核电路、数据交换方法、电子设备及存储介质。
背景技术
人工智能、大数据、物联网蓬勃发展，随之产生了海量的信息需要处理。为了加快信息处理速度，芯片一般会集成多个中央处理器(Central Processing Unit，CPU)核心，简称多核。在处理数据时，多核同时工作，双方需要交换数据时，会使用到进程间通信(Inter-Process Communication，IPC)技术。
IPC本质上是一种同步技术。同步技术对多核通信的效率影响较大，而且不同的同步策略对硬件设计的影响也不相同。芯片设计在实现IPC时，主要采用硬件上增加集中式或分布式同步单元实现读写锁和内存屏障。虽然这种方法减少了IPC通信时软件设计的复杂度，但增加了硬件的复杂程度和成本。
发明内容
本公开提供了一种多核电路、数据交换方法、电子设备及存储介质。
根据本公开的一方面，提供了一种多核电路，包括：
公共存储区；
多个中断寄存器；
多个状态寄存器；以及
多个计算核，每个计算核被配置为：在满足数据交换条件的情况下，将第一数据写入公共存储区，并触发所述多个计算核中除所述每个计算核外的计算核对应的中断寄存器产生中断信号；或者，在所述每个计算核对应的中断寄存器产生中断信号的情况下，根据所述每个计算核对应的状态寄存器记录的公共存储区的数据读写状态，从所述公共存储区读取所述多个计算核中除所述每个计算核外的计算核写入的第二数据。
根据本公开的另一方面，提供了一种数据交换方法，由多核电路中的写入 方计算核执行，包括：
在满足数据交换条件的情况下，将第一数据写入公共存储区；
触发读取方计算核对应的中断寄存器产生中断信号；
其中，所述中断信号用于指示所述读取方计算核获取所对应状态寄存器记录的所述公共存储区的数据读写状态，并根据所述数据读写状态从所述公共存储区读取所述第一数据。
根据本公开的另一方面，提供了另一种数据交换方法，由多核电路中的读取方计算核执行，包括：
在所述读取方计算核对应的中断寄存器产生中断信号的情况下，获取所述读取方计算核对应的状态寄存器记录的公共存储区的数据读写状态；其中，所述中断信号是写入方计算核在满足数据交换条件的情况下，将第一数据写入所述公共存储区后触发所述读取方计算核对应的中断寄存器产生的；
根据获取的所述数据读写状态，从所述公共存储区读取所述写入方计算核写入的第二数据。
根据公开的另一方面，提供了一种数据交换装置，包括：
第一数据写入模块，被配置为在满足数据交换条件的情况下，将第一数据写入公共存储区；
中断信号触发模块，被配置为触发读取方计算核对应的中断寄存器产生中断信号；
其中，所述中断信号用于指示所述读取方计算核获取所对应状态寄存器记录的所述公共存储区的数据读写状态，并根据所述数据读写状态从所述公共存储区读取所述第一数据。
根据公开的另一方面，提供了一种数据交换装置，包括：
数据读写状态获取模块，被配置为在读取方计算核对应的中断寄存器产生中断信号的情况下，获取所述读取方计算核对应的状态寄存器记录的公共存储区的数据读写状态；其中，所述中断信号是写入方计算核在满足数据交换条件的情况下，将第一数据写入所述公共存储区后触发所述读取方计算核对应的中断寄存器产生的；
第二数据读取模块，被配置为根据获取的所述数据读写状态，从所述公共存储区读取所述写入方计算核写入的第二数据。
根据本公开的另一方面，提供了一种电子设备，包括：本公开任一实施例所述的多核电路；以及
与所述多核电路中至少一个计算核通信连接的存储器；其中，
存储器存储有可被计算核执行的指令，指令被所述至少一个计算核执行，以使所述至少一个计算核能够执行上述的数据交换方法。
根据本公开的另一方面，提供了一种存储有计算机指令的非瞬时计算机可读存储介质，其中，计算机指令用于使计算机执行上述的数据交换方法。
附图说明
图1是本公开实施例提供的一种多核电路的示意图；
图2A是本公开实施例提供的一种数据交换方法的流程图；
图2B是本公开实施例提供的另一种数据交换方法的流程图；
图3A是本公开实施例提供的另一种数据交换方法的流程图；
图3B是本公开实施例提供的另一种数据交换方法的流程图；
图4是本公开实施例提供的一种处理函数模型的示意图；
图5是本公开实施例提供的一种双核数字信号处理芯片的数据交换示意图；
图6是本公开实施例提供的一种计算核0的数据处理过程的示意图；
图7是本公开实施例提供的一种计算核1的数据处理过程的示意图；
图8是本公开实施例提供的一种消息结构在环形队列中的分布结果示意图；
图9是本公开实施例提供的一种数据交换装置的示意图；
图10是本公开实施例提供的另一种数据交换装置的示意图；
图11是本公开实施例提供的另一种数据交换装置的示意图；
图12是本公开实施例提供的另一种数据交换装置的示意图；
图13是本公开实施例提供的一种实现数据交换方法的电子设备的示意性框图。
具体实施方式
以下结合附图对本公开的示范性实施例做出说明，其中包括本公开实施例的多种细节以助于理解，应当将它们认为仅仅是示范性的。为了清楚和简明，以下的描述中省略了对公知功能和结构以及与下述实施例相关性低的功能和结构的描述。
在一个示例中，图1是本公开实施例提供的一种多核电路的示意图，如图1 所示，多核电路，包括：公共存储区110；多个中断寄存器120；多个状态寄存器130；以及多个计算核140，每个计算核140被配置为：在满足数据交换条件的情况下，将第一数据写入公共存储区110，并触发其他计算核140对应的中断寄存器120产生中断信号；或者，在该计算核140对应的中断寄存器120产生中断信号的情况下，根据该计算核140对应的状态寄存器130记录的公共存储区110的数据读写状态，从公共存储区110读取其他计算核140写入的第二数据。
多个计算核140的类型可以不同。示例性的，计算核140可以包括高级精简指令计算机(Advanced Reduced Instruction Set Computing Machine，ARM)核以及数字信号处理(Digital Signal Processing，DSP)核等。数据交换条件可以用于表征多个计算核140之间有新消息需要进行多个计算核间的交互。第一数据可以是计算核140自身写入公共存储区110的，以供其他计算核140读取的数据。第二数据可以是写入第一数据的计算核140需要读取的，由其他计算核140写入公共存储区110的数据。公共存储区110可以是多核电路中多个计算核140共用的数据存储区，被配置为实现多核间的数据共享。数据读写状态可以用于表征计算核140对公共存储区110的数据读取以及数据写入的情况。
在本公开实施例中，每个计算核140既可以作为数据写入方，也可以作为数据读取方，当多个计算核140之间需要传输新消息(也即满足数据交换条件)时，如果当前计算核作为数据写入方将第一数据写入公共存储区110后，则当前计算核需要配置作为数据读取方的计算核(例如，计算核A)的中断寄存器120，通过触发该中断寄存器120产生中断信号，以控制计算核A执行从公共存储区110中读取第一数据的操作，进而可以实现将第一数据由当前计算核交换至计算核A的效果。
如果当前计算核作为数据读取方，则当前计算核在基于中断寄存器120产生的中断信号被触发后，例如，该中断信号是由计算核B触发产生的，可以基于当前计算核对应的状态寄存器130中记录的对公共存储区110的数据读写状态，从公共存储区110中读取计算核B在触发产生该中断信号之前所写入的第二数据。
一实施例中，在多核电路中，多个计算核140与多个中断寄存器120具有一一对应关系，此外，一个计算核140对应多个状态寄存器130。
与计算核(例如，计算核1)一一对应的中断寄存器120，可以由其他计算核(例如，计算核2)进行配置，以触发计算核1执行相应的数据读取操作；同时，与每个计算核对应的多个状态寄存器130，被配置为存储该计算核对公共存储区110的数据读取状态以及数据写入状态。
本公开实施例的技术方案，通过公共存储区、多个中断寄存器、多个状态寄存器，以及多个计算核组成多核电路，进而在满足数据交换条件的情况下， 将第一数据写入公共存储区，并触发其他计算核对应的中断寄存器产生中断信号；或者，在该计算核对应的中断寄存器产生中断信号的情况下，根据该计算核对应的状态寄存器记录的公共存储区的数据读写状态，从公共存储区读取其他计算核写入的第二数据，无需构建复杂的集中式或分布式同步单元，仅通过配置简单的中断寄存器和状态寄存器，即可实现复杂的数据同步技术，降低了硬件设计复杂性，减少了芯片的计算时延，保证了芯片整体频率的提升，可以广泛适用于对功耗以及成本敏感的微控制单元领域。
在本公开的一个实施例中，多个中断寄存器120和多个状态寄存器130对每个计算核140可见。
在本公开实施例中，多核电路中多个计算核140的中断寄存器120和状态寄存器130对每个计算核140均是可见的，也即多核电路中一个计算核140可以查询或者设置多核电路中全部的中断寄存器120和状态寄存器130，使得每个计算核140及时感知数据交换需要，触发执行数据交换操作，并快速定位需要存取的数据。
示例性的，多核电路中满足数据交换条件的计算核140可以设置与本核(自身)进行数据交换的其他计算核140的中断寄存器120，并且查询与本核进行数据交换的其他计算核140的状态寄存器130。
在本公开的一个实施例中，公共存储区110中可以包括为每个计算核140分配的环形队列，以存储需要交换的数据。
在本公开实施例中，可以在公共存储区110中分配与计算核数量相匹配的环形队列，以使每个计算核140以首尾相连的数据结构存储需要交互的数据，从而实现计算核140对数据的快速存取。
在本公开的一个实施例中，公共存储区110中可以包括为每个计算核140分配的多个环形队列，每个环形队列可以被配置为存储预设类型的数据，不同类型的数据对应不同的数据处理优先级。
在本公开实施例中，可以根据计算核140需要在公共存储区110内存储的数据类型(也即根据计算核140需要在公共存储区内存储的数据的处理优先级)，在公共存储区110内为每个计算核140分配多个环形队列，以使一个计算核140的每个环形队列存储预设类型的数据，也即一个计算核140的不同环形队列存储不同类型的数据，从而根据数据存储的环形队列的不同实现对不同处理优先级数据的区分，进而便于数据的分类处理。
一实施例中，预设类型的数据与环形队列具有对应存储关系。示例性的，假设报警类型的数据的优先级高于参数类型的数据，则可以将两个环形队列划 分为高优先级环形队列以及低优先级环形队列，进而将报警类型的数据存储于高优先级环形队列，将参数类型的数据存储于低优先级环形队列。
这样设置的原因在于：使用环形队列存放数据，先入队的数据优先被处理，后入队的数据后处理，即使优先级更高仍然得不到及时处理。针对这个问题，可以为每个计算核140配置多个环形队列，不同优先级的数据放入不同优先级的环形队列，读取方计算核140根据环形队列的优先级，优先处理那些高优先级的消息，保证了系统的实时性要求。每个环形队列的容量都可以根据传输的数据量调整大小。
在本公开的一个实施例中，每个环形队列可以包括定长环形子队列以及变长环形子队列；定长环形子队列，被配置为存储数据在变长环形子队列的存储位置和数据大小；变长环形子队列，被配置为存储数据。
也即，一个环形队列中包括两个子队列，一个子队列为被配置为存储定长的数据描述信息的定长环形子队列，另一个子队列为被配置为存储变长实际数据的变长环形子队列。其中，该定长环形子队列，被配置为存储每个数据在变长环形子队列中的存储位置以及数据大小(也即，上文的数据描述信息)，该变长环形子队列，被配置为存储实际的变长数据。由于定长环形子队列中每个存储空间的长度固定，进而，可以通过数据计数值，准确定位相应的存储空间，进而，根据每个定长环形子队列中存储的数据描述信息，可以在变长环形子队列中准确定位每一项的数据。
一实施例中，每个计算核140可以将每个待交换的数据打包为消息，进而，上述环形队列可以为消息队列，其中，定长环形子队列可以是环形队列中被配置为存储消息头，而并非存储消息体的队列。变长环形子队列可以是环形队列中被配置为存储消息体的队列。
在本公开实施例中，可以在环形队列的定长环形子队列中，存储消息体在变长环形子队列的存储位置和数据大小，并将实际的消息体存储在环形队列中的变长环形子队列中。通过将消息头存储于定长环形子队列，将消息体存储于变长环形子队列，可以实现消息头与消息体的分区维护，还可以实现消息体的高效率读取，而无需耗费计算核的计算资源去读取数据。
在本公开的一个实施例中，状态寄存器130可以包括第一类状态寄存器或第二类状态寄存器；每个计算核140对应至少一个第一类状态寄存器和至少一个第二类状态寄存器；第一类状态寄存器，被配置为存储所属计算核140对预设类型的数据的写入计数值；第二类状态寄存器，被配置为存储所属计算核140对其他计算核140中预设类型的数据的读取计数值。
写入计数值可以表征计算核140在公共存储区110中，对预设类型数据所写入的数据项的个数。读取计数值可以表征计算核140在公共存储区110中，对预设类型数据所读取的数据项的个数。
在本公开实施例中，每个计算核140可以根据写入的预设类型的数据的种类配置第一类状态寄存器，并根据读取的设定类型的数据的种类配置第二类状态寄存器，从而得到至少一个第一类状态寄存器和至少一个第二类状态寄存器，通过至少一个第一类状态寄存器存储所属计算核140对预设类型的数据的写入计数值，并通过至少一个第二类状态寄存器存储所属计算核140中预设类型的数据的读取计数值。通过对状态寄存器130的功能区分，如记录对所属计算核140对预设类型的数据写入计数值以及对其他计算核140的数据的读取计数值，可以实现计算核140对数据读写状态的有效管理，从而快速定位需要读取的数据。
示例性的，假设计算核140可以写入2种类型的数据，还可以读取2种类型的数据，则可以配置两个第一类状态寄存器：一个高优先级的第一类状态寄存器，一个低优先级的第一类状态寄存器，两个第二类状态寄存器：一个高优先级的第二类状态寄存器，一个低优先级的第二类状态寄存器，进而由高优先级的第一类状态寄存器存储所属计算核140对高优先级的数据的写入计数值，由低优先级的第一类状态寄存器存储所属计算核140对低优先级的数据的写入计数值，由高优先级的第二类状态寄存器存储所属计算核140中高优先级的数据的读取计数值，由低优先级的第二类状态寄存器存储所属计算核140中低优先级的数据的读取计数值。本公开实施例并不对计算核140可以写入类型的数据的种类，以及可以读取的数据的类型的种类进行限定。
多核电路中与不同计算核对应的第一类状态寄存器的数量可以相同或者不同，与不同计算核对应的第二类状态寄存器的数量可以相同或者不同。
在本公开的一个实施例中，多核电路可以为双核数字信号处理芯片。该双核电路可以被配置为处理音频数据、视频数据以及文本数据等，本公开实施例并不对多核电路的处理功能进行限定，可以实现计算核异构场景下的数据交互。
在一个示例中，图2A是本公开实施例提供的一种数据交换方法的流程图，本实施例可适用于低延时数据交换的情况，该方法可以由数据交换装置来执行，该装置可以由软件和硬件中的至少一项的方式来实现，并一般可集成在如本公开任一实施例所述多核电路的写入方计算核中。相应的，如图2A所示，该方法包括如下操作：
S210、在满足数据交换条件的情况下，将第一数据写入公共存储区。
写入方计算核可以是多核电路中，作为数据写入方的计算核。
在本公开实施例中，当多核电路中的计算核A需要将本核产生的数据发送至其他计算核进行数据交互时，则计算核A为满足数据交换条件的写入方计算核。
相应的，当一个计算核作为写入方计算核，且需要向其他计算核传输新数据时，可以将所需传输的第一数据写入公共存储区。
S220、触发读取方计算核对应的中断寄存器产生中断信号。
中断信号可以用于指示读取方计算核获取所对应状态寄存器记录的公共存储区的数据读写状态，并根据数据读写状态从公共存储区读取第一数据。
读取方计算核可以是由写入方计算核确定的，需要从公共存储区读取该第一数据的计算核。
在本公开实施例中，写入方计算核将第一数据写入公共存储区之后，可以配置读取方计算核的中断寄存器，以触发读取方计算核的相应中断寄存器产生中断信号，以使读取方计算核根据中断信号的指示从公共存储区读取写入方计算核所写入的第一数据。
本公开实施例的技术方案，通过写入方计算核在满足数据交换条件的情况下，将第一数据写入公共存储区，触发读取方计算核对应的中断寄存器产生中断信号，实现读取方计算核对第一数据的读取，不需要复杂的电路以及总线结构，仅通过对状态寄存器以及中断寄存器的配合使用即可完成计算核的数据交互，降低了硬件设计复杂性，减少了芯片的计算时延，保证了芯片整体频率的提升，可以广泛适用于对功耗以及成本敏感的微控制单元领域。
在本公开的一个实施例中，触发读取方计算核对应的中断寄存器产生中断信号，可以包括：将与写入方计算核对应的状态寄存器记录的公共存储区的数据读写状态进行更新，并触发读取方计算核对应的中断寄存器产生中断信号。
在本公开实施例中，写入方计算核在公共存储区写入第一数据之后，可以根据第一数据的写入状态，将与写入方计算核对应的状态寄存器记录的，公共存储区的数据读写状态中的数据写入状态进行更新，进而触发读取方计算核对应的中断寄存器产生中断信号。
写入方计算核对数据读写状态进行更新，并触发读取方计算核对应的中断寄存器产生中断信号，可以实现读取方计算核准确定位所需读取的第一数据，以更好地与写入方计算核完成可靠协作。
在本公开的一个实施例中，将与写入方计算核对应的状态寄存器记录的公共存储区的数据读写状态进行更新，并触发读取方计算核对应的中断寄存器产生中断信号，可以包括：在可见状态寄存器列表中，识别与写入方计算核对应的状态寄存器，并对状态寄存器记录的公共存储区的数据读写状态进行更新； 在可见中断寄存器列表中，识别与读取方计算核对应的中断寄存器，并触发中断寄存器产生中断信号。
可见状态寄存器列表可以是在多核电路中，写入方计算核可见的状态寄存器的列表，也即多核电路所包括的每个计算核的状态寄存器的列表。可见中断寄存器列表可以是在多核电路中，写入方计算核可见的中断寄存器的列表，也即多核电路所包括的全部计算核的中断寄存器的列表。
在本公开实施例中，可以预先获取与每个计算核分别对应的状态寄存器，建立可见状态寄存器列表，进而写入方计算核可以根据可见状态寄存器列表，识别出属于写入方计算核的状态寄存器，从而根据写入方计算核在公共存储区写入第一数据的状态，对识别出的状态寄存器记录的公共存储区的数据读写状态进行更新。
可以预先获取与每个计算核分别对应的中断寄存器，建立可见中断寄存器列表。进而，写入方计算核可以根据可见中断寄存器列表，识别出属于读取方计算核的中断寄存器，并触发所识别出的中断寄存器产生中断信号。
通过查询可见状态寄存器列表，可以快速确定与写入方计算核对应的状态寄存器，以便于对写入方计算核的数据写入状态进行更新，通过查询可见中断寄存器列表，可以快速确定与读取方计算核对应的中断寄存器，以便于准确触发读取方计算核的中断寄存器产生中断信号。
在本公开的一个实施例中，将第一数据写入公共存储区，可以包括：在公共存储区中，获取为写入方计算核分配的第一环形队列；将第一数据写入至第一环形队列中。
第一环形队列可以是在公共存储区中，为写入方计算核分配的一段存储区域，被配置为存储写入方计算核所写入的数据。
在本公开实施例中，可以在公共存储区中，为写入方计算核分配第一环形队列，进而由写入方计算核将第一数据写入至第一环形队列中，通过将第一数据存储于预先配置的第一环形队列，可以便于对第一数据的管理。
在本公开的一个实施例中，在公共存储区中，获取为写入方计算核分配的第一环形队列，可以包括：根据第一数据的类型，在公共存储区中，获取为写入方计算核分配的第一环形队列。
在本公开实施例中，与写入方计算核对应的第一环形队列的数量可以为多个，不同的第一环形队列，被配置为存储写入方计算核写入的，不同类型的数据。
相应的，写入方计算核在将第一数据写入公共存储区之前，首先需要确定 第一数据中数据的类型，进而根据第一数据的类型，在公共存储区为写入方计算核分配的全部第一环形队列中，获取与所述第一数据的类型匹配的第一环形队列。
这样设置的好处是：通过将不同类型的数据存储于不同的第一环形队列中，既可以便于写入方计算核对不同类型的写入数据进行管理，也可以促使读取方计算核按照不同类型数据的优先级顺序，对所需读取的数据进行读取处理。
一般来说，第一数据中可以包括多个数据项，上述多个数据项的类型一般是相同的。但是在一种极端情况下，第一数据中包括的多个数据项的类型不完全相同。
示例性的，假设第一数据中存储2种类型的数据项，其中，数据项1-3为类型a，数据项4-6为类型b，进而，可以将数据项1-3写入至与类型a对应的第一环形队列中，并将数据项4-6写入至与类型b对应的第二环形队列中。
在本公开的一个实施例中，将第一数据写入至第一环形队列中，可以包括：将第一数据写入第一环形队列中的变长环形子队列，并将第一数据的数据大小和第一数据在变长环形子队列中的存储位置，写入至第一环形队列中的定长环形子队列。
在本公开实施例中，第一环形队列中包括有两个子队列：变长环形子队列以及定长环形子队列。其中，定长环形子队列被配置为存储数据大小和数据在变长环形子队列中的存储位置，而变长环形子队列被配置为存储数据本身。
第一数据中包括的数据项可以为一个，也可以为多个，当第一数据中包括的数据项为多个时，可以依次将每个数据项分别存储于所述变长环形子队列中的独立存储空间内，并依次将每个数据项的数据大小，以及在变长环形子队列中的存储位置，分别存储于定长环形子队列中的独立存储空间内。
通过上述设置，可以实现对数据的高效存储，便于读取方计算核快速、准确的定位所需读取的数据。
在本公开的一个实施例中，将与写入方计算核对应的状态寄存器记录的公共存储区的数据读写状态进行更新，可以包括：在写入方计算核对应的状态寄存器中，获取与第一数据的类型对应的第一类状态寄存器；根据第一数据中包括的数据项数量，对第一类状态寄存器中存储的预设类型的数据在第一环形队列中的写入计数值进行更新。
数据项数量可以是第一数据中的数据项总数。
在本公开实施例中，可以先获取写入方计算核对应的状态寄存器，进而根据第一数据的数据类型，从写入方计算核对应的状态寄存器中确定与第一数据 的类型对应的第一类状态寄存器，确定第一数据中包括的数据项，以根据第一数据中包括的数据项数量，对第一类状态寄存器中存储的预设类型的数据在第一环形队列中的写入计数值进行更新。
通过第一数据的类型，以及第一数据的数据项数量可以准确地更新对第一环形队列中该类型的已写入数据的写入计数值。
示例性的，写入方计算核对应的状态寄存器中，包括有多个第一类状态寄存器，每个第一类状态寄存器被配置为存储写入方计算核对预设类型的数据的写入计数值。相应的，在获取第一数据的类型后，可以从全部的第一类状态寄存器中，获取与该类型对应的第一类状态寄存器。进而获取该第一类状态寄存器中存储的写入计数值，例如，可以为500，当确定第一数据的数据项数量为50后，可以确定将该第一类状态寄存器中存储的写入计数值更新为500+50＝550。
在本公开的一个实施例中，将第一数据写入第一环形队列中的变长环形子队列，并将第一数据的数据大小和第一数据在变长环形子队列中的存储位置，写入至第一环形队列中的定长环形子队列，可以包括：在第一数据中依次获取当前数据项，并获取当前数据项在第一环形队列中的当前写入计数值；根据当前写入计数值，在定长环形子队列中，定位定长存储区域；获取变长环形子队列的当前变长存储位置，并将当前变长存储位置和当前数据项的数据大小写入定长存储区域；根据当前变长存储位置，将当前数据项写入变长环形子队列，并按照当前数据项的数据大小，更新当前变长存储位置；返回执行在第一数据中依次获取当前数据项的操作，直至完成对全部数据项的处理。
当前数据项是第一数据中的，当前需要写入第一环形队列的数据项。当前写入计数值可以是写入方计算核在公共存储区中已写入数据项的当前计数值。定长存储区域可以是定长环形子队列中被配置为存储消息头的区域。当前变长存储位置可以是存储新的消息体的起始位置。
在本公开实施例中，可以从第一数据中依次获取当前数据项，并根据当前数据项的写入操作，对第一环形队列的当前写入计数值进行加一更新，进而根据更新的当前写入计数值以及定长环形子队列的定长存储区域总数，在定长环形子队列中定位定长存储区域，获取变长环形子队列的当前变长存储位置，并将当前变长存储位置和当前数据项的数据大小写入定长存储区域，以当前变长存储位置作为当前数据项的起始存储位置，将当前数据项写入变长环形子队列，并按照当前数据项的数据大小，更新当前变长存储位置，也即将当前数据项的末位数据在变长环形子队列的存储位置的下一个存储位置作为当前变长存储位置，进而返回执行在第一数据中依次获取当前数据项的操作，直至完成对全部数据项的处理，通过定长环形子队列以及变长环形子队列的协作，能够记录第 一数据的写入情况，便于读取方计算核读取第一数据。
在一个示例中，图2B是本公开实施例提供的另一种数据交换方法的流程图，如图2B所示，所述方法包括：
S2100、在满足数据交换条件的情况下，获取待写入公共存储区的第一数据。
S2110、根据第一数据的类型，在公共存储区中，获取为写入方计算核分配的第一环形队列。
S2120、在第一数据中依次获取当前数据项，并获取当前数据项在第一环形队列中的当前写入计数值。
S2130、根据当前写入计数值，在定长环形子队列中，定位定长存储区域。
S2140、获取变长环形子队列的当前变长存储位置，并将当前变长存储位置和当前数据项的数据大小写入定长存储区域。
S2150、根据当前变长存储位置，将当前数据项写入变长环形子队列，并按照当前数据项的数据大小，更新当前变长存储位置。
S2160、检测是否完成对第一数据中全部数据项的处理，若完成对第一数据中全部数据项的处理，执行S2170；若未完成对第一数据中全部数据项的处理，返回执行S2120。
S2170、在可见状态寄存器列表中，识别与写入方计算核对应的状态寄存器。
S2180、在写入方计算核对应的状态寄存器中，获取与第一数据的类型对应的第一类状态寄存器。
S2190、根据第一数据中包括的数据项数量，对第一类状态寄存器中存储的预设类型的数据在第一环形队列中的写入计数值进行更新。
S2200、在可见中断寄存器列表中，识别与读取方计算核对应的中断寄存器，并触发中断寄存器产生中断信号。
本公开实施例的技术方案，通过在满足数据交换条件的情况下，获取待写入公共存储区的第一数据，进而根据第一数据的类型，在公共存储区中，获取为写入方计算核分配的第一环形队列，并在第一数据中依次获取当前数据项，获取当前数据项在第一环形队列中的当前写入计数值，进而根据当前写入计数值，在定长环形子队列中，定位定长存储区域。获取变长环形子队列的当前变长存储位置，并将当前变长存储位置和当前数据项的数据大小写入定长存储区域，根据当前变长存储位置，将当前数据项写入变长环形子队列，并按照当前数据项的数据大小，更新当前变长存储位置，检测是否完成对第一数据中全部数据项的处理，若完成对第一数据中全部数据项的处理，则在可见状态寄存器 列表中，识别与写入方计算核对应的状态寄存器；若未完成对第一数据中全部数据项的处理，返回执行在第一数据中依次获取当前数据项，并获取当前数据项在第一环形队列中的当前写入计数值。在写入方计算核对应的状态寄存器中，获取与第一数据的类型对应的第一类状态寄存器，根据第一数据中包括的数据项数量，对第一类状态寄存器中存储的预设类型的数据在第一环形队列中的写入计数值进行更新，在可见中断寄存器列表中，识别与读取方计算核对应的中断寄存器，并触发中断寄存器产生中断信号。本公开方案无需构建复杂的集中式或分布式同步单元，仅通过配置简单的中断寄存器和状态寄存器，即可实现复杂的数据同步技术，降低了硬件设计复杂性，减少了芯片的计算时延，保证了芯片整体频率的提升，可以广泛适用于对功耗以及成本敏感的微控制单元领域。
在一个示例中，图3A是本公开实施例提供的另一种数据交换方法的流程图，本实施例可适用于低延时数据交换的情况，该方法可以由数据交换装置来执行，该装置可以由软件和硬件中的至少一项的方式来实现，并一般可集成在如本公开任一实施例所述多核电路的读取方计算核中。相应的，如图3A所示，该方法包括如下操作：
S310、在读取方计算核对应的中断寄存器产生中断信号的情况下，获取读取方计算核对应的状态寄存器记录的公共存储区的数据读写状态。
中断信号是写入方计算核在满足数据交换条件的情况下，将第二数据写入公共存储区后触发读取方计算核对应的中断寄存器产生的。
在本公开实施例中，当前计算核作为读取方计算核时，写入方计算核将第二数据写入公共存储区后，也即写入方计算核在满足数据交换条件的情况下，可以触发当前计算核对应的中断寄存器产生中断信号。在当前计算核对应的中断寄存器产生中断信号时，当前计算核可以读取本核的状态寄存器记录的公共存储区的数据读写状态。
在本公开的一个实施例中，获取读取方计算核对应的状态寄存器记录的公共存储区的数据读写状态，包括：在可见状态寄存器列表中，识别与读取方计算核对应的第一状态寄存器，并识别与写入方计算核对应的第二状态寄存器；获取与第一状态寄存器和第二状态寄存器分别对应的数据读写状态。
第一状态寄存器可以是记录读取方计算核的数据读写状态的状态寄存器。第二状态寄存器可以是记录写入方计算核数据读写状态的状态寄存器。
在本公开实施例中，在获取到可见状态寄存器列表后，可以根据可见状态寄存器列表，识别出属于当前计算核(也即读取方计算核)的第一状态寄存器， 并识别属于写入方计算核的第二状态寄存器，进而分别对第一状态寄存器和第二状态寄存器存储的数据进行识别，得到与第一状态寄存器和第二状态寄存器分别对应的数据读写状态，也即得到当前计算核的数据读写状态和写入方计算核的数据读写状态，从而能够准确判断计算核的数据读写状态。
S320、根据获取的数据读写状态，从公共存储区读取写入方计算核写入的第二数据。
在本公开实施例中，读取方计算核可以根据状态寄存器存储的数据读写状态，从公共存储区读取写入方计算核写入的第二数据。
本公开实施例的技术方案，在读取方计算核对应的中断寄存器产生中断信号的情况下，通过读取方计算核获取读取方计算核对应的状态寄存器记录的公共存储区的数据读写状态，进而根据获取的数据读写状态，从公共存储区读取写入方计算核写入的第二数据，以实现读取方计算核对写入方计算核写入的第二数据的读取，不需要复杂的电路以及总线结构，仅通过状态寄存器以及中断寄存器即可完成计算核的数据交互，降低了硬件设计复杂性，减少了芯片的计算时延，保证了芯片整体频率的提升，可以广泛适用于对功耗以及成本敏感的微控制单元领域。
在本公开的一个实施例中，根据获取的数据读写状态，从公共存储区读取写入方计算核写入的第二数据，可以包括：在公共存储区中，获取与写入方计算核对应的第二环形队列；根据数据读写状态，从第二环形队列中读取写入方计算核写入的第二数据。
第二环形队列可以是公共存储区中，为写入方计算核分配的一段存储区域，被配置为写入方计算核写入所需进行核间交换的数据。
在本公开实施例中，读取方计算核需要先确定在公共存储区为写入方计算核分配的第二环形队列，进而获取本核(也即读取方计算核)的数据读取状态，以及写入方计算核的第二数据的写入状态，从第二环形队列中读取写入方计算核写入的第二数据，从而准确定位需要读取的第二数据。
在本公开的一个实施例中，根据数据读写状态，从第二环形队列中读取写入方计算核写入的第二数据，可以包括：按照多个第二环形队列所存储数据的数据处理优先级，在多个第二环形队列中，依次获取当前队列；在数据读写状态中，获取读取方计算核针对当前队列的目标数据读取状态，和写入方计算核针对当前队列的目标数据写入状态；根据目标数据读取状态和目标数据写入状态，确定当前队列中是否存储第二数据；若当前队列中存储第二数据，则从当前队列中，读取第二数据；若当前队列中未存储第二数据，则返回执行依次获 取当前队列的操作。
当前队列可以是未处理的第二环形队列中，存储有数据处理最高优先级的数据的队列。目标数据读取状态可以是读取方计算核对当前队列中数据项的读取状态。目标数据写入状态可以是写入方计算核在当前队列中针对数据项的写入状态。
在本公开实施例中，读取方计算核可以先确定多个第二环形队列存储数据的数据处理优先级，进而按照多个第二环形队列所存储数据的数据处理优先级(如优先级由高到低的顺序)，在多个第二环形队列中，依次获取当前队列，进而根据获取的数据读写状态，确定本核针对当前队列的目标数据读取状态，和写入方计算核针对当前队列的目标数据写入状态。读取方计算核可以对目标数据读取状态和目标数据写入状态进行分析，以确定写入方计算核在当前队列是否存储了第二数据，也即当前队列是否写入新数据，如果写入方计算核在当前队列存储了第二数据，则根据目标数据读取状态和目标数据写入状态读取第二数据。如果写入方计算核未在当前队列存储第二数据，则返回执行依次获取当前队列的操作，从而准确定位需要读取的第二数据。
在本公开的一个实施例中，在数据读写状态中，获取读取方计算核针对当前队列的目标数据读取状态，和写入方计算核针对当前队列的目标数据写入状态，可以包括：根据当前队列中存储数据的类型，在与读取方计算核对应的第一状态寄存器中，获取目标第二类状态寄存器，并在与写入方计算核对应的第二状态寄存器中，获取目标第一类状态寄存器；获取目标第二类状态寄存器中存储的读取方计算核对当前队列的目标读取计数值；获取目标第一类状态寄存器中存储的写入方计算核对当前队列的目标写入计数值。
目标第二类状态寄存器可以是与读取方计算核对应的第一状态寄存器中，被配置为记录所属的读取方计算核对写入方计算核中当前队列存储数据的读取计数值的状态寄存器。目标第一类状态寄存器可以是与写入方计算核对应的第二状态寄存器中，被配置为存储所属的写入方计算核在当前队列的写入数据的写入计数值的状态寄存器。目标读取计数值可以是读取方计算核对当前队列数据项的读取计数值。目标写入计数值可以是写入方计算核在当前队列写入数据项的写入计数值。
在本公开实施例中，读取方计算核可以按照当前队列中存储数据的类型，在与读取方计算核对应的第一状态寄存器中，获取目标第二类状态寄存器，并在与写入方计算核对应的第二状态寄存器中，获取目标第一类状态寄存器，读取目标第二类状态寄存器中存储的读取方计算核对当前队列的目标读取计数值，以及目标第一类状态寄存器中存储的写入方计算核对当前队列的目标写入计数 值，从而能够确定本核的数据读取状态以及写入方计算核的数据写入状态，便于本核准确定位需要读取的第二数据。
在本公开的一个实施例中，根据目标数据读取状态和目标数据写入状态，确定当前队列中是否存储第二数据，包括：如果确定目标读取计数值小于目标写入计数值，则确定当前队列中存储第二数据。
在本公开实施例中，读取方计算核可以将获取的目标读取计数值与目标写入计数值进行比较，如果目标读取计数值小于目标写入计数值，则表明当前队列中存储第二数据，如果目标读取计数值等于目标写入计数值，则表明当前队列中未存储第二数据，也即仅需比较目标读取计数值以及目标写入计数值，就可以确定当前队列中是否存储第二数据，而无需复杂的数据分析，简化算法复杂度。
在本公开的一个实施例中，从当前队列中，读取第二数据，包括：对目标第二类状态寄存器中的目标读取计数值进行加一更新；根据更新后的目标读取计数值，在当前队列的定长环形子队列中，定位历史存储区域；在历史存储区域中，获取历史变长存储位置以及目标数据大小；根据历史变长存储位置以及目标数据大小，在当前队列的变长环形子队列中，读取第二数据中的一个数据项；如果确定更新后的目标读取计数值小于目标写入计数值，则返回执行对目标第二类状态寄存器中的目标读取计数值进行加一更新的操作，直至完成对第二数据的完整读取。
历史存储区域是由读取计数值确定的，读取方计算核需要读取的数据项的前一个数据项的相关信息，在定长环形子队列的存储区域。历史变长存储位置可以是变长环形子队列中，存储读取方计算核需要读取的数据项的前一个数据项的起始位置。目标数据可以是与历史存储区域匹配的写入方计算核写入公共存储区的数据项。
在本公开实施例中，读取方计算核可以对目标第二类状态寄存器中的目标读取计数值进行加一更新，根据更新后的目标读取计数值以及定长环形子队列的定长存储区域总数，在当前队列的定长环形子队列中，定位历史存储区域，解析历史存储区域中的数据，得到历史变长存储位置以及目标数据大小进行求和，进而根据求和结果在当前队列的变长环形子队列中，读取第二数据中的一个数据项。在读取第二数据中的一个数据项之后，读取方计算核可以将更新后的目标读取计数值与目标写入计数值进行比较，如果目标读取计数值小于目标写入计数值，则返回执行对目标第二类状态寄存器中的目标读取计数值进行加一更新的操作，直至完成对第二数据的完整读取，从而实现对所需读取的第二数据中数据项的自动读取。
在本公开实施例中，数据交换方法，由多核电路中的读取方计算核执行，还可以包括：预先注册不同类型的处理函数，用于处理不同类型的数据；在从公共存储区读取写入方计算核写入的第二数据之后，还包括：根据第二数据的类型，调用匹配的处理函数进行数据处理。
处理函数可以是能够对公共存储区的数据进行数据处理的函数，本公开实施例对处理函数的类型不做限定，只要能实现计算核的所需功能即可。
在本公开实施例中，可以根据读取方计算核需要实现的功能预先注册不同类型的处理函数，以基于不同的处理函数对公共存储区的不同类型的数据进行处理，读取方计算核可以从公共存储区读取写入方计算核写入的第二数据，确定第二数据的数据类型，进而调用与第二数据的数据类型匹配的处理函数，从而通过处理函数对第二数据进行处理，以实现当前计算核的相应功能。通过处理函数替代传统的功能性编码可以防止由于编码人员无法得知全局编码信息，而导致的代码无法准确处理数据的情况。
一实施例中，读取方计算核通过注册的方式将处理函数注册到消息调度器。消息调度器可以根据第二数据的数据类型调用相应的处理函数。消息头中保存有消息体的循环冗余校验(Cyclic Redundancy Check，CRC)值，使用者可以根据CRC值判断当前消息体中的消息体是否被覆盖。注册到计算核1(CORE1)消息调度系统中的处理函数可以参见图4。
在一个示例中，图3B是本公开实施例提供的另一种数据交换方法的流程图，如图3B所示，所述方法包括：
S3100、在读取方计算核对应的中断寄存器产生中断信号的情况下，在可见状态寄存器列表中，识别与读取方计算核对应的第一状态寄存器，并识别与写入方计算核对应的第二状态寄存器。
S3110、获取与第一状态寄存器和第二状态寄存器分别对应的数据读写状态。
S3120、在公共存储区中，获取与写入方计算核对应的第二环形队列。
S3130、按照多个第二环形队列所存储数据的数据处理优先级，在多个第二环形队列中，依次获取当前队列。
S3140、根据当前队列中存储数据的类型，在与读取方计算核对应的第一状态寄存器中，获取目标第二类状态寄存器，并在与写入方计算核对应的第二状态寄存器中，获取目标第一类状态寄存器。
S3150、获取目标第二类状态寄存器中存储的读取方计算核对当前队列的目标读取计数值。
S3160、获取目标第一类状态寄存器中存储的写入方计算核对当前队列的目标写入计数值。
S3170、判断目标读取计数值是否小于目标写入计数值，若目标读取计数值小于目标写入计数值，则执行S3180；若目标读取计数值不小于目标写入计数值，返回执行S3130。
S3180、从当前队列中，读取第二数据。
本公开实施例的技术方案，通过在读取方计算核对应的中断寄存器产生中断信号的情况下，在可见状态寄存器列表中，识别与读取方计算核对应的第一状态寄存器，并识别与写入方计算核对应的第二状态寄存器，进而获取与第一状态寄存器和第二状态寄存器分别对应的数据读写状态，从而在公共存储区中，获取与写入方计算核对应的第二环形队列，并按照多个第二环形队列所存储数据的数据处理优先级，在多个第二环形队列中，依次获取当前队列，以根据当前队列中存储数据的类型，在与读取方计算核对应的第一状态寄存器中，获取目标第二类状态寄存器，并在与写入方计算核对应的第二状态寄存器中，获取目标第一类状态寄存器。获取目标第二类状态寄存器中存储的读取方计算核对当前队列的目标读取计数值，并获取目标第一类状态寄存器中存储的写入方计算核对当前队列的目标写入计数值，判断目标读取计数值是否小于目标写入计数值，若目标读取计数值小于目标写入计数值，则从当前队列中，读取第二数据；若目标读取计数值不小于目标写入计数值，返回执行按照多个第二环形队列所存储数据的数据处理优先级的操作。本公开方案无需构建复杂的集中式或分布式同步单元，仅通过配置简单的中断寄存器和状态寄存器，即可实现复杂的数据同步技术，降低了硬件设计复杂性，减少了芯片的计算时延，保证了芯片整体频率的提升，可以广泛适用于对功耗以及成本敏感的微控制单元领域。
在本公开的一个示例中，双核数字信号处理芯片可以设计2个中断寄存器、8个状态寄存器，且所有的寄存器对双核均可见，方便软件设置通讯模式。计算核0(CORE0)需要通知计算核1(CORE1)，则设置IPC中断寄存器1触发CORE1产生IPC中断；CORE1需要通知CORE0，则设置IPC中断寄存器0触发CORE0产生IPC中断。双核在触发IPC中断之前，会把需要传递的数据写入公共的静态随机存取寄存器(Static Random Access Memory，SRAM)区域，也即公共存储区。双核数字信号处理芯片需要进行数据同步时，可以会将数据打包成消息的形式，放入环形队列。上行链路和下行链路分别持有自己的消息队列。消息队列为环形队列，有缓存消息的功能，以便协调双核不同的处理数据能力，双核数字信号处理芯片的数据交换示意图如图5所示。
双核数字信号处理芯片通信是双工的，双方同时作为消息的生产者和消费 者，各自持有自己和对方的第一已写入计数值以及已读取计数值。计算核0产生新数据，并向计算核1发送时(图中的上行链路)，计算核0的第一已写入计数值会自增1，并将第一已写入计数值的值填入IPC状态寄存器0，然后触发IPC中断，退出数据处理程序，进而通知计算核1有新消息需要处理。计算核1进入IPC中断服务程序后，从IPC状态寄存器0读出计算核0产生的第一已写入计数值，退出IPC中断服务程序，然后判断第一已写入计数值与已读取计数值(计算核1保存的)是否相等，如果第一已写入计数值与已读取计数值不相等，计算核1将不断处理未处理的数据，已读取计数值加1，直到所有的数据都处理完毕，计算核0的数据处理过程参见图6，计算核1的数据处理过程参见图7。
传递消息时，数据的长度会因数据不同而占用长度不等的内存空间。为了提高内存空间的利用率，通过环形队列存储数据，以支持变长数据的消息结构。消息由消息头和消息体组成，消息头结构固定，消息体长度可变。消息头中保存了消息体在变长环形子队列中的变长存储位置和数据大小。处理器为了协调CPU运行速度和外设输入/输出(Input/Output，I/O)速度之前的巨大差距往往会设计多级缓存，鉴于cacheline长度的因素，为了方便cache回写和刷新，消息体长度设计为64B*N。消息头和消息体分别存放在SRAM，由其中一个DSP核心维护。消息头条数和消息体总长度可配置。消息头和消息体均为环形队列。消息结构在环形队列中的分布如图8所示，所示，定长环形子队列的第10条数据存储的是在变长环形子队列中存储的第10个消息体的存储的起始位置(0x60050000)以及消息体的大小(40B，还需补齐24B)，定长环形子队列的第11条数据存储的是在变长环形子队列中存储的第11个消息体的存储的起始位置(0x60050020)以及消息体的大小(85B，还需补齐43B)，定长环形子队列的第12条数据存储的是在变长环形子队列中存储的第12个消息体的存储的起始位置(0x60050060)以及消息体的大小(122B，还需补齐6B)。
双核数字信号处理芯片在进行数据交换之前，会在消息头和消息体约定数据在公共存储区中存储的起始地址。读取方计算核就可以根据写入方计算核的第一已写入计数值获取到消息头信息，然后从消息头信息中读取消息体的信息，如消息体位置(变长存储位置)，数据体大小等等。
本公开实施例还提供了一种数据交换装置，由多核电路中的写入方计算核执行，被配置为执行上述的数据交换方法。
图9是本公开实施例提供的一种数据交换装置的示意图，如图9所示，该装置包括：第一数据写入模块410以及中断信号触发模块420，其中：
第一数据写入模块410，被配置为在满足数据交换条件的情况下，将第一数据写入公共存储区；中断信号触发模块420，被配置为触发读取方计算核对应的 中断寄存器产生中断信号；其中，所述中断信号用于指示读取方计算核获取所对应状态寄存器记录的公共存储区的数据读写状态，并根据所述数据读写状态从公共存储区读取所述第一数据。
本公开实施例的技术方案，通过写入方计算核在满足数据交换条件的情况下，将第一数据写入公共存储区，触发读取方计算核对应的中断寄存器产生中断信号，实现读取方计算核对第一数据的读取，不需要复杂的电路以及总线结构，仅通过状态寄存器以及中断寄存器即可完成计算核的数据交互，降低了硬件设计复杂性，减少了芯片的计算时延，保证了芯片整体频率的提升，可以广泛适用于对功耗以及成本敏感的微控制单元领域。
一实施例中，中断信号触发模块420，被配置为将与写入方计算核对应的状态寄存器记录的公共存储区的数据读写状态进行更新，并触发读取方计算核对应的中断寄存器产生中断信号。
一实施例中，中断信号触发模块420，被配置为在可见状态寄存器列表中，识别与写入方计算核对应的状态寄存器，并对所述状态寄存器记录的公共存储区的数据读写状态进行更新；在可见中断寄存器列表中，识别与读取方计算核对应的中断寄存器，并触发所述中断寄存器产生中断信号。
一实施例中，第一数据写入模块410，被配置为在所述公共存储区中，获取为写入方计算核分配的第一环形队列；将所述第一数据写入至所述第一环形队列中。
一实施例中，第一数据写入模块410，被配置为根据所述第一数据的类型，在所述公共存储区中，获取为写入方计算核分配的第一环形队列。
一实施例中，第一数据写入模块410，被配置为将所述第一数据写入所述第一环形队列中的变长环形子队列，并将所述第一数据的数据大小和所述第一数据在所述变长环形子队列中的存储位置，写入至所述第一环形队列中的定长环形子队列。
一实施例中，中断信号触发模块420，被配置为在写入方计算核对应的状态寄存器中，获取与所述第一数据的类型对应的第一类状态寄存器；根据所述第一数据中包括的数据项数量，对所述第一类状态寄存器中存储的所述预设类型的数据在第一环形队列中的写入计数值进行更新。
一实施例中，第一数据写入模块410，被配置为在所述第一数据中依次获取当前数据项，并获取所述当前数据项在所述第一环形队列中的当前写入计数值；根据所述当前写入计数值，在所述定长环形子队列中，定位定长存储区域；获取所述变长环形子队列的当前变长存储位置，并将所述当前变长存储位置和所 述当前数据项的数据大小写入所述定长存储区域；根据所述当前变长存储位置，将所述当前数据项写入变长环形子队列，并按照当前数据项的数据大小，更新当前变长存储位置；返回执行在第一数据中依次获取当前数据项的操作，直至完成对全部数据项的处理。
本公开实施例还提供了一种数据交换装置，由多核电路中的读取方计算核执行，被配置为执行上述的数据交换方法。
图10是本公开实施例提供的另一种数据交换装置的示意图，如图10所示，该装置包括：数据读写状态获取模块510以及第二数据读取模块520，其中：
数据读写状态获取模块510，被配置为在读取方计算核对应的中断寄存器产生中断信号的情况下，获取读取方计算核对应的状态寄存器记录的公共存储区的数据读写状态；其中，所述中断信号是写入方计算核在满足数据交换条件的情况下，将第二数据写入公共存储区后触发读取方计算核对应的中断寄存器产生的；第二数据读取模块520，被配置为根据获取的所述数据读写状态，从公共存储区读取写入方计算核写入的第二数据。
本公开实施例的技术方案，通过读取方计算核在读取方计算核对应的中断寄存器产生中断信号的情况下，获取读取方计算核对应的状态寄存器记录的公共存储区的数据读写状态，进而根据获取的数据读写状态，从公共存储区读取写入方计算核写入的第二数据，以实现读取方计算核对写入方计算核写入的第二数据的读取，不需要复杂的电路以及总线结构，仅通过状态寄存器以及中断寄存器即可完成计算核的数据交互，降低了硬件设计复杂性，减少了芯片的计算时延，保证了芯片整体频率的提升，可以广泛适用于对功耗以及成本敏感的微控制单元领域。
一实施例中，数据读写状态获取模块510，被配置为在可见状态寄存器列表中，识别与读取方计算核对应的第一状态寄存器，并识别与写入方计算核对应的第二状态寄存器；获取与所述第一状态寄存器和所述第二状态寄存器分别对应的数据读写状态。
一实施例中，第二数据读取模块520，被配置为在所述公共存储区中，获取与写入方计算核对应的第二环形队列；根据所述数据读写状态，从所述第二环形队列中读取所述写入方计算核写入的第二数据。
一实施例中，第二数据读取模块520，被配置为按照多个第二环形队列所存储数据的数据处理优先级，在多个第二环形队列中，依次获取当前队列；在所述数据读写状态中，获取读取方计算核针对所述当前队列的目标数据读取状态，和写入方计算核针对所述当前队列的目标数据写入状态；根据所述目标数据读 取状态和所述目标数据写入状态，确定所述当前队列中是否存储所述第二数据；若所述当前队列中存储所述第二数据，则从所述当前队列中，读取所述第二数据；若所述当前队列中未存储所述第二数据，则返回执行依次获取当前队列的操作。
一实施例中，第二数据读取模块520，被配置为根据当前队列中存储数据的类型，在与读取方计算核对应的第一状态寄存器中，获取目标第二类状态寄存器，并在与所述写入方计算核对应的第二状态寄存器中，获取目标第一类状态寄存器；获取所述目标第二类状态寄存器中存储的读取方计算核对当前队列的目标读取计数值；获取所述目标第一类状态寄存器中存储的写入方计算核对当前队列的目标写入计数值。
一实施例中，第二数据读取模块520，被配置为如果确定所述目标读取计数值小于所述目标写入计数值，则确定所述当前队列中存储所述第二数据。
一实施例中，第二数据读取模块520，被配置为对所述目标第二类状态寄存器中的目标读取计数值进行加一更新；根据更新后的目标读取计数值，在当前队列的定长环形子队列中，定位历史存储区域；在历史存储区域中，获取历史变长存储位置以及目标数据大小；根据历史变长存储位置以及目标数据大小，在当前队列的变长环形子队列中，读取第二数据中的一个数据项；如果确定所述更新后的目标读取计数值小于所述目标写入计数值，则返回执行对所述目标第二类状态寄存器中的目标读取计数值进行加一更新的操作，直至完成对第二数据的完整读取。
如图11所示，一实施例中，数据交换装置还包括处理函数注册模块530，被配置为预先注册不同类型的处理函数，用于处理不同类型的数据。
如图12所示，一实施例中，数据交换装置还包括数据处理模块540，被配置为根据所述第二数据的类型，调用匹配的处理函数进行数据处理。
本公开的技术方案中，所涉及的数据等的获取，存储和应用等，均符合相关法律法规的规定，且不违背公序良俗。
根据本公开的实施例，本公开还提供了一种电子设备、一种可读存储介质和一种计算机程序产品，以实现上述的数据交换方法。
图13是本公开实施例提供的一种实现数据交换方法的电子设备的示意性框图。电子设备旨在表示多种形式的数字计算机，诸如，膝上型计算机、台式计算机、工作台、个人数字助理、服务器、刀片式服务器、大型计算机、和其它适合的计算机。电子设备还可以表示多种形式的移动装置，诸如，个人数字处理、蜂窝电话、智能电话、可穿戴设备和其它类似的计算装置。本文所示的部 件、它们的连接和关系、以及它们的功能仅仅作为示例，并且不意在限制本文中描述的和/或者要求的本公开的实现。
如图13所示，电子设备600包括多核电路601，其可以根据存储在只读存储器(Read-Only Memory，ROM)602中的计算机程序或者从存储单元608加载到随机访问存储器(Random Access Memory，RAM)603中的计算机程序，来执行多种适当的动作和处理。在RAM 603中，还可存储电子设备600操作所需的多种程序和数据。多核电路601、ROM 602以及RAM 603通过总线604彼此相连。I/O接口605也连接至总线604。ROM 602以及存储单元608可以存储被多核电路601执行的数据交换方法。多核电路601中的计算核被配置为：在满足数据交换条件的情况下，将第一数据写入公共存储区，并触发其他计算核对应的中断寄存器产生中断信号；或者，在该计算核对应的中断寄存器产生中断信号的情况下，根据该计算核对应的状态寄存器记录的公共存储区的数据读写状态，从公共存储区读取其他计算核写入的第二数据。
电子设备600中的多个部件连接至I/O接口605，包括：输入单元606，例如键盘、鼠标等；输出单元607，例如多种类型的显示器、扬声器等；存储单元608，例如磁盘、光盘等；以及通信单元609，例如网卡、调制解调器、无线通信收发机等。通信单元609允许电子设备600通过诸如因特网的计算机网络和/或多种电信网络与其他设备交换信息/数据。
多核电路601可以是多种具有处理和计算能力的通用和/或专用处理组件。多核电路601的一些示例包括但不限于CPU、图形处理单元(Graphics Processing Unit，GPU)、多种专用的人工智能(Artificial Intelligence，AI)计算芯片、多种运行机器学习模型算法的计算核、DSP、以及任何适当的处理器、控制器、微控制器等。多核电路601执行上文所描述的多个方法和处理，例如数据交换方法。例如，在一些实施例中，数据交换方法可被实现为计算机软件程序，其被有形地包含于机器可读介质，例如存储单元608。在一些实施例中，计算机程序的部分或者全部可以经由ROM 602和/或通信单元609而被载入和/或安装到电子设备600上。当计算机程序加载到RAM 603并由多核电路601执行时，可以执行上文描述的数据交换方法的一个或多个步骤。备选地，在其他实施例中，多核电路601可以通过其他任何适当的方式(例如，借助于固件)而被配置为执行数据交换方法。
本文中以上描述的系统和技术的多种实施方式可以在数字电子电路系统、集成电路系统、现场可编程门阵列(Field Programmable Gate Array，FPGA)、专用集成电路(Application Specific Integrated Circuit，ASIC)、专用标准产品(Application Specific Standard Parts，ASSP)、芯片上的系统(System on Chip， SOC)、复杂可编程逻辑设备(Complex Programmable Logic Device，CPLD)、计算机硬件、固件、软件、和/或它们的组合中实现。多种实施方式可以包括：实施在一个或者多个计算机程序中，该一个或者多个计算机程序可在包括至少一个可编程处理器的可编程系统上执行和/或解释，该可编程处理器可以是专用或者通用可编程处理器，可以从存储系统、至少一个输入装置、和至少一个输出装置接收数据和指令，并且将数据和指令传输至该存储系统、该至少一个输入装置、和该至少一个输出装置。
用于实施本公开的方法的程序代码可以采用一个或多个编程语言的任何组合来编写。这些程序代码可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器或控制器，使得程序代码当由处理器或控制器执行时使流程图和/或框图中所规定的功能/操作被实施。程序代码可以完全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。
在本公开的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、RAM、ROM、可擦除可编程只读存储器(Erasable Programmable Read-Only Memory，EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(Compact Disc Read-Only Memory，CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
为了提供与用户的交互，可以在计算机上实施此处描述的系统和技术，该计算机具有：被配置为向用户显示信息的显示装置(例如，阴极射线管(Cathode Ray Tube，CRT)或者液晶显示器(Liquid Crystal Display，LCD)监视器)；以及键盘和指向装置(例如，鼠标或者轨迹球)，用户可以通过该键盘和该指向装置来将输入提供给计算机。其它种类的装置还可以被配置为提供与用户的交互；例如，提供给用户的反馈可以是任何形式的传感反馈(例如，视觉反馈、听觉反馈、或者触觉反馈)；并且可以用任何形式(包括声输入、语音输入或者、触觉输入)来接收来自用户的输入。
可以将此处描述的系统和技术实施在包括后台部件的计算系统(例如，作为数据服务器)、或者包括中间件部件的计算系统(例如，应用服务器)、或者包括前端部件的计算系统(例如，具有图形用户界面或者网络浏览器的用户 计算机，用户可以通过该图形用户界面或者该网络浏览器来与此处描述的系统和技术的实施方式交互)、或者包括这种后台部件、中间件部件、或者前端部件的任何组合的计算系统中。可以通过任何形式或者介质的数字数据通信(例如，通信网络)来将系统的部件相互连接。通信网络的示例包括：局域网(Local Area Network，LAN)、广域网(Wide Area Network，WAN)和互联网。
计算机系统可以包括客户端和服务器。客户端和服务器一般远离彼此并且通常通过通信网络进行交互。通过在相应的计算机上运行并且彼此具有客户端-服务器关系的计算机程序来产生客户端和服务器的关系。服务器可以是云服务器，又称为云计算服务器或云主机，是云计算服务体系中的一项主机产品，以解决了传统物理主机与虚拟专用服务器(Virtual Private Server，VPS)服务中，存在的管理难度大，业务扩展性弱的缺陷。服务器也可以为分布式系统的服务器，或者是结合了区块链的服务器。
可以使用上面所示的多种形式的流程，重新排序、增加或删除步骤。例如，本公开中记载的多个步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本公开公开的技术方案所期望的结果，本文在此不进行限制。

Claims (25)

  1. 一种多核电路，包括：
    公共存储区；
    多个中断寄存器；
    多个状态寄存器；以及
    多个计算核，每个计算核被配置为：在满足数据交换条件的情况下，将第一数据写入公共存储区，并触发所述多个计算核中除所述每个计算核外的计算核对应的中断寄存器产生中断信号；或者，在所述每个计算核对应的中断寄存器产生中断信号的情况下，根据所述每个计算核对应的状态寄存器记录的公共存储区的数据读写状态，从所述公共存储区读取所述多个计算核中除所述每个计算核外的计算核写入的第二数据。
  2. 根据权利要求1的多核电路，其中，所述多个中断寄存器和所述多个状态寄存器对每个计算核可见。
  3. 根据权利要求1的多核电路，其中，所述公共存储区中包括为每个计算核分配的环形队列，所述环形队列被配置为存储需要交换的数据。
  4. 根据权利要求3的多核电路，其中，所述公共存储区中包括为每个计算核分配的多个环形队列，每个环形队列被配置为存储预设类型的数据，不同类型的数据对应不同的数据处理优先级。
  5. 根据权利要求3的多核电路，其中，每个环形队列包括定长环形子队列以及变长环形子队列；
    所述定长环形子队列，被配置为存储数据在变长环形子队列的存储位置和数据大小；
    所述变长环形子队列，被配置为存储数据。
  6. 根据权利要求4的多核电路，其中，所述状态寄存器包括第一类状态寄存器或第二类状态寄存器；每个计算核对应至少一个第一类状态寄存器和至少一个第二类状态寄存器；
    所述第一类状态寄存器，被配置为存储所属计算核对预设类型的数据的写入计数值；
    所述第二类状态寄存器，被配置为存储所属计算核对所述多个计算核中除所述所属计算核外的计算核中预设类型的数据的读取计数值。
  7. 根据权利要求1-6任一项的多核电路，其中，所述多核电路为双核数字信号处理芯片。
  8. 一种数据交换方法，由多核电路中的写入方计算核执行，包括：
    在满足数据交换条件的情况下，将第一数据写入公共存储区；
    触发读取方计算核对应的中断寄存器产生中断信号；
    其中，所述中断信号用于指示所述读取方计算核获取所对应状态寄存器记录的所述公共存储区的数据读写状态，并根据所述数据读写状态从所述公共存储区读取所述第一数据。
  9. 根据权利要求8所述的方法，其中，所述触发读取方计算核对应的中断寄存器产生中断信号，包括：
    将与所述写入方计算核对应的状态寄存器记录的公共存储区的数据读写状态进行更新，并触发所述读取方计算核对应的中断寄存器产生中断信号。
  10. 根据权利要求9所述的方法，其中，所述将与所述写入方计算核对应的状态寄存器记录的公共存储区的数据读写状态进行更新，并触发所述读取方计算核对应的中断寄存器产生中断信号，包括：
    在可见状态寄存器列表中，识别与所述写入方计算核对应的状态寄存器，并对所述状态寄存器记录的公共存储区的数据读写状态进行更新；
    在可见中断寄存器列表中，识别与所述读取方计算核对应的中断寄存器，并触发所述中断寄存器产生中断信号。
  11. 根据权利要求9所述的方法，其中，所述将第一数据写入公共存储区，包括：
    在所述公共存储区中，获取为所述写入方计算核分配的第一环形队列；
    将所述第一数据写入至所述第一环形队列中。
  12. 根据权利要求11所述的方法，其中，所述在所述公共存储区中，获取为所述写入方计算核分配的第一环形队列，包括：
    根据所述第一数据的类型，在所述公共存储区中，获取为所述写入方计算核分配的第一环形队列。
  13. 根据权利要求11所述的方法，其中，所述将所述第一数据写入至所述第一环形队列中，包括：
    将所述第一数据写入所述第一环形队列中的变长环形子队列，并将所述第一数据的数据大小和所述第一数据在所述变长环形子队列中的存储位置，写入至所述第一环形队列中的定长环形子队列。
  14. 根据权利要求12所述的方法，其中，所述将与所述写入方计算核对应 的状态寄存器记录的公共存储区的数据读写状态进行更新，包括：
    在所述写入方计算核对应的状态寄存器中，获取与所述第一数据的类型对应的第一类状态寄存器；
    根据所述第一数据中包括的数据项数量，对所述第一类状态寄存器中存储的预设类型的数据在第一环形队列中的写入计数值进行更新。
  15. 根据权利要求13所述的方法，其中，所述将所述第一数据写入所述第一环形队列中的变长环形子队列，并将所述第一数据的数据大小和所述第一数据在所述变长环形子队列中的存储位置，写入至所述第一环形队列中的定长环形子队列，包括：
    在所述第一数据中依次获取当前数据项，并获取所述当前数据项在所述第一环形队列中的当前写入计数值；
    根据所述当前写入计数值，在所述定长环形子队列中，定位定长存储区域；
    获取所述变长环形子队列的当前变长存储位置，并将所述当前变长存储位置和所述当前数据项的数据大小写入所述定长存储区域；
    根据所述当前变长存储位置，将所述当前数据项写入变长环形子队列，并按照当前数据项的数据大小，更新当前变长存储位置；
    返回执行在第一数据中依次获取当前数据项的操作，直至完成对全部数据项的处理。
  16. 一种数据交换方法，由多核电路中的读取方计算核执行，包括：
    在所述读取方计算核对应的中断寄存器产生中断信号的情况下，获取所述读取方计算核对应的状态寄存器记录的公共存储区的数据读写状态；其中，所述中断信号是写入方计算核在满足数据交换条件的情况下，将第二数据写入所述公共存储区后触发所述读取方计算核对应的中断寄存器产生的；
    根据获取的所述数据读写状态，从所述公共存储区读取所述写入方计算核写入的第二数据。
  17. 根据权利要求16所述的方法，其中，所述获取所述读取方计算核对应的状态寄存器记录的公共存储区的数据读写状态，包括：
    在可见状态寄存器列表中，识别与所述读取方计算核对应的第一状态寄存器，并识别与所述写入方计算核对应的第二状态寄存器；
    获取与所述第一状态寄存器和所述第二状态寄存器分别对应的数据读写状态。
  18. 根据权利要求17所述的方法，其中，所述根据获取的所述数据读写状态，从所述公共存储区读取所述写入方计算核写入的第二数据，包括：
    在所述公共存储区中，获取与所述写入方计算核对应的第二环形队列；
    根据所述数据读写状态，从所述第二环形队列中读取所述写入方计算核写入的第二数据。
  19. 根据权利要求18所述的方法，其中，所述根据所述数据读写状态，从所述第二环形队列中读取所述写入方计算核写入的第二数据，包括：
    按照多个第二环形队列所存储数据的数据处理优先级，在多个第二环形队列中，依次获取当前队列；
    在所述数据读写状态中，获取所述读取方计算核针对所述当前队列的目标数据读取状态，和所述写入方计算核针对所述当前队列的目标数据写入状态；
    根据所述目标数据读取状态和所述目标数据写入状态，确定所述当前队列中是否存储所述第二数据；
    响应于所述当前队列中存储所述第二数据，从所述当前队列中，读取所述第二数据；响应于所述当前队列中未存储所述第二数据，返回执行依次获取当前队列的操作。
  20. 根据权利要求19所述的方法，其中，所述在所述数据读写状态中，获取所述读取方计算核针对所述当前队列的目标数据读取状态，和所述写入方计算核针对所述当前队列的目标数据写入状态，包括：
    根据所述当前队列中存储数据的类型，在与所述读取方计算核对应的第一状态寄存器中，获取目标第二类状态寄存器，并在与所述写入方计算核对应的第二状态寄存器中，获取目标第一类状态寄存器；
    获取所述目标第二类状态寄存器中存储的所述读取方计算核对所述当前队列的目标读取计数值；
    获取所述目标第一类状态寄存器中存储的所述写入方计算核对所述当前队列的目标写入计数值。
  21. 根据权利要求20所述的方法，其中，所述根据所述目标数据读取状态和所述目标数据写入状态，确定所述当前队列中是否存储所述第二数据，包括：
    在确定所述目标读取计数值小于所述目标写入计数值的情况下，则确定所述当前队列中存储所述第二数据。
  22. 根据权利要求21所述的方法，其中，所述从所述当前队列中，读取所 述第二数据，包括：
    对所述目标第二类状态寄存器中的目标读取计数值进行加一更新；
    根据更新后的目标读取计数值，在所述当前队列的定长环形子队列中，定位历史存储区域；
    在所述历史存储区域中，获取历史变长存储位置以及目标数据大小；
    根据所述历史变长存储位置以及所述目标数据大小，在所述当前队列的变长环形子队列中，读取所述第二数据中的一个数据项；
    在确定所述更新后的目标读取计数值小于所述目标写入计数值的情况下，返回执行对所述目标第二类状态寄存器中的目标读取计数值进行加一更新的操作，直至完成对所述第二数据的完整读取。
  23. 根据权利要求16-22任一项所述的方法，还包括：
    预先注册不同类型的处理函数，用于处理不同类型的数据；
    在所述从所述公共存储区读取所述写入方计算核写入的第二数据之后，还包括：
    根据所述第二数据的类型，调用匹配的处理函数进行数据处理。
  24. 一种电子设备，包括：如权利要求1-7任一项所述的多核电路；以及
    与所述多核电路中至少一个计算核通信连接的存储器；其中，
    所述存储器存储有可被计算核执行的指令，指令被所述至少一个计算核执行，以使所述至少一个计算核能够执行权利要求8-23中任一项所述的数据交换方法。
  25. 一种存储有计算机指令的非瞬时计算机可读存储介质，其中，计算机指令用于使计算机执行权利要求8-23中任一项所述的数据交换方法。
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