WO2023191445A1

WO2023191445A1 - Three-dimensional stacked dram array and manufacturing method therefor

Info

Publication number: WO2023191445A1
Application number: PCT/KR2023/004099
Authority: WO
Inventors: 김윤
Original assignee: 서울시립대학교 산학협력단
Priority date: 2022-03-31
Filing date: 2023-03-28
Publication date: 2023-10-05
Also published as: KR20230141326A; KR102622628B1

Abstract

The present invention relates to a three-dimensional stacked DRAM array and a manufacturing method therefor, wherein, by vertically stacking a "U"-shaped drain-BL connection structure having two connection lines, a plurality of horizontal active lines are formed on one connection line while the plurality of horizontal active lines are stacked on the other connection line in a stepped shape and connected to bit lines, and accordingly, space can be efficiently used by sharing a ground electrode of a capacitor, and cell capacitance can be horizontally increased as much as possible and can be expanded as much as possible with a unit structure, such that difficulties in a metal wiring process such as bit lines due to vertical stacking can be solved.

Description

3D stacked DRAM array and manufacturing method thereof

The present invention relates to semiconductor memory DRAM (DRAM), and more specifically, to a three-dimensional stacked DRAM array and a method of manufacturing the same.

Currently, in DRAM technology, high integration through miniaturization of DRAM cells has reached its limit. 3D DRAM technology is attracting attention as a way to solve this problem.

A representative example is HBM (High-Bandwidth Memory), which stacks multiple DRAM chips and connects them with TSV (Through-Silicon Vias). At this time, each substrate (chip) constituting the HBM is composed of a single-layer array.

Another 3D DRAM technology is Monolithic 3D DRAM technology, which has an array structure in which the DRAM cells themselves are stacked within a single substrate (chip).

Regarding 3D DRAM technology, there are Korean registered patents 10-2237739, 10-2368332 and published patent 10-2021-0102094.

However, in the prior art, including the above patents, the capacitors of the stacked cells are limited to neighboring cells even if one electrode is independent or shared, and the capacitors are limited to those of cells stacked with word lines (WLs) or bit lines (BLs) in three dimensions. The contact and interconnection structure was not properly presented.

Accordingly, the present invention ensures that the capacitors of the stacked cells are shared as much as possible not only between the top and bottom electrodes, but also between cells stacked horizontally spaced apart, and how to make connections for operating each layer independently and metal wiring for this efficiently in a limited space. We would like to solve the problem of whether to configure it as .

In order to achieve the above object, the three-dimensional stacked DRAM array according to the present invention has two horizontally parallel connection lines, connected in the middle, and has a “ㄷ” shape, vertically spaced apart, and includes stacked Drain-BL Connection structures. , the Drain-BL Connection structures are spaced apart along the length direction of the one connection line in one of the two connection lines, and a plurality of horizontal active lines are formed perpendicular to the one connection line, and the two connection lines Another one of them is electrically connected to one of a plurality of bit lines, and the plurality of horizontal active lines are stacked vertically side by side as many as the number of the Drain-BL Connection structures and spaced apart along the length direction of the one connection line. and constitutes a plurality of active line blocks, each of the plurality of active line blocks having a gate pillar that jointly forms each gate of a plurality of cell transistors vertically stacked on one side and a plurality of cells spaced apart from the gate pillar. It is characterized by a common ground plate of capacitors connected to each of the transistors.

The common ground plate may include one that is symmetrically positioned and integrally formed between neighboring blocks among the plurality of active blocks.

The Drain-BL Connection structures are stacked vertically and the length of the other one of the connection lines gradually becomes smaller to form a step shape, and a unit structure is formed including the Drain-BL Connection structures forming the step shape, and the unit The plurality of bit lines may be electrically connected using the staircase shape in which two or more structures are arranged in the direction of word lines and repeat.

Each of the plurality of horizontal active lines may be composed of an active area where a cell transistor is formed and an electrode area of a capacitor connected to the active area.

The Drain-BL Connection structures and the electrode area of the capacitor may be formed of silicide.

One of a plurality of common ground plates surrounded by a plurality of separators and a cell capacitor dielectric is positioned between the plurality of active line blocks, and is vertically connected to the plurality of cell transistors, respectively. A plurality of capacitors are stacked symmetrically with one of the plurality of separators interposed therebetween, and each of the plurality of cell transistors has a half-gate-all-around (GAA) channel structure in the active region. You can.

The method of manufacturing a three-dimensional stacked DRAM array according to the present invention includes alternately stacking SiGe layers and Si layers on a silicon substrate, then sequentially stacking a silicon oxide film and a silicon nitride film, and forming a separator forming space divided into a plurality of unit sections. A first step of simultaneously creating a cell transistor formation space and a separator formation space of the same shape for each unit block; A second step of depositing a silicon oxide film on the structure of the silicon substrate to fill the separator formation space, the cell transistor formation space, and the separator formation space, and performing a planarization process; a third step of forming a hole by partially etching the silicon oxide film filling the cell transistor formation space; A fourth step of recessing a portion of the SiGe layer by selective isotropic etching using the hole; A fifth step of forming a dummy gate by depositing amorphous Si or poly Si in the recessed hole by CVD; A sixth step of simultaneously creating a Drain-BL Connection structural trench and a common ground plate formation space for each unit section; A seventh step of selectively removing the SiGe layer using the trench and the common ground plate formation space and doping the exposed Si layer with N+; An eighth step of depositing a cell capacitor dielectric on the exposed Si layer, filling the trench and the space for forming the common ground plate with metal for forming a common ground plate, and then performing a planarization process; A ninth step of partially etching the metal for forming the common ground plate to lower its height, depositing a protective silicon oxide film, and then performing a planarization process again; Step 10 of removing the Dummy Gate; An 11th step of forming a gate pillar by sequentially depositing a gate insulating film and a gate material on the area exposed by removal of the dummy gate; A twelfth step of simultaneously creating a staircase structure for contacting the Si layer with one side of the Drain-BL Connection structural trench for each unit section; and a 13th step of performing a metallization process to electrically connect the step structure of the Si layer, the gate, and the common ground plate to bit lines, word lines, and capacitor ground lines, respectively.

Between the fourth step and the fifth step, a selective etching process may be further performed to round the corners of the Si layer exposed in the recess so that the channel region has a half-gate GAA (Gate-All-Around) shape. .

Between the seventh and eighth steps, a self-aligned silicide process may be performed to further transform the exposed Si layer by doping with N+ into silicide.

In the first step, the plurality of unit sections are divided into an m x n matrix (m and n are natural numbers of 2 or more), the space for forming the cell transistor is formed at a regular interval of three or more on one side of each unit section, and the isolation A plate formation space may be formed between the cell transistor formation spaces.

The present invention is a “ㄷ” shaped Drain-BL Connection structure with two connection lines that is stacked vertically, with a plurality of horizontal active lines on one connection line and a step shape on the other connection line to form bit lines. By connecting them, not only can space be efficiently utilized by sharing the ground electrode of the capacitor, but the cell capacitance can be increased horizontally, and this can be expanded into a unit structure, allowing for metal wiring processes such as bit lines by vertical stacking. It has the effect of resolving difficulties.

Figure 1 is a perspective view showing the basic structure of a three-dimensional stacked DRAM array according to an embodiment of the present invention.

FIG. 2(a) is an equivalent circuit diagram for the one-layer structure of FIG. 1, and FIG. 2(b) is a partially cut away perspective view showing the structure of FIG. 1 corresponding to the dotted line portion of FIG. 2(a).

FIG. 3(a) is a horizontal cross-sectional view of a plurality of cell transistors and a plurality of capacitors stacked vertically on the first active line block and the second active line block with the first separator of FIG. 1 in between. , FIG. 3(b) is a cross-sectional view cut vertically along line aa' in FIG. 3(a).

Figure 4 is a perspective view showing the basic structure of Figure 1 expanded to four.

FIGS. 5 to 18 are process diagrams showing a method of manufacturing a three-dimensional stacked DRAM array according to an embodiment of the present invention. In FIGS. 5 to 17, (a) is a plan view of each step, and (b) is a plan view of (a). This is a perspective view showing a vertical cut along line bb' in .

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

As illustrated in FIGS. 1 and 2, the three-dimensional stacked DRAM array according to an embodiment of the present invention has two

connection lines

102 and 104 parallel to each other horizontally (in the x direction of FIG. 2) and connected in the middle. It has a “ㄷ” shape and includes vertically spaced and stacked Drain-BL Connection structures.

The Drain-BL Connection structures are spaced apart along the longitudinal direction (x direction) of the one connection line on one of the two connection lines (102) for each floor and include a plurality of horizontal active lines (110, 120, 130, 140, 150, 160) are formed perpendicular to the one connection line 102.

Meanwhile, the other one of the two connection lines (104) is electrically connected to one of the plurality of bit lines (BL1, BL2, BL3, BL4, BL5, BL6) (500) through a contact plug (510), etc. .

The plurality of horizontal

active lines

110, 120, 130, 140, 150, and 160 are stacked vertically (in the z direction of FIG. 2) as many as the number of stacked drain-BL connection structures. That is, as in the example shown in FIG. 1, a plurality of horizontal

active lines

110, 120, 130, 140, 150, and 160 on the first floor maintain the same shape and distance in the x direction and form a “ㄷ” shape. It is connected to each of the Drain-BL Connection structures of the shape, is spaced a certain distance in the z direction, and has a repeatedly stacked structure. The vertical stacking structure of the plurality of horizontal

active lines

110, 120, 130, 140, 150, and 160 is spaced apart along the longitudinal direction (x direction) of the one connection line 102, as shown in FIG. 1. A plurality of active line blocks (ALB1, ALB2, ALB3, etc.) are formed equal to the number of horizontal

active lines

110, 120, 130, 140, 150, and 160.

Each of the plurality of active line blocks (ALB1, ALB2, ALB3, etc.) has a gate pillar 312 formed on one side, that is, sharing the gate of a plurality of stacked cell transistors connected to one connection line 102, 322) and the

common ground plates

412, 422, 432, and 442 of the capacitors spaced apart from the gate pillar and respectively connected to the plurality of cell transistors are formed to be shared vertically/horizontally.

Among the common ground plates, referring to FIG. 1, are located symmetrically between neighboring active blocks among the plurality of active blocks (for example, between ALB2 and ALB3) and/or in a space between neighboring blocks. It may include those (422, 432) that are integrally formed and fill the .

The Drain-BL Connection structures are stacked vertically, as shown in FIG. 1, and the length of the other one of the connection lines (104) gradually decreases to form a step shape, and the Drain-BL Connection structures forming the step shape are By including this, the unit structure 100 of the DRAM array can be formed.

Depending on the embodiment, as shown in FIG. 4, the entire array structure 1000 has two or more unit structures 100 arranged in the word line direction (x-direction) to form a plurality of bit lines using a staircase shape that is repeated in the x-direction. BLs can be electrically connected. By doing this, it is possible to solve the problem of making bit line contact difficult as the number of vertical stacks of active lines increases.

In each of the above-described embodiments, the plurality of horizontal

active lines

110, 120, 130, 140, 150, and 160 are respectively connected to

active regions

112, 114, where cell transistors are formed, as shown in FIG. 3(a). It may be composed of 116; 122, 124, 126) and an electrode area 118; 128 of a capacitor connected to the active area.

The “ㄷ” shaped Drain-BL Connection structures (102, 104) and the electrode areas (118; 128) of the capacitor are made of a conductive material such as a semiconductor line doped with metal or impurities (N+ doped silicon line). It can be formed, but as shown in Figure 3(a), it is preferable to form it with silicide because it can form a silicon line and lower the resistance.

Between the plurality of active line blocks (ALB1, ALB2, ALB3, etc.), as shown in FIG. 1, a plurality of

separators

210, 220, 230 formed of an insulator and surrounded by a cell capacitor dielectric (not shown) One of the

common ground plates

422 and 432 may be located. Here, a plurality of cell transistors formed in each of the plurality of active line blocks (ALB1, ALB2, ALB3, etc.) and a plurality of capacitors connected to the plurality of cell transistors and stacked vertically are connected to the plurality of separators. It may be formed symmetrically with one of the

fields

210, 220, and 230 in between. Depending on the embodiment, the plurality of cell transistors may each have a half-gate-all-around (GAA)

channel structure

114 and 124 in the active area, as shown in FIG. 3(b). By doing this, cell transistors can have various advantages of the GAA structure (large current drivability and suppression of short channel effect, etc.).

Referring to FIGS. 3(a) and 3(b), a supplementary description will be given of the cell transistors and the capacitors respectively connected thereto. First, the cell transistors each have a first source/drain (112, 122), channels (114, 124), and a second source in the active area connected to one connection line (102) of the “ㄷ” shaped Drain-BL Connection structure. /Drains 116, 126 are formed and electrically isolated from the connection line 102, the first source/

drain

112, 122, the

channel

114, 124, and the second source/

drain

116, 126.

Gate pillars

312 and 322 are formed to be symmetrical to each other on the separator 210, preferably with the

gate insulating films

314 and 324 in between. The capacitors each have electrode

regions

118, 128 integrally connected to the second source/

drain

116, 126 of the cell transistors with a separator 210 in between, and gates adjacent to the

electrode regions

118, 128.

Common ground plates

412 and 422 are formed to surround three sides of the

electrode areas

118 and 128 with a capacitor dielectric (Cap. Dielectric, 414, 424) in between so as to be insulated from the

pillars

312 and 322.

Figure 4 shows an embodiment in which the basic structure 100 of Figure 1 described above has been expanded to four. In the basic structure 100, word lines (WLs) and bit lines (BLs) are extended and connected to each other to form an arbitrary overall array. It can be seen that metal wiring such as compact BL metal line is possible, like existing 2D DRAM, without wasting space between bit lines. Afterwards, the word lines (WLs) and bit lines (BLs) are connected to the WL decoder circuit and the Sense Amplifier circuit, respectively. Of course, it is not limited to the four basic structures 100 shown in FIG. 4, and can be implemented in any number of ways by utilizing the basic structures 100 in the form of an m x n matrix. Here, m and n are preferably natural numbers of 2 or more, but may be any combination of natural numbers.

Next, referring to FIGS. 5 to 18, a preferred manufacturing method of the above-described three-dimensional stacked DRAM array will be described.

First, as shown in Figure 5, SiGe layers 11 and Si layers 12 are alternately stacked on the silicon substrate 10, and then a silicon oxide film 20 and a silicon nitride film 30 are sequentially stacked, and the entire array area is In (1000a), a separator forming space 36 is divided into a plurality of unit sections (100a, 100b, 100c, 100d), and a cell transistor forming space 32 and a separator forming space 34 of the same shape for each unit section. Make them at the same time (step 1).

Here, the SiGe layer 11 and the Si layer 12 can be formed through single crystal growth (epitaxial growth) by alternately repeating SiGe and Si from above the silicon substrate 10. At this time, the Si layer 12 corresponds to the single crystal silicon line of the active region formed by the DRAM cell, the electrode region of the capacitor, and the connection line region connecting them, and in-situ doping is performed simultaneously with single crystal growth. Through this, it is possible to have a desired channel doping concentration. Later, the SiGe layer 11 is selectively removed. When such single crystal growth is used, like existing commercialized DRAM, it is composed of a single crystal silicon channel, so it can have high mobility and is excellent in terms of reliability.

Additionally, it can be manufactured with amorphous or polycrystalline semiconductors instead of single crystalline silicon lines. For example, it is possible to manufacture the three-dimensional stacked DRAM array described above by alternately depositing an amorphous semiconductor (or polycrystalline semiconductor) and a silicon oxide film (SiO ₂ ). The silicon nitride film 30 at the top is intended to be used as a CMP stopper during the subsequent planarization process. Through the photo process and the etching process, as shown in FIG. 5, in addition to the separator formation space 36, the cell transistor formation space 32 and the separator formation space 34 are created simultaneously through the same process.

Figure 5 illustrates that the

unit sections

100a, 100b, 100c, and 100d are divided into a 2 x 2 matrix, but this is not limited to this and may be divided into an arbitrary m x n matrix. In addition, three cell transistor formation spaces 32 are formed on one side of each unit division, but more than three may be formed at regular intervals. The separator forming space 34 is formed between the cell transistor forming spaces 32.

Then, as shown in FIG. 6,

silicon oxide films

22, 24, and 26 are deposited on the structure of the silicon substrate 10 to form the cell transistor formation space 32, the separator formation space 34, and the separator formation space. (36) is filled and a planarization process is performed (second step).

Here, the planarization process can be performed using known CMP.

Thereafter, as shown in FIG. 7, a hole 37 is formed by partially etching the silicon oxide film 22 filling the cell transistor formation space 32 through a photo process and an etching process (third step).

Next, as shown in FIG. 8, a portion 11a of the SiGe layer 11 is recessed by selective isotropic etching using the hole 37 (step 4). .

At this time, wet etching such as phosphoric acid solution or chemical dry etching process may be used.

Subsequently, it is preferable to further proceed with a process of rounding the corner area of the exposed Si layer 14 using selective etching of the Si layer 12. At this time, wet etching such as SC1 can be used, or a chemical dry etching process can be used. Through this, a channel having a half GAA (Gate-All-Around) format can be formed.

Thereafter, as shown in FIG. 9, amorphous Si or poly Si is deposited on the recessed hole 37 by CVD to form a dummy gate 40 (step 5).

Immediately before forming the dummy gate 40, an active protective silicon oxide film (not shown) can be deposited to a thickness of about 10 nm on the Si layer 12 exposed as a recess using LPCVD. This protective SiO ₂ serves to protect the silicon area (channel and source/drain) of the cell transistor when the dummy gate is selectively removed later. Next, amorphous Si or poly Si for forming the dummy gate (40) is deposited by CVD. Afterwards, it is flattened through the CMP process. Through this, a Dummy Gate (40) is formed, and this Dummy Gate (40) is scheduled to be removed in the future.

Next, as shown in FIG. 10, the drain-BL connection structural trench 33 and the common ground plate formation space 35 are simultaneously created for each unit section through a photo process and an etching process (step 6).

Thereafter, as shown in FIG. 11, the SiGe layer 11 is selectively removed using the trench 33 and the common ground plate formation space 35, and the exposed

Si layers

10a, 10b, 12a, and 12b are removed. Doped with N+ (step 7).

At this time, when selectively removing the SiGe layer 11, wet etching such as a phosphoric acid solution or chemical dry etching can be used. Also, during N+ doping, it is desirable to deposit a thin layer of screening oxide (protective oxide before the ion implantation process) and then perform the doping process. The N+ doping process may use ion implantation, plasma doping, or gas phase doping process. After the doping process, annealing is performed and screening oxide is removed.

Subsequently, as shown in FIG. 12, the step of turning the Si layer exposed by doping with N+ into silicide (10a', 10b', 12a', 12b') can be further performed through a selective self-aligned silicide process.

Next, as shown in FIG. 13, a cell capacitor dielectric (not shown) is deposited on the exposed Si layers 10a', 10b', 12a', and 12b', and the trench 52 is filled with a metal for forming a common ground plate. After filling the common ground plate forming space 54, a planarization process is performed (step 8).

At this time, ALD or LPCVD may be used to deposit the cell capacitor dielectric. And the metal for forming the common ground plate may be TiN, W, etc. The planarization process may use a CMP process.

Next, as shown in Figure 14, the metal for forming the common ground plate is partially etched to lower its height, protective

silicon oxide films

21 and 23 are deposited, and then a planarization process is performed again (step 9).

Next, as shown in FIG. 15, the dummy gate 40 and the active protective silicon oxide film (not shown) are removed (step 10).

Next, as shown in FIG. 16, gate pillars 60 are formed by sequentially depositing a gate insulating film (not shown) and a gate material on the area exposed by removing the dummy gate 40 (step 11).

Here, the gate insulating film may be SiO ₂ or a high-k dielectric, and the gate material may be TiN, W, etc. for the metal gate. ALD and LPCVD can also be used for these depositions. Afterwards, a CMP process is performed and the height of the gate pillar 60 is lowered through additional dry etching.

Next, as shown in FIG. 17, a step structure 39 for contacting the Si layer 12a' is formed on one side of the Drain-BL Connection structural trench 21 for each unit section through a photo process and an etching process. Make them at the same time (step 12).

Finally, as shown in FIG. 18, the step structure 39 of the Si layer 12a', the gate pillar 60, and the common ground plate 54 are connected to predetermined contact plugs 510, 610, 630, and 710. And/or perform a metal process to electrically connect to the bit lines 500, word lines 600, and capacitor ground line 700 through the

connection lines

620 and 720, respectively (step 13).

As mentioned above, according to the above-described embodiment, the unit sections are divided into an arbitrary m x n matrix form in the entire array area 1000a, the basic structures 100 of the unit sections are made simultaneously through the same process, and later, one metal process is performed. It is possible to form all bit lines, word lines, and capacitor ground lines.

The present invention relates to a semiconductor memory DRAM and has industrial applicability.

Claims

It has two horizontally parallel connection lines connected in the middle and has a “ㄷ” shape, which is vertically spaced and includes stacked Drain-BL Connection structures,

The Drain-BL Connection structures are spaced apart from each other along the length direction of the one connection line, and a plurality of horizontal active lines are formed perpendicular to the one connection line, and the two connection lines The other one is electrically connected to one of the plurality of bit lines,

The plurality of horizontal active lines are stacked vertically side by side as many as the number of the Drain-BL Connection structures and are spaced apart along the longitudinal direction of the single connection line to form a plurality of active line blocks,

The plurality of active line blocks each include a gate pillar that jointly forms each gate of a plurality of cell transistors vertically stacked on one side, and a common ground plate of a capacitor spaced apart from the gate pillar and connected to each of the plurality of cell transistors. A three-dimensional stacked DRAM array, characterized in that formed.
According to claim 1,

The common ground plate is symmetrically positioned between neighboring blocks among the plurality of active blocks and is formed integrally with them.
According to claim 1,

The Drain-BL Connection structures are stacked vertically, and the length of the other one of the connection lines gradually decreases to form a step shape,

Forms a unit structure including the Drain-BL Connection structures forming the step shape,

A three-dimensional stacked DRAM array, wherein the unit structures are arranged in the direction of two or more word lines and the plurality of bit lines are electrically connected using the repeated staircase shape.
The method according to any one of claims 1 to 3,

The plurality of horizontal active lines are each composed of an active area where a cell transistor is formed and an electrode area of a capacitor connected to the active area.
According to claim 4,

A three-dimensional stacked DRAM array, wherein the Drain-BL Connection structures and the electrode area of the capacitor are formed of silicide.
According to claim 4,

One of a plurality of common ground plates surrounded by a plurality of separators and a cell capacitor dielectric is positioned between the plurality of active line blocks,

The plurality of cell transistors and a plurality of vertically stacked capacitors respectively connected to the plurality of cell transistors are formed symmetrically with one of the plurality of separators interposed therebetween,

A three-dimensional stacked DRAM array, wherein each of the plurality of cell transistors has a half-gate-all-around (GAA) channel structure in the active area.
SiGe layers and Si layers are alternately stacked on a silicon substrate, and then a silicon oxide film and a silicon nitride film are sequentially stacked, a separator forming space divided into a plurality of unit sections, a cell transistor forming space of the same shape in each unit section, and a separator plate. The first step is to simultaneously create a forming space;

A second step of depositing a silicon oxide film on the structure of the silicon substrate to fill the separator formation space, the cell transistor formation space, and the separator formation space, and performing a planarization process;

a third step of forming a hole by partially etching the silicon oxide film filling the cell transistor formation space;

A fourth step of recessing a portion of the SiGe layer by selective isotropic etching using the hole;

A fifth step of forming a dummy gate by depositing amorphous Si or poly Si in the recessed hole by CVD;

A sixth step of simultaneously creating a Drain-BL Connection structural trench and a common ground plate formation space for each unit section;

A seventh step of selectively removing the SiGe layer using the trench and the common ground plate formation space and doping the exposed Si layer with N+;

An eighth step of depositing a cell capacitor dielectric on the exposed Si layer, filling the trench and the space for forming the common ground plate with metal for forming a common ground plate, and then performing a planarization process;

A ninth step of partially etching the metal for forming the common ground plate to lower its height, depositing a protective silicon oxide film, and then performing a planarization process again;

Step 10 of removing the Dummy Gate;

An 11th step of forming a gate pillar by sequentially depositing a gate insulating film and a gate material on the area exposed by removal of the dummy gate;

A twelfth step of simultaneously creating a staircase structure for contacting the Si layer with one side of the Drain-BL Connection structural trench for each unit section; and

A 13th step of performing a metallization process to electrically connect the step structure of the Si layer, the gate, and the common ground plate to bit lines, word lines, and capacitor ground lines, respectively. Method for manufacturing a stacked DRAM array.
According to claim 7,

A selective etching process is further performed between the fourth step and the fifth step to round the corners of the Si layer exposed by the recess so that the channel region has a half-gate GAA (Gate-All-Around) shape. A method of manufacturing a three-dimensional stacked DRAM array.
According to claim 7,

A method of manufacturing a three-dimensional stacked DRAM array, characterized in that between the seventh step and the eighth step, a step of making silicide is performed on the exposed Si layer by doping with N+ through a self-aligned silicide process.
The method according to any one of claims 7 to 9,

In the first step, the plurality of unit sections are divided into an m x n matrix (m and n are natural numbers of 2 or more), the space for forming the cell transistor is formed at a regular interval of three or more on one side of each unit section, and the isolation A method of manufacturing a three-dimensional stacked DRAM array, characterized in that the plate formation space is formed between the cell transistor formation spaces.