WO2023190407A1 - Semiconductor device and solid-state imaging device - Google Patents

Semiconductor device and solid-state imaging device Download PDF

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Publication number
WO2023190407A1
WO2023190407A1 PCT/JP2023/012331 JP2023012331W WO2023190407A1 WO 2023190407 A1 WO2023190407 A1 WO 2023190407A1 JP 2023012331 W JP2023012331 W JP 2023012331W WO 2023190407 A1 WO2023190407 A1 WO 2023190407A1
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semiconductor
semiconductor region
region
width
box
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PCT/JP2023/012331
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French (fr)
Japanese (ja)
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篤史 谷畑
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ラピスセミコンダクタ株式会社
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Publication of WO2023190407A1 publication Critical patent/WO2023190407A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors

Definitions

  • the present invention relates to a semiconductor device and a solid-state imaging device.
  • Patent Document 1 discloses a structure including a potential barrier layer between a BOX oxide film of an SOI substrate and a support substrate.
  • the imaging device of Patent Document 1 uses an n+ semiconductor region to detect photogenerated carriers in the pixel area.
  • the pixel structure is formed as follows. An n-type charge collection layer with a low impurity concentration is formed on the p-type semiconductor substrate under the BOX oxide film of the SOI substrate by photolithography and etching. Further, a p+ type pixel isolation layer for partitioning individual pixels is formed on the p type semiconductor substrate. Next, the BOX oxide film of the SOI substrate is processed by photolithography and etching to form an opening in the BOX oxide film that reaches the semiconductor region under the BOX oxide film. Through this opening area, a donor element is introduced by photolithography in high concentration into the n-type charge collection layer by ion implantation.
  • An object of the present invention is to provide a semiconductor device having a structure capable of reducing dark current, and a solid-state imaging device having the semiconductor device.
  • a semiconductor device includes a semiconductor region including a semiconductor layer of a first conductivity type, and an opening extending along a surface of the semiconductor region and a BOX window area on the surface of the semiconductor region. a floating semiconductor region of the first conductivity type provided in the semiconductor region in the BOX window area; and a floating semiconductor region of the first conductivity type provided in the semiconductor region so as to surround a pixel area including the BOX window area. a pixel isolation region of a second conductivity type different from the first conductivity type, the semiconductor layer forming a junction with an inner side surface and a bottom surface of the pixel isolation region, and forming a contact area in the BOX window area on the surface of the semiconductor region.
  • the width of the pixel isolation region is 1 time the width of the floating semiconductor region. At least one of the above and 2.2 times or less is satisfied.
  • a solid-state imaging device includes an imaging area that is two-dimensionally arranged and includes a plurality of semiconductor devices according to the first aspect, and control for reading out charges from each of the semiconductor devices in the imaging area.
  • a control unit that performs the following.
  • FIG. 1 is a configuration diagram showing an example of the configuration of a solid-state imaging device according to an embodiment of the present invention.
  • FIG. 2 is a plan view showing a semiconductor device for a pixel according to an embodiment of the present invention.
  • FIG. 3 is a drawing showing a cross section of the semiconductor device according to one embodiment, taken along line III-III shown in FIG.
  • FIG. 4A is a graph showing measured dark current values of the semiconductor device shown in FIG. 3.
  • FIG. 4B is a diagram showing a planar structure of a semiconductor device that is measured to obtain the graph shown in FIG. 4A.
  • FIG. 5A is a graph showing measured dark current values of the semiconductor device shown in FIG. 3.
  • FIG. 5B is a diagram showing a planar structure of a semiconductor device that is measured to obtain the graph shown in FIG. 5A.
  • FIG. 6A is a diagram showing an outline of a method for manufacturing a semiconductor device according to this embodiment.
  • FIG. 6B is a diagram showing an outline of a method for manufacturing a semiconductor device according to this embodiment.
  • FIG. 6C is a diagram showing an outline of a method for manufacturing a semiconductor device according to this embodiment.
  • FIG. 1 is a drawing showing an example of the configuration of a solid-state imaging device according to the present embodiment.
  • the solid-state imaging device 100 is used, for example, as a two-dimensional image sensor. As shown in FIG. 1, the solid-state imaging device 100 includes an imaging region 102, a control section 110, a vertical shift register 112, a horizontal shift register 114, and a signal processing circuit 116.
  • the imaging area 102 includes a plurality of pixels 101.
  • Each of the pixels 101 is a sensor element that detects charges (electrons) generated within the pixel 101, and the pixels 101 are arranged, for example, one-dimensionally or two-dimensionally in the imaging region 102.
  • Each of the pixels 101 will be referred to as a back-illuminated semiconductor device 11 in the description below.
  • the imaging region 102 can have a rectangular shape, for example, but the shape of the imaging region 102 is not limited to this. Further, in the imaging region 102, a plurality of pixels 101 are arranged in a matrix, but the arrangement of the pixels 101 is not limited to this.
  • the solid-state imaging device 100 includes a plurality of signal lines 122 for controlling the pixels 101 for each row of pixels 101.
  • the solid-state imaging device 100 includes a vertical shift register 112 provided along one side of the imaging region 102, and the vertical shift register 112 is connected to the control unit 110.
  • the vertical shift register 112 controls the operation of the pixel 101 under the control of the control unit 110.
  • the solid-state imaging device 100 includes a signal line 120 and a signal processing circuit 116 for selecting the pixels 101 for each column of pixels 101. Charges read out from each pixel 101 are provided to each signal processing circuit 116 via a signal line 120.
  • the solid-state imaging device 100 includes a horizontal shift register 114, and the horizontal shift register 114 is provided on another side of the imaging region 102 that is different from the side on which the vertical shift register 112 is provided. Horizontal shift register 114 is connected to control section 110. The horizontal shift register 114 sequentially selects the signal processing circuits 116 under the control of the control unit 110 and outputs a signal related to the amount of the read charge to the outside.
  • Each of the signal processing circuits 116 performs signal processing on the signal for one pixel row selected by the vertical shift register 112 to generate an analog signal containing image information. After this processing, the A/D conversion circuit converts the readout signal (analog signal) from the pixel into a digital signal. The digital signal (image data for one pixel row) generated in this way is horizontally scanned by the horizontal shift register 114 and output to the outside of the solid-state imaging device 100.
  • FIG. 2 is a plan view showing the semiconductor device 11 according to the embodiment.
  • some solid lines indicate electrodes provided on the BOX insulating layer 19, and some dashed lines indicate dopant concentrations or conductivity type boundaries within the semiconductor region, or the outer edges of conductors.
  • a pixel circuit that receives signals from the detection area is not depicted.
  • FIG. 3 is a drawing showing the semiconductor device in a cross section taken along line III-III shown in FIG. This semiconductor device 11 has a back-illuminated pixel structure.
  • the semiconductor device 11 includes a semiconductor region 13.
  • the semiconductor region 13 includes a semiconductor layer 15 of a first conductivity type (for example, n-type) and a base semiconductor region 17 of a second conductivity type (for example, p-type).
  • the semiconductor region 13 can be, for example, an SOI (Silicon On Insulator) substrate including a second conductivity type (for example, p-type) semiconductor region, but the present embodiment is not limited thereto.
  • the base semiconductor region 17 is provided between the first surface 13a of the semiconductor region 13 (for example, the back surface of the SOI substrate) and the semiconductor layer 15.
  • the semiconductor layer 15 forms a pn junction 20a with the base semiconductor region 17.
  • the semiconductor device 11 receives incident light on the first surface 13a (the back surface of the SOI substrate) of the semiconductor region 13, and collects one carrier (for example, an electron) from a pair of carriers generated by photoelectric conversion.
  • the semiconductor device 11 includes a BOX insulating layer 19 that extends along the surface (second surface 13b) of the semiconductor region 13 and forms a BOX window on the surface (second surface 13b) of the semiconductor region 13. It has an opening 19a in area 10b.
  • the semiconductor device 11 includes a pixel isolation region 21 of a second conductivity type (for example, p-type) and a floating semiconductor region 23 of a first conductivity type (for example, n-type).
  • the pixel isolation region 21 is provided in the semiconductor region 13 so as to surround one pixel area 10a including the BOX window area 10b. The inner edge of the pixel isolation region 21 is separated from the opening 19a of the BOX window area 10b.
  • the floating semiconductor region 23 is provided in the semiconductor layer 15 in the BOX window area 10b.
  • the floating semiconductor region 23 is separated from the pixel isolation region 21.
  • Floating semiconductor region 23 has a dopant concentration greater than the dopant concentration of semiconductor layer 15 and can also have a dopant concentration greater than the dopant concentration of pixel isolation region 21 .
  • the side and bottom surfaces of the pixel isolation region 21 are covered with the semiconductor layer 15 and form a pn junction 20b with the semiconductor layer 15.
  • the pixel isolation region 21 has a higher dopant concentration than the dopant concentration of the semiconductor layer 15 . Therefore, the depletion layer in the pn junction 20b mainly spreads to the semiconductor layer 15.
  • the semiconductor device 11 has a detection region 25 of a first conductivity type (for example, n-type) provided in the semiconductor layer 15 between the floating semiconductor region 23 and the pixel isolation region 21 outside the BOX window area 10b.
  • the semiconductor device 11 has a transfer gate 27 provided on the BOX insulating layer 19, and the transfer gate 27 is configured to change the electric field near the surface of the semiconductor region 13 between the detection region 25 and the floating semiconductor region 23. It is composed of
  • the semiconductor device 11 has a BOX insulating layer 19, a transfer gate 27, and a covering insulating film 31 that covers the surface (13b) of the semiconductor region 13 in the BOX window area 10b.
  • the covering insulating film 31 is in contact with the surface (13b) of the semiconductor region 13 in the BOX window area 10b, and in particular, the surface (13b) of the semiconductor region 13 in the BOX window area 10b is damaged by etching when the BOX window is opened. This leaves a large number of dangling bonds.
  • the semiconductor device 11 has electrodes 29a, 29b, 29c, 29d, and 29e that apply potential to the transfer gate 27, the detection region 25, the pixel separation region 21, the floating semiconductor region 23, and the base semiconductor region 17, respectively.
  • FIG. 4A is a graph showing measured dark current values of the semiconductor device shown in FIG. 3.
  • FIG. 4B is a diagram showing a planar structure of a semiconductor device that is measured to obtain the graph shown in FIG. 4A. Referring to FIG. 4B, the pixel isolation region 21, the floating semiconductor region 23, and the opening 19a of the BOX window area 10b are drawn in one pixel area 10a.
  • the horizontal axis indicates the ratio (BW/FD) of the width (BW) of the BOX window area 10b (opening 19a of the BOX window area 10b) based on the width (FD) of the floating semiconductor region 23.
  • the vertical axis indicates the dark current (unit: 10 ⁇ 11 amperes) measured in the semiconductor device.
  • the semiconductor device used in the measurements has the following structure.
  • Semiconductor layer 15 n-type silicon semiconductor, addition of n-type dopant
  • Pixel isolation region 21 p-type silicon semiconductor, addition of p-type dopant
  • FIG. 4A shows a tendency that dark current increases when the width (BW) of the BOX window area 10b (opening 19a of the BOX window area 10b) is increased based on the width (FD) of the floating semiconductor region 23.
  • BW width of the BOX window area 10b
  • FD width of the floating semiconductor region 23.
  • an excessively large BOX window area 10b is disadvantageous in terms of reducing dark current at the interface between the semiconductor region 13 of the opening 19a and the covering insulating film 31 filling the opening 19a.
  • floating semiconductor region 23 that is too small compared to the size of BOX window area 10b is disadvantageous in terms of reducing dark current at the interface between semiconductor region 13 in opening 19a and covering insulating film 31 filling opening 19a.
  • the dark current is substantially zero at the measurement points (P11, P12, P13).
  • the dark current is less than 1 ⁇ 10 ⁇ 11 amperes.
  • the dark current is less than 2 ⁇ 10 ⁇ 11 amperes.
  • the dark current is less than 5 ⁇ 10 ⁇ 11 amperes.
  • the dark current is less than 8 ⁇ 10 ⁇ 11 amperes.
  • the dark current is less than 1.4 ⁇ 10 ⁇ 10 amperes.
  • the ratio (BW/FD) is 1.5 or less at the measurement points (P11 to P13). At the measurement points (P11 to P14), the ratio (BW/FD) is 1.65 or less. At the measurement points (P11 to P15), the ratio (BW/FD) is 1.9 or less. At the measurement points (P11 to P16), the ratio (BW/FD) is 2.0 or less. At the measurement points (P11 to P17), the ratio (BW/FD) is 2.2 or less. At the measurement points (P11 to P18), the ratio (BW/FD) is 2.3 or less.
  • the width (BW) of the BOX window area 10b is larger than 1 times the width (FD) of the floating semiconductor region 23, and 1 .5 times or less.
  • 1 ⁇ (BW)/(FD) ⁇ 1.5 can be.
  • the upper limit of the ratio (1.5) can be changed depending on the required upper limit of dark current. For example, if the dark current is allowed up to 1 ⁇ 10 ⁇ 11 amps, the upper limit of the ratio is 1.65, and if the dark current is allowed up to 2 ⁇ 10 ⁇ 11 amps, the upper limit of the ratio is 1.9. In this embodiment, the upper limit of the ratio is, for example, 1.5.
  • the shapes of the inner edge of the pixel isolation region 21, the outer edge of the floating semiconductor region 23, and the opening 19a of the BOX window area 10b can be square or rectangular, for example.
  • the shape of the area within the inner edge of the pixel isolation region 21, the shape of the floating semiconductor region 23, and the shape of the opening 19a of the BOX window area 10b are each square.
  • the shapes of the inner edge of the pixel isolation region 21, the outer edge of the floating semiconductor region 23, and the opening 19a of the BOX window area 10b can be rectangular.
  • the area (SBW) of the BOX window area 10b is larger than 1 times the area (SFD) of the floating semiconductor region 23 and is 2. .25 (1.5 ⁇ 1.5) times or less. In other words, 1 ⁇ (SBW)/(SFD) ⁇ 2.25 can be.
  • the upper limit of the area ratio (2.25) is an exemplary value and can be changed depending on the required upper limit of dark current.
  • FIG. 5A is a graph showing measured dark current values of the semiconductor device shown in FIG. 3.
  • FIG. 5B is a diagram showing a planar structure of a semiconductor device that is measured to obtain the graph shown in FIG. 5A. Referring to FIG. 5B, the pixel isolation region 21, the floating semiconductor region 23, and the opening 19a of the BOX window area 10b are drawn in one pixel area 10a.
  • the horizontal axis indicates the ratio (PS/FD) of the width (PS) of the inner edge of the pixel isolation region 21 with respect to the width (FD) of the floating semiconductor region 23.
  • the vertical axis indicates the dark current (unit: 10 ⁇ 13 amperes) measured in the semiconductor device.
  • the dark current is less than 8 ⁇ 10 ⁇ 13 amperes.
  • seven measurement points P21, P22, P23, P24, P25, P26, P27 are plotted.
  • FIG. 5A shows that when the width (PS) of the inner edge of the pixel isolation region 21 is increased based on the width (FD) of the floating semiconductor region 23, the dark current tends to increase.
  • the width of the inner edge of the pixel isolation region 21, which is too large from the viewpoint of the ratio (PS/FD) is This is disadvantageous in terms of reducing the dark current associated with the interface.
  • the floating semiconductor region 23 (or BOX window area 10b) that is too small compared to the size of the inner edge area of the pixel isolation region 21 is disadvantageous in terms of reducing dark current at the interface between the BOX insulating layer and the semiconductor region 13. .
  • the dark current is less than 8 ⁇ 10 ⁇ 13 amperes in the ratio range of 1.6 or more and 2.2 or less.
  • the dark current is 9.5 ⁇ 10 ⁇ 13 amperes or less in the ratio range of 1.6 or more and 2.4 or less.
  • the dark current is 1.1 ⁇ 10 ⁇ 12 ampere or less in the ratio range of 1.6 or more and 2.6 or less.
  • the dark current is 1.3 ⁇ 10 ⁇ 12 ampere or less in the ratio range of 1.6 or more and 2.8 or less.
  • the ratio (PS/FD) is 1.6 or more and 2.2 or less.
  • the ratio (PS/FD) is 1.6 or more and 2.4 or less.
  • the ratio (PS/FD) is 1.6 or more and 2.6 or less.
  • the ratio (PS/FD) is 1.6 or more and 2.8 or less.
  • the distance (PS) between the inner edges of the pixel isolation region 21 is at least one times the width (FD) of the floating semiconductor region 23. and can be 2.2 times or less. In other words, 1 ⁇ (PS)/(FD) ⁇ 2.2 can be.
  • the upper limit of the ratio (2.2) can be changed depending on the required upper limit of dark current.
  • the upper limit of the ratio is 2.2, as an example.
  • the shapes of the inner edge of the pixel isolation region 21, the outer edge of the floating semiconductor region 23, and the opening 19a of the BOX window area 10b are, for example, square or rectangular.
  • the shapes of the inner edge of the pixel isolation region 21, the outer edge of the floating semiconductor region 23, and the opening 19a of the BOX window area 10b are squares of the respective sizes. However, in terms of typical shapes, the shapes of the inner edge of the pixel isolation region 21, the outer edge of the floating semiconductor region 23, and the opening 19a of the BOX window area 10b can be rectangular.
  • the area (SPS) of the area within the inner edge of the pixel isolation region 21 is the area (SFD) of the floating semiconductor region 23.
  • SFD the area of the floating semiconductor region 23.
  • it can be greater than or equal to 1 ((PS) 2 /(FD) 2 which is the square of the lower limit of the ratio (PS)/(FD)) and less than or equal to 4.84 (2.2 ⁇ 2.2) times.
  • 1 ⁇ (SPS)/(SFD) ⁇ 4.84 can be.
  • the upper limit of the area ratio is just an example, and can be changed depending on the required upper limit of dark current.
  • FIGS. 4A and 5A two types of dimensional ratios, specifically dimensional ratios (BW)/(FD) and (PS)/(FD), are shown.
  • BW dimensional ratios
  • PS dimensional ratios
  • FIGS. 6A, 6B, and 6C are drawings showing an overview of a method for manufacturing the semiconductor device 11 according to this embodiment.
  • reference numerals used in the description with reference to FIGS. 1 to 5B will be used where possible.
  • BOX insulating film (19) for a BOX insulating layer 19
  • a BOX insulating film (19) Form a second conductivity type pixel isolation region 21 in the semiconductor region 13 directly below.
  • resist 41 is removed.
  • the semiconductor layer 15 of the first conductivity type can be formed using ion implantation.
  • the BOX insulating film (19) is processed using a resist 43 from photolithography and etching to form a BOX insulating layer 19 having an opening 19a. do.
  • the surface of semiconductor region 13 exposed in opening 19a is exposed to etching. After etching, resist 43 is removed.
  • a floating semiconductor region 23 is formed using a resist 45 from photolithography and ion implantation.
  • the resist 45 is used when forming the floating semiconductor region 23 in an area smaller than the BOX window area 10b. After ion implantation, resist 45 is removed.
  • an insulating film for example, silicon oxide
  • electrodes are formed.
  • a semiconductor device having a structure capable of reducing dark current and a solid-state imaging device having the semiconductor device are provided.
  • This embodiment has various aspects exemplarily shown below.
  • the first side surface includes a semiconductor device.
  • the semiconductor device includes: a semiconductor region including a semiconductor layer of a first conductivity type; a BOX insulating layer extending along a surface of the semiconductor region and having an opening in a BOX window area on the surface of the semiconductor region; a floating semiconductor region of the first conductivity type provided in the semiconductor region in a window area; and a second conductivity type different from the first conductivity provided in the semiconductor region so as to surround a pixel area including the BOX window area.
  • a pixel isolation region of the type the semiconductor layer is in contact with an inner side surface and a bottom surface of the pixel isolation region, and on the surface of the semiconductor region, the width of the BOX window area is equal to the width of the floating semiconductor region.
  • the width of the pixel isolation region is greater than 1 time and less than 1.5 times the width of the floating semiconductor region, and on the surface of the semiconductor region, the width of the pixel isolation region is more than 1 time and less than 2.2 times the width of the floating semiconductor region. At least one of the following is satisfied.
  • a second side according to the first side further includes a transfer gate provided on the BOX insulating layer outside the BOX window area, and an insulating film covering the opening, the BOX insulating layer, and the transfer gate.
  • the semiconductor layer may be provided deeper than the floating semiconductor region with respect to the surface of the semiconductor region, and the pixel isolation region may be provided shallower than the semiconductor layer with respect to the surface of the semiconductor region.
  • the width of the BOX window area may be greater than 1 time and less than or equal to 1.5 times the width of the floating semiconductor region.
  • the width of the pixel isolation region may be at least 1 times the width of the floating semiconductor region and no more than 2.2 times the width of the floating semiconductor region. can.
  • the fifth side includes a solid-state imaging device.
  • the solid-state imaging device includes an imaging region that is two-dimensionally arranged and includes a plurality of semiconductor devices described on one of a first side surface to a fourth side surface, and a charge source from each of the semiconductor devices in the imaging region.
  • a control unit that performs read control.

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Abstract

This semiconductor device comprises: a semiconductor region that includes a semiconductor layer of a first conductivity type; a BOX insulating layer that extends along the surface of the semiconductor region and has openings at BOX window areas of the surface of the semiconductor region; floating semiconductor regions of the first conductivity type that are provided in the BOX window areas in the semiconductor region; and pixel isolation regions of a second conductivity type different from the first conductivity type that are provided in the semiconductor region so as to surround pixel areas containing the BOX window areas. The semiconductor layer forms junctions with the inner side surfaces and bottom surfaces of the pixel isolation regions, and at least one of the following is satisfied: in the surface of the semiconductor region, the width of the BOX window areas is greater than 1 times and at most 1. 5 times the width of the floating semiconductor regions; and in the surface of the semiconductor region, the width of the pixel isolation regions is at least 1 times and at most 2.2 times the width of the floating semiconductor regions.

Description

半導体装置、固体撮像装置Semiconductor devices, solid-state imaging devices
　本発明は、半導体装置、及び固体撮像装置に関する。
　本出願は、２０２２年３月２９日に出願された日本国特許出願第2022-054395号の優先権を主張し、その全内容は、参照により本明細書に組み込まれる。 The present invention relates to a semiconductor device and a solid-state imaging device.
This application claims priority to Japanese Patent Application No. 2022-054395 filed on March 29, 2022, the entire contents of which are incorporated herein by reference.
　特許文献１は、ＳＯＩ基板のＢＯＸ酸化膜と支持基板との間に電位障壁層を含む構造を開示する。 Patent Document 1 discloses a structure including a potential barrier layer between a BOX oxide film of an SOI substrate and a support substrate.
特開2019-106519号公報Japanese Patent Application Publication No. 2019-106519
　特許文献１の撮像装置は、画素エリアにおいて光生成キャリアを検出するためにｎ＋半導体領域を用いる。画素構造は、以下のように形成される。フォトリソグラフィ及びエッチングによりＳＯＩ基板のＢＯＸ酸化膜下のｐ型半導体基板に、低い不純物濃度のｎ型電荷収集層を形成する。また、ｐ型半導体基板に、個々の画素を区画するためのｐ＋型画素分離層を形成する。次いで、フォトリソグラフィ及びエッチングによりＳＯＩ基板のＢＯＸ酸化膜を加工して、ＢＯＸ酸化膜下の半導体領域に到達する開口をＢＯＸ酸化膜に形成する。この開口エリアを介して、フォトリソグラフィによりドナー元素が、イオン注入により高濃度でｎ型電荷収集層に導入される。 The imaging device of Patent Document 1 uses an n+ semiconductor region to detect photogenerated carriers in the pixel area. The pixel structure is formed as follows. An n-type charge collection layer with a low impurity concentration is formed on the p-type semiconductor substrate under the BOX oxide film of the SOI substrate by photolithography and etching. Further, a p+ type pixel isolation layer for partitioning individual pixels is formed on the p type semiconductor substrate. Next, the BOX oxide film of the SOI substrate is processed by photolithography and etching to form an opening in the BOX oxide film that reaches the semiconductor region under the BOX oxide film. Through this opening area, a donor element is introduced by photolithography in high concentration into the n-type charge collection layer by ion implantation.
　このように形成される画素において、製造工程を実質的に追加すること無く暗電流を低減できる構造が求められている。 In pixels formed in this manner, there is a need for a structure that can reduce dark current without adding substantial manufacturing steps.
　本発明は、暗電流を低減可能な構造を有する半導体装置、及び半導体装置を有する固体撮像装置を提供することを目的とする。 An object of the present invention is to provide a semiconductor device having a structure capable of reducing dark current, and a solid-state imaging device having the semiconductor device.
　本発明の第１態様に係る半導体装置は、第１導電型の半導体層を含む半導体領域と、前記半導体領域の表面に沿って延在すると共に前記半導体領域の前記表面のＢＯＸ窓エリアに開口を有するＢＯＸ絶縁層と、前記ＢＯＸ窓エリアにおいて前記半導体領域に設けられた前記第１導電型の浮遊半導体領域と、前記ＢＯＸ窓エリアを含む画素エリアを囲むように前記半導体領域に設けられた前記第１導電型と異なる第２導電型の画素分離領域と、を備え、前記半導体層は、前記画素分離領域の内側面及び底面に接合を成し、前記半導体領域の前記表面において、前記ＢＯＸ窓エリアの幅は、前記浮遊半導体領域の幅の１倍より大きく１．５倍以下であること、及び前記半導体領域の前記表面において、前記画素分離領域の幅は、前記浮遊半導体領域の幅の１倍以上であり２．２倍以下であること、の少なくともいずれか一方が満たされる。 A semiconductor device according to a first aspect of the present invention includes a semiconductor region including a semiconductor layer of a first conductivity type, and an opening extending along a surface of the semiconductor region and a BOX window area on the surface of the semiconductor region. a floating semiconductor region of the first conductivity type provided in the semiconductor region in the BOX window area; and a floating semiconductor region of the first conductivity type provided in the semiconductor region so as to surround a pixel area including the BOX window area. a pixel isolation region of a second conductivity type different from the first conductivity type, the semiconductor layer forming a junction with an inner side surface and a bottom surface of the pixel isolation region, and forming a contact area in the BOX window area on the surface of the semiconductor region. has a width greater than 1 time and less than 1.5 times the width of the floating semiconductor region, and on the surface of the semiconductor region, the width of the pixel isolation region is 1 time the width of the floating semiconductor region. At least one of the above and 2.2 times or less is satisfied.
　本発明の第２態様に係る固体撮像装置は、２次元に配置されており第１態様に係る複数の半導体装置を含む撮像領域と、　前記撮像領域内の前記半導体装置の各々から電荷を読み出す制御を行う制御部と、を備える。 A solid-state imaging device according to a second aspect of the present invention includes an imaging area that is two-dimensionally arranged and includes a plurality of semiconductor devices according to the first aspect, and control for reading out charges from each of the semiconductor devices in the imaging area. A control unit that performs the following.
図１は、本発明の一実施の形態に係る固体撮像装置の構成の一例を示す構成図である。FIG. 1 is a configuration diagram showing an example of the configuration of a solid-state imaging device according to an embodiment of the present invention. 図２は、本発明の一実施の形態に係る画素のための半導体装置を示す平面図である。FIG. 2 is a plan view showing a semiconductor device for a pixel according to an embodiment of the present invention. 図３は、図２に示されたＩＩＩ－ＩＩＩ線に沿って取られた、一実施の形態に係る半導体装置の断面を示す図面である。FIG. 3 is a drawing showing a cross section of the semiconductor device according to one embodiment, taken along line III-III shown in FIG. 図４Ａは、図３に示された半導体装置の暗電流の測定値を示すグラフである。FIG. 4A is a graph showing measured dark current values of the semiconductor device shown in FIG. 3. FIG. 図４Ｂは、図４Ａに示されたグラフを得るために測定される半導体装置の平面構造を示す図面である。FIG. 4B is a diagram showing a planar structure of a semiconductor device that is measured to obtain the graph shown in FIG. 4A. 図５Ａは、図３に示された半導体装置の暗電流の測定値を示すグラフである。FIG. 5A is a graph showing measured dark current values of the semiconductor device shown in FIG. 3. FIG. 図５Ｂは、図５Ａに示されたグラフを得るために測定される半導体装置の平面構造を示す図面である。FIG. 5B is a diagram showing a planar structure of a semiconductor device that is measured to obtain the graph shown in FIG. 5A. 図６Ａは、本実施の形態に係る半導体装置を作製する方法の概要を示す図面である。FIG. 6A is a diagram showing an outline of a method for manufacturing a semiconductor device according to this embodiment. 図６Ｂは、本実施の形態に係る半導体装置を作製する方法の概要を示す図面である。FIG. 6B is a diagram showing an outline of a method for manufacturing a semiconductor device according to this embodiment. 図６Ｃは、本実施の形態に係る半導体装置を作製する方法の概要を示す図面である。FIG. 6C is a diagram showing an outline of a method for manufacturing a semiconductor device according to this embodiment.
　以下、図面を参照して本発明を実施するための各実施の形態について説明する。引き続く説明では、同一又は類似の部分には、同一又は類似の符号を付して、複写的な説明を省略する。 Hereinafter, each embodiment for carrying out the present invention will be described with reference to the drawings. In the following description, the same or similar parts will be given the same or similar reference numerals, and repeated description will be omitted.
　まず、固体撮像装置の構成について説明する。 First, the configuration of the solid-state imaging device will be explained.
　図１は、本実施の形態に係る固体撮像装置の構成の一例を示す図面である。固体撮像装置１００は、例えば二次元のイメージセンサとして用いられる。図１に示されるように、固体撮像装置１００は、撮像領域１０２、制御部１１０、垂直シフトレジスタ１１２、水平シフトレジスタ１１４、及び信号処理回路１１６を備える。 FIG. 1 is a drawing showing an example of the configuration of a solid-state imaging device according to the present embodiment. The solid-state imaging device 100 is used, for example, as a two-dimensional image sensor. As shown in FIG. 1, the solid-state imaging device 100 includes an imaging region 102, a control section 110, a vertical shift register 112, a horizontal shift register 114, and a signal processing circuit 116.
　撮像領域１０２は、複数の画素１０１を備える。画素１０１の各々は、画素１０１内で発生した電荷（電子）を検出するセンサ素子であり、画素１０１は、撮像領域１０２において、例えば１次元又は２次元に配列される。画素１０１の各々は、後述される説明において裏面入射型の半導体装置１１として参照される。 The imaging area 102 includes a plurality of pixels 101. Each of the pixels 101 is a sensor element that detects charges (electrons) generated within the pixel 101, and the pixels 101 are arranged, for example, one-dimensionally or two-dimensionally in the imaging region 102. Each of the pixels 101 will be referred to as a back-illuminated semiconductor device 11 in the description below.
　固体撮像装置１００では、撮像領域１０２が、例えば矩形の形状を有することができ、しかしながら、撮像領域１０２の形状は、これに限定されない。また、撮像領域１０２では、複数の画素１０１がマトリクス状に配置されているが、画素１０１の配置は、これに限定されるものではない。 In the solid-state imaging device 100, the imaging region 102 can have a rectangular shape, for example, but the shape of the imaging region 102 is not limited to this. Further, in the imaging region 102, a plurality of pixels 101 are arranged in a matrix, but the arrangement of the pixels 101 is not limited to this.
　固体撮像装置１００は、画素１０１の行毎に、画素１０１を制御するための複数の信号線１２２を備える。固体撮像装置１００は、撮像領域１０２の一辺に沿って設けられた垂直シフトレジスタ１１２を備え、垂直シフトレジスタ１１２は、制御部１１０に接続される。垂直シフトレジスタ１１２は、制御部１１０の制御に応じて、画素１０１の動作を制御する。 The solid-state imaging device 100 includes a plurality of signal lines 122 for controlling the pixels 101 for each row of pixels 101. The solid-state imaging device 100 includes a vertical shift register 112 provided along one side of the imaging region 102, and the vertical shift register 112 is connected to the control unit 110. The vertical shift register 112 controls the operation of the pixel 101 under the control of the control unit 110.
　固体撮像装置１００は、画素１０１の列毎に、画素１０１を選択するための信号線１２０及び信号処理回路１１６を備える。各画素１０１から読み出された電荷は、信号線１２０を介してそれぞれの信号処理回路１１６に提供される。 The solid-state imaging device 100 includes a signal line 120 and a signal processing circuit 116 for selecting the pixels 101 for each column of pixels 101. Charges read out from each pixel 101 are provided to each signal processing circuit 116 via a signal line 120.
　固体撮像装置１００は、水平シフトレジスタ１１４を備え、水平シフトレジスタ１１４は、垂直シフトレジスタ１１２が設けられた一辺と異なる撮像領域１０２の別辺に設けられる。水平シフトレジスタ１１４は、制御部１１０に接続される。水平シフトレジスタ１１４は、制御部１１０の制御に応じて、信号処理回路１１６を順次選択して、読み出された電荷の量に係る信号を外部に出力する。 The solid-state imaging device 100 includes a horizontal shift register 114, and the horizontal shift register 114 is provided on another side of the imaging region 102 that is different from the side on which the vertical shift register 112 is provided. Horizontal shift register 114 is connected to control section 110. The horizontal shift register 114 sequentially selects the signal processing circuits 116 under the control of the control unit 110 and outputs a signal related to the amount of the read charge to the outside.
　信号処理回路１１６の各々が、垂直シフトレジスタ１１２によって選択された１画素行分の信号に対して信号処理を行って、画像の情報を含むアナログ信号を生成する。この処理の後に、Ａ／Ｄ変換回路が、画素からの読み出し信号（アナログ信号）をデジタル信号に変換する。このように生成されたデジタル信号（１画素行分の画像データ）は、水平シフトレジスタ１１４により水平走査されて、固体撮像装置１００の外部に出力される。 Each of the signal processing circuits 116 performs signal processing on the signal for one pixel row selected by the vertical shift register 112 to generate an analog signal containing image information. After this processing, the A/D conversion circuit converts the readout signal (analog signal) from the pixel into a digital signal. The digital signal (image data for one pixel row) generated in this way is horizontally scanned by the horizontal shift register 114 and output to the outside of the solid-state imaging device 100.
　次に、実施の形態に係る画素１０１のための半導体装置の構成を説明する。図２は、実施の形態に係る半導体装置１１を示す平面図である。図２において、いくつかの実線は、ＢＯＸ絶縁層１９上に設けられた電極を示し、いくつかの破線は、半導体領域内のドーパント濃度若しくは導電型の境界、又は導電体の外縁を示す。また、図２において、検知領域からの信号を受ける画素回路は描かれていない。 Next, the configuration of the semiconductor device for the pixel 101 according to the embodiment will be described. FIG. 2 is a plan view showing the semiconductor device 11 according to the embodiment. In FIG. 2, some solid lines indicate electrodes provided on the BOX insulating layer 19, and some dashed lines indicate dopant concentrations or conductivity type boundaries within the semiconductor region, or the outer edges of conductors. Furthermore, in FIG. 2, a pixel circuit that receives signals from the detection area is not depicted.
　図３は、図２に示されたＩＩＩ－ＩＩＩ線に沿って取られた断面において半導体装置を示す図面である。この半導体装置１１は、裏面入射型の画素構造を有する。 FIG. 3 is a drawing showing the semiconductor device in a cross section taken along line III-III shown in FIG. This semiconductor device 11 has a back-illuminated pixel structure.
　図２及び図３を参照すると、半導体装置１１は、半導体領域１３を備える。半導体領域１３は、第１導電型（例えばｎ型）の半導体層１５及び第２導電型（例えばｐ型）のベース半導体領域１７を含む。また、半導体領域１３は、例えば第２導電型（例えばｐ型）の半導体領域を含むＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板であることができ、しかしながら、本形態はこれに限定されない。ベース半導体領域１７は、半導体領域１３の第１面１３ａ（例えば、ＳＯＩ基板の裏面）から半導体層１５までの間に設けられる。半導体層１５は、ベース半導体領域１７とｐｎ接合２０ａを成す。半導体装置１１は、半導体領域１３の第１面１３ａ（ＳＯＩ基板の裏面）に入射光を受けて、光電変換により生成されたキャリア対のうち一方のキャリア（例えば、電子）を収集する。 Referring to FIGS. 2 and 3, the semiconductor device 11 includes a semiconductor region 13. The semiconductor region 13 includes a semiconductor layer 15 of a first conductivity type (for example, n-type) and a base semiconductor region 17 of a second conductivity type (for example, p-type). Further, the semiconductor region 13 can be, for example, an SOI (Silicon On Insulator) substrate including a second conductivity type (for example, p-type) semiconductor region, but the present embodiment is not limited thereto. The base semiconductor region 17 is provided between the first surface 13a of the semiconductor region 13 (for example, the back surface of the SOI substrate) and the semiconductor layer 15. The semiconductor layer 15 forms a pn junction 20a with the base semiconductor region 17. The semiconductor device 11 receives incident light on the first surface 13a (the back surface of the SOI substrate) of the semiconductor region 13, and collects one carrier (for example, an electron) from a pair of carriers generated by photoelectric conversion.
　半導体装置１１は、ＢＯＸ絶縁層１９を含み、ＢＯＸ絶縁層１９は、半導体領域１３の表面（第２面１３ｂ）に沿って延在すると共に半導体領域１３の表面（第２面１３ｂ）のＢＯＸ窓エリア１０ｂに開口１９ａを有する。半導体装置１１は、第２導電型（例えば、ｐ型）の画素分離領域２１と、第１導電型（例えばｎ型）の浮遊半導体領域２３とを含む。画素分離領域２１は、ＢＯＸ窓エリア１０ｂを含む一画素エリア１０ａを囲むように半導体領域１３に設けられる。画素分離領域２１の内縁は、ＢＯＸ窓エリア１０ｂの開口１９ａから離れている。 The semiconductor device 11 includes a BOX insulating layer 19 that extends along the surface (second surface 13b) of the semiconductor region 13 and forms a BOX window on the surface (second surface 13b) of the semiconductor region 13. It has an opening 19a in area 10b. The semiconductor device 11 includes a pixel isolation region 21 of a second conductivity type (for example, p-type) and a floating semiconductor region 23 of a first conductivity type (for example, n-type). The pixel isolation region 21 is provided in the semiconductor region 13 so as to surround one pixel area 10a including the BOX window area 10b. The inner edge of the pixel isolation region 21 is separated from the opening 19a of the BOX window area 10b.
　浮遊半導体領域２３は、ＢＯＸ窓エリア１０ｂにおいて半導体層１５に設けられる。浮遊半導体領域２３は、画素分離領域２１から離れている。浮遊半導体領域２３は、半導体層１５のドーパント濃度より大きなドーパント濃度を有し、また画素分離領域２１のドーパント濃度より大きなドーパント濃度を有することができる。 The floating semiconductor region 23 is provided in the semiconductor layer 15 in the BOX window area 10b. The floating semiconductor region 23 is separated from the pixel isolation region 21. Floating semiconductor region 23 has a dopant concentration greater than the dopant concentration of semiconductor layer 15 and can also have a dopant concentration greater than the dopant concentration of pixel isolation region 21 .
　画素分離領域２１の側面及び底面は、半導体層１５によって覆われて、半導体層１５とｐｎ接合２０ｂを成す。画素分離領域２１は、半導体層１５のドーパント濃度より大きなドーパント濃度を有する。これ故に、ｐｎ接合２０ｂにおける空乏層は、主に半導体層１５に広がる。 The side and bottom surfaces of the pixel isolation region 21 are covered with the semiconductor layer 15 and form a pn junction 20b with the semiconductor layer 15. The pixel isolation region 21 has a higher dopant concentration than the dopant concentration of the semiconductor layer 15 . Therefore, the depletion layer in the pn junction 20b mainly spreads to the semiconductor layer 15.
　半導体装置１１は、ＢＯＸ窓エリア１０ｂの外側において、浮遊半導体領域２３と画素分離領域２１との間の半導体層１５に設けられた第１導電型（例えばｎ型）の検出領域２５を有する。半導体装置１１は、ＢＯＸ絶縁層１９上に設けられた転送ゲート２７を有し、転送ゲート２７は、検出領域２５と浮遊半導体領域２３との間の半導体領域１３の表面付近の電界を変更するように構成される。 The semiconductor device 11 has a detection region 25 of a first conductivity type (for example, n-type) provided in the semiconductor layer 15 between the floating semiconductor region 23 and the pixel isolation region 21 outside the BOX window area 10b. The semiconductor device 11 has a transfer gate 27 provided on the BOX insulating layer 19, and the transfer gate 27 is configured to change the electric field near the surface of the semiconductor region 13 between the detection region 25 and the floating semiconductor region 23. It is composed of
　半導体装置１１は、ＢＯＸ絶縁層１９、転送ゲート２７、及びＢＯＸ窓エリア１０ｂの半導体領域１３の表面（１３ｂ）を覆う被覆絶縁膜３１を有する。被覆絶縁膜３１は、ＢＯＸ窓エリア１０ｂの半導体領域１３の表面（１３ｂ）に接触を成して、特にＢＯＸ窓エリア１０ｂの半導体領域１３の表面（１３ｂ）にはＢＯＸ窓開口時のエッチングのダメージにより多数のダングリングボンドが残る。 The semiconductor device 11 has a BOX insulating layer 19, a transfer gate 27, and a covering insulating film 31 that covers the surface (13b) of the semiconductor region 13 in the BOX window area 10b. The covering insulating film 31 is in contact with the surface (13b) of the semiconductor region 13 in the BOX window area 10b, and in particular, the surface (13b) of the semiconductor region 13 in the BOX window area 10b is damaged by etching when the BOX window is opened. This leaves a large number of dangling bonds.
　半導体装置１１は、転送ゲート２７、検出領域２５、画素分離領域２１、浮遊半導体領域２３、及びベース半導体領域１７に電位を与えるそれぞれの電極２９ａ、２９ｂ、２９ｃ、２９ｄ、及び２９ｅを有する。 The semiconductor device 11 has electrodes 29a, 29b, 29c, 29d, and 29e that apply potential to the transfer gate 27, the detection region 25, the pixel separation region 21, the floating semiconductor region 23, and the base semiconductor region 17, respectively.
　図４Ａは、図３に示された半導体装置の暗電流の測定値を示すグラフである。図４Ｂは、図４Ａに示されたグラフを得るために測定される半導体装置の平面構造を示す図面である。図４Ｂを参照すると、画素分離領域２１、浮遊半導体領域２３、及びＢＯＸ窓エリア１０ｂの開口１９ａが、一画素エリア１０ａにおいて描かれている。 FIG. 4A is a graph showing measured dark current values of the semiconductor device shown in FIG. 3. FIG. 4B is a diagram showing a planar structure of a semiconductor device that is measured to obtain the graph shown in FIG. 4A. Referring to FIG. 4B, the pixel isolation region 21, the floating semiconductor region 23, and the opening 19a of the BOX window area 10b are drawn in one pixel area 10a.
　図４Ａでは、横軸は、浮遊半導体領域２３の幅（ＦＤ）を基準にしたＢＯＸ窓エリア１０ｂ（ＢＯＸ窓エリア１０ｂの開口１９ａ）の幅（ＢＷ）の比率（ＢＷ／ＦＤ）を示す。縦軸は、半導体装置において測定された暗電流（単位：１０－１１アンペア）を示す。測定に使用された半導体装置は、以下の構造を有する。
半導体層１５：ｎ型シリコン半導体、ｎ型ドーパントの添加
画素分離領域２１：ｐ型シリコン半導体、ｐ型ドーパントの添加 In FIG. 4A, the horizontal axis indicates the ratio (BW/FD) of the width (BW) of the BOX window area 10b (opening 19a of the BOX window area 10b) based on the width (FD) of the floating semiconductor region 23. The vertical axis indicates the dark current (unit: 10 −11 amperes) measured in the semiconductor device. The semiconductor device used in the measurements has the following structure.
Semiconductor layer 15: n-type silicon semiconductor, addition of n-type dopant Pixel isolation region 21: p-type silicon semiconductor, addition of p-type dopant
　図４Ａを参照すると、比率（ＢＷ／ＦＤ）１．５以下のエリアでは、暗電流は、ほぼゼロである。具体的には、８個の測定点（Ｐ１１、Ｐ１２、Ｐ１３、Ｐ１４、Ｐ１５、Ｐ１６、Ｐ１７、Ｐ１８）が図４Ａにプロットされている。 Referring to FIG. 4A, in the area where the ratio (BW/FD) is 1.5 or less, the dark current is almost zero. Specifically, eight measurement points (P11, P12, P13, P14, P15, P16, P17, P18) are plotted in FIG. 4A.
　図４Ａは、浮遊半導体領域２３の幅（ＦＤ）を基準にＢＯＸ窓エリア１０ｂ（ＢＯＸ窓エリア１０ｂの開口１９ａ）の幅（ＢＷ）を大きくすると、暗電流が増加する傾向を示す。比率（ＢＷ／ＦＤ）の観点では、大きすぎるＢＯＸ窓エリア１０ｂは、開口１９ａの半導体領域１３と開口１９ａを埋め込む被覆絶縁膜３１との界面に関する暗電流の低減に関して不利益である。一方、ＢＯＸ窓エリア１０ｂのサイズに比べて小さすぎる浮遊半導体領域２３は、開口１９ａの半導体領域１３と開口１９ａを埋め込む被覆絶縁膜３１との界面に関する暗電流の低減に関して不利益である。 FIG. 4A shows a tendency that dark current increases when the width (BW) of the BOX window area 10b (opening 19a of the BOX window area 10b) is increased based on the width (FD) of the floating semiconductor region 23. From the viewpoint of the ratio (BW/FD), an excessively large BOX window area 10b is disadvantageous in terms of reducing dark current at the interface between the semiconductor region 13 of the opening 19a and the covering insulating film 31 filling the opening 19a. On the other hand, floating semiconductor region 23 that is too small compared to the size of BOX window area 10b is disadvantageous in terms of reducing dark current at the interface between semiconductor region 13 in opening 19a and covering insulating film 31 filling opening 19a.
　暗電流の観点では、測定点（Ｐ１１、Ｐ１２、Ｐ１３）では、暗電流は実質的にゼロである。測定点（Ｐ１４）では、暗電流は１×１０－１１アンペア未満である。測定点（Ｐ１５）では、暗電流は２×１０－１１アンペア以下である。測定点（Ｐ１６）では、暗電流は５×１０－１１アンペア以下である。測定点（Ｐ１７）では、暗電流は８×１０－１１アンペア以下である。測定点（Ｐ１８）では、暗電流は１．４×１０－１０アンペア以下である。 In terms of dark current, the dark current is substantially zero at the measurement points (P11, P12, P13). At the measurement point (P14), the dark current is less than 1×10 −11 amperes. At the measurement point (P15), the dark current is less than 2×10 −11 amperes. At the measurement point (P16), the dark current is less than 5×10 −11 amperes. At the measurement point (P17), the dark current is less than 8×10 −11 amperes. At the measurement point (P18), the dark current is less than 1.4×10 −10 amperes.
　比率の観点では、測定点（Ｐ１１からＰ１３）では、比率（ＢＷ／ＦＤ）が１．５以下である。測定点（Ｐ１１からＰ１４）では、比率（ＢＷ／ＦＤ）が１．６５以下である。測定点（Ｐ１１からＰ１５）では、比率（ＢＷ／ＦＤ）が１．９以下である。測定点（Ｐ１１からＰ１６）では、比率（ＢＷ／ＦＤ）が２．０以下である。測定点（Ｐ１１からＰ１７）では、比率（ＢＷ／ＦＤ）が２．２以下である。測定点（Ｐ１１からＰ１８）では、比率（ＢＷ／ＦＤ）が２．３以下である。 From the perspective of the ratio, the ratio (BW/FD) is 1.5 or less at the measurement points (P11 to P13). At the measurement points (P11 to P14), the ratio (BW/FD) is 1.65 or less. At the measurement points (P11 to P15), the ratio (BW/FD) is 1.9 or less. At the measurement points (P11 to P16), the ratio (BW/FD) is 2.0 or less. At the measurement points (P11 to P17), the ratio (BW/FD) is 2.2 or less. At the measurement points (P11 to P18), the ratio (BW/FD) is 2.3 or less.
　暗電流が非常に低減される一例として、半導体領域１３の表面（１３ｂ）における寸法比率において、ＢＯＸ窓エリア１０ｂの幅（ＢＷ）は、浮遊半導体領域２３の幅（ＦＤ）の１倍より大きく１．５倍以下であることができる。つまり、
１＜（ＢＷ）／（ＦＤ）≦１．５
であることができる。比率の上限（１．５）は、求められる暗電流の上限に応じて変更されることができる。例えば、暗電流が１×１０－１１アンペアまで認められる場合、比率の上限は１．６５であり、暗電流が２×１０－１１アンペアまで認められる場合、比率の上限は１．９である。本実施形態では、比率の上限は、一例として１．５である。 As an example of how the dark current is significantly reduced, in the dimensional ratio at the surface (13b) of the semiconductor region 13, the width (BW) of the BOX window area 10b is larger than 1 times the width (FD) of the floating semiconductor region 23, and 1 .5 times or less. In other words,
1<(BW)/(FD)≦1.5
can be. The upper limit of the ratio (1.5) can be changed depending on the required upper limit of dark current. For example, if the dark current is allowed up to 1×10 −11 amps, the upper limit of the ratio is 1.65, and if the dark current is allowed up to 2×10 −11 amps, the upper limit of the ratio is 1.9. In this embodiment, the upper limit of the ratio is, for example, 1.5.
　半導体装置１１の典型的な形状に関して、例えば画素分離領域２１の内縁、浮遊半導体領域２３の外縁、及びＢＯＸ窓エリア１０ｂの開口１９ａの形状は、例えば正方形、又は長方形であることができる。 Regarding the typical shape of the semiconductor device 11, for example, the shapes of the inner edge of the pixel isolation region 21, the outer edge of the floating semiconductor region 23, and the opening 19a of the BOX window area 10b can be square or rectangular, for example.
　図４Ｂに示された平面構造では、画素分離領域２１の内縁内のエリアの形状、浮遊半導体領域２３の形状、及びＢＯＸ窓エリア１０ｂの開口１９ａの形状は、それぞれの正方形である。しかしながら、典型的な形状の観点では、画素分離領域２１の内縁、浮遊半導体領域２３の外縁、及びＢＯＸ窓エリア１０ｂの開口１９ａの形状は、それぞれの長方形であることができる。 In the planar structure shown in FIG. 4B, the shape of the area within the inner edge of the pixel isolation region 21, the shape of the floating semiconductor region 23, and the shape of the opening 19a of the BOX window area 10b are each square. However, in terms of typical shapes, the shapes of the inner edge of the pixel isolation region 21, the outer edge of the floating semiconductor region 23, and the opening 19a of the BOX window area 10b can be rectangular.
　暗電流が非常に低減される一例として、半導体領域１３の表面（１３ｂ）における面積比率において、ＢＯＸ窓エリア１０ｂの面積（ＳＢＷ）は、浮遊半導体領域２３の面積（ＳＦＤ）の１倍より大きく２．２５（１．５×１．５）倍以下であることができる。つまり、
１＜（ＳＢＷ）／（ＳＦＤ）≦２．２５
であることができる。面積比の上限（２．２５）は、例示的な値であり、求められる暗電流の上限に応じて変更されることができる。 As an example of how the dark current is greatly reduced, in terms of the area ratio on the surface (13b) of the semiconductor region 13, the area (SBW) of the BOX window area 10b is larger than 1 times the area (SFD) of the floating semiconductor region 23 and is 2. .25 (1.5×1.5) times or less. In other words,
1<(SBW)/(SFD)≦2.25
can be. The upper limit of the area ratio (2.25) is an exemplary value and can be changed depending on the required upper limit of dark current.
　図５Ａは、図３に示された半導体装置の暗電流の測定値を示すグラフである。図５Ｂは、図５Ａに示されたグラフを得るために測定される半導体装置の平面構造を示す図面である。図５Ｂを参照すると、画素分離領域２１、浮遊半導体領域２３、及びＢＯＸ窓エリア１０ｂの開口１９ａが、一画素エリア１０ａにおいて描かれている。 FIG. 5A is a graph showing measured dark current values of the semiconductor device shown in FIG. 3. FIG. 5B is a diagram showing a planar structure of a semiconductor device that is measured to obtain the graph shown in FIG. 5A. Referring to FIG. 5B, the pixel isolation region 21, the floating semiconductor region 23, and the opening 19a of the BOX window area 10b are drawn in one pixel area 10a.
　図５Ａでは、横軸は、浮遊半導体領域２３の幅（ＦＤ）を基準にした画素分離領域２１の内縁の幅（ＰＳ）の比率（ＰＳ／ＦＤ）を示す。縦軸は、半導体装置において測定された暗電流（単位：１０－１３アンペア）を示す。 In FIG. 5A, the horizontal axis indicates the ratio (PS/FD) of the width (PS) of the inner edge of the pixel isolation region 21 with respect to the width (FD) of the floating semiconductor region 23. The vertical axis indicates the dark current (unit: 10 −13 amperes) measured in the semiconductor device.
　図５Ａを参照すると、比率（ＰＳ／ＦＤ）２．２以下のエリアでは、暗電流は、８×１０－１３アンペア未満である。図５Ａを参照すると、具体的には７個の測定点（Ｐ２１、Ｐ２２、Ｐ２３、Ｐ２４、Ｐ２５、Ｐ２６、Ｐ２７）がプロットされている。 Referring to FIG. 5A, in areas with a ratio (PS/FD) of 2.2 or less, the dark current is less than 8×10 −13 amperes. Referring to FIG. 5A, specifically, seven measurement points (P21, P22, P23, P24, P25, P26, P27) are plotted.
　図５Ａは、浮遊半導体領域２３の幅（ＦＤ）を基準に画素分離領域２１の内縁の幅（ＰＳ）を大きくすると、暗電流が増加する傾向を示す。暗電流が非常に低減される図４Ａに示される比率の画素エリア１０ａにおいて、比率（ＰＳ／ＦＤ）の観点では、大きすぎる画素分離領域２１の内縁の幅は、ＢＯＸ絶縁層と半導体領域１３との界面に関する暗電流の低減に関して不利益である。一方、画素分離領域２１の内縁エリアのサイズに比べて小さすぎる浮遊半導体領域２３（又は、ＢＯＸ窓エリア１０ｂ）は、ＢＯＸ絶縁層と半導体領域１３との界面に関する暗電流の低減に関して不利益である。 FIG. 5A shows that when the width (PS) of the inner edge of the pixel isolation region 21 is increased based on the width (FD) of the floating semiconductor region 23, the dark current tends to increase. In the pixel area 10a having the ratio shown in FIG. 4A where the dark current is greatly reduced, the width of the inner edge of the pixel isolation region 21, which is too large from the viewpoint of the ratio (PS/FD), is This is disadvantageous in terms of reducing the dark current associated with the interface. On the other hand, the floating semiconductor region 23 (or BOX window area 10b) that is too small compared to the size of the inner edge area of the pixel isolation region 21 is disadvantageous in terms of reducing dark current at the interface between the BOX insulating layer and the semiconductor region 13. .
　電流の観点では、測定点（Ｐ２１、Ｐ２２、Ｐ２３、Ｐ２４）では、暗電流は、比率１．６以上２．２以下の範囲において８×１０－１３アンペア未満である。測定点（Ｐ２１からＰ２５）では、暗電流は、比率１．６以上２．４以下の範囲において９．５×１０－１３アンペア以下である。測定点（Ｐ２１からＰ２６）では、暗電流は、比率１．６以上２．６以下の範囲において１．１×１０－１２アンペア以下である。測定点（Ｐ２１からＰ２７）では、暗電流は、比率１．６以上２．８以下の範囲において１．３×１０－１２アンペア以下である。 In terms of current, at the measurement points (P21, P22, P23, P24), the dark current is less than 8×10 −13 amperes in the ratio range of 1.6 or more and 2.2 or less. At the measurement points (P21 to P25), the dark current is 9.5×10 −13 amperes or less in the ratio range of 1.6 or more and 2.4 or less. At the measurement points (P21 to P26), the dark current is 1.1×10 −12 ampere or less in the ratio range of 1.6 or more and 2.6 or less. At the measurement points (P21 to P27), the dark current is 1.3×10 −12 ampere or less in the ratio range of 1.6 or more and 2.8 or less.
　比率の観点では、測定点（Ｐ２１からＰ２４）では、比率（ＰＳ／ＦＤ）は１．６以上２．２以下である。測定点（Ｐ２１からＰ２５）では、比率（ＰＳ／ＦＤ）は、１．６以上２．４以下である。測定点（Ｐ２１からＰ２６）では、比率（ＰＳ／ＦＤ）は、１．６以上２．６以下である。測定点（Ｐ２１からＰ２７）では、比率（ＰＳ／ＦＤ）は、１．６以上２．８以下である。 From the perspective of the ratio, at the measurement points (P21 to P24), the ratio (PS/FD) is 1.6 or more and 2.2 or less. At the measurement points (P21 to P25), the ratio (PS/FD) is 1.6 or more and 2.4 or less. At the measurement points (P21 to P26), the ratio (PS/FD) is 1.6 or more and 2.6 or less. At the measurement points (P21 to P27), the ratio (PS/FD) is 1.6 or more and 2.8 or less.
　暗電流が非常に低減される一例として、半導体領域１３の表面（１３ｂ）における寸法比率において、画素分離領域２１の内縁の間隔（ＰＳ）は、浮遊半導体領域２３の幅（ＦＤ）の１倍以上であり２．２倍以下であることができる。つまり、
１≦（ＰＳ）／（ＦＤ）≦２．２
であることができる。比率の上限（２．２）は、求められる暗電流の上限に応じて変更されることができる。ここでは、比率の上限は、一例として２．２である。 As an example of how the dark current is greatly reduced, in terms of the dimension ratio at the surface (13b) of the semiconductor region 13, the distance (PS) between the inner edges of the pixel isolation region 21 is at least one times the width (FD) of the floating semiconductor region 23. and can be 2.2 times or less. In other words,
1≦(PS)/(FD)≦2.2
can be. The upper limit of the ratio (2.2) can be changed depending on the required upper limit of dark current. Here, the upper limit of the ratio is 2.2, as an example.
　半導体装置１１の典型的な形状に関して、例えば画素分離領域２１の内縁、浮遊半導体領域２３の外縁、及びＢＯＸ窓エリア１０ｂの開口１９ａの形状は、例えば正方形、又は長方形である。 Regarding the typical shape of the semiconductor device 11, for example, the shapes of the inner edge of the pixel isolation region 21, the outer edge of the floating semiconductor region 23, and the opening 19a of the BOX window area 10b are, for example, square or rectangular.
　図５Ｂに示された平面構造では、画素分離領域２１の内縁、浮遊半導体領域２３の外縁、及びＢＯＸ窓エリア１０ｂの開口１９ａの形状は、それぞれの大きさの正方形である。しかしながら、典型的な形状の観点では、画素分離領域２１の内縁、浮遊半導体領域２３の外縁、及びＢＯＸ窓エリア１０ｂの開口１９ａの形状は、それぞれの長方形であることができる。 In the planar structure shown in FIG. 5B, the shapes of the inner edge of the pixel isolation region 21, the outer edge of the floating semiconductor region 23, and the opening 19a of the BOX window area 10b are squares of the respective sizes. However, in terms of typical shapes, the shapes of the inner edge of the pixel isolation region 21, the outer edge of the floating semiconductor region 23, and the opening 19a of the BOX window area 10b can be rectangular.
　暗電流が非常に低減される一例として、半導体領域１３の表面（１３ｂ）における面積比において、画素分離領域２１の内縁内のエリアの面積（ＳＰＳ）は、浮遊半導体領域２３の面積（ＳＦＤ）の例えば１倍（比率（ＰＳ）／（ＦＤ）の下限の二乗である（ＰＳ）２／（ＦＤ）２）以上であり４．８４（２．２×２．２）倍以下であることができる。例えば
１≦（ＳＰＳ）／（ＳＦＤ）≦４．８４
であることができる。面積比の上限は、例示であって、求められる暗電流の上限に応じて変更されることができる。 As an example of how the dark current is greatly reduced, in terms of the area ratio on the surface (13b) of the semiconductor region 13, the area (SPS) of the area within the inner edge of the pixel isolation region 21 is the area (SFD) of the floating semiconductor region 23. For example, it can be greater than or equal to 1 ((PS) 2 /(FD) 2 which is the square of the lower limit of the ratio (PS)/(FD)) and less than or equal to 4.84 (2.2×2.2) times. . For example, 1≦(SPS)/(SFD)≦4.84
can be. The upper limit of the area ratio is just an example, and can be changed depending on the required upper limit of dark current.
　図４Ａ及び図５Ａでは、２種の寸法比率、具体的には寸法比率（ＢＷ）／（ＦＤ）及び（ＰＳ）／（ＦＤ）が示された。半導体装置１１では、これらの２種の比率（ＢＷ）／（ＦＤ）及び（ＰＳ）／（ＦＤ）に係る少なくともいずれか一方の条件が満たされると、半導体装置１１の暗電流が低減される。 In FIGS. 4A and 5A, two types of dimensional ratios, specifically dimensional ratios (BW)/(FD) and (PS)/(FD), are shown. In the semiconductor device 11, when at least one of the conditions regarding these two ratios (BW)/(FD) and (PS)/(FD) is satisfied, the dark current of the semiconductor device 11 is reduced.
　図６Ａ、図６Ｂ及び図６Ｃは、本実施の形態に係る半導体装置１１を作製する方法の概要を示す図面である。引き続く説明において、理解の容易のために、可能な場合には、図１から図５Ｂを参照した説明において使用された参照符号を使用する。 FIGS. 6A, 6B, and 6C are drawings showing an overview of a method for manufacturing the semiconductor device 11 according to this embodiment. In the following description, for ease of understanding, reference numerals used in the description with reference to FIGS. 1 to 5B will be used where possible.
　本実施の形態に係る半導体装置１１の作製における主要な工程を説明する。 The main steps in manufacturing the semiconductor device 11 according to this embodiment will be explained.
　図６Ａを参照すると、ＢＯＸ絶縁層１９のためのＢＯＸ絶縁膜（以下「ＢＯＸ絶縁膜（１９）」）を有するＳＯＩ基板において、フォトリソグラフィからのレジスト４１及びイオン注入を用いて、ＢＯＸ絶縁膜（１９）直下の半導体領域１３に、第２導電型の画素分離領域２１を形成する。イオン注入の後に、レジスト４１は除去される。画素分離領域２１の形成の後に又は先だって、イオン注入を用いて、第１導電型の半導体層１５を形成することができる。 Referring to FIG. 6A, in an SOI substrate having a BOX insulating film (hereinafter referred to as "BOX insulating film (19)") for a BOX insulating layer 19, using a resist 41 from photolithography and ion implantation, a BOX insulating film ( 19) Form a second conductivity type pixel isolation region 21 in the semiconductor region 13 directly below. After ion implantation, resist 41 is removed. After or before the formation of the pixel isolation region 21, the semiconductor layer 15 of the first conductivity type can be formed using ion implantation.
　図６Ｂを参照すると、ＢＯＸ絶縁膜（１９）を有するＳＯＩ基板において、フォトリソグラフィからのレジスト４３及びエッチングを用いてＢＯＸ絶縁膜（１９）を加工して、開口１９ａを有するＢＯＸ絶縁層１９を形成する。開口１９ａに現れた半導体領域１３の表面は、エッチングにさらされる。エッチングの後に、レジスト４３は除去される。 Referring to FIG. 6B, in an SOI substrate having a BOX insulating film (19), the BOX insulating film (19) is processed using a resist 43 from photolithography and etching to form a BOX insulating layer 19 having an opening 19a. do. The surface of semiconductor region 13 exposed in opening 19a is exposed to etching. After etching, resist 43 is removed.
　図６Ｃを参照すると、ＢＯＸ絶縁膜（１９）に開口１９ａを形成した後に、フォトリソグラフィからのレジスト４５及びイオン注入を用いて、浮遊半導体領域２３を形成する。レジスト４５は、ＢＯＸ窓エリア１０ｂより小さいエリアに浮遊半導体領域２３を形成するときに使用される。イオン注入の後に、レジスト４５は除去される。 Referring to FIG. 6C, after forming an opening 19a in the BOX insulating film (19), a floating semiconductor region 23 is formed using a resist 45 from photolithography and ion implantation. The resist 45 is used when forming the floating semiconductor region 23 in an area smaller than the BOX window area 10b. After ion implantation, resist 45 is removed.
　第２導電型の画素分離領域２１、ＢＯＸ絶縁膜（１９）に開口１９ａ、及び浮遊半導体領域２３を形成した後に、被覆絶縁膜３１のための絶縁膜（例えば、シリコン酸化物）を基板全面に堆積する。この堆積は、化学的気相成長法によって行われる。被覆絶縁膜３１のための絶縁膜を形成した後に、電極を形成する。 After forming the pixel isolation region 21 of the second conductivity type, the opening 19a in the BOX insulating film (19), and the floating semiconductor region 23, an insulating film (for example, silicon oxide) for the covering insulating film 31 is formed over the entire surface of the substrate. accumulate. This deposition is performed by chemical vapor deposition. After forming an insulating film for the covering insulating film 31, electrodes are formed.
　本実施形態によれば、暗電流を低減可能な構造を有する半導体装置、及び半導体装置を有する固体撮像装置が提供される。 According to the present embodiment, a semiconductor device having a structure capable of reducing dark current and a solid-state imaging device having the semiconductor device are provided.
　本実施形態は、以下に例示的に示される様々な側面を有する。 This embodiment has various aspects exemplarily shown below.
　本実施形態に係る第１側面は、半導体装置を含む。半導体装置は、第１導電型の半導体層を含む半導体領域と、前記半導体領域の表面に沿って延在すると共に前記半導体領域の前記表面のＢＯＸ窓エリアに開口を有するＢＯＸ絶縁層と、前記ＢＯＸ窓エリアにおいて前記半導体領域に設けられた前記第１導電型の浮遊半導体領域と、前記ＢＯＸ窓エリアを含む画素エリアを囲むように前記半導体領域に設けられた前記第１導電型と異なる第２導電型の画素分離領域と、を備え、前記半導体層は、前記画素分離領域の内側面及び底面に接合を成し、前記半導体領域の前記表面において、前記ＢＯＸ窓エリアの幅は、前記浮遊半導体領域の幅の１倍より大きく１．５倍以下であること、及び前記半導体領域の前記表面において、前記画素分離領域の幅は、前記浮遊半導体領域の幅の１倍以上であり２．２倍以下であること、の少なくともいずれか一方が満たされる。 The first side surface according to this embodiment includes a semiconductor device. The semiconductor device includes: a semiconductor region including a semiconductor layer of a first conductivity type; a BOX insulating layer extending along a surface of the semiconductor region and having an opening in a BOX window area on the surface of the semiconductor region; a floating semiconductor region of the first conductivity type provided in the semiconductor region in a window area; and a second conductivity type different from the first conductivity provided in the semiconductor region so as to surround a pixel area including the BOX window area. a pixel isolation region of the type, the semiconductor layer is in contact with an inner side surface and a bottom surface of the pixel isolation region, and on the surface of the semiconductor region, the width of the BOX window area is equal to the width of the floating semiconductor region. The width of the pixel isolation region is greater than 1 time and less than 1.5 times the width of the floating semiconductor region, and on the surface of the semiconductor region, the width of the pixel isolation region is more than 1 time and less than 2.2 times the width of the floating semiconductor region. At least one of the following is satisfied.
　第１側面に従う第２側面は、前記ＢＯＸ窓エリアの外において前記ＢＯＸ絶縁層の上に設けられた転送ゲートと、前記開口、前記ＢＯＸ絶縁層、前記転送ゲートを覆う絶縁膜と、を更に備え、前記半導体層は、前記半導体領域の前記表面を基準に前記浮遊半導体領域より深く設けられ、前記画素分離領域は、前記半導体領域の前記表面を基準に前記半導体層より浅く設けられることができる。 A second side according to the first side further includes a transfer gate provided on the BOX insulating layer outside the BOX window area, and an insulating film covering the opening, the BOX insulating layer, and the transfer gate. The semiconductor layer may be provided deeper than the floating semiconductor region with respect to the surface of the semiconductor region, and the pixel isolation region may be provided shallower than the semiconductor layer with respect to the surface of the semiconductor region.
　第１側面又は第２側面に従う第３側面では、前記半導体領域の前記表面において、前記ＢＯＸ窓エリアの幅は、前記浮遊半導体領域の幅の１倍より大きく１．５倍以下であることができる。 In a third side surface that follows the first side surface or the second side surface, on the surface of the semiconductor region, the width of the BOX window area may be greater than 1 time and less than or equal to 1.5 times the width of the floating semiconductor region. .
　第１側面又は第２側面に従う第４側面では、前記半導体領域の前記表面において、前記画素分離領域の幅は、前記浮遊半導体領域の幅の１倍以上であり２．２倍以下であることができる。 In a fourth side according to the first side or the second side, on the surface of the semiconductor region, the width of the pixel isolation region may be at least 1 times the width of the floating semiconductor region and no more than 2.2 times the width of the floating semiconductor region. can.
　本実施形態に係る第５側面は、固体撮像装置を備える。固体撮像装置は、２次元に配置されており第１側面から第４側面のいずれか一側面に記載された複数の半導体装置を含む撮像領域と、前記撮像領域の前記半導体装置の各々から電荷を読み出す制御を行う制御部と、を備える。 The fifth side according to the present embodiment includes a solid-state imaging device. The solid-state imaging device includes an imaging region that is two-dimensionally arranged and includes a plurality of semiconductor devices described on one of a first side surface to a fourth side surface, and a charge source from each of the semiconductor devices in the imaging region. A control unit that performs read control.
　本発明は上述した実施の形態に限定されるものではなく、本発明の主旨を逸脱しない範囲内で種々変更して実施することが可能である。そして、それらはすべて、本発明の技術思想に含まれるものである。 The present invention is not limited to the embodiments described above, and can be implemented with various changes without departing from the spirit of the present invention. All of these are included in the technical idea of the present invention.

Claims (5)

  1. 　第１導電型の半導体層を含む半導体領域と、
    　前記半導体領域の表面に沿って延在すると共に前記半導体領域の前記表面のＢＯＸ窓エリアに開口を有するＢＯＸ絶縁層と、
    　前記ＢＯＸ窓エリアにおいて前記半導体領域に設けられた前記第１導電型の浮遊半導体領域と、
    　前記ＢＯＸ窓エリアを含む画素エリアを囲むように前記半導体領域に設けられた前記第１導電型と異なる第２導電型の画素分離領域と、
    を備え、
    　前記半導体層は、前記画素分離領域の内側面及び底面に接合を成し、
    　前記半導体領域の前記表面において、前記ＢＯＸ窓エリアの幅は、前記浮遊半導体領域の幅の１倍より大きく１．５倍以下であること、
    及び
    　前記半導体領域の前記表面において、前記画素分離領域の幅は、前記浮遊半導体領域の幅の１倍以上であり２．２倍以下であること、
    の少なくともいずれか一方が満たされる、
    　半導体装置。     a semiconductor region including a first conductivity type semiconductor layer;
    a BOX insulating layer extending along a surface of the semiconductor region and having an opening in a BOX window area on the surface of the semiconductor region;
    a floating semiconductor region of the first conductivity type provided in the semiconductor region in the BOX window area;
    a pixel isolation region of a second conductivity type different from the first conductivity type provided in the semiconductor region so as to surround a pixel area including the BOX window area;
    Equipped with
    The semiconductor layer forms a junction with an inner surface and a bottom surface of the pixel isolation region,
    In the surface of the semiconductor region, the width of the BOX window area is greater than 1 time and less than 1.5 times the width of the floating semiconductor region;
    and on the surface of the semiconductor region, the width of the pixel isolation region is at least 1 time and no more than 2.2 times the width of the floating semiconductor region;
    at least one of the following is satisfied,
    Semiconductor equipment.
  2. 　前記ＢＯＸ窓エリアの外において前記ＢＯＸ絶縁層の上に設けられた転送ゲートと、
    　前記開口、前記ＢＯＸ絶縁層、前記転送ゲートを覆う絶縁膜と、
    を更に備え、
    　前記半導体層は、前記半導体領域の前記表面を基準に前記浮遊半導体領域より深く設けられ、
    　前記画素分離領域は、前記半導体領域の前記表面を基準に前記半導体層より浅く設けられる、
    　請求項１に記載された半導体装置。     a transfer gate provided on the BOX insulating layer outside the BOX window area;
    an insulating film covering the opening, the BOX insulating layer, and the transfer gate;
    further comprising;
    The semiconductor layer is provided deeper than the floating semiconductor region with respect to the surface of the semiconductor region,
    The pixel isolation region is provided shallower than the semiconductor layer with respect to the surface of the semiconductor region,
    A semiconductor device according to claim 1.
  3. 　前記半導体領域の前記表面において、前記ＢＯＸ窓エリアの幅は、前記浮遊半導体領域の幅の１倍より大きく１．５倍以下である、
    　請求項１に記載された半導体装置。     In the surface of the semiconductor region, the width of the BOX window area is greater than 1 time and less than 1.5 times the width of the floating semiconductor region,
    A semiconductor device according to claim 1.
  4. 　前記半導体領域の前記表面において、前記画素分離領域の幅は、前記浮遊半導体領域の幅の１倍以上であり２．２倍以下である、
    　請求項１に記載された半導体装置。     In the surface of the semiconductor region, the width of the pixel isolation region is at least 1 times the width of the floating semiconductor region and at most 2.2 times,
    A semiconductor device according to claim 1.
  5. 　２次元に配置されており請求項１から請求項４のいずれか一項に記載された複数の半導体装置を含む撮像領域と、
    　前記撮像領域の前記半導体装置の各々から電荷を読み出す制御を行う制御部と、
    　を備えた固体撮像装置。     an imaging area that is two-dimensionally arranged and includes a plurality of semiconductor devices according to any one of claims 1 to 4;
    a control unit that controls reading out charges from each of the semiconductor devices in the imaging region;
    A solid-state imaging device equipped with
PCT/JP2023/012331 2022-03-29 2023-03-27 Semiconductor device and solid-state imaging device WO2023190407A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008004547A1 (en) * 2006-07-03 2008-01-10 Hamamatsu Photonics K.K. Photodiode array
JP2011044548A (en) * 2009-08-20 2011-03-03 Sony Corp Solid state imaging device, electronic apparatus, and method of manufacturing the solid state imaging device
JP2011171597A (en) * 2010-02-19 2011-09-01 Oki Semiconductor Co Ltd Semiconductor device and method of manufacturing the same
WO2021205662A1 (en) * 2020-04-10 2021-10-14 株式会社オプトハブ Semiconductor image sensor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008004547A1 (en) * 2006-07-03 2008-01-10 Hamamatsu Photonics K.K. Photodiode array
JP2011044548A (en) * 2009-08-20 2011-03-03 Sony Corp Solid state imaging device, electronic apparatus, and method of manufacturing the solid state imaging device
JP2011171597A (en) * 2010-02-19 2011-09-01 Oki Semiconductor Co Ltd Semiconductor device and method of manufacturing the same
WO2021205662A1 (en) * 2020-04-10 2021-10-14 株式会社オプトハブ Semiconductor image sensor

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