WO2023185204A1

WO2023185204A1 - Control method for ferroelectric memory and related apparatus

Info

Publication number: WO2023185204A1
Application number: PCT/CN2023/071225
Authority: WO
Inventors: 刘晓真; 卜思童; 方亦陈; 谭万良; 吕杭炳; 许俊豪
Original assignee: 华为技术有限公司
Priority date: 2022-03-31
Filing date: 2023-01-09
Publication date: 2023-10-05
Also published as: CN116935918A

Abstract

Embodiments of the present application provide a control method for a ferroelectric memory and a related apparatus, used for stably enabling partial flipping of a ferroelectric device of a ferroelectric memory during write and read operations, such that the durability of the ferroelectric device is improved, and at the same time, the positive and negative stress of a ferroelectric material can be effectively balanced, thereby reducing the imprinting effect. Specific operation is as follows: within a first time period of a write operation, a control apparatus for the ferroelectric memory setting the voltage of a pre-charged line to a first voltage, and pre-charging the voltage of a floating gate to a second voltage, wherein the first voltage is greater than the second voltage, and a difference obtained by subtracting the second voltage from the first voltage is used for turning on a transistor on the pre-charged line; and within a second time period of the write operation, setting the voltage of the pre-charged line to 0 V, and setting the voltage of a selected word line to a third voltage, the third voltage and the second voltage being used for writing data to be written.

Description

A control method and related devices for ferroelectric memory

This application requires the priority of the Chinese patent application submitted to the State Intellectual Property Office of China on March 31, 2022, with the application number 202210333051.0 and the invention title "A control method for ferroelectric memory and related devices", and its entire content is approved by This reference is incorporated into this application.

Technical field

The present application relates to the field of storage, and in particular, to a control method of a ferroelectric memory and related devices.

Background technique

Ferroelectric memory utilizes the characteristics that ferroelectric materials can undergo spontaneous polarization, and the polarization intensity can be reoriented with the action of an external electric field for storage. Specifically, when the ferroelectric material is in an electric field, it spontaneously emits polarization; when the electric field is removed, part of the polarization state can still be maintained, and the polarization intensity at this time is called the residual polarization intensity; and then the direction of the residual polarization intensity is used. Different, applying an electric field in the same direction makes the ferroelectric flip charges different, so that the different flip charges are used to store

information

0 and 1. The relationship between flipping charge and voltage can be shown in Figure 1.

The current writing operation method of ferroelectric memory is usually to use strong writing during writing (that is, the charge of the ferroelectric material completes the full-loop flip), and when reading message 0, the destruction operation is weak writing. , the write-back operation is a forced write. If it is read continuously, it will cause an imbalance between the two states of the ferroelectric material, causing the charge flip in the ferroelectric material to shift to one side.

That is, the reversal of the full-loop charge of the ferroelectric memory during the writing operation will cause the writing performance of the ferroelectric memory to deteriorate as the use time increases.

Contents of the invention

Embodiments of the present application provide a control method and related devices for a ferroelectric memory, which are used to enable the ferroelectric memory to stably enter the partial flip of the ferroelectric device during writing and reading operations, thereby improving the durability of the ferroelectric device. performance, while effectively balancing the positive and negative stress balance of ferroelectric materials, thereby mitigating the imprinting effect.

In a first aspect, the present application provides a control method for a ferroelectric memory. The specific operation is as follows: the control device of the ferroelectric memory sets the voltage of the precharge line to the first voltage during the first time period of the write operation. And precharge the voltage of the floating gate to a second voltage, wherein the first voltage is greater than the second voltage, and the difference between the first voltage minus the second voltage is used to turn on the transistor on the precharge line; During the second time period of the write operation, the voltage of the precharge line is set to 0 volts V, and the voltage of the selected ferroelectric memory cell is set to a third voltage. The third voltage and the second voltage are used for Write the data to be written. In the technical solution provided by this application, when performing a write operation, one end of the selected ferroelectric storage unit in the ferroelectric memory is precharged, so that one end of the ferroelectric storage unit has a fixed voltage and the other end is floating. The state is similar to the state when the ferroelectric memory unit performs a read operation, so that the charge of the ferroelectric material in the ferroelectric memory unit does not have to undergo full-loop flipping, thereby improving the performance of the ferroelectric device in the ferroelectric memory. Durability, while effectively balancing the positive and negative stress balance of ferroelectric materials, thereby mitigating the imprinting effect.

Optionally, depending on the writing message, the polarity of the electric field loaded between the capacitors of the ferroelectric memory is different, that is, the voltages across the capacitors are different. Specifically, when the data to be written is 0, the The third voltage is greater than the second voltage; when the data to be written is 1, the third voltage is less than the second voltage.

Optionally, when the voltages at both ends of the capacitor of the ferroelectric memory are different, the specific settings can be as follows: when the data to be written is 0, the second voltage is 0V, and the third voltage is the first preset voltage. value, wherein the first preset value is smaller than the first voltage but greater than 0V; when the data to be written is 1, the second voltage is the first preset value, and the third voltage is 0V.

Optionally, based on the above solution, this control method may also include a control method for the read operation, which specifically includes: setting the voltage of the precharge line to the first voltage during the first time period of the read operation. and precharge the voltage of the floating gate to the second voltage, wherein the first voltage is greater than the second voltage, and the difference between the first voltage minus the second voltage is used to turn on the precharge line. transistor, the second voltage is greater than 0V; during the second time period of the read operation, the voltage of the precharge line is set to 0V, and the voltage of the selected ferroelectric memory cell is set to 0V.

Optionally, based on the above solution, this control method may also include a control method for the read operation, specifically including:

During the first time period of the read operation, the voltage of the precharge line is set to the first voltage and the voltage of the floating gate is precharged to 0V, wherein the first voltage is used to turn on the precharge line on the transistor; during the second time period of the read operation, set the voltage of the precharge line to 0V, and set the voltage of the selected ferroelectric memory cell to the second voltage, and the first voltage is greater than the second voltage and the second voltage is greater than 0V.

Optionally, the ferroelectric memory cells of the ferroelectric memory can have different structures, such as one transmission tube and one capacitor (One Transistor One Capacitor, 1T1C) structure, one transmission tube n capacitors (One Transistor N Capacitor, 1TnC) 1TnC structure, 2T1C structure, 2T2C structure or 2TnC structure, etc. Depending on the structure, the control device has different ways of setting the voltage of the selected ferroelectric memory cell:

In one possible implementation, the precharge line is a control line, and the control device can set the voltage of the selected word line in the selected ferroelectric memory unit to the third voltage.

In another possible implementation, if the precharge line is a selected word line, the control device can set the voltage of the selected plate line in the selected ferroelectric memory unit to be the third voltage.

In a second aspect, the present application provides a control device for a ferroelectric memory, which device has the function of realizing the behavior of the control device of the ferroelectric memory in the first aspect. This function can be implemented by hardware, or it can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

In a possible implementation, the device includes a unit or circuit for performing each step of the above first aspect. For example, the device includes: a first setting circuit for setting the voltage of the precharge line to a first voltage and precharging the voltage of the floating gate to a second voltage during a first time period of the write operation, wherein, The first voltage is greater than the second voltage, and the difference between the first voltage minus the second voltage is used to turn on the transistor on the precharge line; a second setting circuit is used to perform the second step of the write operation. During the time period, the voltage of the precharge line is set to 0 volts V, and the voltage of the selected ferroelectric memory cell is set to a third voltage. The third voltage and the second voltage are used to write data to be written.

Optionally, a storage circuit is also included for saving necessary program instructions and data for the control device of the ferroelectric memory.

In a possible implementation, the device includes: a processor and a transceiver, and the processor is configured to support the control device of the ferroelectric memory to perform corresponding functions in the method provided by the first aspect. The transceiver is used to instruct the communication between the control device of the ferroelectric memory and other devices, such as receiving instructions to write message 0 or write message 1 or read messages sent by other devices. Optionally, this device may also include a memory coupled to the processor, which stores necessary program instructions and data for controlling the ferroelectric memory.

In a possible implementation, when the device is a chip within a control device of a ferroelectric memory, the chip includes: a processing module and a transceiver module. The processing module may be, for example, a processor, and the processor is used to write During the first period of operation, the voltage of the precharge line is set to a first voltage and the voltage of the floating gate is precharged to a second voltage, wherein the first voltage is greater than the second voltage, and the first voltage minus The difference between the second voltage and the second voltage is at least greater than the conduction threshold used to turn on the transistor on the precharge line; during the second time period of the write operation, the voltage of the precharge line is set to 0 volts V , and set the voltage of the selected ferroelectric memory cell to a third voltage, and the electric field formed by the third voltage and the second voltage corresponds to be used to write the data to be written. The transceiver module may be, for example, an input/output interface, a pin or a circuit on the chip, and transmits writing or reading instructions to other chips or modules coupled to the chip. The processing module can execute computer execution instructions stored in the storage unit to support the control device of the ferroelectric memory to execute the method provided in the first aspect. Optionally, the storage unit may be a storage unit within the chip, such as a register, cache, etc., or the storage unit may be a storage unit located outside the chip, such as a read-only memory (ROM) or a memory unit. Other types of static storage devices that store static information and instructions, random access memory (random access memory, RAM), etc.

In a possible implementation, the device includes a communication interface and a logic circuit, the communication interface is used to receive a write instruction; the logic circuit is used to change the voltage of the precharge line during the first time period of the write operation. Set to a first voltage and precharge the voltage of the floating gate to a second voltage, where the first voltage is greater than the second voltage, and the difference between the first voltage minus the second voltage is used to turn on the precharge transistor on the line; during the second time period of the write operation, the voltage of the precharge line is set to 0 volts V, and the voltage of the selected ferroelectric memory cell is set to a third voltage, the third voltage is the same as the The second voltage is used to write data to be written.

Among them, the processor mentioned in any of the above places can be a general central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more Integrated circuit for controlling program execution of the above aspects of data transmission methods.

In a third aspect, embodiments of the present application provide a computer-readable storage medium that stores computer instructions, and the computer instructions are used to execute the method of any possible implementation of any of the above aspects.

In a fourth aspect, embodiments of the present application provide a computer program product containing instructions that, when run on a computer, cause the computer to execute the method in any one of the above aspects.

In a fifth aspect, the present application provides a chip system that includes a processor for supporting a control device of a ferroelectric memory to implement the functions involved in the above aspects, such as generating or processing the data involved in the above methods and /or information. In a possible design, the chip system also includes a memory, which is used to save the necessary program instructions and data for the control device of the ferroelectric memory to realize the functions of any of the above aspects. The chip system can be composed of chips or include chips and other discrete devices.

Description of drawings

Figure 1 is a schematic diagram of the relationship between electric field and charge reversal of ferroelectric materials in ferroelectric memory;

Figure 2a is a structural schematic diagram of the write 0 operation in the 2TnC structure;

Figure 2b is a schematic diagram of the charge flip of writing 0 operation in the 2TnC structure;

Figure 3a is a structural schematic diagram of the read operation under the 2TnC structure;

Figure 3b is a schematic diagram of the charge flipping of the read operation under the 2TnC structure;

Figure 4 is a schematic diagram of the imprinting effect;

Figure 5 is a schematic structural diagram of a ferroelectric memory applied in an embodiment of the present application;

Figure 6 is a schematic diagram of a control method of a ferroelectric memory in an embodiment of the present application;

Figure 7a is a structural schematic diagram of the write 0 operation and the write 1 operation under the 2TnC structure in the embodiment of the present application;

Figure 7b is a schematic diagram of charge flipping between write 1 operation and write 0 operation in the 2TnC structure in the embodiment of the present application;

Figure 8 is a schematic diagram and simulation waveform diagram of charge reversal in which the initial state is 0 and alternately writes 0 and 1 in the embodiment of the present application;

Figure 9 is a schematic diagram and simulation waveform diagram of charge reversal in which the initial state is 1 and alternately writes 0 and 1 in the embodiment of the present application;

Figure 10a is a schematic structural diagram of a control device of a ferroelectric memory in an embodiment of the present application;

Figure 10b is another structural schematic diagram of the control device of the ferroelectric memory in the embodiment of the present application;

Figure 10c is another structural schematic diagram of the control device of the ferroelectric memory in the embodiment of the present application;

FIG. 11 is another structural schematic diagram of a control device of a ferroelectric memory in an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application are described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. . Persons of ordinary skill in the art will know that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

The terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments described herein can be practiced in sequences other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or modules and need not be limited to those explicitly listed. Those steps or modules may instead include other steps or modules not expressly listed or inherent to the processes, methods, products or devices. The naming or numbering of steps in this application does not mean that the steps in the method flow must be executed in the time/logical sequence indicated by the naming or numbering. The process steps that have been named or numbered can be implemented according to the purpose to be achieved. The order of execution can be changed for technical purposes, as long as the same or similar technical effect can be achieved. The division of units presented in this application is a logical division. In actual applications, there may be other divisions. For example, multiple units may be combined or integrated into another system, or some features may be ignored. , or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed may be through some interfaces, and the indirect coupling or communication connection between units may be electrical or other similar forms. There are no restrictions in the application. Furthermore, the units or subunits described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed into multiple circuit units, and some or all of them may be selected according to actual needs. unit to achieve the purpose of this application plan.

It should be noted that components in the various figures may be exaggerated for illustration and are not necessarily proportionally correct. In the various figures, identical or functionally identical components are assigned the same reference numerals. In the present invention, unless otherwise specified, “arranged on,” “arranged on,” and “arranged on” do not exclude the presence of intermediates between the two. In addition, "arranged on or above" only indicates the relative positional relationship between the two components. Under certain circumstances, such as after reversing the product direction, it can also be converted to "arranged on or below", and vice versa. Of course. Here, the term "substrate" refers to the material to which subsequent layers of material are added. The substrate itself can be patterned. Material added over the substrate can be patterned, or can remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, arsenide, indium phosphide, etc. Alternatively, the substrate may be made of electrically non-conductive material, such as glass, plastic, or sapphire wafers. In the present invention, each embodiment is only intended to illustrate the solution of the present invention and should not be construed as limiting. In the present invention, unless otherwise specified, the quantifiers "a" and "一" do not exclude the scenario of multiple elements.

It should also be noted here that in the embodiments of the present invention, for the sake of clarity and simplicity, only some parts or assemblies may be shown. However, those of ordinary skill in the art can understand that under the teachings of the present invention, they may be modified according to specific The scene needs to add the required parts or components. In addition, features of different embodiments of the invention may be combined with each other unless stated otherwise. For example, a certain feature in the second embodiment can be used to replace a corresponding feature in the first embodiment or a feature with the same or similar function, and the resulting embodiment also falls within the disclosure scope or recording scope of the present application. It should also be noted here that within the scope of the present invention, terms such as "the same", "equal", and "equal to" do not mean that the two values are absolutely equal, but allow a certain reasonable error. That is to say, the The wording also covers "substantially the same", "substantially equal", and "substantially equal to". By analogy, in the present invention, the terms "perpendicular to", "parallel to", etc. indicating directions also include the meanings of "substantially perpendicular to" and "substantially parallel to".

In addition, the numbering of the steps of each method of the present invention does not limit the execution order of the method steps. Unless otherwise stated, method steps may be performed in a different order.

Finally, in the present invention, the controller may be implemented in software, hardware or firmware or a combination thereof. A controller can exist alone or be part of a component.

information

0 and 1. The relationship between flipping charge and voltage can be shown in Figure 1. The current writing operation method of ferroelectric memory usually uses forced writing during writing (that is, the charge of the ferroelectric material completes the full-loop flip). When the read operation reads message 0, the destruction operation is weak writing, and the write-back operation is strong writing. If the reading operation is continued, the two states of the ferroelectric material will be unbalanced, causing the charge in the ferroelectric material to flip in the opposite direction. Offset on one side. For example, the 2TnC structure shown in Figure 2a is used to illustrate the write 0 operation: during the writing process, the voltage of CL is raised to 2.5V to turn on the transistor on the CL, and then the selected write bit is The voltage on the write bit line (WBL) is transmitted to the floating gate (FG) in the ferroelectric memory; finally, the voltage of the word line is pulled up or down to complete the writing of the ferroelectric memory. The ferroelectric storage unit of the ferroelectric memory maintains a stable voltage difference of 2V across the capacitor, causing the charge of the capacitor to complete a full-loop flip, so the write operation is defined as a strong write. The schematic diagram of the voltage and charge flip is shown in Figure 2b. The reading operation is explained with the 2TnC structure shown in Figure 3a: During the reading process, in the first period of time, the voltage of CL is pulled up to 2.5V so that the transistor on CL is turned on, and then the The voltage on the selected WBL is transferred to the FG in the ferroelectric memory to precharge FG to 2V; during the second period, the voltage of CL is pulled down to 0V, thereby turning off the transistor on the CL, and then pulled up Low WL makes the ferroelectric flip. Since the transistor on CL is turned off, the FG terminal is in a floating state, and its voltage will gradually decrease with the ferroelectric flip, thereby reducing the voltage difference between the two ends of the ferroelectric and inhibiting the subsequent ferroelectric flip, so the ferroelectric eventually Failure to complete a complete full-loop flip is defined as weak writing. The writeback after the read message 0 operation is to turn on the transistor on the CL, which is equivalent to a complete write 0 operation, so it is a forced write. It can be seen from the above description that the reversal of the full-loop charge of the ferroelectric memory during the write operation will cause the ferroelectric memory to have a tendency to deteriorate in its writing performance as the use time increases. The destruction operation when reading message 0 is a weak write, and the write-back operation is a strong write. If read continuously, it will cause an imbalance between the two states of ferroelectricity, causing the capacitor in the ferroelectric storage unit of the ferroelectric memory to The charge flip is shifted to one side, which is the imprinting effect (Imprint). The schematic diagram of the effect can be shown in Figure 4.

In order to solve this problem, this application provides the following technical solution: during the first period of writing operation, the control device of the ferroelectric memory sets the voltage of the precharge line to the first voltage and precharges the voltage of the floating gate. to a second voltage, wherein the first voltage is greater than the second voltage, and the difference between the first voltage and the second voltage is at least greater than the conduction threshold of the transistor on the precharge line; During the second period of the write operation, the voltage of the precharge line is set to 0, and the voltage of the selected word line is set to a third voltage, and the third voltage corresponds to the electric field formed by the second voltage. Data to be written.

It can be understood that the technical solution provided by this application can be applied to ferroelectric memories of various structures, such as the 2TnC structure ferroelectric memory shown in Figure 2a, and can also be applied to the 1T1C structure ferroelectric memory shown in Figure 5. Electric storage and ferroelectric memory with 1TnC structure are not limited here.

Please refer to Figure 6 for details. The control method of the ferroelectric memory in the embodiment of the present application is explained:

601. During the first time period of the write operation, set the voltage of the precharge line to the first voltage and precharge the voltage of the floating gate to the second voltage, wherein the first voltage is greater than the second voltage, and the The difference between the first voltage minus the second voltage is used to turn on the transistor on the precharge line.

In this embodiment, during the first time period of the write operation, the control device sets the voltage of the precharge line to the first voltage and precharges the voltage of the floating gate of the ferroelectric memory to the second voltage, that is, The control device preliminarily pulls up one end of the ferroelectric memory to a fixed voltage, wherein the first voltage is greater than the second voltage, and the difference between the first voltage and the second voltage is at least greater than the precharge line The conduction threshold of the transistor.

Taking the 2TnC structure shown in Figure 7a as an example, when writing 0 to the ferroelectric memory cell in the ferroelectric memory shown in Figure 7a, the first voltage can be set to 2.5V during the first time period. (Assume that 2.5V is the conduction threshold of the CL transistor). At this time, the CL transistor is turned on, thereby transmitting the voltage 0V on the WBL to the FG of the ferroelectric memory cell, that is, the first voltage at this time is 2.5V, and the second voltage is 0V. When writing 1 to the ferroelectric memory cell in the ferroelectric memory shown in Figure 7a, during the first time period, the first voltage can be set to 2.5V (assuming that 2.5V is the conduction of the transistor of the CL threshold), at this time the transistor of the CL is turned on, thereby transferring the voltage 2V on the WBL to the FG of the ferroelectric memory cell. That is, the first voltage is 2.5V and the second voltage is 2V.

602. During the second time period of the write operation, set the voltage of the precharge line to 0, and set the voltage of one end of the selected ferroelectric memory unit to a third voltage. The third voltage is the same as the second voltage. Used to write data to be written.

In this embodiment, during the second time period of the write operation, the control device lowers the voltage setting of the precharge line from the first voltage to the turn-off threshold of the transistor on the precharge line, such as 0V. Then the voltage at one end of the selected ferroelectric memory cell is set to a third voltage. At this time, the electric field formed by the third voltage and the second voltage corresponds to the data to be written.

Taking the 2TnC structure shown in Figure 7a as an example, when the ferroelectric memory cell in the ferroelectric memory shown in Figure 7a writes 0, the first voltage can be pulled down to 0V during the second time period. , (assuming that 0V is the turn-off threshold of the CL transistor), at this time, the CL transistor is turned off, and the voltage on the selected word line is pulled up to 2V. At the same time, because the transistor is turned off, FG is in a floating state. , so the voltage of the FG will gradually increase with the ferroelectric flip, thereby reducing the voltage difference between the two ends of the ferroelectric, thereby inhibiting the subsequent ferroelectric flip, so the capacitor of the ferroelectric memory cannot ultimately complete a complete full-loop flip. The charge flip situation can be shown in (a) in Figure 7b.

When writing 1 to the ferroelectric memory cell in the ferroelectric memory shown in Figure 7a, during the second time period, the first voltage can be pulled down to 0V (assuming that 0V is the turn-off of the CL transistor threshold), at this time the transistor of the CL is turned off, and the voltage on the selected word line is pulled down to 0V. At the same time, because the transistor is turned off, the FG is in a floating state, so the voltage of the FG will change with the iron The ferroelectric flip gradually decreases, thereby reducing the voltage difference between the two ends of the ferroelectric, thereby inhibiting subsequent ferroelectric flips, so the capacitor of the ferroelectric memory cannot ultimately complete a complete full-loop flip. The charge flip situation can be shown as (b) in Figure 7b.

In this embodiment, the loading conditions of the precharge line and the third voltage and the second voltage may vary according to the structure of the ferroelectric memory:

In one possible implementation, when the ferroelectric memory has a 2TnC structure, the precharge line is a control line, and the control device can set the voltage of the selected word line in the selected ferroelectric memory unit to the third voltage, and at the same time Precharge the second voltage of the write bit line to the FG.

In another possible implementation, when the ferroelectric memory has a 1TnC structure or a 1T1C structure, and the precharge line is the selected word line, the control device can set the voltage of the selected plate line in the selected ferroelectric memory unit to The third voltage also precharges the second voltage on the bit line to the FG.

In this solution, the read operation of the ferroelectric memory can be controlled according to the solution shown in Figure 3a and Figure 3b, which will not be described again here.

The technical solution provided by this application is explained below with a specific simulation result. By establishing a nonlinear data fitting model for ferroelectric materials, circuit simulation is performed. For a full-loop case with a charge amount of 32, 0 and 1 are alternately written (or Reading and writing back is equivalent to the operation of alternately writing 0 and writing 1). The simulation results are shown in Figure 8 to Figure 9:

In the results shown in Figure 8, the initial state is 0, and after 6 consecutive readings, it enters a stable subloop, and the positive and negative Pr is approximately +10.9/-9.

In the results shown in Figure 9, the initial state is 1, and after 7 consecutive readings, it enters a stable subloop, and the positive and negative Pr is approximately +8.3/-11.8.

In the technical solution provided by this application, when performing a write operation, one end of the selected ferroelectric storage unit in the ferroelectric memory is precharged, so that one end of the ferroelectric storage unit has a fixed voltage and the other end is floating. The state is similar to the state when the ferroelectric memory unit performs a read operation, so that the charge of the ferroelectric material in the ferroelectric memory unit does not have to undergo full-loop flipping, thereby improving the performance of the ferroelectric device in the ferroelectric memory. Durability, while effectively balancing the positive and negative stress balance of ferroelectric materials, thereby mitigating the imprinting effect.

Specifically, please refer to Figure 10a. In the embodiment of the present application, the control device 1000 of the ferroelectric memory includes: a first setting circuit 1001, used to set the voltage of the precharge line to The first voltage precharges the voltage of the floating gate to a second voltage, wherein the first voltage is greater than the second voltage, and the difference between the first voltage minus the second voltage is used to turn on the The transistor on the precharge line;

The second setting circuit 1002 is used to set the voltage of the precharge line to 0 volts V, and set the voltage of the selected ferroelectric memory cell to a third voltage. The third voltage and the second voltage are used for writing Enter the data to be written.

Optionally, when the data to be written is 0, the third voltage is greater than the second voltage;

When the data to be written is 1, the third voltage is smaller than the second voltage.

Optionally, when the data to be written is 0, the second voltage is 0V, and the third voltage is a first preset value, wherein the first preset value is smaller than the first voltage but Greater than 0V;

When the data to be written is 1, the second voltage is the first preset value, and the third voltage is 0V.

Optional, as shown in Figure 10b for details, the device also includes:

The third setting circuit 1003 is used to set the voltage of the precharge line to the first voltage and precharge the voltage of the floating gate to the second voltage during the first time period of the read operation. , wherein the first voltage is greater than the second voltage, the difference between the first voltage minus the second voltage is used to turn on the transistor on the precharge line, and the second voltage is greater than 0V ;

The fourth setting circuit 1004 is used to set the voltage of the precharge line to 0V and set the voltage of the selected ferroelectric memory cell to 0V during the second time period of the read operation.

Optionally, please refer to FIG. 10c for details. The device further includes: a fifth setting circuit 1005, configured to set the voltage of the precharge line to the first voltage during the first time period of the read operation. A voltage and precharging the voltage of the floating gate to 0V, wherein the first voltage is used to turn on the transistor on the precharge line;

The sixth setting circuit 1006 is used to set the voltage of the precharge line to 0V during the second time period of the read operation, and set the voltage of the selected ferroelectric memory unit to the second voltage, so The first voltage is greater than the second voltage and the second voltage is greater than 0V.

Optionally, the precharge line is a control line, and the second setting circuit 1002 is specifically used to set the voltage of the selected word line to the third voltage.

Optionally, the precharge line is a selected word line, and the second setting circuit 1002 is specifically used to set the voltage of the selected plate line to the third voltage.

Figure 11 shows a possible structural schematic diagram of a control device 1100 of a ferroelectric memory in the above embodiment. The control device 1100 of the ferroelectric memory can be configured as the control device of the aforementioned ferroelectric memory. The control device 1100 of the ferroelectric memory may include: a processor 1102, a computer-readable storage medium/memory 1103, a transceiver 1104, an input device 1105 and an output device 1106, and a bus 1101. Among them, processors, transceivers, computer-readable storage media, etc. are connected through the bus. The embodiments of the present application do not limit the specific connection medium between the above components.

In an exemplary solution, the processor 1102 is configured to set the voltage of the precharge line to the first voltage and precharge the voltage of the floating gate to the second voltage during the first time period of the write operation, wherein, The first voltage is greater than the second voltage, and the difference between the first voltage minus the second voltage is used to turn on the transistor on the precharge line; during the second time period of the write operation Within, the voltage of the precharge line is set to 0 volts V, and the voltage of the selected ferroelectric memory cell is set to a third voltage. The third voltage and the second voltage are used to write data to be written.

Optionally, the processor 1102 is configured to set the voltage of the precharge line to the first voltage and precharge the voltage of the floating gate to the third voltage during the first period of the read operation. Two voltages, wherein the first voltage is greater than the second voltage, the difference between the first voltage minus the second voltage is used to turn on the transistor on the precharge line, and the second voltage Greater than 0V; during the second time period of the read operation, the voltage of the precharge line is set to 0V, and the voltage of the selected ferroelectric memory unit is set to 0V.

Optionally, the processor 1102 is configured to set the voltage of the precharge line to the first voltage and precharge the voltage of the floating gate to 0V during the first time period of the read operation. , wherein the first voltage is used to turn on the transistor on the pre-charge line; during the second time period of the read operation, the voltage of the pre-charge line is set to 0V, and the selected iron The voltage of the electrical storage unit is the second voltage, the first voltage is greater than the second voltage, and the second voltage is greater than 0V.

Optionally, the precharge line is a control line, and the processor 1102 is specifically configured to set the voltage of the selected word line to the third voltage.

Optionally, the precharge line is a selected word line, and the processor 1102 is specifically configured to set the voltage of the selected board line to the third voltage.

It can be understood that Figure 11 only shows a simplified design of the control device of the ferroelectric memory. In actual applications, the control device of the ferroelectric memory can include any number of transceivers, processors, memories, etc., and all can The control devices that implement the ferroelectric memory of the present application are all within the protection scope of the present application.

The processor 1102 involved in the above device 1100 can be a general-purpose processor, such as a CPU, a network processor (NP), a microprocessor, etc., or it can be an ASIC, or one or more programs used to control the solution of the present application. implemented integrated circuit. It can also be a digital signal processor (DSP), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The controller/processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of DSP and microprocessors, and so on. A processor typically performs logical and arithmetic operations based on program instructions stored in memory.

The bus 1101 involved above may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in Figure 11, but it does not mean that there is only one bus or one type of bus.

The computer-readable storage medium/memory 1103 mentioned above may also store operating systems and other application programs. Specifically, the program may include program code, which includes computer operating instructions. More specifically, the above-mentioned memory may be ROM, other types of static storage devices that can store static information and instructions, RAM, other types of dynamic storage devices that can store information and instructions, disk memory, etc. Memory 1103 may be a combination of the above storage types. And the above-mentioned computer-readable storage medium/memory can be in the processor, can also be distributed outside the processor, or distributed on multiple entities including the processor or processing circuits. The above computer-readable storage medium/memory can be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials.

Alternatively, embodiments of the present application also provide a general processing system, for example, commonly referred to as a chip. The general processing system includes: one or more microprocessors that provide processor functions; and an external memory that provides at least a part of the storage medium. , all of which are connected together with other supporting circuits through an external bus architecture. When the instructions stored in the memory are executed by the processor, the processor is caused to execute some or all of the steps in the data transmission method in the embodiment shown in FIG. 6 by the control device of the ferroelectric memory, and/or for the steps described in this application. other processes of technology.

The steps of the method or algorithm described in connection with the disclosure of this application can be implemented in hardware or by a processor executing software instructions. Software instructions can be composed of corresponding software modules, and the software modules can be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, mobile hard disks, CD-ROM or any other form of storage well known in the art. in the medium. An exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage media may be located in an ASIC. Additionally, the ASIC can be located in the terminal. Of course, the processor and the storage medium can also exist as discrete components in the control device of the ferroelectric memory.

Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be described again here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated units can be implemented in the form of hardware or software functional units.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code. .

Claims

A control method for a ferroelectric memory, characterized by including:

During the first time period of the write operation, the voltage of the precharge line is set to a first voltage and the voltage of the floating gate is precharged to a second voltage, wherein the first voltage is greater than the second voltage, so The difference between the first voltage minus the second voltage is used to turn on the transistor on the precharge line;

During the second time period of the write operation, the voltage of the precharge line is set to 0 volts V, and the voltage of the selected ferroelectric memory cell is set to a third voltage, and the third voltage is the same as the third voltage. The second voltage is used to write the data to be written.
The method according to claim 1, characterized in that when the data to be written is 0, the third voltage is greater than the second voltage;

When the data to be written is 1, the third voltage is smaller than the second voltage.
The method according to claim 2, characterized in that when the data to be written is 0, the second voltage is 0V, and the third voltage is a first preset value, wherein the first preset value The set value is less than the first voltage but greater than 0V;

When the data to be written is 1, the second voltage is the first preset value, and the third voltage is 0V.
The method according to any one of claims 1 to 3, characterized in that the method further includes:

During a first time period of a read operation, the voltage of the precharge line is set to the first voltage and the voltage of the floating gate is precharged to the second voltage, wherein the first voltage Greater than the second voltage, the difference between the first voltage minus the second voltage is used to turn on the transistor on the precharge line, and the second voltage is greater than 0V;

During the second time period of the read operation, the voltage of the precharge line is set to 0V, and the voltage of the selected ferroelectric memory cell is set to 0V.
The method according to any one of claims 1 to 3, characterized in that the method further includes:

During the first period of the read operation, the voltage of the precharge line is set to the first voltage and the voltage of the floating gate is precharged to 0V, wherein the first voltage is used to turn on The transistor on the precharge line;

During the second time period of the read operation, the voltage of the precharge line is set to 0V, and the voltage of the selected ferroelectric memory unit is set to the second voltage, and the first voltage is greater than the third voltage. two voltages and the second voltage is greater than 0V.
The method according to any one of claims 1 to 5, wherein the precharge line is a control line, and setting the voltage of the selected ferroelectric memory unit to the third voltage includes:

The voltage of the selected word line is set to the third voltage.
The method according to any one of claims 1 to 5, wherein the precharge line is a selected word line, and setting the voltage of the selected ferroelectric memory cell to a third voltage includes:

Set the voltage of the selected board line to the third voltage.
A control device for a ferroelectric memory, which is characterized by including:

A first setting circuit configured to set the voltage of the precharge line to a first voltage and precharge the voltage of the floating gate to a second voltage during a first period of writing operation, wherein the first voltage is greater than The second voltage, the difference between the first voltage minus the second voltage is used to turn on the transistor on the precharge line;

A second setting circuit, configured to set the voltage of the precharge line to 0V during the second time period of the writing operation, and set the voltage of the selected ferroelectric memory unit to a third voltage, the third The voltage and the second voltage are used to write data to be written.
The device according to claim 8, wherein when the data to be written is 0, the third voltage is greater than the second voltage;

When the data to be written is 1, the third voltage is smaller than the second voltage.
The device according to claim 9, characterized in that when the data to be written is 0, the second voltage is 0V, and the third voltage is a first preset value, wherein the first preset value The set value is less than the first voltage but greater than 0V;

When the data to be written is 1, the second voltage is the first preset value, and the third voltage is 0V.
The device according to any one of claims 8 to 10, characterized in that the device further includes:

a third setting circuit configured to set the voltage of the precharge line to the first voltage and precharge the voltage of the floating gate to the second voltage during the first time period of the read operation, Wherein, the first voltage is greater than the second voltage, the difference between the first voltage minus the second voltage is used to turn on the transistor on the precharge line, and the second voltage is greater than 0V;

A fourth setting circuit is used to set the voltage of the precharge line to 0V and set the voltage of the selected ferroelectric memory cell to 0V during the second time period of the read operation.
The device according to any one of claims 8 to 10, characterized in that the device further includes:

A fifth setting circuit, configured to set the voltage of the precharge line to a first voltage and precharge the voltage of the floating gate to 0V during the first time period of the read operation, wherein the first The voltage is used to turn on the transistor on the precharge line;

A sixth setting circuit is used to set the voltage of the precharge line to 0V during the second time period of the read operation, and set the voltage of the selected ferroelectric memory unit to the second voltage, the The first voltage is greater than the second voltage and the second voltage is greater than 0V.
The device according to any one of claims 8 to 12, wherein the precharge line is a control line, and the second setting circuit is specifically used to set the voltage of the selected word line to the third voltage. .
The device according to any one of claims 8 to 12, wherein the precharge line is a selected word line, and the second setting circuit is specifically used to set the voltage of the selected plate line to the third Voltage.
A computer-readable storage medium stores computer instructions, and the computer instructions are used to execute the control method described in any one of the above claims 1 to 7.
A computer program product containing instructions that, when run on a computer, causes the computer to execute the control method described in any one of claims 1 to 7 above.