WO2023181892A1

WO2023181892A1 - Memory controller and memory device

Info

Publication number: WO2023181892A1
Application number: PCT/JP2023/008414
Authority: WO
Inventors: 英明大久保; 健一中西
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2022-03-22
Filing date: 2023-03-06
Publication date: 2023-09-28

Abstract

A memory controller according to one aspect of the present disclosure controls a read operation for a nonvolatile memory cell array unit, and includes a detection unit and a control unit. The detection unit detects the number of bits in which information corresponding to a high resistance state is erroneously read as information corresponding to a low resistance state, on the basis of first data with an error correction code read from a plurality of first memory cells that are part of a plurality of memory cells, and second data obtained by performing error correction using an error correction code on the first data. The control unit determines whether or not to change read voltages applied to the plurality of first memory cells, on the basis of the number of bits detected by the detection unit.

Description

Memory controller and memory device

The present disclosure relates to a memory controller and a memory device.

A memory system that can store data in a non-volatile manner is known (for example, see Patent Document 1). In such a memory system, a cell structure in which a storage element and a selection element are connected in series is provided for each memory cell. In each memory cell, read failure may occur for various reasons. As a measure to reduce read failures, for example, the invention described in Patent Document 1 has been proposed.

Japanese Patent Application Publication No. 2021-007061

However, in the method described in Patent Document 1, the read voltage is changed depending on the number of occurrences of read failures, so appropriate processing is not performed depending on the cause of read failures. Therefore, it is desirable to provide a memory controller that can perform read processing depending on the cause of a read failure, and a memory device equipped with such a memory controller.

A memory controller according to one aspect of the present disclosure controls a read operation for a nonvolatile memory cell array unit. Here, the nonvolatile memory cell array unit includes a plurality of memory cells. Each memory cell has a memory element that records one bit of information depending on the state of high or low resistance value, and a selection element connected in series to the memory element. This memory controller includes a detection section and a control section. The detection unit performs error correction using the error correction code on the first data with the error correction code read from the plurality of first memory cells that are part of the plurality of memory cells, and the first data. Based on the second data obtained by this, the number of bits in which the information corresponding to the high resistance state is mistakenly read as the information corresponding to the low resistance state is detected. The control section determines whether or not it is necessary to change the read voltage applied to the plurality of first memory cells based on the number of bits detected by the detection section.

A memory device according to one aspect of the present disclosure includes a nonvolatile memory cell array unit and a memory controller that controls read operations for the nonvolatile memory cell array unit. A nonvolatile memory cell array unit includes a plurality of memory cells. Each memory cell has a memory element that records one bit of information depending on the state of high or low resistance value, and a selection element connected in series to the memory element. The memory controller includes a detection section and a control section. The detection unit performs error correction using the error correction code on the first data with the error correction code read from the plurality of first memory cells that are part of the plurality of memory cells, and the first data. Based on the second data obtained by this, the number of bits in which the information corresponding to the high resistance state is mistakenly read as the information corresponding to the low resistance state is detected. The control section determines whether or not it is necessary to change the read voltage applied to the plurality of first memory cells based on the number of bits detected by the detection section.

In the memory controller and memory device according to one aspect of the present disclosure, the number of bits that have been erroneously read out as information corresponding to a high resistance state as information corresponding to a low resistance state is detected based on information obtained by error correction. , it is determined whether or not the read voltage needs to be changed based on the detected number of bits. This reduces the occurrence of reading failures caused by a drop in operating voltage as the number of times data is written to a memory cell increases.

FIG. 1 is a diagram illustrating an example of a schematic configuration of an information processing system including a nonvolatile storage device (memory device) according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of functional blocks of the nonvolatile storage device of FIG. 1. FIG. 3 is a diagram showing an example of an address translation table. FIG. 4 is a diagram illustrating an example of a schematic configuration of a memory cell array. FIG. 5 is a diagram showing an example of the distribution of operating voltages when each memory cell included in the memory cell array is in a low resistance state (LRS) and a high resistance state (HRS). FIG. 6 shows the distribution of operating voltages in the low resistance state (LRS) and high resistance state (HRS) of each memory cell after writing to each memory cell included in the memory cell array is performed a predetermined number of times. It is a figure showing an example. FIG. 7 is a diagram illustrating an example of an unused physical address table. FIG. 8 is a diagram showing an example of a read voltage table. FIG. 9 is a diagram illustrating an example of a read command processing procedure. FIG. 10 is a diagram illustrating an example of a read voltage change processing procedure. FIG. 11 is a diagram illustrating an example of a write command processing procedure. FIG. 12 is a diagram showing a modified example of the address translation table. FIG. 13 is a diagram showing an example of a tag table. FIG. 14 is a diagram illustrating an example of a write command processing procedure. FIG. 15 is a diagram showing a modified example of the address translation table. FIG. 16 is a diagram showing a modified example of the read voltage table. FIG. 17 is a diagram showing a modified example of the physical address table. FIG. 18 is a diagram showing a modified example of the read command processing procedure. FIG. 19 is a diagram illustrating an example of a read voltage change processing procedure. FIG. 20 is a diagram illustrating an example of the processing procedure following FIG. 19.

Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. However, the embodiments described below are merely examples, and there is no intention to exclude the application of various modifications and techniques not specified below. The present technology can be implemented with various modifications (for example, by combining the embodiments) without departing from the spirit of the technology. In addition, in the description of the drawings below, the same or similar parts are denoted by the same or similar symbols. The drawings are schematic and do not necessarily correspond to actual dimensions or proportions. The drawings may also include portions that differ in dimensional relationships and ratios.

<1. Embodiment>
[composition]
FIG. 1 represents an example of a schematic configuration of an information processing system according to an embodiment of the present disclosure. This information processing system includes, for example, a host 10 and a nonvolatile storage device 20, as shown in FIG. For example, as shown in FIG. 1, the non-volatile memory device 20 includes a memory controller 210 and a non-volatile memory (NVM) cell array unit (NVM 220).

The memory controller 210 communicates with the host 10 and receives write commands or read commands from the host 10. The memory controller 210 controls write operations to or read operations from the NVM 220 based on the received commands.

When the memory controller 210 receives a write command from the host 10, it further receives write data from the host 10. The memory controller 210 issues a write request to the NVM 220 and transmits the data received from the host 10 to the NVM 220. NVM 220 writes data received from memory controller 210 into an internal memory cell array (see FIG. 2).

When the memory controller 210 receives a read command from the host 10, it issues a read request to the NVM 220 and transmits it to the NVM 220. The nonvolatile memory cell array unit 220 reads data from the memory cell array in response to a read request, and transmits the read data to the memory controller 210. The memory controller 210 transmits the data received from the NVM 220 to the host 10.

When the host 10 generates a write command and a read command, it specifies a logical address as an address representing the location of data to be written or read. The area indicated by one logical address has a size of, for example, 64 bytes. The logical addresses that can be specified by the host 10 are, for example, 0x00000000 to 0x1F3FFFFFF (size of 500 GB). The host 10 writes or reads, for example, 64 bytes of data with one write command or read command.

When the memory controller 210 makes a write request or a read request to the NVM 220, a physical address is used as an address representing data location information. The memory area indicated by one physical address is, for example, 79 bytes. Of the 79 bytes, 64 consecutive bytes from the beginning are data to be exchanged with the host 10 in write commands and read commands, and the remaining 15 bytes are used for ECC. The memory controller 210 converts a logical address specified by a command from the host 10 into a physical address using, for example, an address table as shown in FIG. 3, and uses the converted physical address to issue a write request or Generate a read request.

FIG. 2 shows an example of functional blocks of the memory controller 210 and the nonvolatile memory cell array unit 220. For example, as shown in FIG. 2, the memory controller 210 includes a host interface section (host IF) 211, a storage section 212, a memory control section 213, a memory interface section (memory IF) 214, an error correction section 215, and an error detection section. It has 216. The nonvolatile memory cell array unit 220 includes, for example, a memory interface section (memory IF) 221, an array control section 222, a memory cell array 223, and a buffer 224, as shown in FIG.

The memory cell array 223 includes, for example, a plurality of tiles 223A. In this embodiment, as an example, the memory cell array 223 has 2588672 tiles 223A. Each tile 223A includes, for example, 4096×4096 memory cells MC. The memory cell array 223 has a capacity of, for example, 632 GB, and can execute write commands and read commands in units of 79 bytes. The physical address is, for example, 0x00000000 to 0x1FFFFFFFF.

FIG. 4 shows an example of a schematic configuration of the tile 223A. For example, as shown in FIG. 4, the tile 223A includes a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC. The plurality of memory cells MC are arranged one by one at the intersections of the plurality of bit lines BL and the plurality of word lines WL. This structure is called a so-called cross-point structure. Memory cell MC is a writable nonvolatile memory. The memory cell MC includes a memory element ME (Memory Element) that records 1-bit information depending on the state of high or low resistance value, and a selector element SE (Selector Element) connected in series to the memory element ME.

The memory element ME is, for example, a phase change memory (PCM), and can be formed of a chalcogenide alloy of germanium (Ge), antimony (Sb), and tellurium (Te). Various elements may be added from the viewpoint of retention characteristics and operating current. Further, the memory element ME may be a resistance change memory material such as Oxide-based RAM (OxRAM) or Conductive Bridge RAM (CBRAM), and is not limited to the material. In the case of a memory material in which a drift phenomenon in which the operating voltage is displaced does not occur, a refresh operation that returns the operating voltage to the voltage before the drift phenomenon occurs can be applied to the selection element SE.

The selection element SE is, for example, an Ovonic Threshold Switch (OTS). The selection element SE can be formed of, for example, a material containing at least one chalcogen element selected from the group consisting of tellurium (Te), selenium (Se), and sulfur (S). In addition, the selection element SE is made of boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), germanium (Ge) for the purpose of stabilizing the amorphous structure and reducing leakage current. , arsenic (As), silicon (Si), oxygen (O), nitrogen (N), and the like. The material of the selection element SE is not limited to the above-mentioned materials, and any material that causes a drift phenomenon may be used.

Note that in the memory cell MC, an intermediate electrode may be provided between the memory element ME and the selection element SE. The memory element ME and the selection element SE may be directly joined to each other. Conversely, from the viewpoint of adhesion and material diffusion, an adhesive layer, a diffusion prevention layer, or the like may be provided between the memory element ME and the selection element SE. Further, in place of the memory element ME and the selection element SE, the memory cell MC may be provided with a single layer that has both the functions of the memory element ME (information recording) and the selection element SE (information selection). Such a single layer may include, for example, an Ovonic threshold switch. For example, in an ovonic threshold switch, by using a plurality of threshold states generated depending on the operating current and voltage application direction as storage data, it becomes possible to perform the functions of the storage element ME and the selection element SE in a single layer.

The memory element ME has, for example, one resistance state of a low resistance state (LRS) and a high resistance state (HRS) that are mutually transitionable. Further, as an example, LRS corresponds to the first value, and HRS corresponds to the second value. The first value corresponds to "1" and the second value corresponds to "0". Alternatively, the first value may correspond to "0" and the second value may correspond to "1". In this embodiment, it is assumed that LRS corresponds to "1" and HRS corresponds to "0", but the present invention is not limited to this.

FIG. 5 shows an example of the distribution of operating voltages when each memory cell MC included in the memory cell array 223 is in a low resistance state (LRS) and a high resistance state (HRS). As shown in FIG. 5, when a set pulse for writing data "1" and a reset pulse for writing data "0" are alternately and repeatedly applied to memory cell MC, the operating voltage of memory cell MC However, the distribution is as shown in FIG. 5, for example. As the number of times (that is, the number of writes) of alternately and repeatedly applying a set pulse and a reset pulse to the memory cell MC increases, the operating voltage of the memory cell MC changes to the lower voltage side, for example, as shown in FIG. will shift to. As a result, for example, when reading is performed using the read voltage Vread in the memory cell MC corresponding to the shaded area in FIG. 6, "1" data is erroneously read as "0" data. I end up. For example, in the memory cell MC corresponding to the shaded area in FIG. 6, in order to correctly read "1" data as 1 data, it is necessary to set the read voltage to Vread'.

An example of a method for reading data from memory cells MC will be explained. Pulses of voltages -Vread/2 and Vread/2 are applied to the word line WL and bit line BL connected to the selected memory cell MC, respectively. A read pulse of a predetermined read voltage Vread (=Vread/2−(−Vread/2)) is applied to the selected memory cell MC. Based on the current flowing through the memory cell MC, it is determined whether the resistance state of the memory element ME is LRS or HRS. When selection element SE is turned on, current flows through memory cell MC. In this case, the resistance state of the memory element ME is assumed to be LRS, and data of "1" is read out. When selection element SE is not turned on, no current flows through memory cell MC. In this case, the resistance state of the memory element ME is assumed to be HRS, and data of "0" is read.

If the operating voltage is lower than the predetermined read voltage due to the occurrence of drift, even if the storage element ME is an HRS, the selection element SE will be turned on by applying the predetermined read voltage. Therefore, even if the resistance state of the memory element ME is HRS, a current necessary for determining HRS and LRS flows. As a result, the state of the memory element ME is erroneously determined to be LRS. That is, although the memory cell MC actually stores "0" data, it is determined that "1" data is stored therein.

An example of a method for writing data into memory cells MC will be explained. When writing "1" data to a memory cell MC (called a set), voltage pulses of -Vset/2 and Vset/2 are applied to the word line WL and bit line BL connected to the selected memory cell MC, respectively. be done. A set pulse of a predetermined set voltage Vset (=Vset/2−(−Vset/2)) is applied to the selected memory cell MC. When the resistance state of the memory element ME is HRS, it changes to LRS. As a result, data "1" is written into the memory cell MC.

When writing "0" data to a memory cell MC (referred to as a reset), a voltage pulse of -Vreset/2 and Vreset/2 is applied to the word line WL and bit line BL connected to the selected memory cell MC, respectively. be done. A reset pulse of a predetermined reset voltage Vreset (=Vreset/2−(−Vreset/2)) is applied to the selected memory cell MC. Note that depending on the material of the memory cell MC, the direction of the voltage of the reset pulse may be opposite to that of the set pulse. When the resistance state of the memory element ME is LRS, it changes to HRS. As a result, data "0" is written into the memory cell MC.

In order to keep the threshold voltage below the predetermined read voltage Vread so that the selection element SE turns on at the predetermined read voltage Vread, it is necessary to periodically reduce the read voltage Vread to eliminate the influence of drift. By periodically reducing the read voltage Vread, it is possible to prevent "1" data from being erroneously read as "0" data.

Next, other configurations of the NVM 220 will be explained.

The memory IF 221 communicates with the memory controller 210. When the memory IF 221 receives a request from the memory controller 210, it provides the received request to the array control unit 222. Types of requests include read requests and write requests. When the memory IF 221 receives write data from the memory controller 210, it writes the data to the write data buffer of the buffer 224.

The array control unit 222 receives a request from the memory controller 210 via the memory IF 221. The array control unit 222 performs operations depending on the type of request received. The array control section 222 controls the word line driving section and the bit line driving section of the memory cell array 223. When accessing (reading, setting, resetting) a memory cell MC in the memory cell array 223, the array control unit 222 selects the word line WL and bit line BL connected to the memory cell MC to be accessed, and selects the word line WL and bit line BL connected to the memory cell MC to be accessed. Apply necessary voltages to WL and bit line BL.

When executing a read request, the array control unit 222 applies a read pulse as a voltage to the selected word line WL and bit line BL. Thereby, data is read from the corresponding memory cell MC. This reading is performed for a plurality of memory cells MC belonging to the physical address specified in the read request. Data read from the plurality of memory cells MC is held in a read data buffer of the buffer 224. The array control unit 222 transmits the data held in the read data buffer to the memory controller 210 via the memory IF 221.

When executing a write request, the array control unit 222 first reads data from a plurality of memory cells MC belonging to the physical address specified in the write request, and holds it in the read data buffer of the buffer 224. The array control unit 222 compares the data held in the read data buffer and the data held in the write data buffer. The array control unit 222 writes “1” to the memory cell MC corresponding to the bit whose value held in the write data buffer is “1” and whose value held in the read data buffer is “0”. (set). That is, the array control unit 222 applies a set pulse as a voltage to the word line WL and bit line BL connected to such a memory cell MC. The array control unit 222 writes “0” to the memory cell MC corresponding to the bit whose value held in the write data buffer is “0” and whose value held in the read data buffer is “1”. (Reset). That is, the array control unit 222 applies a reset pulse as a voltage to the word line WL and bit line BL connected to such a memory cell MC. The array control unit 222 does not write anything if the value held in the write data buffer and the value held in the read data buffer are the same.

Note that the above is an example, and when executing a write request, the array control unit 222 performs writing without reading data from the plurality of memory cells MC belonging to the physical address specified in the write request. Good too. In that case, the number of writes increases, but the time required to read and compare data with held data is shortened.

Next, the configuration of the memory controller 210 will be explained.

The host IF 211 receives a command (write command or read command) from the host 10. The host IF 211 transmits the received command to the memory control unit 213. Further, the host IF 211 receives data instructed to be written by a write command from the host 10, and transmits the received data to the memory control unit 213 in association with the write command. The host IF 211 receives data read from the NVM 220 and transmits the received data to the host 10.

The storage unit 212 includes, for example, an address conversion table 212A as shown in FIG. 3, an unused physical address list 212B as shown in FIG. 7, and a read voltage table 212C as shown in FIG. 8.

The address translation table 212A includes setting information indicating the correspondence between logical addresses and physical addresses. The address conversion table 212A holds, for example, logical addresses from 0x000000000 to 0x1F3FFFFFF, which correspond to the capacity of the memory cell array 223, and physical addresses assigned to each logical address.

The unused physical address list 212B describes one or more physical addresses whose correspondence with logical addresses is not described in the address conversion table 212A. When the host 10 specifies a logical address for which no correspondence with a physical address is described in the address conversion table 212A, the memory control unit 213 converts one physical address selected from the unused physical address list 212B into It is written in the address translation table 212A as a physical address corresponding to the specified logical address.

The read voltage table 212C describes the correspondence between physical addresses and read voltages. The read voltage table 212C may be recorded at a specific physical address in the NVM 220, read from the specific physical address in the NVM 220 when the nonvolatile storage device 200 is started, and held and managed in the RAM. In this case, the read voltage table 212C can be held even when power is not supplied to the nonvolatile memory device 200.

When the memory control unit 213 receives a write command from the host 10, it converts the logical address specified by the command from the host 10 into a physical address using the address conversion table 212A. The memory control unit 213 further reads the write voltage set at the physical address corresponding to the logical address specified by the command from the host 10 from a write voltage table (not shown). The memory control unit 213 generates a write request using the converted physical address and the read write voltage. The memory control unit 213 transmits the generated write request together with the data received from the host 10 to the NVM 220 via the memory IF 214.

When the memory control unit 213 receives a read command from the host 10, it converts the logical address specified by the command from the host 10 into a physical address using an address conversion table 212A as shown in FIG. The memory control unit 213 further reads the read voltage set at the physical address corresponding to the logical address specified by the command from the host 10 from the read voltage table 212C. The memory control unit 213 generates a read request using the converted physical address and the read voltage. The memory control unit 213 transmits the generated read request to the NVM 220 via the memory IF 214.

Next, the read command processing procedure will be explained. FIG. 9 shows an example of a read command processing procedure.

The memory control unit 213 obtains a read command from the host 10. Then, the memory control unit 213 uses the address conversion table 212A to obtain a physical address from the logical address specified by the obtained read command (step S101). The memory control unit 213 further uses the read voltage table 212C to obtain the read voltage set at the physical address corresponding to the logical address specified by the obtained read command (step S102). The memory control unit 213 generates a read request using the converted physical address and the read voltage. In this way, the memory control unit 213 sets the read voltage to the plurality of memory cells MC to be read (step S103). The memory control unit 213 transmits the generated read request to the NVM 220 via the memory IF 214.

The memory control unit 213 reads data (first data) with an error correction code (ECC) from the plurality of memory cells MC to be read (step S104). The memory control unit 213 outputs the read data with an error correction code (ECC) to the error correction unit 215. The error correction unit 215 performs error correction on the input data using an error correction code (ECC) (step S105). The error correction unit 215 outputs the data (second data) obtained by error correction to the memory control unit 213. The memory control unit 213 outputs data with an error correction code (ECC) (first data) and data obtained by error correction (second data) to the error detection unit 216.

The error detection unit 216 determines whether the error correction unit 215 has successfully corrected the error (step S106). For example, error correction is possible when the number of erroneous bits is 12 bits or less, and error correction is not possible when the number of erroneous bits is 13 bits or more. If the error has been corrected (step S106; Y), the error detection unit 216 counts the number of erroneous bits (step S107). Specifically, the error detection unit 216 detects a high resistance state (HRS) based on data with an error correction code (ECC) (first data) and data obtained by error correction (second data). Detects the number of bits in which information corresponding to the low resistance state (LRS) is read out incorrectly as information corresponding to the low resistance state (LRS). The error detection section 216 outputs the detected number of bits to the memory control section 213.

If the number of erroneous bits is greater than the predetermined number n (step S108; Y), or if error correction has not been possible (step S106; N), the memory control unit 213 performs read voltage change processing. Execute (step S109). In the process of changing the read voltage, the memory control unit 213 determines whether it is necessary to change the read voltage, changes the read voltage in response to the decision to change the read voltage, and the like. The specific procedure will be detailed later.

If the read voltage change process has ended normally (step S110; Y), the memory control unit 213 updates the read voltage table 212C (step S111). The memory control unit 213 changes, for example, a read voltage setting value corresponding to a physical address of a plurality of memory cells MC to be read, which is stored in the storage unit 212. After that, the memory control unit 213 transfers the read data (data after error correction) to the host 10 (step S112). If the read voltage changing process does not end normally (step S110; N), the memory control unit 213 notifies the host 10 of the error (step S113). In this way, read command processing by the memory control unit 213 is executed.

Next, the procedure for changing the read voltage in step S109 will be explained. FIG. 10 shows an example of a procedure for changing the read voltage. Note that although FIG. 10 includes steps similar to the steps before step S109, this is because the processing procedure has not been optimized. Therefore, the processing procedure may be optimized as necessary.

The memory control unit 213 executes the same procedure as steps S101 to S106 (steps S201 to S206). If error correction is not possible in step S206 (step S206; N), the memory control unit 213 determines whether or not the held read voltage exists (step S212). As a result, if the held read voltage does not exist (step S212; N), it is assumed that an error has occurred, and the read voltage changing process ends (error end).

On the other hand, if the error correction is successful in step S206 (step S206; Y), the memory control unit 213 temporarily holds the read voltage used for reading (step S207). After that, the error detection unit 216 counts the number of erroneous bits (step S208). Specifically, the error detection unit 216 detects a high resistance state (HRS) based on data with an error correction code (ECC) (first data) and data obtained by error correction (second data). Detects the number of bits in which information corresponding to the low resistance state (LRS) is read out incorrectly as information corresponding to the low resistance state (LRS). The error detection section 216 outputs the detected number of bits to the memory control section 213.

Next, if the number of erroneous bits is smaller than the predetermined number m (step S209; Y), or if the read voltage held in step S212 exists (step S212; Y), the memory control unit 213 , determines changes in read voltages for the plurality of memory cells MC to be read from next time onwards (step S210). The memory control unit 213 determines to change the next and subsequent read voltages for the plurality of memory cells MC to be read to the read voltage held in step S207.

If the number of erroneous bits is equal to or greater than the predetermined number m in step S209 (step S209; N), the memory control unit 213 sets the next and subsequent read voltages for the plurality of memory cells MC to be read in step S212. The read voltage is lowered below the held read voltage (step S211). After that, the memory control unit 213 returns to step S202 and continues to execute the procedures from step S202 onwards. In this way, in the read voltage changing process, either a normal end or an error end can be obtained.

Next, the write command processing procedure will be explained. FIG. 11 shows an example of a write command processing procedure.

The memory control unit 213 obtains a write command from the host 10. Then, the memory control unit 213 uses the address conversion table 212A to obtain a physical address from the logical address specified by the obtained write command (step S301). The memory control unit 213 adds an error correction code (ECC) to the write data included in the acquired write command (step S302).

The memory control unit 213 uses a write voltage table (not shown) to obtain the write voltage set at the physical address corresponding to the logical address specified by the obtained write command. The memory control unit 213 generates a write request using the converted physical address, data with an error correction code (ECC), and the read write voltage. In this way, the memory control unit 213 sets the write voltage to the plurality of memory cells MC to be written. The memory control unit 213 transmits the generated write request to the NVM 220 via the memory IF 214. In this way, the memory control unit 213 writes data with an error correction code (ECC) to the plurality of memory cells MC to be written (step S303). The memory control unit 213 notifies the host 10 of the completion of writing (step S304). In this way, the write command processing by the memory control unit 213 is executed.

[effect]
Next, the effects of the information processing system according to this embodiment will be explained.

In this embodiment, the number of bits in which information corresponding to a high resistance state is incorrectly read as information corresponding to a low resistance state is detected based on information obtained by error correction, and the number of bits is detected based on the detected number of bits. Then, it is determined whether or not the read voltage needs to be changed. This reduces the occurrence of read failures caused by a drop in operating voltage as the number of writes to the memory cell MC increases. Therefore, read processing can be performed depending on the cause of the read failure.

In the present embodiment, when it is decided to change the read voltage, the read voltage setting value corresponding to the physical address of the plurality of memory cells MC to be read, which is stored in the storage unit 212, is changed. This reduces the occurrence of read failures caused by a drop in operating voltage as the number of writes to the memory cell MC increases. Therefore, read processing can be performed depending on the cause of the read failure.

<2. Modified example>
Hereinafter, a modification of the information processing system according to the above embodiment will be described. In the following modified examples, the same components as those in the above embodiment will be described with the same reference numerals.

[Modification A]
In the above embodiment, instead of the address translation table 212A, for example, an address translation table 212D as shown in FIG. 12 and a tag table 212E as shown in FIG. 13 may be provided. The address conversion table 212D includes setting information in which physical addresses and logical addresses are associated with each other for each section in which a plurality of physical addresses are grouped together. In the address conversion table 212D, tags are further assigned to each section. The tag table 212E describes the correspondence between a tag and the access order of a plurality of physical addresses included in the section corresponding to the tag. At this time, if the memory control unit 213 determines to change the read voltage, the memory control unit 213 changes the read voltage setting value corresponding to the section of the plurality of memory cells MC to be read, which is stored in the storage unit 212, for example. .

Next, the processing procedure of the write command in this modification will be explained. FIG. 14 shows an example of a write command processing procedure in this modification.

The memory control unit 213 obtains a write command from the host 10. Then, the memory control unit 213 uses the address conversion table 212D to obtain a physical address from the logical address specified by the obtained write command (step S401). The memory control unit 213 adds an error correction code (ECC) to the write data included in the acquired write command (step S402).

The memory control unit 213 generates pseudo-random numbers for determining whether to perform Wear Leveling (step S403). Wear Leveling refers to a process of changing the order of a plurality of physical addresses assigned to logical addresses on a section-by-section basis within a section. The memory control unit 213 determines whether to perform Wear Leveling based on the generated pseudo-random number (step S404). For example, assume that WearLeveling is executed with a probability of 0.1% when a write command is executed. At this time, in generating the pseudo-random number in step S403, the memory control unit 213 generates one integer from 0 to 999, and selects execution of Wear Leveling when the value of the random number is 0 (step S404; Y ). The memory control unit 213 selects non-execution of Wear Leveling when the random number value is any value from 1 to 999 (step S404; N).

When selecting not to perform Wear Leveling, the memory control unit 213 uses a write voltage table (not shown) to acquire the write voltage set at the physical address corresponding to the logical address specified by the acquired write command. The memory control unit 213 generates a write request using the converted physical address, data with an error correction code (ECC), and the read write voltage. In this way, the memory control unit 213 sets the write voltage to the plurality of memory cells MC to be written. The memory control unit 213 transmits the generated write request to the NVM 220 via the memory IF 214. In this way, the memory control unit 213 writes data with an error correction code (ECC) to the plurality of memory cells MC to be written (step S409). The memory control unit 213 notifies the host 10 of the completion of writing (step S408).

When selecting execution of Wear Leveling, the memory control unit 213 generates pseudo-random numbers for determining the order of physical addresses within the section (step S405). At this time, in generating the pseudo-random number in step S405, the memory control unit 213 generates one integer from 0 to 31, and uses the value of the random number as the value of the tag. The memory control unit 213 uses the tag table 212E to obtain the order of physical addresses corresponding to the tags of the generated random number values, and executes WearLeveling in that order (step S406). In this way, the memory control unit 213 writes data with an error correction code (ECC) to the plurality of memory cells MC to be written. The memory control unit 213 updates the address conversion table 212D by writing the value of the selected tag into the address conversion table 212D (step S407). The memory control unit 213 notifies the host 10 of the completion of writing (step S408). In this way, the write command processing by the memory control unit 213 is executed.

In this modification, when it is decided to change the read voltage, the read voltage setting value corresponding to the section of the plurality of memory cells MC to be read, which is stored in the storage unit 212, is changed. This reduces the occurrence of read failures caused by a drop in operating voltage as the number of writes to the memory cell MC increases. Therefore, read processing can be performed depending on the cause of the read failure.

[Modification B]
In the above embodiment, an address conversion table 212F as shown in FIG. 15, for example, may be provided instead of the address conversion table 212A and the read voltage table 212C. The address conversion table 212F describes the correspondence between logical addresses and physical addresses, and also describes the correspondence between physical addresses and read voltages. By using such an address conversion table 212F, read command processing similar to that of the above embodiment can be executed.

[Modification C]
In the embodiment described above, for example, a read voltage table 212G as shown in FIG. 16 in which read voltages for unused physical addresses are described may be provided in the storage unit 212. In this case, the memory control unit 213 uses the read voltage table 212G to obtain the read voltage set to the unused physical address corresponding to the logical address specified by the obtained read command. I can do it. As a result, it is possible to reduce the occurrence of read failures at unused physical addresses due to a decrease in operating voltage due to an increase in the number of writes to memory cells.

[Modification D]
In the above embodiment and modifications B and C, for example, the storage unit 212 may be provided with a physical address table 212H as shown in FIG. 17 in which physical addresses to be changed in the read voltage are registered. In this case, the read command processing and the read voltage change processing can be performed separately, as will be described later.

FIG. 18 shows an example of a read command processing procedure according to this modification. First, the memory control unit 213 executes the same procedure as steps S101 to S108 (steps S501 to S508). In step S208, if the number of erroneous bits is greater than the predetermined number n (step S508; Y), the memory control unit 213 determines to change the read voltage for the memory cell MC to be read from next time onwards. At this time, the memory control unit 213 registers the physical address corresponding to the memory cell MC to be read in the physical address table 212H as the physical address to be changed in the read voltage (step S509). If the number of erroneous bits is less than or equal to the predetermined number n (step S508; N), or if step S509 is executed, the memory control unit 213 transfers the read data (data after error correction) to the host 10. Transfer (step S510).

If error correction is not possible in step S506 (step S506; N), the memory control unit 213 determines to change the read voltage for the memory cell MC to be read from next time onwards. At this time, the memory control unit 213 registers the physical address corresponding to the memory cell MC to be read in the physical address table 212H as the physical address to be changed in the read voltage (step S511). After that, the memory control unit 213 notifies the host 10 of the error (step S512).

FIGS. 19 and 20 illustrate an example of the read voltage change processing procedure performed after the read command processing of FIG. 18 is executed.

First, the memory control unit 213 acquires the physical address to be changed in the read voltage from the physical address table 212H (step S601). Next, the memory control unit 213 executes the same procedure as steps S202 to S212 for the acquired physical address (steps S602 to S612). After executing step S610, the memory control unit 213 updates the read voltage table 212C (step S613). The memory control unit 213 changes, for example, a read voltage setting value corresponding to a physical address of a plurality of memory cells MC to be read, which is stored in the storage unit 212. Subsequently, the memory control unit 213 updates the physical address table 212H (step S614). Specifically, the memory control unit 213 erases the physical address acquired in step S601 from the physical address table 212H, and ends the read voltage changing process (normal end). In this manner, the memory control unit 213 performs the read voltage change process after the read command process is completed.

In this modification, when it is decided to change the read voltage, the physical address corresponding to the memory cell MC to be read is registered in the storage unit 212 (physical address table 212H) as read voltage change information. After the read operation is finished, the read voltage setting value stored in the read voltage table 212C is changed based on the physical address table 212H. In this way, by performing the read voltage changing process after the read command process is completed, it is possible to suppress an increase in the processing time required for the read command process itself.

Note that in this modification, for example, an address conversion table 212D as shown in FIG. 12 and a tag table 212E as shown in FIG. 13 may be provided instead of the address conversion table 212A. In this case, in step S208, if the number of erroneous bits is greater than the predetermined number n (step S508; Y), the memory control unit 213 determines a change in the read voltage for the section to be read from next time onwards. . At this time, the memory control unit 213 registers the physical address assigned to the section to be read in the physical address table 212H as the physical address to be changed in the read voltage (step S509). In this case, the occurrence of read failures due to a decrease in operating voltage due to an increase in the number of writes to the memory cell MC is reduced. Therefore, read processing can be performed depending on the cause of the read failure.

Although the present technology has been described above with reference to the embodiments, the present disclosure is not limited to the above embodiments, and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described herein. The present disclosure may have advantages other than those described herein.

Further, for example, the present disclosure can take the following configuration.
(1)
A memory controller that controls a read operation for a nonvolatile memory cell array unit,
The nonvolatile memory cell array unit includes a plurality of memory cells,
Each of the memory cells has a memory element that records one bit of information depending on the state of high or low resistance value, and a selection element connected in series to the memory element,
The memory controller is
performing error correction using the error correction code on first data with an error correction code read from a plurality of first memory cells that are a part of the plurality of memory cells, and on the first data; a detection unit that detects the number of bits in which information corresponding to a high resistance state is incorrectly read as information corresponding to a low resistance state, based on the second data obtained by;
A control section that determines whether or not a read voltage applied to the plurality of first memory cells needs to be changed based on the number of bits detected by the detection section.
(2)
further comprising a storage unit containing setting information indicating a correspondence relationship between the physical address and the read voltage setting value,
(1) When the control unit determines to change the read voltage, the control unit changes the read voltage setting value corresponding to the physical address of the plurality of first memory cells stored in the storage unit. Memory controller as described.
(3)
further comprising a storage unit containing setting information in which physical addresses and logical addresses are associated with each other for each section in which a plurality of physical addresses are grouped;
When the control unit determines to change the read voltage, the control unit changes a read voltage setting value corresponding to the section of the plurality of first memory cells stored in the storage unit (1) or ( 2) The memory controller described in 2).
(4)
Further comprising a storage unit including setting information indicating a correspondence relationship between the physical address and the read voltage setting value and read voltage change information,
When the control unit determines to change the read voltage, the control unit stores the physical addresses of the plurality of first memory cells as the read voltage change information in the storage unit, and after the read operation is finished, the control unit stores the physical addresses of the plurality of first memory cells as the read voltage change information, and The memory controller according to (1) or (2), wherein the read voltage setting value stored in the storage unit is changed based on read voltage change information.
(5)
Further comprising a storage unit containing setting information in which the physical addresses and the logical addresses are associated with each other for each section including a plurality of physical addresses,
When the control unit determines to change the read voltage, the control unit stores the physical address assigned to the section of the plurality of first memory cells as the read voltage change information in the storage unit, and performs the read operation. The memory controller according to (1) or (3), wherein the read voltage setting value stored in the storage unit is changed based on the read voltage change information after the read voltage change information is completed.
(6)
The memory controller according to any one of (1) to (5), wherein the memory element is a phase change memory (PCM).
(7)
a nonvolatile memory cell array unit,
a memory controller that controls a read operation for the nonvolatile memory cell array unit;
The nonvolatile memory cell array unit includes a plurality of memory cells,
Each of the memory cells has a memory element that records one bit of information depending on the state of high or low resistance value, and a selection element connected in series to the memory element,
The memory controller includes:
performing error correction using the error correction code on first data with an error correction code read from a plurality of first memory cells that are a part of the plurality of memory cells, and on the first data; a detection unit that detects the number of bits in which information corresponding to a high resistance state is incorrectly read as information corresponding to a low resistance state, based on the second data obtained by;
and a control section that determines whether or not a read voltage applied to the plurality of first memory cells needs to be changed based on the number of bits detected by the detection section.

In a memory device and a memory control method according to an aspect of the present disclosure, the number of bits that have been incorrectly read as information corresponding to a high resistance state as information corresponding to a low resistance state is detected based on information obtained by error correction. Based on the detected number of bits, it is determined whether or not the read voltage needs to be changed. As a result, it is possible to reduce the occurrence of reading failures caused by a decrease in operating voltage due to an increase in the number of times of writing to a memory cell. Therefore, read processing can be performed depending on the cause of the read failure.

This application claims priority based on Japanese Patent Application No. 2022-045965 filed at the Japan Patent Office on March 22, 2022, and all contents of this application are incorporated herein by reference. Incorporate it into your application.

Various modifications, combinations, subcombinations, and changes may occur to those skilled in the art, depending on design requirements and other factors, which may come within the scope of the appended claims and their equivalents. It is understood that the

Claims

A memory controller that controls a read operation for a nonvolatile memory cell array unit,
The nonvolatile memory cell array unit includes a plurality of memory cells,
Each of the memory cells has a memory element that records one bit of information depending on the state of high or low resistance value, and a selection element connected in series to the memory element,
The memory controller is
performing error correction using the error correction code on first data with an error correction code read from a plurality of first memory cells that are a part of the plurality of memory cells, and on the first data; a detection unit that detects the number of bits in which information corresponding to a high resistance state is incorrectly read as information corresponding to a low resistance state, based on the second data obtained by;
A control section that determines whether or not a read voltage applied to the plurality of first memory cells needs to be changed based on the number of bits detected by the detection section.
further comprising a storage unit containing setting information indicating a correspondence relationship between the physical address and the read voltage setting value,
The control unit changes the read voltage setting value corresponding to the physical address of the plurality of first memory cells stored in the storage unit when determining to change the read voltage. Memory controller as described.
further comprising a storage unit containing setting information in which physical addresses and logical addresses are associated with each other for each section in which a plurality of physical addresses are grouped;
The control unit changes a read voltage setting value corresponding to the section of the plurality of first memory cells stored in the storage unit when determining to change the read voltage. memory controller.
Further comprising a storage unit including setting information indicating a correspondence relationship between the physical address and the read voltage setting value and read voltage change information,
When the control unit determines to change the read voltage, the control unit stores the physical addresses of the plurality of first memory cells as the read voltage change information in the storage unit, and after the read operation is finished, the control unit stores the physical addresses of the plurality of first memory cells as the read voltage change information, and The memory controller according to claim 1, wherein the read voltage setting value stored in the storage unit is changed based on read voltage change information.
Further comprising a storage unit containing setting information in which the physical addresses and the logical addresses are associated with each other for each section including a plurality of physical addresses,
When the control unit determines to change the read voltage, the control unit stores the physical address assigned to the section of the plurality of first memory cells as the read voltage change information in the storage unit, and performs the read operation. The memory controller according to claim 1, wherein the read voltage setting value stored in the storage unit is changed based on the read voltage change information after the read voltage change information is completed.
The memory controller according to claim 1, wherein the memory element is a phase change memory (PCM).
a nonvolatile memory cell array unit,
a memory controller that controls a read operation for the nonvolatile memory cell array unit;
The nonvolatile memory cell array unit includes a plurality of memory cells,
Each of the memory cells has a memory element that records one bit of information depending on the state of high or low resistance value, and a selection element connected in series to the memory element,
The memory controller includes:
performing error correction using the error correction code on first data with an error correction code read from a plurality of first memory cells that are a part of the plurality of memory cells, and on the first data; a detection unit that detects the number of bits in which information corresponding to a high resistance state is incorrectly read as information corresponding to a low resistance state, based on the second data obtained by;
and a control section that determines whether or not a read voltage applied to the plurality of first memory cells needs to be changed based on the number of bits detected by the detection section.