WO2023180483A1  Computing qubit allocations using a quantum annealer  Google Patents
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 WO2023180483A1 WO2023180483A1 PCT/EP2023/057559 EP2023057559W WO2023180483A1 WO 2023180483 A1 WO2023180483 A1 WO 2023180483A1 EP 2023057559 W EP2023057559 W EP 2023057559W WO 2023180483 A1 WO2023180483 A1 WO 2023180483A1
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Definitions
 the disclosure relates to qubit allocations and, in particular, though not exclusively, to methods and systems for computing qubit allocations using a quantum computer, and a computer program product enabling a data processing system comprising a quantum annealer to compute qubit allocations.
 the problem of qubit allocation (also referred to as qubit routing) is an important subproblem in the compilation process of gatebased quantum computing. It consists on finding optimal mappings of the algorithmic qubits (also referred to as virtual qubits) present in the instruction set r of a quantum program, represented by a quantum circuit, onto physical qubits of a quantum processor with limited connectivity Q. These optical mappings may also be referred to as qubit allocations, which define instances of the qubit allocation problem.
 a valid solution of the qubit allocation problem consists of an initial mapping and a new quantum circuit that incorporates a sequence of transformations necessary to realize the original quantum program in the quantum processor with limited connectivity.
 An exact or optimal solution of this problem is the one that guarantees that the cost of the new quantum circuit will be minimum in terms of both circuit depth and gate error.
 a classical solution for the qubit allocation problem has been described in the article by Marcos Yukio Siraichi et al. “Qubit allocation”, Proceedings of the 2018 International Symposium on Code Generation and Optimization, Vienna Austria: ACM, Feb. 2018, pp.
 aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Functions described in this disclosure may be implemented as an algorithm executed by a microprocessor of a computer. Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied, e.g., stored, thereon.
 the computer readable medium may be a computer readable signal medium or a computer readable storage medium.
 a computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.
 a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
 a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof.
 a computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
 Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber, cable, RF, etc., or any suitable combination of the foregoing.
 Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an objectoriented programming language such as Java(TM), Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages.
 the program code may execute entirely on the user’s computer, partly on the user’s computer, as a standalone software package, partly on the user’s computer and partly on a remote computer, or entirely on the remote computer or server.
 the remote computer may be connected to the user’s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
 LAN local area network
 WAN wide area network
 Internet Service Provider an Internet Service Provider
 These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
 the computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
 the Instructions may be executed by any type of processors, including but not limited to one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FP GAs), or other equivalent integrated or discrete logic circuitry.
 DSPs digital signal processors
 ASICs application specific integrated circuits
 FP GAs field programmable logic arrays
 each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s).
 the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
 the embodiments in this application relate to algorithms for solving for the problem of qubit allocation within the framework of adiabatic quantum computation (AQC).
 AQC adiabatic quantum computation
 the latter constitutes a different paradigm of quantum computation from the gatebased approach that encodes the solution in the ground state (GS) of a problem Hamiltonian, in such a way that measuring this GS will provide the soughtafter solution.
 the adiabatic theorem which ensures that a system in the GS of a certain Hamiltonian will remain in the GS after this Hamiltonian is altered as long as the change is slow enough, provides a means for the preparation of the GS of the problem Hamiltonian, which is a nontrivial task: starting from a simple Hamiltonian whose GS is easy to prepare experimentally, by slowly interpolating between this and the problem Hamiltonian we are guaranteed to reach the solution of our problem in a slow enough process. With this procedure it is possible to tackle many optimization problems, and it is within this context that it is referred to as quantum annealing.
 the embodiments in this application relate to a method for computing an optimal mapping for algorithmic qubits of a quantum circuit onto physical qubits of a quantum computer using a quantum annealer.
 the quantum annealer may comprise a qubit register of controllable qubits.
 the method may comprise one or more of the following steps: determining or receiving an initial Hamiltonian and a final Hamiltonian, the initial and final Hamiltonian comprising a first term comprising first Pauli operators acting on a first set of qubits of the qubit register, the first set of qubits forming a configuration register for representing mappings of the algorithmic qubits onto the physical qubits as defined by the quantum circuit, and a second term comprising second Pauli operators acting on a second set of qubits of the qubit register the second set of qubits forming a clock register for representing the different time instances of the quantum circuit; executing a quantum annealing scheme based on the initial and final Hamiltonian using the quantum annealer determining an optimal mapping, wherein the executing includes: controlling the qubits of the qubit register to implement the initial Hamiltonian in the qubits of the quantum register and controlling the qubits to evolve the ground state of the initial Hamiltonian to the ground state of the final Hamiltonian; measuring one or more qubit
 the final Hamiltonian may further comprise a third term comprising third Pauli operators acting on the qubits of the configuration and of the clock registers for providing a penalty to a mapping that requires one or more auxiliary gate operations in addition to the set of gate operations of the quantum circuit.
 the method includes an annealing scheme for determining an optimal mapping of logical qubits of a quantum circuit to physical qubits of a quantum computer.
 the scheme uses separation of the qubit register of the annealer into a clock register comprising only information about the time variable, and an allocation register comprising information about the mapping of the set of algorithmic qubits onto the set of physical qubits. Due to the entanglement generated between the clock and configuration register, the measurement of the clock register collapses to a relevant state of the configuration register.
 each qubit of the clock register may be associated to a time instance of the quantum circuit.
 the final Hamiltonian may further comprise a fourth term comprising Pauli operators acting on the qubits of the clock register for introducing a bias towards the initial or final time instance of the quantum circuit so that the optimal mapping is the optimal mapping associated with one or more gate operations of the quantum circuit that need to be executed at the initial or final time instance of the quantum circuit respectively.
 the physical qubits may be associated with a hardware connectivity and wherein the one or more auxiliary gate operations allow the algorithmic qubits to have a connectivity that matches the hardware connectivity of the physical qubits.
 the set of gate operations and the one or more auxiliary gate operations may form a transformed quantum circuit, the optimal mapping corresponding to a transformed quantum circuit with a low cost in terms of depth and/or error rate per gate operation.
 the low cost can be the minimum cost. This can be the case, for example, when the quantum circuit is a shallow quantum circuit.
 a shallow quantum circuit is a quantum circuit in which the number of qubits exceeds the depth of the circuit.
 the one or more auxiliary operations may include one or more SWAP gates and/or one or more bridge gates, and wherein the second term of the final Hamiltonian includes a first term for implementing one or more SWAP transformations and a second term for implementing one or more bridge transformations.
 measuring one or more qubit states of the clock register may further include: measuring the qubits of the clock register in a reverse time order starting from a qubit of the clock register representing a final time instance.
 the second Pauli operators acting on the qubits of the clock register may be configured to provide a penalty term for states not belonging to the clock register space.
 the first Pauli operators acting on qubits of the configuration register may be configured to restrict the qubit mappings such that: a physical qubit of the configuration register can only have one associated algorithmic qubit; the configuration register has a total of N v occupied physical qubits wherein N v is the number of algorithmic (virtual) qubits, and, each algorithmic qubit is allocated to a physical qubit of the configuration register once per time instance.
 the first Pauli operators acting on qubits of the configuration register may be configured to restrict the configuration register to mappings that are physically accessible in the quantum processor, preferably based on an adjacency matrix D a p associated with the hardware graph of the quantum processor.
 the initial Hamiltonian may include a second term comprising Pauli operators acting on the qubits of the clock register for initialization of the clock register.
 the executing a quantum annealing scheme may further comprise: preparing the ground state of the initial Hamiltonian based on a further annealing scheme, the further annealing scheme including; controlling the qubits of the quantum register into a standard Hamiltonian, preferably an Isingtype Hamiltonian having a ground state which can be prepared experimentally; and, controlling the qubits of the quantum register to evolve from a ground state of the standard Hamiltonian to a ground state of the initial Hamiltonian.
 the method may further include: constructing a new final Hamiltonian based on the final Hamiltonian and a Hamiltonian term describing an optimal mapping solution at a previously computed time instance; and, executing the quantum annealing scheme based on the initial and the new final Hamiltonian to determine an optimal mapping for the algorithmic qubits associated with a time instance that precedes the time instance of the quantum circuit associated with the previously computed mapping.
 the embodiments in this application may relate to a system for allocating qubits, using a data processing system comprising a classical computer system and a quantum computer system, wherein the system is configured to: determining or receiving an initial Hamiltonian and a final Hamiltonian, the initial and final Hamiltonian comprising a first term comprising first Pauli operators acting on a first set of qubits of the qubit register, the first set of qubits forming a configuration register for representing mappings of the algorithmic qubits onto the physical qubits as defined by the quantum circuit, and a second term comprising second Pauli operators acting on a second set of qubits of the qubit register the second set of qubits forming a clock register for representing the different time instances of the quantum circuit; and, executing a quantum annealing scheme based on the initial and final Hamiltonian using the quantum annealer determining an optimal mapping, wherein the executing includes: controlling the qubits of the qubit register to implement the initial Hamiltonian in the qubit
 the final Hamiltonian may further comprise a third term comprising third Pauli operators acting on the qubits of the configuration and of the clock registers for providing a penalty to a mapping that requires one or more auxiliary gate operations in addition to the set of gate operations of the quantum circuit.
 the embodiments may also relate to a program or suite of computer programs comprising at least one software code portion or a computer program product storing at least one software code portion, the software code portion, when run on a classical computer system wherein the classical computer is part of a data processing system comprising the classical computer system connected to a quantum annealer, being configured for executing the method steps as described with reference to the embodiments in this application.
 the embodiments exploit the inherent parallelization achievable with superposition of the qubits of a quantum annealer to explore all possible paths towards the desired connectivity at once.
 the intuitive idea of what the proposed algorithm is doing is a bruteforce calculation of all the possible “transformation paths” (i.e. , the sequence of transformations applied to the qubits in order to keep up with all the links required throughout the quantum circuit) with their corresponding penalties, in such a way that the final allocation of the qubits relative to the transformation path with the lowest overall penalty can be identified in the final ground state.
 a solution of the qubit allocation problem corresponds to an initial mapping and a particular transformation path, i.e., a sequence of transformations designed to allow for the required connectivity at all steps of the circuit (said set of transformations including the identity transformation).
 a “configuration path” may be defined as the series of mappings between the set of algorithmic qubits and the set of hardware qubits that corresponds to a particular transformation path. The proposed quantum algorithm allows to compute the initial point of the configuration path.
 this algorithm can be used in an iterative manner.
 a configuration path does not uniquely define a transformation path, as several of the latter may present the same configuration path.
 the most costeffective transformations between two given configurations constitute a less complex problem that can be tackled in parallel (connecting a pair of consecutive configurations can be done independently for any pair) more efficiently, e.g. through a breadthfirst search (BFS) algorithm.
 BFS breadthfirst search
 the embodiments follow the dynamical transformation of the embedding.
 the embodiments consider the possibility of having bridge gates apart from SWAPs, thus taking into consideration the full search space.
 the invention may further relate to a nontransitory computerreadable storage medium storing at least one software code portion, the software code portion, when executed or processed by a computer, is configured to perform any of the method steps as described above.
 a nontransitory computerreadable storage medium storing at least one software code portion, the software code portion, when executed or processed by a computer, is configured to perform any of the method steps as described above.
 Fig. 1 depicts a hybrid data processing system comprising a classical computer and a quantum processor
 Fig. 2A2C illustrates an instance of a qubit allocation problem and a solution for this qubit allocation problem instance
 Fig 3 depicts a schematic of translating SWAP and bridge gate operations into CNOT operations
 Fig 4 illustrates the time dependent energy spectrum for an Hamiltonian that slowly evolves from an initial Hamiltonian to a final Hamiltonian
 Fig. 5 schematically depicts a quantum register for encoding the problem Hamiltonian according to an embodiment of the invention
 Fig. 6 depicts an illustration of the shortest paths connecting two qubits in a quantum register
 Fig. 7 illustrates an example showing the relation between the instruction set and the adjacency matrix of a connectivity graph
 Fig. 8 illustrates the different sets of transformations that may bring within interaction distance the algorithmic qubits allocated at the extremes of a certain hardware path
 Fig. 9 depicts a flowchart for determining an optimized process for the preparation of the ground state of the initial Hamiltonian for the quantum annealing scheme according to an embodiment of the invention
 Fig. 10 depicts a flowchart for determining a solution to a qubit allocation problem using a quantum annealing scheme according to an embodiment of the invention.
 Fig. 11 depicts a flow chart of a method for computing an optimal mapping for algorithmic qubits of a quantum circuit onto physical qubits of a quantum computer using a quantum annealer according to an embodiment of the invention.
 Fig. 1 depicts a hybrid data processing system 102 including a classical computer 104 comprising one or more classical processors (CPUs and/or GPUs) and a quantum processor 106 comprising a plurality of interacting quantum elements, e.g. qubits, that can be controlled by the classical computer.
 the qubits may be implemented based on different types of technologies, including but not limited to superconducting qubits, quantum dot qubits, neutral atom type qubits, optical qubits, etc.
 the quantum processor may be controlled via a controller system 108 comprising input output (I/O) devices which form an interface between the quantum processor and classical computer 106.
 the controller system may include a system for generating control signals 110 for controlling the quantum processing elements.
 the control signals may include for example pulses, e.g. microwave pulses, voltage pulses and/or optical pulses, for manipulating the qubits, e.g. bringing them in an initial state and manipulating the state of the qubit and/or the interaction (coupling) between two or more qubits.
 the controller may include a data acquisition system for readout of state of the quantum processing elements.
 the data acquisition system may receive an output signal 112 originating from the quantum processor in response to a readout pulse for reading the state of a quantum element.
 at least a part of the data acquisition system may be located or integrated with the chip that includes the qubits.
 the classical computing system may include different modules for enabling execution programs, in particular quantum annealing programs, to be executed on the quantum processor.
 the classical computer may include a problem encoder module 114 configured to receive a computational problem that needs to be solved and encoded that problem into a problem Hamilton of the quantum processor.
 the computational problem may be an NPhard problem, such as the bit allocation problem as described hereunder in more detail.
 the problem Hamiltonian may have an Isinglike Hamiltonian based on Pauli operators acting on a Zcth qubit of the plurality of qubits.
 the problem Hamiltonian may also include one or more adjustable parameters which can be controlled by external electromagnetic control signals, e.g. electromagnetic or magnetic fields, which may be used to locally adjust the electromagnetic or magnetic environment at one or more qubits.
 external electromagnetic control signals e.g. electromagnetic or magnetic fields
 a plurality of such adjustable external control signals may be used to control a single qubit or a part of the plurality of qubits. By adjusting the external control signals, these parameters may be adjusted depending on the computational problem.
 Encoding the computational problem into the problem Hamiltonian, as performed by the classical computing system includes determining, from the computational problem, a configuration for the plurality of adjustable parameters.
 the classical computer may further include a quantum annealing module adapted to perform a quantum annealing scheme which may include initializing the quantum processor based on an initial Hamiltonian and slowly (adiabatically) evolving the Hamiltonian to a final Hamiltonian which includes the problem Hamiltonian.
 the initial Hamiltonian may be based on Pauli operators acting on the qubits. Typically the initial Hamiltonian may be selected so that it does not commute with the final Hamiltonian.
 the computational problem is encoded in the problem Hamiltonian so that a ground state of the final Hamiltonian comprises information about a solution to the problem that is encoded in the problem Hamiltonian.
 a ground state of the final Hamiltonian comprises information about a solution to the problem that is encoded in the problem Hamiltonian.
 the quantum processor is evolving from the ground state of the initial Hamiltonian towards the ground state of the final Hamiltonian, wherein the plurality of adjustable parameters of the problem Hamiltonian are in the problemencoding configuration.
 the evolution of the quantum processor may be controlled by the programmable quantum annealing module using the external electromagnetic control signals.
 the controller system may include a data acquisition system configured to measure the states of at least part of the qubits of the quantum processor, wherein the measured information may include at least part of the solution to the problem that is encoded in the problem Hamiltonian.
 the classical computer may determine a trial solution to the computational problem based on the measured information, and verify if the trial solution actually is a solution to the computational problem.
 the verification is a computation which can be carried out in polynomial time, and can typically be easily computed. This process may be repeated until a solution to the computational problem is found.
 the embodiments in this application deal with the problem of qubit allocation which is an important subproblem in the compilation process of gatebased quantum computing, wherein algorithmic qubits need to be allocated to physical qubits of a quantum processor.
 An instance of such NP hard problem and a solution thereof are schematically illustrated with reference to Fig. 2A2C.
 Fig. 2A shows a socalled quantum circuit 202 defining a quantum algorithm or a part thereof.
 the quantum circuit describes a sequence of gate operations 208,210 to be executed at predetermined time instances ti,t2,ts,t4 involving in this case four algorithmic qubits Q0Q3 206, followed by measurements 212 of the states of the algorithmic qubits.
 a quantum circuit may include more than one gate operation per time instance. These gate operations associated with one time instance may be referred to as a circuit layer. These operations need to be executed on a physical quantum processor 204, which means that the quantum circuit is compiled into a set of specific gate operations for a physical quantum computer.
 the qubits of stateoftheart quantum processors comprise coupled physical qubits 21616, wherein  due to current date manufacturing constraints  not all qubits of the quantum processor are coupled to all other qubits.
 physical qubit 2161 is connected via a first coupling 2181 (or link) to physical qubit 2162 and via a second coupling 2182 (or link) to physical qubit 2163.
 This particular coupling layout of the physical qubits of the quantum processor also referred to as the connectivity of the physical qubits of the quantum processor, limits the way the gate operations of the quantum circuit can be executed on the qubits of the quantum processor.
 a very popular choice for direct hardware implementation is the set of single qubit operations and the CNOT gate, which is universal. Because of its widespread use, the examples in this application are based on this native gate set. Once in this setting, there are several ways in which one can patch up their circuit in order to achieve a connectivity that goes beyond hardware capabilities.
 Fig. 2B illustrates the qubit allocation problem in more detail. As shown in the figure, the problem relates to finding the optimal mapping of the algorithmic qubits
 the instruction set represents a set of gate operations to be applied on the algorithmic qubits at different time instances ti,... ,te, wherein each gate operation is characterized by a certain connectivity. So the first entry in the instruction set table indicates that at ti an interaction between the first virtual qubit q% and the second virtual qubit q% is needed.
 the hardware graph fl may represent a physical qubit at each vertex 221 , while a line 219 connecting 2 vertices in the graph may identify a connection between two physical qubits. Hence, the lines indicate which physical qubits can interact (e.g. entangle).
 the link may also be associated with a quality, e.g. a fidelity.
 the instruction set r may define a set of connections (a connectivity) between algorithmic qubits that are needed for execution of the gate operations defined by the quantum circuit. The absence of a link between two qubits that need to interact according to de gate operations of a quantum circuit requires the addition of extra gates that may end up increasing the circuit’s depth greatly, which in turn translates to a greater exposure to noise.
 FIG. 2C illustrates a possible way of executing the six qubit operations of quantum circuit 224 in a sequential way (at time instances ti,...teY
 the first two instructions ti and fc requiring a connection between algorithmic qubit q% and q% and between algorithmic qubit q% and q% respectively, can be directly allocated to physical qubit q$ that is coupled to physical qubit q ⁇ and physical qubit (73 respectively.
 the next instruction t3 however requires a connection between algorithmic qubit q% and q% .
 this instruction cannot be executed as at t3 there is no physical connection between physical qubit q ⁇ (which holds algorithmic qubit q”) and physical qubit q% (which holds algorithmic qubit q%).
 a compiler that is processing the gate operations of the quantum circuit may be configured to introduce one or more transformations, i.e. additional gate operations, to enable execution of the quantum circuit on the physical qubit register with limited connectivity.
 the transformation may include socalled SWAP gates 227,229 that swap the states of two qubits.
 the compiler may decide to introduce a first SWAP gate 227 to swap the states of qubits q$ and (73 so that algorithmic qubit q% is mapped on physical qubit q$ and algorithmic qubit q% is mapped on physical qubit q% . Thereafter, instruction 6 (requiring a connection between algorithmic qubit q% and q%) can be executed.
 a second SWAP gate 229 may be introduced to allow execution of instructions ts.
 additional gates need to be introduced in order to execute the gate operations of a quantum circuit leading to increasing circuit depts and longer runtime.
 This especially in the NISQ (Noisy IntermediateScale Quantum) era, may be a severe enough problem that a bad solution to an initial mapping results in a computation too noisy to be of any use.
 the process of including additional gate instructions to achieve the required connectivity is referred to as circuit transformation.
 Fig. 3A and 3B depict examples of gate operations that can be used to achieve connectivity.
 Fig. 3A illustrates the swap gate operation, which is translated into 3 CNOT gates 304 to exchange qubit states of two physical qubits 302. The swapping operation is not reversed after execution and thus the application of this gate causes the algorithmictophysical qubit assignment to dynamically change along the quantum program.
 the quantum algorithm presented by the embodiments in this application for solving this problem using a quantum annealer follows the possible tracks of the qubit allocation problem by exploiting superposition and entanglement, such that information about an optimal set of configurations the system is in at each time instance can be retrieved.
 the embodiments address the problem of qubit allocation within the framework of adiabatic quantum computation (AQC).
 AQC constitutes a quantum computation paradigm that is different from the gatebased quantum computation approach.
 the problem to be solved is encoded in a socalled problem Hamiltonian such that the ground state (GS) of the problem Hamiltonian holds the solution to the problem.
 GS ground state
 measuring the GS will provide the soughtafter solution.
 the adiabatic theorem which ensures that a system in the GS of a certain Hamiltonian will remain in the GS after this Hamiltonian is altered as long as the change is slow enough, provides a means for the preparation of the GS of the problem Hamiltonian.
 the qubits of the quantum annealer are prepared based ib a simple (initial) Hamiltonian H o whose ground state may be relatively easy to realize experimentally, the quantum annealer may be controlled to slowly interpolate between the initial Hamiltonian H o and the problem Hamiltonian to reach a final ground state as is schematically depicted in Fig. 4. This final ground state may provide a solution to an instance of the qubit allocation problem. Following this adiabatic quantum computation scheme, it is possible to tackle optimization problems. In this application such scheme may also be referred to as a quantum annealing scheme.
 a quantum annealer depicts a hybrid data processing system as described with reference to Fig. 1, comprising a classical computer connected to a quantum processor, comprising an array of coupled qubits, wherein the hybrid data processing system is configured to execute a quantum annealing scheme.
 Such array of coupled qubits may be referred to as a qubit register.
 Each individual qubit of the quantum annealer may be associated with two ground states, e.g. a spin up
 Several ways may exist to map the qubit register to an allocation assignment, each corresponding to a different cost in qubit expenses.
 the first step requires the encoding of the qubit allocation problem into a problem Hamiltonian of the quantum processor.
 the encoding of the problem requires (N v + 1) • N h + L v qubits, where N v is the number of virtual (algorithmic) qubits, N h is the number of physical qubits of the quantum processor that is evaluated (here it is considered that N h > N v here) and L v is the number of instructions of the evaluated circuit that should be executed on the quantum processor.
 the qubit register of the quantum annealer may be subdivided in sub registers as shown in Fig. 5A.
 This figure shows a first sub register 504 (referred to as the clock register C) comprising L v clock qubits, ⁇ xf ⁇ 0 f° r encoding the instructions of the quantum circuit that is evaluated and a second sub register 502 (also referred to as the configuration register A) comprising (N v + 1) • N h qubits for encoding different possible configurations (mappings) of algorithmic qubits onto physical qubits.
 the clock register C comprising L v clock qubits, ⁇ xf ⁇ 0 f° r encoding the instructions of the quantum circuit that is evaluated
 a second sub register 502 also referred to as the configuration register A
 N v + 1 N h qubits
 Fig. 5B shows that the configuration register comprises N h subblocks
 the string qubits in each subblock encodes a possible mapping of the algorithmic qubit on a physical qubit.
 the extra qubit per hardware subblock corresponds to sites x a0 which, if full, indicates hardware site a is empty. As such, this only becomes relevant N Restriction to the correct subspace allows allocating a single upwards spin in each subblock, all in different virtual positions, thus obtaining the desired map.
 the clock qubits are configured to keep track of time (i.e. the sequence of gate operations of the quantum circuit that is part of the allocation problem) by populating the register, initialized with all zeros, with ones in an orderly manner, i.e., the register corresponding to time instance t(t e 0, ...,L V ) may be identified by
 xg) In order to enforce this encoding, corresponding penalization terms need to be included in both initial and final Hamiltonians.
 the encoding relies on the restriction of the solution space (i.e. the Hilbert space of the qubit register) to physically relevant qubit registers.
 the solution space i.e. the Hilbert space of the qubit register
 the following requirements are taken into account:
 a physical qubit of the configuration register can only have one associated virtual qubit
 the configuration register has a total of N v occupied physical qubits
 each virtual qubit must be allocated to a physical qubit of the configuration register once per time instance.
 the proposed algorithm can be realized more efficiently (i.e., the resulting algorithm will produce a larger minimum gap) by tailoring it for the connectivity of the qubits of a particular gatebased quantum processor, i.e. the processor on which the quantum circuit is to be executed.
 This tailoring includes restriction to configurations that are physically accessible in the quantum processor.
 the adjacency matrix D a p associated with the hardware graph 12 of the quantum processor may be used. This way, the connectivity may be added to the Hamiltonian as an additional constraint term.
 the adjacency matrix may be based on a weighted device graph to include other relevant factors, including but not limited to the quality of the connection.
 embodiments will be described which take this into account.
 Hamiltonian term that takes into account the connectivity of the physical qubits of a quantum register may be described by the following Hamiltonian:
 an additional matrix Q may be used for storing the success probability of each 2qubit gate operation to distinguish the different costs of bridge and SWAP operations realizing the same connectivity as shown for example in Fig. 2.
 a restriction Hamiltonian H r As already briefly described above, an annealing algorithm is based on the interpolation between some initial Hamiltonian H o (associated with a ground state that one knows how to prepare) and a final Hamiltonian (associated with a ground state in which the solution of the qubit allocation problem is encoded). In an embodiment, in its simplest form, this interpolation may be a linear interpolation. The embodiments described in this application are not limited to linear schedules.
 Nonlinear functions may also be used as viable schedules as long as the conditions are respected, wherein s is a dimensional time parameterizing the whole annealing process.
 s is a dimensional time parameterizing the whole annealing process.
 the formulation of the qubit allocation problem in the AQC framework may be described based on a linear schedule when referring to the annealing process.
 the interpolation between H o is realized using continuous modulation of the parameters of the device. This may be realized by slowly turning off the interactions and local fields that govern H o while at the same time the interactions and local fields that govern are being turned on. For example, one may use the electromagnetic control signals, e.g. magnetic control signals, as described with reference to Fig. 1 to control the initial and problem Hamiltonian.
 electromagnetic control signals e.g. magnetic control signals
 the initial Hamiltonian H o corresponds to a quantum Ising model that has a nontrivial ground state. Therefore, this ground state needs to be prepared in a separate annealing process, which will be described hereunder in more detail with reference to Fig. 9.
 the annealing process may start from a state that encodes the equal superposition of all the possible embeddings of N v qubits, along with an initialized clock register.
 a mixing Hamiltonian H mixture e.g. an Isingtype Hamiltonian term, and the abovedescribed restriction Hamiltonian H r may be used.
 H ciockinit has to be included in the initial Hamiltonian H o . This way the following expressions for H mixture , H ciockinit and in the initial Hamiltonian H o can be written down as follows: where A r » 1 is the Lagrange multiplier for the constraints.
 the final Hamiltonian defining the problem Hamiltonian may include ⁇ transformations which describes the instruction set that needs to be evaluated and the allowed transformations with their respective gate cost (which will be considered hereunder in more detail).
 the problem Hamiltonian may further include the restriction Hamiltonian H r and a term to introduce some bias towards a predetermined time instance of the instruction set.
 a Hamiltonian term H ciock f inca may be selected to introduce bias to the final time instance L v , such that at the end of the annealing scheme, the ground state may include information about the configuration that is associated with the final time instance of an optimal configuration path:
 a Hamiltonian H trans formations may be introduced. In this manner, transition amplitudes are engineered such that they constitute a reward if the connectivity required by the instruction at that time instance is satisfied, and a penalty (damping) that reflects an additional effort required to fix that connectivity if the connectivity is not satisfied.
 the transformation Hamiltonian may include three terms: a first (noswap) Hamiltonian term H ns (Eqs. (11) and (12)) which represents the part of the transformation Hamiltonian that provides a reward for an absence of a transformation, a second Hamiltonian term H b (Eq. (13)) that imposes a penalty when considering implementation of a bridge gate and a third Hamiltonian term H s (Eq. (21)) that switches to the new hardware configuration for the next time instance, as the actual device would do.
 Fig. 6 shows a hardware graph 604 comprising physical qubits (indicated by Greek letters) and an algorithmic graph 602 defining the associated algorithmic qubits (indicated by Latin letters).
 This figure provides an illustration of the different shortest paths that are possible for connecting two qubits in the device (both for the physical qubits and the virtual qubits levels).
 each algorithmic qubit may be allocated to one hardware qubit: algorithmic qubit i 6O61 may be assigned to physical qubit a 6O81; algorithmic qubit j 6O62 may be assigned to physical qubit (3 6O82 etc.
 physical qubits a and (3 are not directly connected, but connected via at least one intermediate qubit.
 the shortest paths in the graph between the two qubits go via at least one intermediate qubit.
 Interaction between the qubits may be realized either through a bridge gate utilizing yi or y 2 . or by performing the swaps depicted through 610i (Wj 7;i 612i in algorithmic space) or through o) a p i2 6102 (w ⁇ 6122 in algorithmic space).
 a total of 6 different options for connecting algorithmic qubits i and j are possible in this example.
 a discriminating function D(o>) may be designed that evaluates to one if 0) is a shortest path present in the device and to zero in the opposite case. This function may be built on the basis of the adjacency matrix D as follows:
 an ordered sequence of algorithmic qubits may be defined, starting from i and ending with j, with I steps in between, that recounts the virtual qubits allocated along some simple path defined in the device.
 a pair specifies some allocation of I + 2 qubits onto the device, as depicted in Fig. 6.
 Fig. 7 illustrates the relation between the instruction set and PT
 hardware graphs 712,714 represent a particular allocation of algorithmic qubits (numbers) into the available physical qubits (represented by circles) of a qubit register.
 the hardware connectivity of the qubit register may be given by adjacency matrix D a p.
 708 and 710 are lists of and E t of algorithmic qubits each involved in a 2qubit gate of a quantum circuit including instructions, e.g.
 a discriminating matrix may be constructed wherein % indexes the various links required at time instance t.
 the discriminating matrix may comprise matrix elements which are one if a link is present and a zero otherwise.
 712 illustrates a graph that includes the required links for the instructions of the instruction set at t  1, indicating that links between algorithmic qubits (0,1), (2, 3), (5, 4) are needed. As shown in the graph, at t  1 the instructions can be executed on the physical qubits because the connectivity of the physical qubits matches the required connectivity of the algorithmic qubits.
 each % encodes two indices i,j of algorithmic qubits that are to be linked at time instance t, and all % belonging to the same time instance refer to different algorithmic qubits.
 the allocation configuration satisfies the required hardware connectivity at time instance t  1, but it requires some further transformations (addition of swap or bridge operations) in order to satisfy it at t.
 the transformation Hamiltonian ⁇ transformations may be expressed as follows: wherein H ns provides a reward when no additional transformations are required.
 H b and H s relate to the bridge and swap gate operations.
 This penalty may be decreasing with increasing path distance I, preferably monotonically, as it is desirable to have a smaller contribution of longer paths at later times.
 the path distance is always 1 , i.e.
 Equation (13) only accounts for the implementation of a single bridge for fixing connectivity requirements at time instance t. In order to include richer possibilities, such as having more than one bridge gate or the combination of bridge gates and SWAP gates, more convoluted expressions may be formulated based on the above described equations.
 Fig. 8 provides an illustration of the different sets of transformations that may bring the algorithmic qubits allocated at the extremes of a certain hardware path of length I within interaction distance for the first orders of separation. Note that that there are I + 1 possibilities per path distance I.
 a function z(l,m; ij, k) (equation 19) may be defined that does the same to the string of virtual qubits that results from the swapping transformation.
 a further aspect that may be taken into account in the problem of qubit allocation is the quality of the physical qubits, which may vary because of for example fabrication defects.
 the quality (fidelity) of the physical qubits is an important parameter for nearterm quantum computers, since the high error rates may push a minimaldepth solution far from the optimum.
 these quality considerations break the degeneracy of the optimal path, which in an ideal case would be very likely to exist because of the symmetries present in the hardware graph. This degeneracy is undesirable in general because trying to extract several steps of the optimal path may provide a suboptimal solution by mixing the actual solutions.
 Imperfections of the introduced CNOT gates may be taken into account by identifying the probability of success of performing the desired CNOT between each hardware qubit pair as Q a p e [0,1],
 the problem Hamiltonian as described above provides the initial configuration of an optimal configuration path.
 the proposed scheme may be used to extract further information about the optimal configuration path, since the computation of the latter is still performed in full by the algorithm, however it cannot be accessed directly.
 the new problem Hamiltonian may be constructed based on the initial problem Hamiltonian and a Hamiltonian term describing the optimal mapping associated with the previously computed time instance, and this new problem Hamiltonian may then be used in a next annealing step to determine an optimal mapping for the algorithmic qubits associated with a time instance that precedes the time instance of the previously computed mapping.
 the algorithm described above carries the core of the computation to be performed, but further considerations need to be taken into account.
 the ground state of the initial Hamiltonian needs to be prepared, which requires a separate annealing process because the ground state is nontrivial.
 this initial annealing process may be optimized independently of the problem at hand (for this specific machine), such that a very good approximation to the initial ground state can be guaranteed when starting the algorithm.
 a learning process may be performed for the optimal schedule to reach the initial Hamiltonian from a standard, easytoprepare Hamiltonian, which is experimentally available.
 the measurement of the final state of the whole computation needs to be performed carefully as, based on the current state of the art technology, it is not possible to perform joint measurements of all the qubits in the configuration register A, which comprises information about the configurations (e.g. the mappings from algorithmic qubits to physical qubits).
 the configuration register A comprises information about the configurations (e.g. the mappings from algorithmic qubits to physical qubits).
 the solution is not degenerate, i.e. there is a single set of transformations that provides the minimal number of gates
 the suboptimal configurations can be filtered out by the algorithm for large enough differences between the cost of the optimal path and the rest.
 additional statistical checks need to be performed.
 Fig. 9 depicts a flowchart for determining an initial Hamiltonian for the quantum annealing scheme according to an embodiment of the invention.
 a learning process is needed for the optimal schedule to reach the ground state of the initial Hamiltonian H o of the quantum allocation algorithm.
 Regular minimization techniques in machine learning can be used to perform this optimization.
 the parameters 0 Ttot may be selected such that the ground state of H o is reached with a high probability.
 the annealing schedule and the measurement step may be repeated for a number of shots (step 922). Once all shots have been executed (step 1014), a reliable statistical result may be obtained for the state of the system compared with the expected ground state of H o . If both states are similar enough (step 916 1), the ground state of H o has been reached with high probability and the optimization routine may be stopped (step 918). Otherwise, a new set or parameters ⁇ may be selected (step 920) and used for executing the optimization routine again (step 924) until convergence is reached.
 Fig. 10 depicts a flowchart of a process for determining a solution to a qubit allocation problem instance using a quantum annealing scheme according to an embodiment of the invention.
 This process may be executed on a hybrid data processing system comprising a classical computer and a quantum processor as described with reference to Fig. 1.
 the process may include a first step 1002 wherein a ground state GS of H o is prepared using an optimization routine as described with reference to Fig. 9.
 the annealing schedule may be executed on the quantum processor which interpolates between H o and the final Hamiltonian i.e. the problem Hamiltonian, which encodes a qubit allocation configuration of an optimal qubit allocation mapping (step 1004).
 first clock register C is measured.
 This measurement may include measuring the states of the qubits of the clock register in order, going from the last clock qubit xf v to the first x£ (step 1006).
 the qubits are measured in order until a qubit x£ is measured in the state
 the measurement of the clock register can be stopped as the measurement state
 the measurement of the clock register indicates if the configuration register is in a state that comprises information about an optimal mapping.
 the qubits of register A can be measured in a predetermined order (step 1008) and the measured states may be stored (step 1010). Due to the probabilistic nature of quantum measurements and to obtain a reliable statistical result, the entire annealing schedule including the measurements of the clock and configuration registers may be repeated a predetermined number of epochs (step 1014).
 a reliable statistical result for the state of the system may be obtained that corresponds to a configuration for an instruction at time t.
 different measuring orders for measuring clock register A may be considered (step 1016).
 the annealing algorithm may be executed multiple times for each of these measurement orders (step 1120).
 Fig. 11 depicts a flow chart of a method for computing an optimal mapping for algorithmic qubits of a quantum circuit onto physical qubits of a quantum computer using a quantum annealer according to an embodiment of the invention.
 the quantum annealer may comprise a qubit register comprising externally controllable qubits.
 the quantum annealer may be part of a hybrid data processing system as described with reference to Fig. 1.
 a first step 1102 an initial Hamiltonian and a final Hamiltonian may be determined or received by a classical computer.
 the initial and final Hamiltonian may comprise a first Hamiltonian term comprising first Pauli operators acting on a first set of qubits of the qubit register, wherein the first set of qubits may form a configuration register for representing mappings of the algorithmic qubits onto the physical qubits for different gate operations that need to be executed by the algorithmic qubits at different time instances as defined by the quantum circuit.
 the initial and final Hamiltonians may comprise a second term comprising second Pauli operators acting on a second set of qubits of the qubit register, wherein the second set of qubits may form a clock register for representing the different time instances of the quantum circuit.
 the final Hamiltonian may further comprise a third term comprising third Pauli operators acting on the qubits of the configuration and of the clock registers for providing a penalty to a mapping that requires one or more auxiliary gate operations in addition to the set of gate operations of the quantum circuit.
 the classical computer may translate the Hamiltonian into control signals for controlling the qubits. These control signals may be adjusted depending on the computational problem. Encoding the computational problem into the problem Hamiltonian, as performed by the classical computing system, may include determining, from the computational problem, a configuration for the plurality of adjustable parameters.
 a quantum annealing scheme may be executed using the quantum annealer, wherein the executing includes controlling the qubits of the qubit register based on the control signals to implement the initial Hamiltonian into the qubits of the quantum register and controlling the qubits to evolve the ground state of the initial Hamiltonian to the ground state of the final Hamiltonian.
 one or more qubit states of the clock register may be measured and if the one or more measured qubit states of the clock register indicate that the entangled qubits of the clock register have collapsed to a state associated with a time instance of the quantum circuit, then one or more qubit states of the configuration register may be measured to determine the mapping associated with the time instance of the quantum circuit (step 1106). Then, an optimal mapping for the gate operation associated with the measured time instance of the quantum circuit may be determined based on the one or more measured qubit states of the configuration register (step 1108).
 the embodiments provide an annealing scheme for determining an optimal mapping of logical qubits of a quantum circuit to physical qubits of a quantum computer.
 the scheme uses separation of the qubit register of the annealer into a clock register comprising only information about the time variable, and an allocation register comprising information about the mapping of the set of algorithmic qubits onto the set of physical qubits. This separation makes use of the quantum phenomenon of entanglement in order to correlate physically meaningful mappings with the time ordered set of gate operations of a quantum circuit in order to solve a qubit allocation problem instance that implies a dynamical evolution of a variable or set of variables in time.
 Qubit allocation schemes within the quantum annealing framework in the prior art do not account for the dynamical change of the mapping between algorithmic and physical qubits in the quantum circuit, leaving out a large part of the search space, where better solutions are likely to be found.
 the invention provides a solution taking into account this dynamical evolution.
 the techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set).
 IC integrated circuit
 a set of ICs e.g., a chip set.
 Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a codec hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.
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Abstract
Methods and system for computing an optimal mapping for algorithmic qubits of a quantum circuit onto physical qubits of a quantum computer using a quantum annealer are described wherein, the quantum annealer comprising a qubit register of controllable qubits. The method may comprise determining or receiving an initial Hamiltonian and a final Hamiltonian, the initial and final Hamiltonian comprising a first term comprising first Pauli operators acting on a first set of qubits of the qubit register, the first set of qubits forming a configuration register for representing mappings of the algorithmic qubits onto the physical qubits for different gate operations that need to be executed by the algorithmic qubits at different time instances as defined by the quantum circuit, and a second term comprising second Pauli operators acting on a second set of qubits of the qubit register the second set of qubits forming a clock register for representing the different time instances of the quantum circuit, the final Hamiltonian further comprising a third term comprising third Pauli operators acting on the qubits of the configuration and of the clock registers for providing a penalty to a mapping that requires one or more auxiliary gate operations in addition to the set of gate operations of the quantum circuit; executing a quantum annealing scheme using the quantum annealer, wherein the executing includes controlling the qubits of the qubit register to implement the initial Hamiltonian in the qubits of the quantum register and controlling the qubits to evolve the ground state of the initial Hamiltonian to the ground state of the final Hamiltonian.
Description
Computing qubit allocations using a quantum annealer
Technical field
The disclosure relates to qubit allocations and, in particular, though not exclusively, to methods and systems for computing qubit allocations using a quantum computer, and a computer program product enabling a data processing system comprising a quantum annealer to compute qubit allocations.
Background
The problem of qubit allocation (also referred to as qubit routing) is an important subproblem in the compilation process of gatebased quantum computing. It consists on finding optimal mappings of the algorithmic qubits (also referred to as virtual qubits) present in the instruction set r of a quantum program, represented by a quantum circuit, onto physical qubits of a quantum processor with limited connectivity Q. These optical mappings may also be referred to as qubit allocations, which define instances of the qubit allocation problem.
During compilation of the quantum circuit, algorithmic qubits need to be mapped onto the physical qubits at a certain time instance within the quantum program. Hence, at each time instance, the quantum program prescribes a certain connectivity between the algorithmic qubits that should match the connectivity of the physical qubits, however it may happen that due to limitations of the hardware connectivity, a certain required connectivity is not possible. Such absence of a link between two qubits that need to interact according to the quantum circuit may require the addition of extra gate operations that may end up increasing the circuit’s depth greatly, which in turn translates to a greater exposure to noise. Especially in the NISQ (Noisy IntermediateScale Quantum) era, a bad solution to a qubit routing problem may result in a computation that is too noisy to be of any use.
A valid solution of the qubit allocation problem consists of an initial mapping and a new quantum circuit that incorporates a sequence of transformations necessary to realize the original quantum program in the quantum processor with limited connectivity. An exact or optimal solution of this problem is the one that guarantees that the cost of the new quantum circuit will be minimum in terms of both circuit depth and gate error.
A classical solution for the qubit allocation problem has been described in the article by Marcos Yukio Siraichi et al. “Qubit allocation”, Proceedings of the 2018 International Symposium on Code Generation and Optimization, Vienna Austria: ACM, Feb. 2018, pp. 113125, however all the classical solutions that they present are suboptimal with respect to the qubit allocation problem that has been defined above, and the most rigorous one is exponential with the number of qubits, and thus becomes unbearable for large sizes. Bryan Dury and Olivia Di Matteo, “A QllBO Formulation for Qubit Allocation”, Nov. 2020, arXiv: 2009.00140, http://arxiv.org/abs/2009.00140 propose a quantum annealing algorithm to solve the problem within the QllBO (Quadratic Unconstrained Binary Optimization) framework. However, this formulation greatly limits the optimality of the solutions, since it does not account for the dynamical change of the mapping between virtual and physical qubits throughout the quantum program. Such approach leaves out the larger part of the search space, where better solutions are likely to be found.
Hence, from the above, it follows that there is therefore a need in the art for improved methods and systems for computing qubit allocations, i.e. instances of the qubit allocation problem. In particular, there is a need in the art for improved methods and systems for computing qubit allocations that makes use of the full search space in order to reach optimal solutions.
As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Functions described in this disclosure may be implemented as an algorithm executed by a microprocessor of a computer. Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied, e.g., stored, thereon.
Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.
More specific examples (a nonexhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a readonly memory (ROM), an erasable programmable readonly memory (EPROM or Flash memory), an optical fiber, a portable compact disc readonly memory (CDROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber, cable, RF, etc., or any suitable combination of the foregoing. Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an objectoriented programming language such as Java(TM), Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user’s computer, partly on the user’s computer, as a standalone software package, partly on the user’s computer and partly on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user’s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor, in
particular a microprocessor or central processing unit (CPU), of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer, other programmable data processing apparatus, or other devices create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. Additionally, the Instructions may be executed by any type of processors, including but not limited to one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FP GAs), or other equivalent integrated or discrete logic circuitry.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardwarebased systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The embodiments in this application relate to algorithms for solving for the problem of qubit allocation within the framework of adiabatic quantum computation (AQC).
The latter constitutes a different paradigm of quantum computation from the gatebased approach that encodes the solution in the ground state (GS) of a problem Hamiltonian, in such a way that measuring this GS will provide the soughtafter solution. The adiabatic theorem, which ensures that a system in the GS of a certain Hamiltonian will remain in the GS after this Hamiltonian is altered as long as the change is slow enough, provides a means for the preparation of the GS of the problem Hamiltonian, which is a nontrivial task: starting from a simple Hamiltonian whose GS is easy to prepare experimentally, by slowly interpolating between this and the problem Hamiltonian we are guaranteed to reach the solution of our problem in a slow enough process. With this procedure it is possible to tackle many optimization problems, and it is within this context that it is referred to as quantum annealing.
In another aspect, the embodiments in this application relate to a method for computing an optimal mapping for algorithmic qubits of a quantum circuit onto physical qubits of a quantum computer using a quantum annealer. The quantum annealer may comprise a qubit register of controllable qubits. In an embodiment, the method may comprise one or more of the following steps: determining or receiving an initial Hamiltonian and a final Hamiltonian, the initial and final Hamiltonian comprising a first term comprising first Pauli operators acting on a first set of qubits of the qubit register, the first set of qubits forming a configuration register for representing mappings of the algorithmic qubits onto the physical qubits as defined by the quantum circuit, and a second term comprising second Pauli operators acting on a second set of qubits of the qubit register the second set of qubits forming a clock register for representing the different time instances of the quantum circuit; executing a quantum annealing scheme based on the initial and final Hamiltonian using the quantum annealer determining an optimal mapping, wherein the executing includes: controlling the qubits of the qubit register to implement the initial Hamiltonian in the qubits of the quantum register and controlling the qubits to evolve the ground state of the initial Hamiltonian to the ground state of the final Hamiltonian; measuring one or more qubit states of the clock register and if the one or more measured qubit states of the clock register indicate that the entangled qubits of the clock register have collapsed to a state associated with a time instance of the quantum circuit, then measuring one or more qubit states of the configuration register to determine the mapping of algorithmic qubits onto the physical qubits associated with the time instance of the quantum circuit; and, determining an optimal mapping for the one or more gate operations associated with the time instance of the quantum circuit based on the one or more measured qubit states of the configuration register.
In an embodiment, the final Hamiltonian may further comprise a third term
comprising third Pauli operators acting on the qubits of the configuration and of the clock registers for providing a penalty to a mapping that requires one or more auxiliary gate operations in addition to the set of gate operations of the quantum circuit.
Hence, the method includes an annealing scheme for determining an optimal mapping of logical qubits of a quantum circuit to physical qubits of a quantum computer. The scheme uses separation of the qubit register of the annealer into a clock register comprising only information about the time variable, and an allocation register comprising information about the mapping of the set of algorithmic qubits onto the set of physical qubits. Due to the entanglement generated between the clock and configuration register, the measurement of the clock register collapses to a relevant state of the configuration register. This separation makes use of the quantum phenomenon of entanglement in order to correlate physically meaningful mappings with the time ordered set of gate operations of a quantum circuit in order to solve a qubit allocation problem instance that implies a dynamical evolution of a variable or set of variables in time. Here, optimal mappings of the algorithmic qubits onto the physical qubits are determined for different gate operations that need to be executed by the algorithmic qubits at different time instances as defined by the quantum circuit. Qubit allocation schemes within the quantum annealing framework in the prior art do not account for the dynamical change of the mapping between algorithmic and physical qubits of the quantum circuit, leaving out a large part of the search space, where better solutions are likely to be found. In contrast, the invention provides an solution taking into account this dynamical evolution.
In an embodiment, each qubit of the clock register may be associated to a time instance of the quantum circuit.
In an embodiment, the final Hamiltonian may further comprise a fourth term comprising Pauli operators acting on the qubits of the clock register for introducing a bias towards the initial or final time instance of the quantum circuit so that the optimal mapping is the optimal mapping associated with one or more gate operations of the quantum circuit that need to be executed at the initial or final time instance of the quantum circuit respectively.
In an embodiment, the physical qubits may be associated with a hardware connectivity and wherein the one or more auxiliary gate operations allow the algorithmic qubits to have a connectivity that matches the hardware connectivity of the physical qubits.
In an embodiment, the set of gate operations and the one or more auxiliary gate operations may form a transformed quantum circuit, the optimal mapping corresponding to a transformed quantum circuit with a low cost in terms of depth and/or error rate per gate operation. The low cost can be the minimum cost. This can be the case, for example, when
the quantum circuit is a shallow quantum circuit. A shallow quantum circuit is a quantum circuit in which the number of qubits exceeds the depth of the circuit.
In an embodiment, the one or more auxiliary operations may include one or more SWAP gates and/or one or more bridge gates, and wherein the second term of the final Hamiltonian includes a first term for implementing one or more SWAP transformations and a second term for implementing one or more bridge transformations.
In an embodiment, measuring one or more qubit states of the clock register may further include: measuring the qubits of the clock register in a reverse time order starting from a qubit of the clock register representing a final time instance.
In an embodiment, the second Pauli operators acting on the qubits of the clock register may be configured to provide a penalty term for states not belonging to the clock register space.
In an embodiment, the first Pauli operators acting on qubits of the configuration register may be configured to restrict the qubit mappings such that: a physical qubit of the configuration register can only have one associated algorithmic qubit; the configuration register has a total of N_{v} occupied physical qubits wherein N_{v} is the number of algorithmic (virtual) qubits, and, each algorithmic qubit is allocated to a physical qubit of the configuration register once per time instance.
In an embodiment, the first Pauli operators acting on qubits of the configuration register may be configured to restrict the configuration register to mappings that are physically accessible in the quantum processor, preferably based on an adjacency matrix D_{a}p associated with the hardware graph of the quantum processor.
In an embodiment, the initial Hamiltonian may include a second term comprising Pauli operators acting on the qubits of the clock register for initialization of the clock register.
In an embodiment, the executing a quantum annealing scheme may further comprise: preparing the ground state of the initial Hamiltonian based on a further annealing scheme, the further annealing scheme including; controlling the qubits of the quantum register into a standard Hamiltonian, preferably an Isingtype Hamiltonian having a ground state which can be prepared experimentally; and, controlling the qubits of the quantum register to evolve from a ground state of the standard Hamiltonian to a ground state of the initial Hamiltonian.
In an embodiment, the method may further include: constructing a new final Hamiltonian based on the final Hamiltonian and a Hamiltonian term describing an optimal mapping solution at a previously computed time instance; and, executing the quantum annealing scheme based on the initial and the new final Hamiltonian to determine an optimal
mapping for the algorithmic qubits associated with a time instance that precedes the time instance of the quantum circuit associated with the previously computed mapping.
In a further aspect, the embodiments in this application may relate to a system for allocating qubits, using a data processing system comprising a classical computer system and a quantum computer system, wherein the system is configured to: determining or receiving an initial Hamiltonian and a final Hamiltonian, the initial and final Hamiltonian comprising a first term comprising first Pauli operators acting on a first set of qubits of the qubit register, the first set of qubits forming a configuration register for representing mappings of the algorithmic qubits onto the physical qubits as defined by the quantum circuit, and a second term comprising second Pauli operators acting on a second set of qubits of the qubit register the second set of qubits forming a clock register for representing the different time instances of the quantum circuit; and, executing a quantum annealing scheme based on the initial and final Hamiltonian using the quantum annealer determining an optimal mapping, wherein the executing includes: controlling the qubits of the qubit register to implement the initial Hamiltonian in the qubits of the quantum register and controlling the qubits to evolve the ground state of the initial Hamiltonian to the ground state of the final Hamiltonian; measuring one or more qubit states of the clock register and if the one or more measured qubit states of the clock register indicate that the entangled qubits of the qubit register have collapsed to a state associated with a time instance of the quantum circuit, then measuring one or more qubit states of the configuration register to determine the mapping of one or more gate operations associated with the time instance of the quantum circuit; and, determining an optimal mapping for the one or more gate operations associated with the time instance of the quantum circuit based on the one or more measured qubit states of the configuration register.
In an embodiment, the final Hamiltonian may further comprise a third term comprising third Pauli operators acting on the qubits of the configuration and of the clock registers for providing a penalty to a mapping that requires one or more auxiliary gate operations in addition to the set of gate operations of the quantum circuit.
The embodiments may also relate to a program or suite of computer programs comprising at least one software code portion or a computer program product storing at least one software code portion, the software code portion, when run on a classical computer system wherein the classical computer is part of a data processing system comprising the classical computer system connected to a quantum annealer, being configured for executing the method steps as described with reference to the embodiments in this application.
The embodiments exploit the inherent parallelization achievable with superposition of the qubits of a quantum annealer to explore all possible paths towards the
desired connectivity at once. Thus, the intuitive idea of what the proposed algorithm is doing is a bruteforce calculation of all the possible “transformation paths” (i.e. , the sequence of transformations applied to the qubits in order to keep up with all the links required throughout the quantum circuit) with their corresponding penalties, in such a way that the final allocation of the qubits relative to the transformation path with the lowest overall penalty can be identified in the final ground state.
It is important to highlight the distinction between the solution to the qubit allocation problem as it has been previously defined, and the solution that the present algorithm is able to access and how they both relate. A solution of the qubit allocation problem corresponds to an initial mapping and a particular transformation path, i.e., a sequence of transformations designed to allow for the required connectivity at all steps of the circuit (said set of transformations including the identity transformation). A “configuration path” may be defined as the series of mappings between the set of algorithmic qubits and the set of hardware qubits that corresponds to a particular transformation path. The proposed quantum algorithm allows to compute the initial point of the configuration path.
This initial allocation is of great use to subsequent algorithms, e.g. heuristics, that aim to find good sets of transformations to solve the qubit allocation problem, which are the most common approaches in the literature.
To obtain the rest of the points from an optimal configuration path, this algorithm can be used in an iterative manner. With regards to finding several configurations corresponding to different time instances of the circuit, it is remarked that a configuration path does not uniquely define a transformation path, as several of the latter may present the same configuration path. However, the most costeffective transformations between two given configurations constitute a less complex problem that can be tackled in parallel (connecting a pair of consecutive configurations can be done independently for any pair) more efficiently, e.g. through a breadthfirst search (BFS) algorithm. Thus, from the optimal path it is possible to reconstruct the optimal transformation path (or parts of it, if only parts of the optimal configuration path are available).
In contrast to prior art schemes, the embodiments follow the dynamical transformation of the embedding. In addition, the embodiments consider the possibility of having bridge gates apart from SWAPs, thus taking into consideration the full search space.
The invention may further relate to a nontransitory computerreadable storage medium storing at least one software code portion, the software code portion, when executed or processed by a computer, is configured to perform any of the method steps as described above.
The invention will be further illustrated with reference to the attached drawings, which schematically will show embodiments according to the invention. It will be understood that the invention is not in any way restricted to these specific embodiments.
Brief description of the drawings
Fig. 1 depicts a hybrid data processing system comprising a classical computer and a quantum processor;
Fig. 2A2C illustrates an instance of a qubit allocation problem and a solution for this qubit allocation problem instance;
Fig 3 depicts a schematic of translating SWAP and bridge gate operations into CNOT operations;
Fig 4 illustrates the time dependent energy spectrum for an Hamiltonian that slowly evolves from an initial Hamiltonian to a final Hamiltonian;
Fig. 5 schematically depicts a quantum register for encoding the problem Hamiltonian according to an embodiment of the invention;
Fig. 6 depicts an illustration of the shortest paths connecting two qubits in a quantum register;
Fig. 7 illustrates an example showing the relation between the instruction set and the adjacency matrix of a connectivity graph;
Fig. 8 illustrates the different sets of transformations that may bring within interaction distance the algorithmic qubits allocated at the extremes of a certain hardware path;
Fig. 9 depicts a flowchart for determining an optimized process for the preparation of the ground state of the initial Hamiltonian for the quantum annealing scheme according to an embodiment of the invention;
Fig. 10 depicts a flowchart for determining a solution to a qubit allocation problem using a quantum annealing scheme according to an embodiment of the invention.
Fig. 11 depicts a flow chart of a method for computing an optimal mapping for algorithmic qubits of a quantum circuit onto physical qubits of a quantum computer using a quantum annealer according to an embodiment of the invention.
Description of the embodiments
Fig. 1 depicts a hybrid data processing system 102 including a classical computer 104 comprising one or more classical processors (CPUs and/or GPUs) and a
quantum processor 106 comprising a plurality of interacting quantum elements, e.g. qubits, that can be controlled by the classical computer. Here, the qubits may be implemented based on different types of technologies, including but not limited to superconducting qubits, quantum dot qubits, neutral atom type qubits, optical qubits, etc. The quantum processor may be controlled via a controller system 108 comprising input output (I/O) devices which form an interface between the quantum processor and classical computer 106. The controller system may include a system for generating control signals 110 for controlling the quantum processing elements. The control signals may include for example pulses, e.g. microwave pulses, voltage pulses and/or optical pulses, for manipulating the qubits, e.g. bringing them in an initial state and manipulating the state of the qubit and/or the interaction (coupling) between two or more qubits. Further, the controller may include a data acquisition system for readout of state of the quantum processing elements. Hence, the data acquisition system may receive an output signal 112 originating from the quantum processor in response to a readout pulse for reading the state of a quantum element. In some embodiments, at least a part of the data acquisition system may be located or integrated with the chip that includes the qubits.
The classical computing system may include different modules for enabling execution programs, in particular quantum annealing programs, to be executed on the quantum processor. To that end, the classical computer may include a problem encoder module 114 configured to receive a computational problem that needs to be solved and encoded that problem into a problem Hamilton of the quantum processor. Typically, the computational problem may be an NPhard problem, such as the bit allocation problem as described hereunder in more detail.
The problem Hamiltonian may have an Isinglike Hamiltonian based on Pauli operators acting on a Zcth qubit of the plurality of qubits. The problem Hamiltonian may also include one or more adjustable parameters which can be controlled by external electromagnetic control signals, e.g. electromagnetic or magnetic fields, which may be used to locally adjust the electromagnetic or magnetic environment at one or more qubits. A plurality of such adjustable external control signals may be used to control a single qubit or a part of the plurality of qubits. By adjusting the external control signals, these parameters may be adjusted depending on the computational problem. Encoding the computational problem into the problem Hamiltonian, as performed by the classical computing system, includes determining, from the computational problem, a configuration for the plurality of adjustable parameters. For each of the adjustable parameters a parameter value may be determined depending on the computational problem.
The classical computer may further include a quantum annealing module adapted to perform a quantum annealing scheme which may include initializing the quantum processor based on an initial Hamiltonian and slowly (adiabatically) evolving the Hamiltonian to a final Hamiltonian which includes the problem Hamiltonian. The initial Hamiltonian may be based on Pauli operators acting on the qubits. Typically the initial Hamiltonian may be selected so that it does not commute with the final Hamiltonian.
The computational problem is encoded in the problem Hamiltonian so that a ground state of the final Hamiltonian comprises information about a solution to the problem that is encoded in the problem Hamiltonian. Thus, if the quantum processor is in the ground state of the final Hamiltonian, information about the problem may be obtained by measuring the states of the qubits.
Hence, during the annealing process, the quantum processor is evolving from the ground state of the initial Hamiltonian towards the ground state of the final Hamiltonian, wherein the plurality of adjustable parameters of the problem Hamiltonian are in the problemencoding configuration. The evolution of the quantum processor may be controlled by the programmable quantum annealing module using the external electromagnetic control signals.
The controller system may include a data acquisition system configured to measure the states of at least part of the qubits of the quantum processor, wherein the measured information may include at least part of the solution to the problem that is encoded in the problem Hamiltonian. In particular, the classical computer may determine a trial solution to the computational problem based on the measured information, and verify if the trial solution actually is a solution to the computational problem. For NP problems, the verification is a computation which can be carried out in polynomial time, and can typically be easily computed. This process may be repeated until a solution to the computational problem is found.
The embodiments in this application deal with the problem of qubit allocation which is an important subproblem in the compilation process of gatebased quantum computing, wherein algorithmic qubits need to be allocated to physical qubits of a quantum processor. An instance of such NP hard problem and a solution thereof are schematically illustrated with reference to Fig. 2A2C.
Here, Fig. 2A shows a socalled quantum circuit 202 defining a quantum algorithm or a part thereof. The quantum circuit describes a sequence of gate operations 208,210 to be executed at predetermined time instances ti,t2,ts,t4 involving in this case four algorithmic qubits Q0Q3 206, followed by measurements 212 of the states of the algorithmic qubits. As shown by the figure, a quantum circuit may include more than one gate operation
per time instance. These gate operations associated with one time instance may be referred to as a circuit layer. These operations need to be executed on a physical quantum processor 204, which means that the quantum circuit is compiled into a set of specific gate operations for a physical quantum computer. However, the qubits of stateoftheart quantum processors comprise coupled physical qubits 21616, wherein  due to current date manufacturing constraints  not all qubits of the quantum processor are coupled to all other qubits. For example, as shown in Fig. 2A, physical qubit 2161 is connected via a first coupling 2181 (or link) to physical qubit 2162 and via a second coupling 2182 (or link) to physical qubit 2163.
This particular coupling layout of the physical qubits of the quantum processor, also referred to as the connectivity of the physical qubits of the quantum processor, limits the way the gate operations of the quantum circuit can be executed on the qubits of the quantum processor.
One of the defining features of the physical quantum processor, along with its connectivity, is its native set of gates, i.e., the set of operations that it is able to implement directly. If this set is universal, the device may implement any arbitrary operation by decomposing it as a series of gates of its native set. Currently, a very popular choice for direct hardware implementation is the set of single qubit operations and the CNOT gate, which is universal. Because of its widespread use, the examples in this application are based on this native gate set. Once in this setting, there are several ways in which one can patch up their circuit in order to achieve a connectivity that goes beyond hardware capabilities.
Fig. 2B illustrates the qubit allocation problem in more detail. As shown in the figure, the problem relates to finding the optimal mapping of the algorithmic qubits
= 0, ...,3) 223 (also referred to a virtual qubits) present in the instruction set r 222 of a quantum circuit onto a physical qubit arrangement (as presented by hardware graph fl 220) having a predetermined (limited) connectivity. The connectivity of the hardware graph fl may be described by the adjacency matrix D_{a}p 217. As shown in the figure, the instruction set represents a set of gate operations to be applied on the algorithmic qubits at different time instances ti,... ,te, wherein each gate operation is characterized by a certain connectivity. So the first entry in the instruction set table indicates that at ti an interaction between the first virtual qubit q% and the second virtual qubit q% is needed. The hardware graph fl may represent a physical qubit at each vertex 221 , while a line 219 connecting 2 vertices in the graph may identify a connection between two physical qubits. Hence, the lines indicate which physical qubits can interact (e.g. entangle). The link may also be associated with a quality, e.g. a fidelity. Similarly, the instruction set r may define a set of connections (a connectivity) between algorithmic qubits that are needed for execution of the gate operations defined by the quantum circuit.
The absence of a link between two qubits that need to interact according to de gate operations of a quantum circuit requires the addition of extra gates that may end up increasing the circuit’s depth greatly, which in turn translates to a greater exposure to noise. This is shown in Fig. 2C, which illustrates a possible way of executing the six qubit operations of quantum circuit 224 in a sequential way (at time instances ti,...teY As shown in the first allocation graph 226, the first two instructions ti and fc, requiring a connection between algorithmic qubit q% and q% and between algorithmic qubit q% and q% respectively, can be directly allocated to physical qubit q$ that is coupled to physical qubit q^ and physical qubit (73 respectively. The next instruction t3 however requires a connection between algorithmic qubit q% and q% . As shown by graph 226 however this instruction cannot be executed as at t3 there is no physical connection between physical qubit q^ (which holds algorithmic qubit q”) and physical qubit q% (which holds algorithmic qubit q%).
To address this problem a compiler that is processing the gate operations of the quantum circuit may be configured to introduce one or more transformations, i.e. additional gate operations, to enable execution of the quantum circuit on the physical qubit register with limited connectivity. In this example, the transformation may include socalled SWAP gates 227,229 that swap the states of two qubits. In this particular case, for example the compiler may decide to introduce a first SWAP gate 227 to swap the states of qubits q$ and (73 so that algorithmic qubit q% is mapped on physical qubit q$ and algorithmic qubit q% is mapped on physical qubit q% . Thereafter, instruction 6 (requiring a connection between algorithmic qubit q% and q%) can be executed. In the same way, after execution of instructions t4 and ts, a second SWAP gate 229 may be introduced to allow execution of instructions ts, Thus, due to the limited connectivity of the physical qubits, additional gates need to be introduced in order to execute the gate operations of a quantum circuit leading to increasing circuit depts and longer runtime. This, especially in the NISQ (Noisy IntermediateScale Quantum) era, may be a severe enough problem that a bad solution to an initial mapping results in a computation too noisy to be of any use. The process of including additional gate instructions to achieve the required connectivity is referred to as circuit transformation.
Fig. 3A and 3B depict examples of gate operations that can be used to achieve connectivity. Fig. 3A illustrates the swap gate operation, which is translated into 3 CNOT gates 304 to exchange qubit states of two physical qubits 302. The swapping operation is not reversed after execution and thus the application of this gate causes the algorithmictophysical qubit assignment to dynamically change along the quantum program. When the distance between the two qubits of interest is just 1 (i.e., they are not connected but both are linked to the same third qubit), there is another convenient identity, the socalled
bridge gate, that allows implementing the desired CNOT, at the same gate cost as performing a SWAP and applying the desired CNOT afterwards (so effectively involving four CNOT gates), without altering the current allocation of the qubits. Fig. 3B illustrates the bridge gate which requires four CNOT gates. Thus, for fixing connectivity at a distance of 1, both swap and bridge are equally expensive solutions that produce different allocation graphs. However, for saving distances greater than 1 , concatenated swaps and the corresponding CNOTs is the only possible option. This compilation of the circuit into the hardware’s (sparser) physical connectivity will always result in a quantum circuit with an effective circuit depth that is larger than the initial circuit depth of the quantum circuit without taking the connectivity of the physical qubits into account.
It is an aim of the embodiments in this application to find optimal solutions to the qubit allocation problem as described above using quantum annealing schemes. In particular, it is an aim of the embodiments in this application to determine a quantum algorithm that builds a cost function, in the form of a Hamiltonian (a mathematical description of the physics of a system of interest, including the relevant processes that the system under consideration is subject to) that has a global minimum that provides access to the configuration path of an optimal solution to the qubit allocation problem. The quantum algorithm presented by the embodiments in this application for solving this problem using a quantum annealer follows the possible tracks of the qubit allocation problem by exploiting superposition and entanglement, such that information about an optimal set of configurations the system is in at each time instance can be retrieved.
The embodiments address the problem of qubit allocation within the framework of adiabatic quantum computation (AQC). As will be described hereunder in more detail, AQC constitutes a quantum computation paradigm that is different from the gatebased quantum computation approach. In the AQC scheme the problem to be solved is encoded in a socalled problem Hamiltonian such that the ground state (GS) of the problem Hamiltonian holds the solution to the problem. Thus, measuring the GS will provide the soughtafter solution. The adiabatic theorem, which ensures that a system in the GS of a certain Hamiltonian will remain in the GS after this Hamiltonian is altered as long as the change is slow enough, provides a means for the preparation of the GS of the problem Hamiltonian. Preparing such GS is a nontrivial task. In an embodiment, first the qubits of the quantum annealer are prepared based ib a simple (initial) Hamiltonian H_{o} whose ground state may be relatively easy to realize experimentally, the quantum annealer may be controlled to slowly interpolate between the initial Hamiltonian H_{o} and the problem Hamiltonian
to reach a final ground state as is schematically depicted in Fig. 4. This final ground state may provide a solution to an instance of the qubit allocation problem. Following
this adiabatic quantum computation scheme, it is possible to tackle optimization problems. In this application such scheme may also be referred to as a quantum annealing scheme.
Encoding
As will be described hereunder in more detail, a quantum annealer depicts a hybrid data processing system as described with reference to Fig. 1, comprising a classical computer connected to a quantum processor, comprising an array of coupled qubits, wherein the hybrid data processing system is configured to execute a quantum annealing scheme. Such array of coupled qubits may be referred to as a qubit register. Each individual qubit of the quantum annealer may be associated with two ground states, e.g. a spin up l)and a spin down state0). According to the superposition principle, each superposition of the form ci0> + bl) forms a possible quantum state of the qubits. Hence, the qubits of the quantum annealer can be described in terms of binary variables x = {0,1}, wherein
correspond to
and wherein a? is the Pauli operator acting on (annealer) qubit /z. This way, x = 1 may represent an upward (zpositive) spin and x = 0 a downward spin (znegative). Several ways may exist to map the qubit register to an allocation assignment, each corresponding to a different cost in qubit expenses.
The first step requires the encoding of the qubit allocation problem into a problem Hamiltonian of the quantum processor. The encoding of the problem requires (N_{v} + 1) • N_{h} + L_{v} qubits, where N_{v} is the number of virtual (algorithmic) qubits, N_{h} is the number of physical qubits of the quantum processor that is evaluated (here it is considered that N_{h} > N_{v} here) and L_{v} is the number of instructions of the evaluated circuit that should be executed on the quantum processor. To that end, the qubit register of the quantum annealer may be subdivided in sub registers as shown in Fig. 5A. This figure shows a first sub register 504 (referred to as the clock register C) comprising L_{v} clock qubits, {xf }^_{0} f°^{r} encoding the instructions of the quantum circuit that is evaluated and a second sub register 502 (also referred to as the configuration register A) comprising (N_{v} + 1) • N_{h} qubits for encoding different possible configurations (mappings) of algorithmic qubits onto physical qubits.
Fig. 5B shows that the configuration register comprises N_{h} subblocks
A = each containing N_{v} + 1 configuration qubits, which may be labeled as follows This way, as shown by the example of in the figure, subblock A_{3} 506 may
comprise a string of qubits x_{3i} = 0010 ....0 including “one” (spin up) bit at position 2 in the string, indicating that algorithmic qubit is mapped on physical qubit q_{3} . Hence, the string
qubits in each subblock encodes a possible mapping of the algorithmic qubit on a physical qubit. The extra qubit per hardware subblock corresponds to sites x_{a0} which, if full, indicates hardware site a is empty. As such, this only becomes relevant N Restriction to the
correct subspace allows allocating a single upwards spin in each subblock, all in different virtual positions, thus obtaining the desired map.
As shown in Fig. 5C, the clock qubits are configured to keep track of time (i.e. the sequence of gate operations of the quantum circuit that is part of the allocation problem) by populating the register, initialized with all zeros, with ones in an orderly manner, i.e., the register corresponding to time instance t(t e 0, ...,L_{V}) may be identified by xg) = In order to enforce this encoding,
corresponding penalization terms need to be included in both initial and final Hamiltonians.
Constraints
As described above, the encoding relies on the restriction of the solution space (i.e. the Hilbert space of the qubit register) to physically relevant qubit registers. For the space associated with the configuration register for mapping the algorithmic qubits to the physical qubits, the following requirements (constraints) are taken into account:
1. a physical qubit of the configuration register can only have one associated virtual qubit;
2. the configuration register has a total of N_{v} occupied physical qubits; and,
3. each virtual qubit must be allocated to a physical qubit of the configuration register once per time instance.
These requirements may be fulfilled using the following Hamiltonian
term in both the initial Hamiltonian H_{0o} and in the final Hamiltonian
For the clock register, in order to stay in the proper clock register space, the penalty Hamiltonians as described in the article by Aharonov et al. Adiabatic Quantum Computation is Equivalent to Standard Quantum Computation: arXiv:quantph/0405098 (Mar. 2005) http: //arxiv.org/abs/quantph/0405098 may be used. According to the choice of
clock states, a penalty term for all states not belonging to the allowed subspace (as illustrated in Fig. 5C) may be built by penalizing any state with a consecutive 101) sequence. Thus, for the clock register the constraints can be introduced using the following Hamiltonian Hf! term:
in both the initial Hamiltonian H_{o} and in the final Hamiltonian H_{}}
Hardware connectivity
The proposed algorithm can be realized more efficiently (i.e., the resulting algorithm will produce a larger minimum gap) by tailoring it for the connectivity of the qubits of a particular gatebased quantum processor, i.e. the processor on which the quantum circuit is to be executed. This tailoring includes restriction to configurations that are physically accessible in the quantum processor. To that end, the adjacency matrix D_{a}p associated with the hardware graph 12 of the quantum processor (see e.g. Fig. 2B) may be used. This way, the connectivity may be added to the Hamiltonian as an additional constraint term. In an embodiment, in the simple case, the adjacency matrix may be defined as D_{a}p = 0,1. In another embodiment, the adjacency matrix may be based on a weighted device graph to include other relevant factors, including but not limited to the quality of the connection. Hereunder, embodiments will be described which take this into account. Hence, the Hamiltonian term that takes into account the connectivity of the physical qubits of a quantum register may be described by the following Hamiltonian:
In some embodiments, an additional matrix Q may be used for storing the success probability of each 2qubit gate operation to distinguish the different costs of bridge and SWAP operations realizing the same connectivity as shown for example in Fig. 2.
The abovementioned terms restrict the qubit registers to the search space that is relevant for the physical qubits. This way one may define a restriction Hamiltonian H_{r} as:
As already briefly described above, an annealing algorithm is based on the interpolation between some initial Hamiltonian H_{o} (associated with a ground state that one knows how to prepare) and a final Hamiltonian
(associated with a ground state in which the solution of the qubit allocation problem is encoded). In an embodiment, in its simplest form, this interpolation may be a linear interpolation. The embodiments described in this application are not limited to linear schedules. Nonlinear functions may also be used as viable schedules as long as the conditions are respected, wherein s is a
dimensional time
parameterizing the whole annealing process. For simplicity, the formulation of the qubit allocation problem in the AQC framework may be described based on a linear schedule when referring to the annealing process. (5)
The interpolation between H_{o}
is realized using continuous modulation of the parameters of the device. This may be realized by slowly turning off the interactions and local fields that govern H_{o} while at the same time the interactions and local fields that govern
are being turned on. For example, one may use the electromagnetic control signals, e.g. magnetic control signals, as described with reference to Fig. 1 to control the initial and problem Hamiltonian.
In contrast to typical annealing problems, for the qubit allocation problem, the initial Hamiltonian H_{o} corresponds to a quantum Ising model that has a nontrivial ground state. Therefore, this ground state needs to be prepared in a separate annealing process, which will be described hereunder in more detail with reference to Fig. 9. In an embodiment, the annealing process may start from a state that encodes the equal superposition of all the possible embeddings of N_{v} qubits, along with an initialized clock register.
To that end, a mixing Hamiltonian H_{mixture} , e.g. an Isingtype Hamiltonian term, and the abovedescribed restriction Hamiltonian H_{r} may be used. For ensuring an initialized (allzero) clock register, a term H_{ciockinit} has to be included in the initial Hamiltonian H_{o}. This way the following expressions for H_{mixture} , H_{ciockinit} and in the initial Hamiltonian H_{o} can be written down as follows:
where A_{r} » 1 is the Lagrange multiplier for the constraints.
The final Hamiltonian
defining the problem Hamiltonian, may include ^transformations which describes the instruction set that needs to be evaluated and the allowed transformations with their respective gate cost (which will be considered hereunder in more detail). The problem Hamiltonian may further include the restriction Hamiltonian H_{r} and a term to introduce some bias towards a predetermined time instance of the instruction set. In an embodiment, a Hamiltonian term H_{ciock}f_{inca} may be selected to introduce bias to the final time instance L_{v} , such that at the end of the annealing scheme, the ground state may include information about the configuration that is associated with the final time instance of an optimal configuration path:
Transformations
To implement rewards and penalties to possible routes that satisfy the prescribed connectivity for each operation (i.e. , time instance), while respecting the hardware connectivity limitations of the physical qubits as imposed by D_{a}p , a Hamiltonian H trans formations may be introduced. In this manner, transition amplitudes are engineered such that they constitute a reward if the connectivity required by the instruction at that time instance is satisfied, and a penalty (damping) that reflects an additional effort required to fix that connectivity if the connectivity is not satisfied.
Hence, the transformation Hamiltonian may include three terms: a first (noswap) Hamiltonian term H_{ns} (Eqs. (11) and (12)) which represents the part of the transformation Hamiltonian that provides a reward for an absence of a transformation, a second Hamiltonian term H_{b} (Eq. (13)) that imposes a penalty when considering implementation of a bridge gate and a third Hamiltonian term H_{s} (Eq. (21)) that switches to the new hardware configuration for the next time instance, as the actual device would do.
To properly formulate the terms forming H_{transformations} some notation is necessary. To formulate the relevant expressions in a clear manner, one is interested in the shortest path(s) of all possible paths between two physical qubits a and /?. To that end, based on a hardware graph of the quantum processor that is under evaluation, one may define an ordered sequence of physical qubits that constitutes a path between qubit a
and qubit (3, with I intermediate qubits in between, where is an index to number the different possibilities. Here, I may define a path distance between physical qubits a and (3, wherein the possible values of the path distance are 1, ..., d_{max}. There are at most A = (_{n} 5^+2))! ^{s}'^{m}P'^{e} P^{at}hs of distance I between any two sites.
Fig. 6 shows a hardware graph 604 comprising physical qubits (indicated by Greek letters) and an algorithmic graph 602 defining the associated algorithmic qubits (indicated by Latin letters). This figure provides an illustration of the different shortest paths that are possible for connecting two qubits in the device (both for the physical qubits and the virtual qubits levels). As shown in this figure, each algorithmic qubit may be allocated to one hardware qubit: algorithmic qubit i 6O61 may be assigned to physical qubit a 6O81; algorithmic qubit j 6O62 may be assigned to physical qubit (3 6O82 etc. In this particular example, physical qubits a and (3 are not directly connected, but connected via at least one intermediate qubit. Hence, the shortest paths in the graph between the two qubits go via at least one intermediate qubit. The patch distance in this particular example is one, i.e. I = 1. Interaction between the qubits may be realized either through a bridge gate utilizing yi or y_{2}. or by performing the swaps depicted through
610i (Wj_{7;i} 612i in algorithmic space) or through o)_{a}p_{i2} 6102 (w^ 6122 in algorithmic space). As a consequence, a total of 6 different options for connecting algorithmic qubits i and j are possible in this example.
A discriminating function D(o>) may be designed that evaluates to one if 0) is a shortest path present in the device and to zero in the opposite case. This function may be built on the basis of the adjacency matrix D as follows:
In a similar manner, an ordered sequence of algorithmic qubits
may be defined, starting from i and ending with j, with I steps in between, that recounts the virtual qubits allocated along some simple path defined in the device. Thus, a pair
specifies some allocation of I + 2 qubits onto the device, as depicted in Fig. 6.
The ordered set of instructions at time instances t = 1 through t = L_{v} that contains the circuit’s twoqubit gates may be indicated as r
This is explained in more detail with reference to Fig. 7, which illustrates the relation between the instruction set and PT For a chunk of an input program 704,706, hardware graphs 712,714 represent a particular allocation of algorithmic qubits (numbers) into the available physical qubits (represented by circles) of a qubit register. The hardware connectivity of the qubit register
may be given by adjacency matrix D_{a}p. Here, 708 and
710 are lists of
and E_{t} of algorithmic qubits each involved in a 2qubit gate of a quantum circuit including instructions, e.g. multiple gate operations between different algorithmic qubits at t  1 and at t, that can be performed simultaneously. Based on the instruction set r^{f} at time instance t, a discriminating matrix
may be constructed wherein % indexes the various links required at time instance t. The discriminating matrix may comprise matrix elements which are one if a link is present and a zero otherwise. For example, 712 illustrates a graph that includes the required links for the instructions of the instruction set at t  1, indicating that links between algorithmic qubits (0,1), (2, 3), (5, 4) are needed. As shown in the graph, at t  1 the instructions can be executed on the physical qubits because the connectivity of the physical qubits matches the required connectivity of the algorithmic qubits. In contrast, as shown by hardware graph 714, at t two links between algorithmic qubits (1,6) and (0,3) are required. The discriminating matrix
thus can be seen as a type of adjacency matrix in the space of algorithmic qubits at time instance t. Thus, each % encodes two indices i,j of algorithmic qubits that are to be linked at time instance t, and all % belonging to the same time instance refer to different algorithmic qubits. As shown in Fig. 7, the allocation configuration satisfies the required hardware connectivity at time instance t  1, but it requires some further transformations (addition of swap or bridge operations) in order to satisfy it at t.
Based on the above definitions, the transformation Hamiltonian ^transformations may be expressed as follows:
wherein H_{ns} provides a reward when no additional transformations are required.
Hereunder, a more detail description of Hamiltonian terms H_{b} and H_{s} are provided, which relate to the bridge and swap gate operations. The bridge gates, taking into account through the Hamiltonian term H_{b}may be constructed in a similar way as H_{ns}, but in this case the qubits of interest are not hardwareconnected, while sharing a common neighbor (thus I = 1):
where the function f (Z) sets for a transformation fixing a distance between the qubits of interest of order of path distance /, which corresponds to adding 31 CNOT gates to the circuit. This penalty may be decreasing with increasing path distance I, preferably monotonically, as it is desirable to have a smaller contribution of longer paths at later times. For bridge gates the path distance is always 1 , i.e. I = 1, while for the swapping transformation different path distances may be taken into account I = 1, ..., d_{max},. However, the maximum path distance I to be considered may be reduced without impacting the optimality of the solution in general, since the exact solution will rarely rely on such convoluted transformations. Equation (13) only accounts for the implementation of a single bridge for fixing connectivity requirements at time instance t. In order to include richer possibilities, such as having more than one bridge gate or the combination of bridge gates and SWAP gates, more convoluted expressions may be formulated based on the above described equations.
To construct a generalized expression for the swapping Hamiltonian term H_{s}, some definitions may be introduced. First an operator is considered that acts on a configuration that has algorithmic qubit i allocated in site a and algorithmic qubit p allocated in y by interchanging i and p (i.e.,(ai,yp) * (ap,yi)). This operator may be written as follows:
wherein
. This operation is configured to bring algorithmic qubits i and j together in a configuration ai  yp  (ij, which may be denoted in short as (ay ft, ipj). In this context, to maintain a compact notation, it is convenient to refer to it as:
By concatenating several operators as the one in equation (14), all transformations happening in the hardware can be described due to the consecutive action of SWAP gates in order to bring together the algorithmic qubits that are meant to interact next. As an illustration, consider the case for configuration ai  yyp  y_{2}q  Pj, which according to the notation would correspond to (ay^p, ipqj) If one would like to bring qubits i and j to neighboring sites so that they can interact, there are several ways to realize this
(exactly I for an initial distance of I between the target qubits), as depicted in Fig. 7 for a distance of I = 2, and all of them need to be included in the Hamiltonian to keep track of all possible paths. The operator taking i towards j, for example, would be:
where we have used the identity
= 1  n_{p}. The operator that has i and j meet halfway, on the other hand, would be:
*5^ (07172/3, ipqj) = S^{1} (759: ftj)S^{1}(7ip; af) = a_{g}a^_{i}a+_{p}a^_{i}a_{72g}a_{w}a_{71}pa_{ti} (IT)
Fig. 8 provides an illustration of the different sets of transformations that may bring the algorithmic qubits allocated at the extremes of a certain hardware path of length I within interaction distance for the first orders of separation. Note that that there are I + 1 possibilities per path distance I.
From this realization, it follows that we need to keep track of the initial and resulting configurations. From the parametrization of a string of algorithmic qubits
_{k} as defined with reference to Fig. 6, a function may be defined that considers the consecutive pairs of qubits defined from the string:
_{k}) = {(j, kJ, (k_{b} k_{2}), ..., (k_{b}J} (equation 20).
Similarly, a function z(l,m; ij, k) (equation 19) may be defined that does the same to the string of virtual qubits that results from the swapping transformation. These expressions will influence the cost of the transformation once the quality of the individual links are taken into account. With this, the following expression for the swap operator can be derived:
Here, the swap operator of Eq. (18) is constructed such that it only acts on configurations that do not fully respect the connectivity required at time instance t.
Connection quality
A further aspect that may be taken into account in the problem of qubit allocation is the quality of the physical qubits, which may vary because of for example fabrication defects. The quality (fidelity) of the physical qubits is an important parameter for nearterm quantum computers, since the high error rates may push a minimaldepth solution far from the optimum. Moreover, these quality considerations break the degeneracy of the optimal path, which in an ideal case would be very likely to exist because of the symmetries present in the hardware graph. This degeneracy is undesirable in general because trying to extract several steps of the optimal path may provide a suboptimal solution by mixing the actual solutions.
Imperfections of the introduced CNOT gates may be taken into account by identifying the probability of success of performing the desired CNOT between each hardware qubit pair as Q_{a}p e [0,1],
As can be seen in Fig. 3A and 3B, even though the total number of introduced CNOTs is the same for both bridge and SWAP (recall the extra CNOT that is implicit in the latter), we observe that the cost will be different according to the distinct qualities of connection. The term accounting for the penalty for a single bridge transformation may then be described as follows:
For the swapping transformation, on the other hand, we need to account for the connection quality to the cube in all links involved except for the targeted connection, where we will perform a single CNOT. In this case, it is the particular movement of the algorithmic qubits within a given path what determines the physical location of the targeted link, which we are indicating by the subindex m. Thus, we will denote the relevant pair of hardware sites as
For example, if we identify m = 0 with a right arrow,
and m = 1 with a left arrow,
for I = 1 in Fig. 8. The relevant hardware sites will be the last two of the path
for m = 0, and the first two for m = 1.
Iterative algorithm
The problem Hamiltonian as described above provides the initial configuration of an optimal configuration path. However, in an embodiment, the proposed scheme may be used to extract further information about the optimal configuration path, since the computation of the latter is still performed in full by the algorithm, however it cannot be accessed directly. To that end, the annealing scheme may be executed again by interpolating from the initial Hamiltonian H_{o} and a new problem Hamiltonian
= H_{1} + AbtasHct = + A_{bias}H_{cLv} , where H_{ct} is the projector onto the full register state describing configuration c at time instance t = L_{v} . In this new problem Hamiltonian, the allocation configuration is favored that was already found, which helps the algorithm discard paths that do not finish in such configuration and thus enhances the probability amplitude of the configuration c’ corresponding to an optimal path at the previous time instance t = L_{v}  1 .
For the next iteration, the biases towards both allocations would be included, updating the problem Hamiltonian to be of the form H"_{r} = H_{1}
which would lead to finding c” at time instance t = L_{v}  2 . Hence, the new problem Hamiltonian may be constructed based on the initial problem Hamiltonian and a Hamiltonian term describing the optimal mapping associated with the previously computed time instance, and this new problem Hamiltonian may then be used in a next annealing step to determine an optimal mapping for the algorithmic qubits associated with a time instance that precedes the time instance of the previously computed mapping.
However, this procedure cannot be extended further when the probability amplitude of the optimal configuration at a given time instance becomes less distinguishable from that of the other configurations. Thus, there is no guarantee that one is able to resolve the full optimal configuration path, although once one cannot properly resolve the optimal configuration one may invert the order of the quantum program (since quantum computation is reversible) and extract further information starting from the other end of the circuit. Once all the possible points of the optimal configuration path are extracted, the task of finding the optimal set of transformations that connects them is much lighter than the full allocation problem and may, in fact, be parallelized for each pair of configurations to be connected.
Additional implementation considerations
The algorithm described above carries the core of the computation to be performed, but further considerations need to be taken into account. Firstly, the ground state of the initial Hamiltonian needs to be prepared, which requires a separate annealing process because the ground state is nontrivial. However, since the initial Hamiltonian will be the same for qubit allocation instances referring to the same device connectivity D, this initial annealing process may be optimized independently of the problem at hand (for this specific machine), such that a very good approximation to the initial ground state can be guaranteed when starting the algorithm. Thus, prior to solving any qubit allocation instances, a learning process may be performed for the optimal schedule to reach the initial Hamiltonian from a standard, easytoprepare Hamiltonian, which is experimentally available. This standard Hamiltonian may have the falling expression H$^{tandard} =
Hence, the annealing scheme for obtaining an optimized initial Hamiltonian may be described by the following expression:
where A(s) is the schedule that we are to optimize. The optimization could be done by different schemes, for example a machine learning method. This optimization only needs to be done once for a given device connectivity.
The measurement of the final state of the whole computation needs to be performed carefully as, based on the current state of the art technology, it is not possible to perform joint measurements of all the qubits in the configuration register A, which comprises information about the configurations (e.g. the mappings from algorithmic qubits to physical qubits). In the scenario in which the solution is not degenerate, i.e. there is a single set of transformations that provides the minimal number of gates, the suboptimal configurations can be filtered out by the algorithm for large enough differences between the cost of the optimal path and the rest. However, in case the solution is degenerate (or in case very close lowestenergy solutions), additional statistical checks need to be performed. This is due to the fact that these optimal configurations at the final (or at a given) time may share some qubit assignments, and thus the reduced density matrix of the system after measuring the shared assignment will mix them both. This way, one may end up measuring a suboptimal configuration. For this reason, one may measure the register qubits of the configuration register A in all possible orders, as well as several times for statistical purposes. The qubits
of the clock register C, on the other hand, need to be measured before the qubits of the configuration register A. Additionally, they need to be measured in reverse order (from the last clock qubit, x[_{v}, to the first, xg), since in this case the enforcing of the unary encoding is enough to avoid this mixup without the need for statistics. Following this procedure, if the last clock qubit measured in the whole measurement procedure of a single shot (i.e. , xf_{v}) is in state 1) (or, equivalently, with its spin pointing upwards according to the chosen convention), one may stop measuring the clock qubits of clock register C as it has collapsed to the weighted configurations corresponding to the final time instance (t = L_{v}) of the instruction set. In that case, the qubits of the configuration register A may be measured. Alternatively, zero states 0) may be measured in the clock register C until a one state 1) in qubit is measured. It that case, one would stop measuring the clock register and switch to measuring A knowing that our measurements correspond to time instance t.
Implementation
Fig. 9 depicts a flowchart for determining an initial Hamiltonian for the quantum annealing scheme according to an embodiment of the invention. Prior to solving a qubit allocation instance, a learning process is needed for the optimal schedule to reach the ground state of the initial Hamiltonian H_{o} of the quantum allocation algorithm. For this, in a first step 902, the system may be initialized in a first standard (easytoprepare) ground state of an Isingtype Hamiltonian H$^{tandard} =
Then, an annealing schedule may be used to optimize this ground state by interpolating between the first standard state H^^{tandard} and a second optimized state W_{o}: H^{prior}(s) = + A(0; S)H_{O} (step 904). Regular minimization techniques
in machine learning can be used to perform this optimization. The annealing schedule includes a function A(0; S) that depends on a set of parameters 0 and s, which define the shape of the function and the interpolation time (s = — ), respectively. The parameters 0 Ttot may be selected such that the ground state of H_{o} is reached with a high probability. After running the annealing schedule, the state of the system may be measured (step 910) and the measurement results may be stored (step 912). Due to the probabilistic nature of quantum measurements and to have a reliable statistical result, the annealing schedule and the measurement step may be repeated for a number of shots (step 922).
Once all shots have been executed (step 1014), a reliable statistical result may be obtained for the state of the system compared with the expected ground state of H_{o} . If both states are similar enough (step 916
1), the ground state of H_{o} has been reached with high probability and the optimization routine may be stopped (step 918). Otherwise, a new set or parameters § may be selected (step 920) and used for executing the optimization routine again (step 924) until convergence is reached.
Fig. 10 depicts a flowchart of a process for determining a solution to a qubit allocation problem instance using a quantum annealing scheme according to an embodiment of the invention. This process may be executed on a hybrid data processing system comprising a classical computer and a quantum processor as described with reference to Fig. 1. As shown by Fig. 10, the process may include a first step 1002 wherein a ground state GS of H_{o} is prepared using an optimization routine as described with reference to Fig. 9. Then, the annealing schedule may be executed on the quantum processor which interpolates between H_{o} and the final Hamiltonian
i.e. the problem Hamiltonian, which encodes a qubit allocation configuration of an optimal qubit allocation mapping (step 1004).
After execution of the annealing scheme, first clock register C is measured. This measurement may include measuring the states of the qubits of the clock register in order, going from the last clock qubit xf_{v} to the first x£ (step 1006). The qubits are measured in order until a qubit x£ is measured in the state 1). In that case, the measurement of the clock register can be stopped as the measurement state 1) indicates that the quantum state of the qubits of the configuration register A is in a configuration corresponding to a time instance t. Hence, due to the entanglement generated between the clock and configuration registers, the measurement of the clock register indicates if the configuration register is in a state that comprises information about an optimal mapping.
Then, the qubits of register A can be measured in a predetermined order (step 1008) and the measured states may be stored (step 1010). Due to the probabilistic nature of quantum measurements and to obtain a reliable statistical result, the entire annealing schedule including the measurements of the clock and configuration registers may be repeated a predetermined number of epochs (step 1014).
After evaluating the measurement data of all epochs (step 1012), a reliable statistical result for the state of the system may be obtained that corresponds to a configuration for an instruction at time t. To prevent the measurements to lead to a sub optimal configuration (the state of A can be in a superposition of configurations with similar probabilities) different measuring orders for measuring clock register A may be considered (step 1016). The annealing algorithm may be executed multiple times for each of these
measurement orders (step 1120). Once the configurations corresponding to all the circuit instruction time instances have been measured for all the different measurement orders, the stored results can be processed (step 1018) to obtain a solution to the qubit allocation problem instance.
Fig. 11 depicts a flow chart of a method for computing an optimal mapping for algorithmic qubits of a quantum circuit onto physical qubits of a quantum computer using a quantum annealer according to an embodiment of the invention. Here, the quantum annealer may comprise a qubit register comprising externally controllable qubits. Further, the quantum annealer may be part of a hybrid data processing system as described with reference to Fig. 1. In a first step 1102, an initial Hamiltonian and a final Hamiltonian may be determined or received by a classical computer. Here, the initial and final Hamiltonian may comprise a first Hamiltonian term comprising first Pauli operators acting on a first set of qubits of the qubit register, wherein the first set of qubits may form a configuration register for representing mappings of the algorithmic qubits onto the physical qubits for different gate operations that need to be executed by the algorithmic qubits at different time instances as defined by the quantum circuit. Further, the initial and final Hamiltonians may comprise a second term comprising second Pauli operators acting on a second set of qubits of the qubit register, wherein the second set of qubits may form a clock register for representing the different time instances of the quantum circuit. The final Hamiltonian may further comprise a third term comprising third Pauli operators acting on the qubits of the configuration and of the clock registers for providing a penalty to a mapping that requires one or more auxiliary gate operations in addition to the set of gate operations of the quantum circuit. The classical computer may translate the Hamiltonian into control signals for controlling the qubits. These control signals may be adjusted depending on the computational problem. Encoding the computational problem into the problem Hamiltonian, as performed by the classical computing system, may include determining, from the computational problem, a configuration for the plurality of adjustable parameters.
In a further step 1104 a quantum annealing scheme may be executed using the quantum annealer, wherein the executing includes controlling the qubits of the qubit register based on the control signals to implement the initial Hamiltonian into the qubits of the quantum register and controlling the qubits to evolve the ground state of the initial Hamiltonian to the ground state of the final Hamiltonian.
Thereafter, one or more qubit states of the clock register may be measured and if the one or more measured qubit states of the clock register indicate that the entangled qubits of the clock register have collapsed to a state associated with a time instance of the quantum circuit, then one or more qubit states of the configuration register may be measured
to determine the mapping associated with the time instance of the quantum circuit (step 1106). Then, an optimal mapping for the gate operation associated with the measured time instance of the quantum circuit may be determined based on the one or more measured qubit states of the configuration register (step 1108).
Hence, the embodiments provide an annealing scheme for determining an optimal mapping of logical qubits of a quantum circuit to physical qubits of a quantum computer. The scheme uses separation of the qubit register of the annealer into a clock register comprising only information about the time variable, and an allocation register comprising information about the mapping of the set of algorithmic qubits onto the set of physical qubits. This separation makes use of the quantum phenomenon of entanglement in order to correlate physically meaningful mappings with the time ordered set of gate operations of a quantum circuit in order to solve a qubit allocation problem instance that implies a dynamical evolution of a variable or set of variables in time. Qubit allocation schemes within the quantum annealing framework in the prior art do not account for the dynamical change of the mapping between algorithmic and physical qubits in the quantum circuit, leaving out a large part of the search space, where better solutions are likely to be found. In contrast, the invention provides a solution taking into account this dynamical evolution.
The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a codec hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure,
material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims
1. A method for computing an optimal mapping for algorithmic qubits of a quantum circuit onto physical qubits of a quantum computer using a quantum annealer, the quantum annealer comprising a qubit register of controllable qubits, the method comprising: determining or receiving an initial Hamiltonian and a final Hamiltonian, the initial and final Hamiltonian comprising a first term comprising first Pauli operators acting on a first set of qubits of the qubit register, the first set of qubits forming a configuration register for representing mappings of the algorithmic qubits onto the physical qubits as defined by the quantum circuit, and a second term comprising second Pauli operators acting on a second set of qubits of the qubit register the second set of qubits forming a clock register for representing the different time instances of the quantum circuit, the final Hamiltonian further comprising a third term comprising third Pauli operators acting on the qubits of the configuration and of the clock registers for providing a penalty to a mapping that requires one or more auxiliary gate operations in addition to the set of gate operations of the quantum circuit; and, executing a quantum annealing scheme based on the initial and final Hamiltonian using the quantum annealer determining an optimal mapping, wherein the executing includes:
 controlling the qubits of the qubit register to implement the initial Hamiltonian and controlling the qubits to evolve the ground state of the initial Hamiltonian to the ground state of the final Hamiltonian;
 measuring one or more qubit states of the clock register and if the one or more measured qubit states of the clock register indicate that the entangled qubits of the clock register have collapsed to a state associated with a time instance of the quantum circuit, then measuring one or more qubit states of the configuration register to determine the mapping of algorithmic qubits onto the physical qubits associated with the time instance of the quantum circuit; and,
 determining an optimal qubit mapping for the one or more gate operations associated with the time instance of the quantum circuit based on the one or more measured qubit states of the configuration register.
2. Method according to claim 1 wherein each qubit of the clock register is associated to a time instance of the quantum circuit.
3. Method according to claims 1 or 2 wherein the final Hamiltonian further
comprises a fourth term comprising Pauli operators acting on the qubits of the clock register for introducing a bias towards the initial or final time instance of the quantum circuit so that the optimal mapping is the optimal mapping associated with one or more gate operations of the quantum circuit that need to be executed at the initial or final time instance of the quantum circuit respectively.
4. Method according to any of claims 13 wherein the physical qubits are associated with a hardware connectivity and wherein the one or more auxiliary gate operations allow the algorithmic qubits to have a connectivity that matches the hardware connectivity of the physical qubits.
5. Method according to any of claims 14, wherein the set of gate operations and the one or more auxiliary gate operations form a transformed quantum circuit, the optimal mapping corresponding to a transformed quantum circuit with a low cost in terms of depth and/or error rate per gate operation.
6. Method according to any of claims 15, wherein the one or more auxiliary operations include one or more SWAP gates and/or one or more bridge gates, and wherein the second term of the final Hamiltonian includes a first term for implementing one or more SWAP transformations and a second term for implementing one or more bridge transformations.
7. Method according to any of claims 16 wherein measuring one or more qubit states of the clock register further includes: measuring the qubits of the clock register in a reverse time order starting from a qubit of the clock register representing a final time instance.
8. Method according to any of claims 17 wherein the second Pauli operators acting on the qubits of the clock register are configured to provide a penalty term for states not belonging to the clock register space.
9. Method according to any of claims 18 wherein the first Pauli operators acting on qubits of the configuration register are configured to restrict the qubit mappings such that: a physical qubit of the configuration register can only have one associated algorithmic qubit;
 the configuration register has a total of N_{v} occupied physical qubits wherein N_{v} is the number of algorithmic (virtual) qubits, and,
 each algorithmic qubit is allocated to a physical qubit of the configuration register once per time instance.
10. Method according to any of claims 19 wherein the first Pauli operators acting on qubits of the configuration register are configured to restrict the configuration register to mappings that are physically accessible in the quantum processor, preferably based on an adjacency matrix D_{a}p associated with the hardware graph of the quantum processor.
11. Method according to any of claims 110 wherein the initial Hamiltonian includes a second term comprising Pauli operators acting on the qubits of the clock register for initialization of the clock register.
12. Method according to any of claims 111 wherein the executing a quantum annealing scheme further comprises: preparing the ground state of the initial Hamiltonian based on a further annealing scheme, the further annealing scheme including: controlling the qubits of the quantum register into a standard Hamiltonian, preferably an Isingtype Hamiltonian having a ground state which can be prepared experimentally; and, controlling the qubits of the quantum register to evolve from a ground state of the standard Hamiltonian to a ground state of the initial Hamiltonian.
13. Method according to any of claims 112, wherein the method further includes: constructing a new final Hamiltonian based on the final Hamiltonian and a Hamiltonian term describing the optimal mapping solution at the previously computed time instance; and, executing the quantum annealing scheme based on the initial and the new final Hamiltonian to determine an optimal mapping for the algorithmic qubits associated with a time instance that precedes the time instance of the quantum circuit associated with the previously computed mapping.
14. A system for allocating qubits, using a data processing system comprising a classical computer system and a quantum computer system, wherein the system is configured to: determining or receiving an initial Hamiltonian and a final Hamiltonian, the initial and final Hamiltonian comprising a first term comprising first Pauli operators acting on a first set of qubits of the qubit register, the first set of qubits forming a configuration register for representing mappings of the algorithmic qubits onto the physical qubits as defined by the quantum circuit, and a second term comprising second Pauli operators acting on a second set of qubits of the qubit register the second set of qubits forming a clock register for representing the different time instances of the quantum circuit, the final Hamiltonian further comprising a third term comprising third Pauli operators acting on the qubits of the configuration and of the clock registers for providing a penalty to a mapping that requires one or more auxiliary gate operations in addition to the set of gate operations of the quantum circuit; and, executing a quantum annealing scheme based on the initial and final Hamiltonian using the quantum annealer determining an optimal mapping, wherein the executing includes:
 controlling the qubits of the qubit register to implement the initial Hamiltonian and controlling the qubits to evolve the ground state of the initial Hamiltonian to the ground state of the final Hamiltonian;
 measuring one or more qubit states of the clock register and if the one or more measured qubit states of the clock register indicate that the entangled qubits of the qubit register have collapsed to a state associated with a time instance of the quantum circuit, then measuring one or more qubit states of the configuration register to determine the mapping of one or more gate operations associated with the time instance of the quantum circuit; and,
 determining an optimal qubit mapping for the one or more gate operations associated with the time instance of the quantum circuit based on the one or more measured qubit states of the configuration register.
15. A computer program or suite of computer programs comprising at least one software code portion or a computer program product storing at least one software code portion, the software code portion, when run on a classical computer system wherein the classical computer is part of a data processing system comprising the classical computer system connected to a quantum computer system, being configured for executing the method steps according any of claims 113.
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