WO2023179850A1 - Module d'égalisation pour un récepteur numérique - Google Patents

Module d'égalisation pour un récepteur numérique Download PDF

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Publication number
WO2023179850A1
WO2023179850A1 PCT/EP2022/057594 EP2022057594W WO2023179850A1 WO 2023179850 A1 WO2023179850 A1 WO 2023179850A1 EP 2022057594 W EP2022057594 W EP 2022057594W WO 2023179850 A1 WO2023179850 A1 WO 2023179850A1
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llrs
block
symbol
siso
llr
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PCT/EP2022/057594
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English (en)
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Nebojsa Stojanovic
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Huawei Technologies Co., Ltd.
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Priority to PCT/EP2022/057594 priority Critical patent/WO2023179850A1/fr
Publication of WO2023179850A1 publication Critical patent/WO2023179850A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03312—Arrangements specific to the provision of output signals
    • H04L25/03318—Provision of soft decisions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H04L25/03076—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure not using decision feedback
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0055—MAP-decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03254—Operation with other circuitry for removing intersymbol interference

Definitions

  • the disclosure relates to receivers, more particularly, the disclosure relates to an equalisation module for a digital receiver, the digital receiver, and a method of equalisation for the digital receiver.
  • Receivers are mostly used in communication systems in terms of networking and cellular communication, that receives and decodes signals and conditions or transforms the signals into another signal that another machine understands. Most of the communication systems are based on pulse-amplitude modulation, PAM or quadrature amplitude modulation, QAM.
  • PAM-n modulation formats include PAM-2 and PAM-4 that are cheap low-complexity non-coherent optical systems, that cover distances up to 100 kms, where n-QAM modulation formats, utilized in more expensive coherent systems, including 4-QAM, 16-QAM, and 32-QAM, that cover much longer distances. Forecasted traffic demands in near future, and require high-bandwidth low-noise optical and electrical components and high-order modulation formats, that are very sensitive to any transmission impairments.
  • Bandwidth-limited systems use advanced digital signal processing, DSP to minimize the requirements on component bandwidth. Further, intensity-modulation direct-detection, IMDD optical systems suffer from chromatic dispersion, CD that limits transmission distance. Compensating frequency deeps caused by the CD is to use maximum likelihood sequence estimation, MLSE based on Viterbi algorithm, VA that outputs hard information. Normally, many communication channels have extremely irregular transfer characteristics and the MLSE is the only way to reconstruct the transmitted data. Sometimes, enhanced forward-error correction, FEC code based on soft input placed after MLSE is necessary for reconstructing the transmitted data. The MLSE must be modified to output soft information for soft FEC, SFEC. Soft-input soft-output, SISO algorithms, and blocks are designed to any of equalize, restore, improve, or correct the received signal and to provide high-quality soft information for the next SISO block.
  • FIG. 1A illustrates a block diagram of a receiver 100 in accordance with the prior art.
  • the receiver 100 includes an analog-to-digital converter, ADC 102, a voltage-controlled oscillator, VCO 104, a timing recovery, TR block 106, a first SISO block 108, and a second SISO block 110.
  • the analog-to-digital converter, ADC 102 quantizes a received signal x, which can be complex and multidimensional. For example, in coherent optical systems, four ADCs are used to quantize complex signals from two polarizations.
  • the ADC 102 may provide samples at a baud rate i.e. at Isps sampling (one sample per symbol), to save power, and a DSP block may rely on this information.
  • a local oscillator i.e. the VCO 104
  • the first SISO block 108 generates a log-likelihood ratio, Hr for the second SISO block 110.
  • the second SISO block 110 also generates Hr values and feedback them to the first SISO block 108. After a few iterations between the first SISO block 106 and the second SISO block 110, the second SISO block 110 delivers decoded bits.
  • FIG. IB illustrates a block diagram of the receiver 100 for bandwidth-limited systems in accordance with the prior art.
  • the receiver 100 includes the analog-to-digital converter, ADC 102, the voltage-controlled oscillator, VCO 104, the timing recovery, TR block 106, the first SISO block 108, and the second SISO block 110.
  • the first SISO block 108 includes a feedforward equalisation, FFE 112, a post-filter, PF 114, and a signal memory decoder 116.
  • the receiver 100 receives the signal x, which for the bandwidth-limited systems, Rx signal is first equalized by the FFE 112. Output of the FFE 112 suffers from noise amplification that can be handled by the PF 114.
  • the PF 114 is a linear filter transforming the FFE output to a partial response signal.
  • MLSE or any algorithm deals with the signal memory decoder 116, and outputs soft-FEC signal from the first SISO block 108.
  • 2-state binary trellis may calculate state probabilities by applying forward and backward recursions, and enables adding branch probabilities to the state probabilities to enable Hr calculation. These calculations may include simplifications with predecisions, and other trellises reducing techniques, which will affect performance.
  • the disclosure provides an equalisation module for a digital receiver, the digital receiver and a method of equalisation for the digital receiver.
  • an equalisation module for a digital receiver.
  • the equalisation module includes a first soft-input soft-output, SISO, block, a log-likelihood ratio, LLR, reconstructor, a LLR equaliser, llrE, a LLR converter, and a second SISO block.
  • the first soft-input soft-output, SISO, block is configured to calculate one or more symbol LLRs for each symbol in a received sequence of symbols.
  • the LLR reconstructor is configured to reconstruct a signal constellation based on the one or more symbol LLRs.
  • the LLR equaliser, llrE is configured to generate improved LLRs based on the one or more symbol LLRs.
  • the LLR converter is configured to generate one or more bit LLRs based on the one or more symbol LLRs and the reconstructed signal constellation, and provide the one or more bit LLRs to the second SISO block.
  • the second SISO block is configured to decode one or more output bits based on the one or more bit LLRs.
  • the equalisation module improves a quality of the LLR if the quality of the LLR is weak.
  • the equalisation module can be used in digital transmission systems supported by advanced DSP for data recovery.
  • the advanced DSP includes an array of equalizers and SISO blocks that can exchange information.
  • the equalisation module improves soft information before the second SISO block and performance in receivers including SISO blocks.
  • the equalisation module can be applied to any modulation format and works with any detection schemes.
  • the equalisation module architecture can be used in simplified trellis-based equalisers using M algorithm or trellis search supported by pre-decisions.
  • the equalisation module improves the performance in cascaded SISO receivers.
  • the LLR reconstructor requires only mean values and simple logical circuits.
  • LLR converter utilizes pdf shape to improve performance that is forbidden in large trellis-based equalisers dur to enormous complexity.
  • the LLR equalizer, llrE complexity is negligible compared to total DSP complexity and can dramatically save the DSP power consumption.
  • the LLR equaliser, llrE improves the LLRs and enhances a performance of the second SISO block.
  • the first SISO block calculates the one or more symbol LLRs using a Bahl, Cocke, Jelinek, and Raviv, BCJR, algorithm.
  • the first SISO block calculates the one or more symbol LLRs using a BCJR simplification selected from Log- maximum posteriori probability, Log-MAP, MaxLogMAP, or Soft-Output Viterbi algorithm, SOVA.
  • the equalisation module can be applied in systems using BCJR/SOVA/MLP equalizers and soft FEC codes, and can be easily modified to be used in iterative turbo demodulation receivers.
  • the equalisation module further includes an equaliser block including a feed forward equaliser, FFE, and a post filter, PF.
  • the equaliser block is configured to provide the received sequence of symbols to the first SISO block.
  • the FFE is an 11 -tap linear FFE
  • the PF is a linear filter utilising any of a maximum likelihood sequence estimation, MLSE, algorithm, the soft-output Viterbi algorithm, SOVA, or BCJR restore signal.
  • the received sequence of symbols is pulse amplitude modulated or quadrature amplitude modulated.
  • a digital receiver includes an analog-to-digital converter, ADC, a voltage-controlled oscillator, VCO, a timing recovery, TR, block, and an equalisation module.
  • the analog-to-digital converter, ADC is configured to receive and quantise an input signal.
  • the voltage-controlled oscillator, VCO is configured to provide a sampling clock to the ADC.
  • the timing recovery, TR, block is configured to lock the VCO frequency to a data clock frequency.
  • the equalisation module in the digital receiver improves a quality of the LLR if the quality of the LLR is weak.
  • the equalisation module can be used in digital transmission systems supported by advanced DSP for data recovery.
  • the advanced DSP consists of an array of equalizers and SISO blocks that can exchange information.
  • the equalisation module improves soft information before a second SISO block.
  • the equalisation module can be applied to any modulation format and works with any detection schemes.
  • the equalisation module architecture can be used in simplified trellis-based equalisers using a M algorithm or trellis search supported by pre-decisions.
  • a block of a maximum likelihood sequence estimation, MLSE may be directly used after the ADC to enable best performance at a price of high complexity.
  • a method of equalisation for a digital receiver includes calculating one or more symbol log-likelihood ratios, LLRs, for each symbol in a received sequence of symbols in a first soft-input soft-output, SISO, block.
  • the method includes reconstructing a signal constellation based on the one or more symbol LLRs.
  • the method includes generating one or more improved LLRs based on the one or more symbol LLRs.
  • the method includes generating one or more bit LLRs based on the one or more symbol LLRs and the reconstructed signal constellation, and providing the one or more bit LLRs to a second SISO block.
  • the method includes decoding one or more output bits based on the one or more bit LLRs in the second SISO block.
  • This method improves a quality of the LLR if the quality of the LLR is weak.
  • This method can be used in digital transmission systems supported by advanced DSP for data recovery.
  • the advanced DSP consists of an array of equalizers and SISO blocks that can exchange information.
  • This method improves soft information before the second SISO block, and performance in receivers including SISO blocks.
  • This method can be applied to any modulation format and works with any detection schemes.
  • This method architecture can be used in simplified trellis-based equalisers using a M algorithm or trellis search supported by predecisions. This method improves the performance in cascaded SISO receivers.
  • the first SISO block calculates the one or more symbol LLRs using a Bahl, Cocke, Jelinek and Raviv, BCJR, algorithm.
  • the first SISO block calculates the one or more symbol LLRs using a BCJR simplification selected from Log-MAP, MaxLogMAP, or SOVA. This method can be applied in systems using BCJR/SOVA/MLP equalizers and soft FEC codes, and can be easily modified to be used in iterative turbo demodulation receivers.
  • the received sequence of symbols is pulse amplitude modulated or quadrature amplitude modulated. Therefore, in contradistinction to the prior art, according to the equalisation module for the digital receiver, the digital receiver and the method of equalisation for the digital receiver, improve the soft information, and the performance of the digital receiver.
  • the equalisation module, the digital receiver, and the method also improve the quality of the LLR if the quality of the LLR is weak and can be applied on any modulation formats and works with any detection schemes.
  • FIG. 1 A illustrates a block diagram of a receiver in accordance with the prior art
  • FIG. IB illustrates a block diagram of a receiver for bandwidth-limited systems in accordance with the prior art
  • FIG. 2 is a block diagram of an equalisation module for a digital receiver in accordance with an implementation of the disclosure
  • FIG. 3 illustrates a block diagram of a digital receiver in accordance with an implementation of the disclosure
  • FIG. 4 A illustrates a schematic diagram of 1 -symbol memory PAM4 trellis in accordance with an implementation of the disclosure
  • FIG. 4B illustrates a graphical representation of LLR histograms after trellis processing in accordance with an implementation of the disclosure
  • FIG. 4C illustrates a graphical representation of a reconstructed PAM4 constellation in accordance with an implementation of the disclosure
  • FIG. 4D illustrate graphical representations of an equalized PAM4 constellation in accordance with an implementation of the disclosure
  • FIG. 4E illustrates a graphical representation of results of a LLR converter in accordance with an implementation of the disclosure
  • FIG. 4F illustrates a graphical representation of output histograms of a LLR converter in accordance with an implementation of the disclosure
  • FIGS. 5A-5E illustrate graphical representations of experimental results of an equalisation module in accordance with an implementation of the disclosure.
  • FIGS. 6A-6B are flow diagrams that illustrate a method of equalisation for a digital receiver in accordance with an implementation of the disclosure.
  • Implementations of the disclosure provide an equalisation module for a digital receiver, that improves soft information in output signals, and performance of the digital receiver.
  • the disclosure also provides the digital receiver and a method of equalisation for the digital receiver that improves the soft information in the output signals, and the performance of the digital receiver.
  • FIG. 2 is a block diagram of an equalisation module 204 for a digital receiver 202 in accordance with an implementation of the disclosure.
  • the equalisation module 204 includes a first soft- input soft-output, SISO, block 206, a log-likelihood ratio, LLR, reconstructor 208, a LLR equaliser, llrE 210, a LLR converter 212, and a second SISO block 214.
  • the first soft-input soft-output, SISO, block 206 is configured to calculate one or more symbol LLRs for each symbol in a received sequence of symbols.
  • the LLR reconstructor 208 is configured to reconstruct a signal constellation based on the one or more symbol LLRs.
  • the LLR equaliser, llrE 210 is configured to generate improved LLRs based on the one or more symbol LLRs.
  • the LLR converter 212 is configured to generate one or more bit LLRs based on the one or more symbol LLRs and the reconstructed signal constellation, and provide the one or more bit LLRs to the second SISO block 214.
  • the second SISO block 214 is configured to decode one or more output bits based on the one or more bit LLRs.
  • the equalisation module 204 improves a quality of the LLR if the quality of the LLR is weak.
  • the equalisation module 204 can be used in digital transmission systems supported by advanced DSP for data recovery.
  • the advanced DSP consists of an array of equalizers and SISO blocks that can exchange information.
  • the equalisation module 204 improves soft information before the second SISO block 214 and performance in receivers including SISO blocks.
  • the equalisation module 204 can be applied to any modulation format and works with any detection scheme.
  • the equalisation module 204 architecture can be used in simplified trellis-based equalisers using a M algorithm or trellis search supported by pre-decisions.
  • the equalisation module 204 improves the performance in cascaded SISO receivers.
  • the LLR reconstructor 208 requires only mean values and simple logical circuits.
  • LLR converter utilizes pdf shape to improve performance that is forbidden in large trellis-based equalisers dur to enormous complexity.
  • the LLR equalizer, llrE 210 complexity is negligible compared to total DSP complexity and can dramatically save the DSP power consumption.
  • the LLR equaliser, llrE 210 improves the LLRs and enhances a performance the second SISO block 214
  • the equalisation module 204 recovers signal suffering from noise and intersymbol interference, 1ST
  • the equalisation module 204 may be a linear feed forward equalizer, FFE, or a nonlinear FFE, followed by decision feedback equaliser, DFE, or maximum likelihood sequence estimation, MLSE.
  • the equalisation module 204 is a Volterra filter.
  • the first SISO block 206 processes soft input information and provides soft output information, i.e. the log- likelihood ratio, LLR with the equalisation module 204.
  • the LLR may be a posteriory probability L value.
  • the first SISO block 206 calculates the one or more symbol LLRs using a Bahl, Cocke, Jelinek and Raviv, BCJR, algorithm.
  • the first SISO block 206 calculates the one or more symbol LLRs using a BCJR simplification selected from Log- maximum posteriori probability, Log-MAP, MaxLogMAP, or a Soft-Output Viterbi algorithm, SOVA.
  • the equalisation module 204 can be applied in systems using BCJR/SOVA/MLP equalizers and soft FEC codes, and can be easily modified to be used in iterative turbo demodulation receivers.
  • the BCJR algorithm is the MAP algorithm that provides soft information in the first SISO block 206.
  • the MLSE may be modified to include features of the BCJR.
  • the LLR reconstructor 208 is configured to reconstruct the signal constellation with the one or more symbol LLRs, which enables constellation visualization.
  • the signal constellation can be used in measurement equipment.
  • the LLR equaliser, llrE 210 is configured to equalize the reconstructed signal constellation.
  • the LLR reconstructor 208 can reconstruct the signal constellation for multilevel signals.
  • the LLR equaliser, llrE 210 may equalize the reconstructed multilevel signal constellation.
  • the LLR reconstructor 208, the LLR equaliser, llrE 210, the LLR converter 212 may provide soft information to the second SISO block 214.
  • the soft information is the one or more bit LLRs.
  • the LLR converter 212 may generate one or more improved bit LLRs and transmit to the second SISO block 214.
  • the soft information may feedback soft output information to proceeding blocks.
  • the proceeding blocks are a turbo equalization.
  • the second SISO block 214 may use a soft forward error correction to decode the one or more output bits.
  • the first SISO block 206 and the second SISO block 214 can be an equaliser, FEC, or a demapper.
  • LLR equalization can be done using the equalisation module 204 with the LLR reconstructor 208, the LLR equaliser, llrE 210, the LLR converter 212 for modulation formats.
  • the modulation formats are simple, the LLR reconstructor 208, and the LLR converter 212 may not be required for the LLR equalisation.
  • the modulation format is a PAM2
  • the LLR reconstructor 208, and the LLR converter 212 are not required for the LLR equalisation.
  • binary LLRs may not be used.
  • the modulation format can be QAM, or PSK formats, that enables treating of each dimension separately.
  • the equalisation module 204 further includes an equaliser block including a feed forward equaliser, FFE, and a post filter, PF.
  • the equaliser block is configured to provide the received sequence of symbols to the first SISO block 206.
  • the FFE is an 11 -tap linear FFE
  • the PF is a linear filter utilising any of a maximum likelihood sequence estimation, MLSE, algorithm, the soft-output Viterbi algorithm, SOVA, or BCJR restore signal.
  • the FFE may be any equaliser including DFE.
  • Output of the PF may be processed by the first SISO block 206.
  • the received sequence of symbols is pulse amplitude modulated or quadrature amplitude modulated.
  • FIG. 3 illustrates a block diagram of a digital receiver 302 in accordance with an implementation of the disclosure.
  • the digital receiver 302 includes an analog-to-digital converter, ADC 304, a voltage-controlled oscillator, VCO 306, a timing recovery, TR, block 308, and an equalisation module 310.
  • the analog-to-digital converter, ADC 304 is configured to receive and quantise an input signal.
  • the voltage-controlled oscillator, VCO 306 is configured to provide a sampling clock to the ADC 304.
  • the timing recovery, TR, block 308 is configured to lock the VCO frequency to a data clock frequency.
  • the equalisation module 310 in the digital receiver 302 improves a quality of the LLR if the quality of the LLR is weak.
  • the equalisation module 310 can be used in digital transmission systems supported by advanced DSP for data recovery.
  • the advanced DSP consists of an array of equalizers and SISO blocks that can exchange information.
  • the equalisation module 310 improves soft information before a second SISO block.
  • the equalisation module 310 can be applied to any modulation format and works with any detection schemes.
  • the equalisation module 310 architecture can be used in simplified trellis-based equalisers using a M algorithm or trellis search supported by pre-decisions.
  • FIG. 4A illustrates a schematic diagram of 1 -symbol memory PAM4 trellis 400 in accordance with an implementation of the disclosure.
  • the 1 -symbol memory PAM4 trellis 400 includes one or more states 402A-N, and one or more branches for calculating symbol log-likelihood ratios, LLRs.
  • the one or more branches enters each of the one or more states 402A-N and leaves each of the one or more states 402A-N that defines the LLRs.
  • New Bahl, Cocke, Jelinek and Raviv, BCJR LLRs may be defined as an equation as follows,
  • the above equation may define LLRs for any trellis and any modulation formats.
  • ISI channels include a very large number of states.
  • FIG. 4B illustrates a graphical representation 406 of LLR histograms after trellis processing in accordance with an implementation of the disclosure.
  • the graphical representation 406 shows the llrD in an X-axis and counters in a Y-axis.
  • the graphical representation 406 includes 3 different histograms, where each histogram is similar to a binary noisy histogram.
  • positions with the highest counter values can be defined on both sides.
  • the positions of highest counter values may be denoted by p(k,0) and p(k,l) that may be derived after a long channel estimation time and by using mean value estimation techniques.
  • multidimensional equalisation can be considered for reconstructing PAM constellation.
  • a suboptimum reconstruction procedure may be done separately on two dimensions.
  • Reconstructing PAM constellation includes five steps.
  • llr(m,t) represents Hr of symbol m at position t.
  • the first step for reconstructing PAM constellation includes sorting of all the LLRs. For example, consider llr(l,t) ⁇ llr(2,t) ⁇ llr(0,t) ⁇ llr(3,t). Sorting matrix s includes values 1, 2, 0, 3 in column t.
  • Setting x(t m ) llr(m, t m )-llr(m+l, t m ).
  • the fifth step for reconstructing PAM constellation includes adding Z(m) for all x at positions tm-
  • FIG. 4C illustrates a graphical representation 408 of the reconstructed PAM4 constellation in accordance with an implementation of the disclosure.
  • the reconstructed PAM4 constellation may be affected by different noise statistics depending on PAM levels.
  • FIG. 4D illustrates graphical representations 410, 412 of equalized PAM4 constellation in accordance with an implementation of the disclosure.
  • the graphical representation 410 depicts the equalized PAM4 constellation for MLP.
  • the graphical representation 412 depicts the equalized PAM4 constellation for BCJR.
  • the graphical representations 410, 412 show the improved constellations that result in lower symbol/bit rate and higher natural generalized mutual information, NGMI. Following table shows improvements on the NGMI and Eb/NO.
  • the equalized PAM4 constellation uses a 11-tap linear filter to equalize the LLRs.
  • LLR converter generates the one or more bits LLRs by using PAM4 constellation for the equalized PAM4 constellation.
  • Mean values and standard deviations, and approximate equivalent noise statistics by Gaussian one may be calculated with the reconstructed PAM4 constellation.
  • the gray labels are 00, 01, 11, 10.
  • PAM4 llrs are MSB(x): log(max(pdf(x,3), pdf(x,3)))- log(max(pdf(x,l), pdf(x,2))), and LSB(x): log(max(pdf(x,l), pdf(x,4)))-log(max(pdf(x,2), pdf(x,3))).
  • For Gaussian pdf values above the value Q obtain pdf from histograms and the rest obtain Gaussian pdf, which is hybrid pdf Hr, HLLR.
  • FIG. 4E illustrates a graphical representation 414 of results of the LLR converter in accordance with an implementation of the disclosure.
  • the graphical representation 414 includes x value on an X-axis and pdf values on a Y-axis for one or more converter results curves.
  • the one or more converter results curves include a Gaussian curve, a histogram curve, and a hybrid curve.
  • a Gaussian pdf Hr, GLLR may follow Gaussian distribution while hybrid pdf Hr, HLLR combine histograms-based pdf and Gaussian pdf.
  • the HLLR performance may be slightly better and requires a complicated LLR converter.
  • FIG. 4F illustrates a graphical representation 416 of output histograms of the LLR converter in accordance with an implementation of the disclosure.
  • the graphical representation 416 includes LLR on an X-axis and counters on a Y-axis for output histograms of BCJR and EBCJR.
  • the graphical representation clearly recognizes 2-level BCJR LLRs while EBCJR LLRs are irregular that affects soft FEC performance.
  • the LLR converter outputs may be clipped to improve performance.
  • the clipping level depends on soft FEC decoding algorithm. The clipping may be done at 10 for the graphical representation 416.
  • FIGS. 5A-5E illustrate graphical representations of experimental results of an equalisation module in accordance with an implementation of the disclosure.
  • FIG. 5A depict graphical representations 502, 504 of experimental results of BER improvement with the equalisation module.
  • the graphical representation 502 shows experimental results of BER improvement using Mach-Zehnder modulator, MZM in C band, CMZM for 112GB PAM4.
  • the graphical representation 502 includes Pin in dBm in an X-axis, and BER in a Y-axis for FFE, MLP, BCJR, EMLP, and EBCJR.
  • the graphical representation 504 shows experimental results of BER improvement using electro-absorption modulated laser, EML in O band, OEML for the 112GB PAM4.
  • the graphical representation 504 includes Pin in dBm in an X-axis, and BER in a Y-axis for FFE, MLP, BCJR, EMLP, and EBCJR.
  • the BCJR performs a bit better than the MLP, and LLR equaliser improves performance in any scenario.
  • FIG. 5B depicts graphical representations 506, 508 of experimental results of sensitivity gain with the equalisation module.
  • the graphical representation 506 shows experimental results of the sensitivity gain with the BER improvements.
  • the graphical representation 506 includes input power, Pin in dBm in an X-axis, and Pin gain in dB in a Y-axis for CMZM EMLP, CMZM EBCJR, OEML EMLP, AND OEML EBCJR.
  • the sensitivity gain is around 0.4dB at low input power values.
  • the graphical representation 508 shows experimental results of mutual information, MI gain with the BER improvements.
  • the graphical representation 508 includes Pin in dBm in an X-axis, and Pin gain in dB in a Y-axis for CMZM EMLP, CMZM EBCJR, OEML EMLP, AND OEML EBCJR. Results in the MI gain can be converted into the sensitivity gain, which indicates effectiveness of the equalisation module with an average gain of 0.2dB.
  • FIG. 5C depicts a graphical representation 510 of experimental results of OOK performance.
  • the graphical representation 510 includes optical signal-to-noise ratio, OSNR in dB in an X- axis, and BER in a Y-axis for one or more curves.
  • the experimental results are with 60Gbits/s OOK signal.
  • DSP uses Isps diagonal nonlinear Volterra filter VF where linear taps were varied from 25 to 45 in step of 5 and second order Volterra filter includes 0 or 5 symbols, 2-tap PF (1+ aD) and 2-state MLSE/SOVA.
  • Diagonal VF uses only x A 2 taps. FFE BER are above le-2, thereby improving performance in all cases.
  • FIG. 5D depicts a graphical representation 512 of DSP complexity reduction in OOK performance.
  • the graphical representation 512 includes OSNR in dB in an X-axis, and BER in a Y-axis for one or more curves for complexity reduction in the OOK performance.
  • 45-tap linear FFE performance is similar or worse than linear 25-tap FFE with 2-tap Hr FFR.
  • a 2-tap Hr FFE includes one multiplier that save multiplications.
  • the multiple may save upto 14 multiplications.
  • LLR equalizer output may be adjusted by adding some de value, thereby resulting in gain.
  • FIG. 5E depicts a graphical representation 514 of OSNR gain in OOK performance.
  • the graphical representation 514 includes OSNR in dB in an X-axis, and OSNR gain in dB in a Y- axis for one or more curves for calculating the Hr FFE gain at different OSNR values.
  • the Hr FFE gain starts from 0.5dB and may be greater than IdB for the linear FFE.
  • the OOK performance may use nonlinear Volterra filter that squeezed more from received samples, which results in smaller gain that starts from 0.3dB and goes up to 0.8dB.
  • FIGS. 6A-6B are flow diagrams that illustrate a method of equalisation for a digital receiver in accordance with an implementation of the disclosure.
  • one or more symbol loglikelihood ratios, LLRs, for each symbol in a received sequence of symbols are calculated in a first soft-input soft-output, SISO, block.
  • SISO soft-input soft-output
  • a signal constellation is reconstructed based on the one or more symbol LLRs.
  • one or more improved LLRs are generated based on the one or more symbol LLRs.
  • one or more bit LLRs are generated based on the one or more symbol LLRs and the reconstructed signal constellation, and the one or more bit LLRs are provided to a second SISO block.
  • one or more output bits are decoded based on the one or more bit LLRs in the second SISO block.
  • This method improves a quality of the LLR if the quality of the LLR is weak.
  • This method can be used in digital transmission systems supported by advanced DSP for data recovery.
  • the advanced DSP includes an array of equalizers and SISO blocks that can exchange information.
  • This method improves soft information before the second SISO block, and performance in receivers including SISO blocks.
  • This method can be applied to any modulation format and works with any detection schemes.
  • This method architecture can be used in simplified trellisbased equalisers using a M algorithm or trellis search supported by pre-decisions. This method improves the performance in cascaded SISO receivers.
  • the first SISO block calculates the one or more symbol LLRs using a Bahl, Cocke, Jelinek and Raviv, BCJR, algorithm.
  • the first SISO block calculates the one or more symbol LLRs using a BCJR simplification selected from Log-MAP, MaxLogMAP, or SOVA. This method can be applicable in systems using BCJR/SOVA/MLP equalizers and soft FEC codes, and can be easily modifies to be used in iterative turbo demodulation receivers.
  • the received sequence of symbols is pulse amplitude modulated or quadrature amplitude modulated.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

L'invention concerne un module d'égalisation (204) pour un récepteur numérique (202), comprenant un premier bloc à entrées et à sorties logicielles, SISO, (206), un rapport de vraisemblance logarithmique, LLR, un reconstructeur (208), un dispositif de réégalisation LL, llrE (210), un convertisseur LLR (212), et un second bloc SISO (214). Le premier bloc SISO étant configuré pour calculer un ou plusieurs LLR de symbole pour chaque symbole dans une séquence de symboles reçue. Le reconstructeur LLR étant configuré pour reconstruire une constellation de signaux sur la base du ou des LLR de symbole. Le llrE étant configuré pour générer des LLR améliorés sur la base d'un ou de plusieurs LLR de symbole. Le convertisseur LLR étant configuré pour générer une ou plusieurs rafales de bits sur la base du ou des LLR de symbole et de la constellation de signaux reconstruits, et fournir un ou plusieurs LLR de bits au second bloc SISO. Le second bloc SISO étant configuré pour décoder un ou plusieurs bits de sortie sur la base du ou des LLR de bits.
PCT/EP2022/057594 2022-03-23 2022-03-23 Module d'égalisation pour un récepteur numérique WO2023179850A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120216093A1 (en) * 2011-02-22 2012-08-23 Nec Laboratories America, Inc. Soft-decision non-binary ldpc coding for ultra-long-haul optical transoceanic transmissions
WO2021243607A1 (fr) * 2020-06-03 2021-12-09 Huawei Technologies Co., Ltd. Procédé et appareil d'égalisation

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US20120216093A1 (en) * 2011-02-22 2012-08-23 Nec Laboratories America, Inc. Soft-decision non-binary ldpc coding for ultra-long-haul optical transoceanic transmissions
WO2021243607A1 (fr) * 2020-06-03 2021-12-09 Huawei Technologies Co., Ltd. Procédé et appareil d'égalisation

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LIU SHUANGYUE ET AL: "Simplified Soft-Output Direct Detection FTN Algorithm for 56-Gb/S Optical PAM-4 System Using 10G-Class Optics", IEEE ACCESS, IEEE, USA, vol. 8, 2 June 2020 (2020-06-02), pages 104518 - 104526, XP011792417, DOI: 10.1109/ACCESS.2020.2999346 *

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