WO2023178859A1

WO2023178859A1 - Dma data transfer method and device

Info

Publication number: WO2023178859A1
Application number: PCT/CN2022/100634
Authority: WO
Inventors: 马成勇; 秦旋; 袁峰
Original assignee: 奥比中光科技集团股份有限公司
Priority date: 2022-03-21
Filing date: 2022-06-23
Publication date: 2023-09-28
Also published as: CN114756490A

Abstract

The present application is suitable for the technical field of computers, and provides a DMA data transfer method and device. The data transfer method is applied to a DMA controller, and comprises: obtaining a read instruction set, wherein the read instruction set comprises first configuration information, and the first configuration information comprises first discrete address information and first continuous address information; and according to the first configuration information in the read instruction set, transferring, to a continuous address range corresponding to the first continuous address information, data within a discrete address range corresponding to the first discrete address information. According to embodiments of the present application, a DMA data transfer operation is controlled by means of the instruction set, and normal work of a CPU would not be affected by DMA interruption during DMA data transfer.

Description

A DMA data transfer method and device

This application claims priority to the Chinese patent application submitted to the China Patent Office on March 21, 2022, with the application number 202210276686.1 and the invention title "A DMA data transfer method and device", the entire content of which is incorporated into this application by reference. middle.

Technical field

This application belongs to the field of computer technology, and in particular relates to a direct memory access (Direct Memory Access, DMA) data transfer method and device.

Background technique

DMA transfer refers to copying data from one address space to another address space. DMA transfer occupies an important position in fields such as high-performance embedded system algorithms and networks. In the existing technology, DMA can only move data in a certain address area to another address area. For example, data in the address range [a, b] can be moved to the address range [h, j], where "within the address range [a, b]" can be understood as the distance between location a and location b within the memory. space area.

However, when data in multiple discrete address ranges needs to be moved to a continuous address range, multiple DMA transfer operations need to be initiated, such as moving the address ranges to [a1,b1], [a2,b2], When the data in [a3, b3] is transferred to the [h, j] address range in sequence, DMA needs to initiate three transfer operations. Similarly, if you want to transfer the data in the address range [a, b] to three discrete address ranges [h1, j1], [h2, j2], [h3, j3] in sequence, you also need to initiate three transfers by DMA. operate.

It can be seen that in related technologies, when the above data transfer requirements exist, DMA needs to perform multiple operations to complete the transfer of all data. This will frequently generate DMA interrupts, affecting the central processing unit (Centre Processor Unit, CPU) or other co-processors to assist the CPU in completing processing tasks that it cannot perform or performs inefficiently and ineffectively.

Contents of the invention

In view of this, embodiments of the present application provide a DMA data transfer method and device, which can solve one or more technical problems in related technologies.

In a first aspect, an embodiment of the present application provides a DMA data transfer method, which is applied to a DMA controller. The DMA data transfer method includes: obtaining a read instruction set, the read instruction set includes first configuration information, and the The first configuration information includes first discrete address information and first continuous address information; according to the first configuration information in the read instruction set, the data in the discrete address range corresponding to the first discrete address information is transported to the within the continuous address range corresponding to the first continuous address information.

In the second aspect, an embodiment of the present application provides a DMA data transfer method, which is applied to a DMA controller. The DMA data transfer method includes: obtaining a write instruction set, the write instruction set includes second configuration information, and the The second configuration information includes second discrete address information and second continuous address information; according to the second configuration information in the write instruction set, the data in the continuous address range corresponding to the second continuous address information is transported to each Within the discrete address range corresponding to the second discrete address information.

In a third aspect, an embodiment of the present application provides a DMA data transfer device, which is configured in a DMA controller and includes: a first acquisition module for acquiring a read instruction set, where the read instruction set includes first configuration information, so The first configuration information includes first discrete address information and first continuous address information; a data reading module is configured to read the discrete address information corresponding to the first discrete address information according to the first configuration information in the read instruction set. The data within the address range is moved to the continuous address range corresponding to the first continuous address information.

In the fourth aspect, an embodiment of the present application provides a DMA data transfer device, which is configured in a DMA controller and includes: a second acquisition module for acquiring a write instruction set, where the write instruction set includes second configuration information, so The second configuration information includes second discrete address information and second continuous address information; a data writing module is configured to write the continuous address information corresponding to the second continuous address information according to the second configuration information in the write instruction set. The data within the address range is moved to the discrete address range corresponding to each of the second discrete address information.

In the fifth aspect, an embodiment of the present application provides a coprocessor, the coprocessor is coupled with a DMA controller, or the DMA controller is coupled and integrated with the coprocessor, and the DMA controller includes The DMA data transfer device according to the third aspect, and/or the DMA data transfer device according to the fourth aspect.

In a sixth aspect, an embodiment of the present application provides an electronic device, including a memory, a coprocessor, and a computer program stored in the memory and executable on the coprocessor. The coprocessor executes the The computer program implements the DMA data transfer method as described in any embodiment of the first aspect, and/or implements the DMA data transfer method as described in any embodiment of the second aspect.

In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium. The computer storage medium stores a computer program. When the computer program is executed by a coprocessor, the computer program implements the method described in any embodiment of the first aspect. The DMA data transfer method, and/or, implement the DMA data transfer method as described in any embodiment of the second aspect.

In an eighth aspect, an embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the DMA data transfer method as described in any embodiment of the first aspect, and /Or, implement the DMA data transfer method as described in any embodiment of the second aspect.

The embodiment of the present application controls the DMA data transfer operation through the instruction set, realizing the transfer of data in the discrete address range to the continuous address range, or transferring the data in the continuous address range to each discrete address range, so that in the DMA During the data transfer process, the normal operation of the CPU will not be affected by DMA interrupts.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the purpose of the present application. For some embodiments, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic flow chart of the implementation of a DMA data transfer method provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a read instruction set provided by an embodiment of the present application;

Figure 3 is a schematic diagram of the meaning of configuration information provided by an embodiment of the present application;

Figure 4 is a schematic diagram of the meaning of configuration information provided by an embodiment of the present application;

Figure 5 is a schematic diagram of an image and its sub-images provided by an embodiment of the present application;

Figure 6 is a schematic diagram of the meaning of configuration information in an image processing application scenario provided by an embodiment of the present application;

Figure 7 is a schematic flow chart of the implementation of a DMA data transfer method provided by an embodiment of the present application;

Figure 8 is a schematic structural diagram of a write instruction set provided by an embodiment of the present application;

Figure 9 is a schematic process diagram of a DMA data transfer method provided by an embodiment of the present application;

Figure 10 is a schematic diagram of an image processing application scenario provided by an embodiment of the present application;

Figure 11 is a schematic diagram of the meaning of configuration information in an image processing application scenario provided by an embodiment of the present application;

Figure 12 is a schematic structural diagram of a DMA data transfer device provided by an embodiment of the present application;

Figure 13 is a schematic structural diagram of a DMA data transfer device provided by an embodiment of the present application;

FIG. 14 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures and technologies are provided to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

As used in this specification and the appended claims, the term "and/or" means and includes any and all possible combinations of one or more of the associated listed items.

Reference in the specification of this application to "one embodiment" or "some embodiments" or the like means that a particular feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Therefore, the phrases "in one embodiment", "in some embodiments", "in other embodiments", "in other embodiments", etc. appearing in different places in this specification are not necessarily References are made to the same embodiment, but rather to "one or more but not all embodiments" unless specifically stated otherwise. The terms “including,” “includes,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized.

In addition, in the description of this application, "plurality" means two or more. The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

It should also be understood that, unless otherwise expressly stipulated or limited, the term "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection or an intermediate connection. The medium is indirectly connected, which can be the internal connection between two components or the interaction between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

The DMA data transfer in the embodiment of this application is divided into two parts. One is DMA data transfer based on the read instruction set, which mainly realizes moving each data in certain discrete addresses to a continuous address range. The other one is DMA data transfer based on the write instruction set, which mainly implements moving data in a continuous address range to various discrete address areas. Therefore, data transfer based on the write instruction set can be regarded as the reverse process of data transfer based on the read instruction set. . In addition, DMA data transfer based on the read instruction set has a locking function.

It should be noted that the DMA data transfer method provided by this application can be executed by a DMA controller, and the DMA controller can be coupled with a coprocessor or integrated with a coprocessor; if the DMA controller can be coupled with a coprocessor or integrated with a coprocessor, processor, the DMA data transfer method is executed under the control of the coprocessor, and there is no limit here.

Figure 1 is a schematic flowchart of a DMA data transfer method based on a read instruction set provided by an embodiment of the present application. The method may include steps S110 to S120.

S110, obtain the read instruction set.

Among them, the read instruction set includes configuration information, and the configuration information includes discrete address information, continuous address information and other information. Among them, the discrete address information includes one or more, and the discrete address information is the source address information; the continuous address information is the target address information, and the data in one or more source addresses is moved to a target address.

As a possible implementation, the configuration information is determined based on user operations and/or system settings, and a read instruction set is generated based on the configuration information.

In some embodiments, the discrete address information in the read instruction set includes the starting offset address of the source memory, the address space size of a single discrete address, the address distance of two adjacent discrete addresses of the same data source, and the address space of the same data source. The number of addresses, the address distance between two adjacent discrete addresses of different data sources, and the number of data sources, etc.; continuous address information includes the starting offset address information of the destination memory, etc.

S120: According to the configuration information in the read instruction set, transfer the data in the discrete address range corresponding to the discrete address information to the continuous address range corresponding to the continuous address information.

In some embodiments, Figure 2 shows a schematic structural diagram of the read instruction set. As shown in Figure 2, the read instruction set has a total of 256 bits. The configuration information included in the read instruction set is shown in Table 1 below.

Table 1

The specific meanings of sector_length, L1_sector_gap, L1_sector_num, L2_sector_gap, and L2_sector_num in the configuration information shown in Table 1 can be seen in Figures 3 and 4. As shown in Figure 3 and Figure 4, assuming that the discrete address where the data in the source memory is located is a large interval A, then A can be divided into multiple small intervals, for example, into five small areas: a1, a2, a3, a4, and a5. time, where a1, a3, and a5 areas are areas that need to read data and the three address spaces are equal in size, a2 and a4 are areas that do not need to read data, and the address spaces of the two are equal in size; a1, a3, The total number of small intervals between a2 and a5 is L2_sector_num, and the address space size of a2 and a4 is L2_sector_gap. Furthermore, assuming that the gray areas in the figure are the same size and the data in the area needs to be moved, and the blank area is the same size but the data in the area does not need to be moved, then the address space size of the gray area is sector_length, and the address of the blank area is sector_length. The space size is L1_sector_gap, and the number of gray areas within each small interval a1, a3, and a5 is L1_sector_num. Based on the above configuration information, an address schedule can be established within the DMA. After moving the data in a gray area address space, it will automatically jump to the next gray area address space to move data until all gray area data in the source memory has been moved. When moved to the destination memory, that is, the data at each discrete address is moved to a continuous address range, as shown in Figures 3 and 4. Through these configuration information, DMA can move data in multiple discrete address ranges to a continuous address range at one time.

Taking image data as an example, the DMA data transfer method provided by the embodiment of the present application will be described in detail below.

In the process of image processing, there are often many images to be processed. Generally, the memory stores the images according to the order in which the images to be processed are arranged. As shown in Figure 5, the memory first stores the first image in the order in which the images to be processed are arranged. image, followed by a second image, then a third image, until all images have been stored. It should be noted that when storing images, the image data of a single image is stored row by row in sequence.

However, in the image processing process, in order to consider the cost of hardware resources, a single image that is too large will be split into multiple small images, that is, sub-images, for processing during design, as shown in Figure 5. A single image can be viewed as consisting of many sub-images, such as A0, B0, A1, B1, A2, B2, A3, and B3. During each processing, sub-images of the same position and size of all images are taken out for processing. For example, as shown in Figure 5, sub-images A0, A1, A2, and A3 are first taken out for parallel processing. When sub-images A0, A1 , A2, and A3 are processed, then take out the sub-images B0, B1, B2, and B3 for processing, repeat the same operation, and process all sub-images in sequence, that is, the processing of all images is completed. In the above process of fetching sub-images for processing, the sub-image data needs to be transferred to the corresponding co-processor for processing. However, if the conventional DMA data transfer method is used, A0 needs to be moved first, then A1, and then Move A2, then A3, then B0, then B1, until all sub-images are moved. It can be seen that the conventional method will cause the DMA to generate an interrupt signal to the CPU every time it moves a sub-image, so that the CPU frequently generates interrupt signals, affecting its normal operation.

Based on the above problems, embodiments of the present application provide a DMA data transfer method based on a read instruction set. First, the configuration information is determined through user operations and/or system settings, and then a read instruction set is generated based on the configuration information, and then the read instruction set is used to complete the data. Handling to ensure the normal operation of the CPU.

In one embodiment, as shown in Figure 6, sector_length can be set to the image width of the sub-image, L1_sector_gap is set to the distance from the end of the first row to the beginning of the second row in two adjacent rows of the sub-image, and L1_sector_num is The image height of the sub-image, L2_sector_num is the total number of all images, (L2_sector_num is 4 in Figure 6). Combining Figure 5 and Figure 6, assuming that the last pixel of sub-image A0 in the first image in Figure 6 is C, and the first pixel of sub-image A1 in the second image is D, the addresses of these two pixels The distance is recorded as |CD|, then L2_sector_gap = |CD|-L1_sector_gap, where L2_sector_gap is the address distance between the two images, that is, the length of the data does not need to be read.

Further, based on the configuration information obtained above, a read instruction set is generated according to the structure shown in Figure 2, and the read instructions are used to transfer the four sub-images A0, A1, A2, and A3 from the four images at discrete addresses to within a contiguous address range. After the data transfer is completed, the DMA controller directly notifies the co-processor for subsequent processing. According to the above configuration, all sub-images after splitting the image can be transferred to the co-processor in sequence by reading the instruction set to avoid frequent interrupt signals affecting the CPU.

In some embodiments of this application, the DMA based on the read instruction set also has a locking function, that is, the configuration information in the instruction set lock_bn_begin (i.e., the starting position for executing the locking function) and lock_bn_end (i.e., the end position for executing the locking function) The address space between is locked. Once the space is locked, the DMA controller cannot transfer data to the address space. If the next read instruction set is configured to transfer data to the locked space, the DMA transfer will stop until the space is unlocked. , unlocking is controlled by the coprocessor. Generally, the locking and unlocking scenario is caused by the fact that the data in the address space has not been used by the coprocessor or needs to be used by the coprocessor later. Locking can prevent the data in the address space from being overwritten, or reduce duplication. The number of times to read the sub-image. When the data in this address space no longer needs to be used by the coprocessor, the coprocessor needs to send an unlock signal to the DMA controller. After receiving the unlock signal, the DMA controller will unlock the address space so that it can access the address space. Transfer data within.

The embodiment of the present application also provides a DMA data transfer method based on a write instruction set. It should be noted that the DMA data transfer method based on the write instruction set can be understood as the reverse operation of the DMA data transfer method based on the read instruction set, which transfers data in the continuous address range to each discrete address range.

In one embodiment, as shown in FIG. 7 , the DMA data transfer method based on the write instruction set may include steps S210 to S220.

S210, obtain the write instruction set.

The write instruction set includes configuration information, and the configuration information at least includes discrete address information and continuous address information. Among them, the continuous address information is the source address information; the discrete address information includes one or more, and the discrete address information is the target address information. Move data from a source address to one or more discrete destination addresses.

As a possible implementation, the configuration information is determined based on user operations and/or system settings, and a write instruction set is generated based on the configuration information.

In some embodiments, the continuous address information of the write instruction set includes the starting offset address information of the source memory, etc.; the discrete address information includes the starting offset address of the destination memory, the address space size of a single discrete address, and the same data source. The address distance of two adjacent discrete addresses, the number of discrete addresses with the same data source, the address distance of two adjacent discrete addresses with different data sources, and the number of data sources, etc.

S220: According to the configuration information in the write instruction set, transfer the data in the continuous address range corresponding to the continuous address information to the discrete address range corresponding to each discrete address information.

In some embodiments, FIG. 8 shows a schematic structural diagram of the write instruction set. As shown in FIG. 8 , the write instruction set has a total of 256 bits. The configuration information included in the write instruction set is shown in Table 2 below.

Table 2

The specific meanings of sector_length, L1_sector_gap, L1_sector_num, L2_sector_gap, and L2_sector_num in the configuration information shown in Table 2 are the same as those in Table 1, and can also be seen in Figures 3 and 4. No further details will be given here, please refer to the above.

DMA data transfer based on the write instruction set can be viewed as the operation shown in Figure 9. As shown in Figure 9, DMA data transfer based on the write instruction set can complete reading out continuous data and writing one or more discrete blocks. within the address range. By writing the configuration information in the instruction set, DMA can move data in a continuous address range to multiple discrete address ranges at one time.

The following continues the aforementioned embodiment of image data shown in Figures 5 to 6, and applies the DMA data transfer method to image processing. In the image processing process, continue to refer to Figures 5 and 6 to split a large single image into multiple small sub-images for processing. It is necessary to divide all images into sub-images A0, A1, A2, A0, A1, A2, and A3 are moved out, that is, the data in the discrete address space is moved to the continuous address space. As shown in Figure 10, when the coprocessor completes the processing, the data of the sub-images A0, A1, A2, and A3 are processed into After A'0, A'1, A'2, and A'3, the processed data needs to be moved out. After each sub-image is processed, it needs to be written to the corresponding location, that is, the data in the continuous address is moved to the discrete address space. The above operation can be completed by using the DMA data transfer method based on the write instruction set provided by the embodiment of the present application. At this time, the information such as sector_length, L1_sector_gap, L1_sector_num, L2_sector_gap, and L2_sector_num configured in the write instruction set is the corresponding relevant information on the final output image, as shown in Figure 11. Specifically, as shown in Figure 11, sector_length can be set to the image width of the sub-image, L1_sector_gap is set to the distance from the end of the first row to the beginning of the second row in two adjacent rows of the sub-image, and L1_sector_num is the width of the sub-image. Image height, L2_sector_num is the total number of images (4 in Figure 11). Assume that the last pixel of sub-image A'0 in the first image in Figure 11 is C', and the first pixel of sub-image A'1 in the second image is D'. The address distance of these two pixels is recorded as |C'D'|, then L2_sector_gap=|C'D'|-L1_sector_gap.

It should be understood that the sequence number of each step in the above embodiment does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

An embodiment of the present application also provides a DMA data transfer device. The DMA data transfer device is configured in a DMA controller. For details about the DMA data transfer device that are not described in detail, please refer to the relevant descriptions of the foregoing method embodiments and will not be described again here.

Referring to Figure 12, Figure 12 is a schematic structural diagram of a DMA data transfer device provided by an embodiment of the present application. As shown in Figure 12, the DMA data transfer device includes: a first acquisition module 1210 and a data reading module 1220.

Among them, the first acquisition module 1210 is used to acquire the read instruction set.

The data reading module 1220 is used to transfer data in the discrete address range corresponding to the discrete address information to the continuous address range corresponding to the continuous address information according to the configuration information in the read instruction set.

Referring to Figure 13, Figure 13 is a schematic structural diagram of a DMA data transfer device provided by an embodiment of the present application. As shown in Figure 13, the DMA data transfer device includes: a second acquisition module 1310 and a data writing module 1320.

The second acquisition module 1310 is used to acquire the write instruction set.

The data writing module 1320 is used to transfer data in the continuous address range corresponding to the continuous address information to the discrete address range corresponding to each discrete address information according to the configuration information in the write instruction set.

An embodiment of the present application also provides a DMA controller. The DMA controller includes the DMA data transfer device of the embodiment shown in FIG. 12 and/or the DMA data transfer device of the embodiment shown in FIG. 13 .

An embodiment of the present application also provides a coprocessor. The coprocessor is integrated with the foregoing DMA controller, or the coprocessor is coupled with the foregoing DMA controller.

An embodiment of the present application also provides an electronic device. As shown in FIG. 14 , the electronic device may include one or more coprocessors 1400 (only one is shown in FIG. 14 ), a memory 1410 , and a program stored in the memory 1410 and operable on the one or more coprocessors 1400 . Computer program 1420, for example, a program for DMA data transfer. When one or more coprocessors 1400 execute the computer program 1420, they may implement the DMA data transfer method of the embodiment shown in FIG. 1, and/or the steps in the DMA data transfer method of the embodiment shown in FIG. 7. . Alternatively, when one or more co-processors 1400 execute the computer program 1420, they can implement the DMA data transfer apparatus of the embodiment shown in FIG. 12, and/or each of the DMA data transfer apparatus of the embodiment shown in FIG. 13. The functions of modules/units are not limited here.

For example, the computer program 1420 may be divided into one or more modules/units, and the one or more modules/units are stored in the memory 1410 and executed by the coprocessor 1400 to complete the present application. One or more modules/units may be a series of computer program instruction segments capable of completing specific functions. The instruction segments are used to describe the execution process of the computer program 1420 in the processing unit.

For example, the computer program 1420 can be divided into several modules as follows. The specific functions of each module are as follows:

The first acquisition module is used to acquire the read instruction set;

The data reading module is used to transfer data in the discrete address range corresponding to the discrete address information to the continuous address range corresponding to the continuous address information according to the configuration information in the read instruction set.

and / or,

The second acquisition module is used to acquire the write instruction set;

The data writing module is used to transfer data in the continuous address range corresponding to the continuous address information to the discrete address range corresponding to each discrete address information according to the configuration information in the write instruction set.

Those skilled in the art can understand that FIG. 14 is only an example of an electronic device and does not constitute a limitation on the electronic device. The electronic device may include more or less components than shown in the figures, or a combination of certain components, or different components. For example, the electronic device may also include input and output devices, network access devices, buses, etc.

In one embodiment, the so-called coprocessor 1400 can be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field- Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

In one embodiment, the memory 1410 may be an internal storage unit of the electronic device, such as a hard disk or memory of the electronic device. The memory 1410 can also be an external storage device of the electronic device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, or a flash card equipped on the electronic device. wait. Further, the memory 1410 may also include both an internal storage unit of the electronic device and an external storage device. Memory 1410 is used to store computer programs and other programs and data required by the electronic device. The memory 1410 may also be used to temporarily store data that has been output or is to be output.

An embodiment of the present application also provides another preferred embodiment of an electronic device. In this embodiment, the electronic device includes one or more co-processors. One or more coprocessors are used to execute the following program modules stored in memory:

The first acquisition module is used to acquire the read instruction set;

and / or,

The second acquisition module is used to acquire the write instruction set;

Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above functional units and modules is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs. Module completion means dividing the internal structure of the device into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be hardware-based. It can also be implemented in the form of software functional units. In addition, the specific names of each functional unit and module are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application. For the specific working processes of the units and modules in the above system, please refer to the corresponding processes in the foregoing method embodiments, and will not be described again here.

An embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the DMA data transfer method of the embodiment shown in Figure 1 can be implemented. And/or, the DMA data transfer method of the embodiment shown in FIG. 7 .

An embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the DMA data transfer method of the embodiment shown in Figure 1, and/or the method shown in Figure 7. The DMA data transfer method of the embodiment is shown.

In the above embodiments, each embodiment is described with its own emphasis. For parts that are not detailed or documented in a certain embodiment, please refer to the relevant descriptions of other embodiments.

According to different design requirements, the above-mentioned first acquisition module, data reading module, second acquisition module, and data writing module can be implemented in the form of hardware (hardware), firmware (firmware), software (software, that is, computer program). ) or a combination of more of the above three. In terms of hardware, the above-mentioned first acquisition module, data reading module, second acquisition module, data writing module, etc. may be logic circuits implemented on an integrated circuit. The related functions of the above-mentioned first acquisition module, data reading module, second acquisition module, and data writing module can be implemented using hardware description languages (hardware description languages, such as Verilog HDL or VHDL) or other suitable programming languages. hardware. For example, the related functions of the above-mentioned first acquisition module, data reading module, second acquisition module, and data writing module can be implemented in one or more controllers, microcontrollers, microprocessors, special applications Various logic areas in integrated circuits (Application-specific integrated circuits, ASICs), digital signal processors, DSPs, field programmable gate arrays, and/or other processing units Blocks, modules and circuits. In terms of software form and/or firmware form, the related functions of the above-mentioned first acquisition module, data reading module, second acquisition module, data writing module, etc. can be implemented as computer programs. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. Computer program code may be recorded/stored in computer-readable media. Computer-readable media may include: any entity or device capable of carrying computer program code, recording media, USB flash drives, mobile hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), RAM, electronic Carrier signals, telecommunications signals, and software distribution media, etc. A central processing unit (Central Processing Unit, CPU), controller, microcontroller or microprocessor can read and execute the computer program code from the computer-readable medium, thereby realizing the above-mentioned first acquisition module, data reading Relevant functions of the acquisition module, the second acquisition module, and the data writing module. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include Electrical carrier signals and telecommunications signals.

The above embodiments are only used to illustrate the technical solutions of the present application, but are not intended to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments. Modifications are made to the recorded technical solutions, or equivalent substitutions are made to some of the technical features; these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and shall be included in this application. within the scope of protection.

Claims

A DMA data transfer method, applied to a DMA controller, characterized in that the DMA data transfer method includes:

Obtain a read instruction set, the read instruction set includes first configuration information, and the first configuration information includes first discrete address information and first continuous address information;

According to the first configuration information in the read instruction set, the data in the discrete address range corresponding to the first discrete address information is moved to the continuous address range corresponding to the first continuous address information.
The DMA data transfer method of claim 1, wherein the first configuration information further includes indication information of whether to perform a locking function.
The DMA data transfer method according to claim 1, wherein the first configuration information also includes the starting and ending positions for executing the locking function,

The DMA data transfer method further includes: when it is determined that the indication information of whether to execute the locking function in the first configuration information is to execute the locking function, determining the starting and ending positions of the locking function. The address space between is locked.
The DMA data transfer method according to claim 3, wherein locking the address space between the start and end positions of the locking function includes: stopping the locking function. Data is moved within the address space between the start and end locations until the address space is unlocked.
The DMA data transfer method according to any one of claims 1 to 4, wherein the first discrete address information includes the starting offset address of the source memory, the address space size of a single discrete address, and the address space of the same data source. The address distance of two adjacent discrete addresses, the number of discrete addresses with the same data source, the address distance of two adjacent discrete addresses with different data sources, and the number of data sources;

The first continuous address information includes starting offset address information of the destination memory.
The DMA data transfer method of claim 5, wherein when applied to image processing, multiple sub-images corresponding to multiple images can be transferred from a discrete address space to a continuous address range; wherein the single discrete address The size of the address space is the image width of the sub-image, and the address distance of two adjacent discrete addresses of the same data source is the distance from the end of the first line to the beginning of the second line in two adjacent lines of the sub-image. , the number of discrete addresses from the same data source is the image height of the sub-image, and the address distance of two adjacent discrete addresses from different data sources is the last pixel of the previous sub-image in the two adjacent sub-images. and the address distance between the first pixel of the next sub-image, and the number of data sources is the number of the sub-images.
The DMA data transfer method according to any one of claims 1 to 4, further comprising:

Obtain a write instruction set, the write instruction set includes second configuration information, and the second configuration information includes second discrete address information and second continuous address information;

According to the second configuration information in the write instruction set, the data in the continuous address range corresponding to the second continuous address information is moved to the discrete address range corresponding to each of the second discrete address information.
A DMA data transfer method, applied to a DMA controller, characterized in that the DMA data transfer method includes:

Obtain a write instruction set, the write instruction set includes second configuration information, and the second configuration information includes second discrete address information and second continuous address information;

According to the second configuration information in the write instruction set, the data in the continuous address range corresponding to the second continuous address information is moved to the discrete address range corresponding to each of the second discrete address information.
The DMA data transfer method of claim 8, wherein when applied to image processing, multiple sub-images can be transferred from a continuous address range to each discrete address space.
A DMA data transfer device, configured in a DMA controller, characterized in that the DMA data transfer device includes:

A first acquisition module, configured to acquire a read instruction set, where the read instruction set includes first configuration information, and the first configuration information includes first discrete address information and first continuous address information;

A data reading module, configured to transfer data in the discrete address range corresponding to the first discrete address information to the continuous address corresponding to the first continuous address information according to the first configuration information in the read instruction set. within the range.
A DMA data transfer device, configured in a DMA controller, characterized in that the DMA data transfer device includes:

a second acquisition module, configured to acquire a write instruction set, where the write instruction set includes second configuration information, and the second configuration information includes second discrete address information and second continuous address information;

A data writing module, configured to transfer data in the continuous address range corresponding to the second continuous address information to discrete addresses corresponding to each of the second discrete address information according to the second configuration information in the write instruction set. within the address range.
A co-processor, characterized in that the co-processor is coupled with a DMA controller, or the DMA controller is coupled and integrated with the co-processor, and the DMA controller includes the DMA controller as claimed in claim 10 The DMA data transfer device, and/or the DMA data transfer device according to claim 11.
An electronic device, characterized in that it includes a memory, a coprocessor, and a computer program stored in the memory and executable on the coprocessor. When the coprocessor executes the computer program, it implements the following rights: The DMA data transfer method described in any one of claims 1 to 7, and/or, the DMA data transfer method described in any one of claims 8 to 9 is implemented.
A computer-readable storage medium, the computer storage medium stores a computer program, characterized in that, when the computer program is executed by a coprocessor, the DMA data transfer method as described in any one of claims 1 to 7 is implemented, And/or, implement the DMA data transfer method as described in any one of claims 8 to 9.