WO2023178682A1 - Doherty功率放大器及电子设备 - Google Patents

Doherty功率放大器及电子设备 Download PDF

Info

Publication number
WO2023178682A1
WO2023178682A1 PCT/CN2022/083157 CN2022083157W WO2023178682A1 WO 2023178682 A1 WO2023178682 A1 WO 2023178682A1 CN 2022083157 W CN2022083157 W CN 2022083157W WO 2023178682 A1 WO2023178682 A1 WO 2023178682A1
Authority
WO
WIPO (PCT)
Prior art keywords
power amplifier
drain
channel layer
transistor
electron mobility
Prior art date
Application number
PCT/CN2022/083157
Other languages
English (en)
French (fr)
Inventor
丁瑶
汤岑
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2022/083157 priority Critical patent/WO2023178682A1/zh
Publication of WO2023178682A1 publication Critical patent/WO2023178682A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

Definitions

  • the present application relates to the field of power amplifiers, and in particular, to a Doherty power amplifier and electronic equipment.
  • Doherty power amplifier is a high-power amplifier currently widely used in wireless communication systems.
  • the 3-way Doherty power amplifier has a larger fallback range than the 2-way Doherty power amplifier, but currently in the Doherty power amplifier, different dies need to be set for the amplifier tubes in different power amplifier circuits. , and the gate voltage needs to be configured separately, which leads to a series of problems such as complex peripheral circuits, poor consistency in mass production, and high cost, making it difficult to apply the 3way-Doherty power amplifier in actual products.
  • Embodiments of the present application provide a Doherty power amplifier and electronic equipment, which can reduce the number of dies used in the Doherty power amplifier.
  • This application provides a Doherty power amplifier, which includes a main power amplifier circuit, a first auxiliary power amplifier circuit, and a second auxiliary power amplifier circuit.
  • the main power amplifier circuit includes a first amplifier tube, which is used to amplify the signal input to the main power amplifier circuit.
  • the first auxiliary power amplifier circuit includes a second amplifier tube, and the second amplifier tube is used to amplify the signal input to the first auxiliary power amplifier circuit.
  • the second auxiliary power amplifier circuit includes a third amplifier tube, and the third amplifier tube is used to amplify the signal input to the second auxiliary power amplifier circuit.
  • the Doherty power amplifier includes a high electron mobility transistor (a first high electron mobility transistor); the high electron mobility transistor includes a source, a gate, a first channel layer, a second channel layer, a first drain, a third Two drains.
  • the first drain electrode is electrically connected to the first channel layer, and the second drain electrode is electrically connected to the second channel layer.
  • the source electrode of the first amplifier tube and the source electrode of the third amplifier tube are the same, and the source electrode of the high electron mobility transistor is multiplexed.
  • the gate electrode of the first amplifier tube is the same as the gate electrode of the third amplifier tube, and the gate electrode of the high electron mobility transistor is reused.
  • the first drain of the high electron mobility transistor serves as the drain of the first amplifier tube.
  • the second drain of the high electron mobility transistor serves as the drain of the third amplifier tube.
  • multi-channel high electron mobility transistors are used as the two amplifier tubes in the above-mentioned main power amplifier circuit and the second auxiliary power amplifier circuit.
  • the main power amplifier circuit and the second auxiliary power amplifier circuit The amplifier tube in the power amplifier circuit can meet the needs with one bare chip, and the first auxiliary power amplifier circuit can meet the needs with one bare chip; at the same time, it also avoids the need to separately configure the gate voltage for the first amplifier tube and the third amplifier tube, thus simplifying It reduces the circuit complexity of the Doherty power amplifier and reduces the cost.
  • the turn-on voltage of the second amplifier tube is greater than the turn-on voltage of the third amplifier tube.
  • the source of the high electron mobility transistor is connected to the ground terminal; after the input signal of the gate of the high electron mobility transistor is amplified by the first amplifier tube and the third amplifier tube, it passes through the first amplifier tube respectively. drain and second drain for output.
  • the Doherty power amplifier further includes: a first microstrip line, a second microstrip line, a third microstrip line, a fourth microstrip line, a fifth microstrip line, and a power divider.
  • the power divider includes a first output terminal and a second output terminal. The first output terminal is connected to the gate of the high electron mobility transistor through a first microstrip line. The second output terminal is connected to the gate of the second amplifier tube.
  • the first drain is connected to the combining point through the second microstrip line; the drain of the second amplifier tube is connected to the combining point through the third microstrip line and the fourth microstrip line in turn; the second drain is connected to the third Between the microstrip line and the fourth microstrip line; the combining point is connected to the output end of the Doherty power amplifier through the fifth microstrip line.
  • phase compensation is performed on the output signal of the first output terminal through the first microstrip line to ensure that the total phase of the main power amplifier circuit, the total phase of the first auxiliary power amplifier circuit, and the total phase of the second auxiliary power amplifier circuit are basically the same.
  • the second microstrip line, the third microstrip line, the fourth microstrip line and the fifth microstrip line are used for impedance transformation to realize the Doherty impedance pulling function.
  • the above-mentioned high electron mobility transistor includes a substrate; a first channel layer and a first barrier layer are stacked on the substrate, and the first barrier layer is located away from the first channel layer and the substrate. bottom side.
  • a second channel layer and a second barrier layer are stacked on the first barrier layer, and the second barrier layer is located on a side of the second channel layer away from the substrate.
  • a cap layer is provided on a side of the second barrier layer away from the substrate.
  • the first drain electrode is disposed on the first channel layer and is electrically connected to the first channel layer.
  • the source electrode, the gate electrode, and the second drain electrode are arranged on the cap layer.
  • the second drain electrode is electrically connected to the second channel layer, and the source electrode is electrically connected to both the first channel layer and the second channel layer.
  • the first drain electrode is in ohmic contact with the first channel layer; the second drain electrode is in ohmic contact with the second channel layer; and the source electrode is in ohmic contact with the first channel layer and the second channel layer.
  • ways to achieve ohmic contact may include etching ohmic contact, implanting ohmic contact, and high-temperature metal ohmic contact.
  • a first insertion layer is provided between the first channel layer and the first barrier layer; and a second insertion layer is provided between the second channel layer and the second barrier layer.
  • the electron mobility of the two-dimensional electron gas generated at the channel can be improved by the arrangement of the insertion layer.
  • a nucleation layer and a buffer layer are provided between the substrate and the first channel layer; the nucleation layer is close to the substrate relative to the buffer layer.
  • the high electron mobility transistor includes a plurality of transistor units arranged in sequence and in parallel.
  • the plurality of transistor units include a first transistor unit, a second transistor unit, and a third transistor unit that are arranged adjacently in sequence.
  • the first transistor unit and the second transistor unit share the same source, and the first transistor unit and the second transistor unit are symmetrically arranged along the source.
  • the second transistor unit and the third transistor unit share the same first drain, and the second transistor unit and the third transistor unit are symmetrical along the first drain.
  • the second drain electrode is located in a region between the source electrode and the first drain electrode
  • the gate electrode is located in a region between the source electrode and the second drain electrode.
  • the high electron mobility transistor is a GaNHEMT.
  • An embodiment of the present application also provides an electronic device, including a transmitter; the transmitter adopts the Doherty power amplifier provided in any of the above possible implementation methods.
  • Figure 1 is a schematic circuit diagram of a Doherty power amplifier provided by an embodiment of the present application.
  • Figure 2 is a schematic circuit diagram of a Doherty power amplifier provided by an embodiment of the present application.
  • Figure 3 is the operating efficiency curve of the Doherty power amplifier in Figure 1;
  • Figure 4 is a schematic structural diagram of a high electron mobility transistor provided in the prior art
  • Figure 5 is a schematic structural diagram of a high electron mobility transistor provided by an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of a high electron mobility transistor provided by an embodiment of the present application.
  • FIG. 7 is a schematic layout design diagram of a high electron mobility transistor used in a Doherty power amplifier according to an embodiment of the present application.
  • At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • at least one of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c” ”, where a, b, c can be single or multiple.
  • “Installation”, “connection”, “connection”, etc. should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediary, or it can be It is the internal connection between two components.
  • the terms “including” and “having” and any variations thereof are intended to cover a non-exclusive inclusion, for example, the inclusion of a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such processes, methods, products or devices. "Up”, “down”, “left”, “right”, “top”, “bottom”, etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. Relative descriptions and clarifications are used, which may vary accordingly depending on changes in the orientation in which components in the drawings are placed.
  • An embodiment of the present application provides an electronic device.
  • the electronic device is provided with a transmitter, and the transmitter is provided with a Doherty power amplifier.
  • the Doherty power amplifier includes at least three power amplifier circuits.
  • the Doherty power amplifier amplifies the multi-channel power amplifier.
  • the amplifier tube in the circuit is replaced by a new multi-channel high electron mobility transistor (HEMT), which is equivalent to using one bare chip to meet the needs of multiple amplifier tubes, while also avoiding the need for multiple amplifier tubes.
  • HEMT high electron mobility transistor
  • the gate voltage of the amplifier tube is configured individually, thus simplifying the circuit complexity of the Doherty power amplifier and reducing the cost.
  • the electronic device can be a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet, a radar, a base station and other electronic products.
  • FIG. 1 is a schematic circuit diagram of a 3way-Doherty power amplifier provided by an embodiment of the present application.
  • the 3way-Doherty power amplifier includes a main power amplifier circuit 1 (main), a first auxiliary power amplifier circuit 2 (peak1), and a second auxiliary power amplifier circuit 3 (peak2).
  • the main power amplifier circuit 1 includes a first amplifier tube D_1, through which the signal input to the main power amplifier circuit can be amplified.
  • the first auxiliary power amplifier circuit 2 includes a second amplifier tube D_2, through which the signal input to the first auxiliary power amplifier circuit 2 can be amplified.
  • the second auxiliary power amplifier circuit 2 includes a third amplifier tube D_3, through which the signal input to the second auxiliary power amplifier circuit 3 can be amplified.
  • the multi-channel power amplifier circuit in the Doherty power amplifier usually includes a main power amplifier circuit (main), and at least one auxiliary power amplifier circuit (peak) in addition to the main power amplifier circuit (main).
  • main main
  • auxiliary power amplifier circuit peak
  • the embodiment of the present application is explained by taking the main power amplifier circuit (main) and the two auxiliary power amplifier circuits 2 as an example.
  • the Doherty power amplifier may include three or more auxiliary power amplifier circuits (peaks).
  • this application also provides a new type of dual-channel high electron mobility transistor (HEMT).
  • HEMT high electron mobility transistor
  • the dual-channel transistor (HEMT) is used to replace the above-mentioned first amplifier tube D_1 and the third amplifier tube D_3, that is, the first amplifier tube D_1 and the third amplifier tube D_3
  • the dual channel transistor (HEMT) is multiplexed.
  • the dual-channel transistor (HEMT) includes a gate G, a source S, a first channel layer 21, a second channel layer 22, a first drain D1, and a second drain D2.
  • the first drain electrode D1 is electrically connected to the first channel layer 21, and the second drain electrode D2 is electrically connected to the second channel layer 22. That is, the first drain electrode D1 and the second drain electrode D2 are respectively connected to two different channels.
  • Tao (101, 102).
  • the first drain D1 of the dual-channel transistor (HEMT) serves as the drain of the first amplifier D_1; the second drain D2 of the dual-channel transistor (HEMT) serves as the drain of the third amplifier D_3.
  • the gate G of the dual-channel transistor (HEMT) serves as the gate of the first amplifier tube D_1 and the third amplifier tube D_3, and the source S of the dual-channel transistor (HEMT) serves as the first amplifier tube D_1 and the third amplifier tube.
  • the source electrode of D_3 that is, the gate electrode of the first amplifier tube D_1 and the gate electrode of the third amplifier tube D_3 are the same, and the gate electrode of the dual-channel transistor (HEMT) is multiplexed; the source electrode of the first amplifier tube D_1 and the gate electrode of the third amplifier tube D_3 are the same.
  • the sources of the three amplifier tubes D_3 are the same, and the sources of the dual-channel transistor (HEMT) are multiplexed.
  • the source of the dual-channel transistor can be connected to the ground, the gate is connected to the input terminal IN of the Doherty power amplifier, the first drain D1 and the second drain D2 is connected to the output terminal OUT of the Doherty power amplifier through relevant circuits.
  • the input signal at the input terminal IN is amplified by the first amplifier tube D_1 and the third amplifier tube D_3, it is output to the output terminal OUT through the first drain electrode D1 and the second drain electrode D2 respectively.
  • the first high electron mobility transistor HEMT1 multi-channel high electron mobility transistor
  • D_1, D_3 the two amplifier tubes
  • the amplification tubes in the main power amplifier circuit 1 and the second auxiliary power amplifier circuit 3 can meet the needs by using one bare chip (HEMT1), and the first auxiliary power amplifier circuit 2 can meet the needs by using a bare chip (HEMT2); at the same time, it also avoids the need for
  • the first amplifier tube D_1 and the third amplifier tube D_3 configure gate voltages independently, thus simplifying the circuit complexity of the Doherty power amplifier and reducing the cost.
  • the single-channel second high electron mobility transistor HEMT2 can be used as the second amplifier tube D_2 in the second auxiliary power amplifier circuit 3.
  • a 3-way power amplifier circuit (1 , 2, 3) requirements are required.
  • the order of turning on the amplifier tubes is different.
  • the amplifier tube in the main power amplifier circuit (main) is turned on first, and the auxiliary power amplifier is turned on first.
  • the amplifier tube in the circuit (peak) is then turned on.
  • the first amplifier tube D_1, the second amplifier tube D_2, and the third amplifier tube D_3 can be turned on in sequence, that is, the turn-on voltage of the third amplifier tube D_3 (i.e., the gate-source voltage Vgs_main) is greater than
  • the turn-on voltage of the second amplifier tube D_2 (Vgs_peak2) is greater than the turn-on voltage of the first amplifier tube D_1 (Vgs_peak1), that is, Vgs_main>Vgs_peak1>Vgs_peak2.
  • the first amplifier tube D_1 is biased in the class AB state
  • the second amplifier tube D_2 and the third amplifier tube D_3 are biased in the class C state
  • the working status of the three-way power amplifier circuit (1, 2, 3) will also change.
  • the second amplifier tube D_2 (peak1) gradually turns on and pulls the impedance of the first amplifier tube D_1 (main).
  • the circuit reaches the second peak efficiency point.
  • the Doherty power amplifier may also include a fourth power amplifier circuit, a fifth power amplifier circuit, etc.; the first high electron mobility transistor HEMT1 may also include three or more channels, thereby realizing Doherty power amplifiers are replaced by multiple amplifier tubes with in-phase input signals.
  • the 3way-Doherty power amplifier is used as an example for schematic explanation.
  • the Doherty power amplifier includes the aforementioned three amplifier tubes (D_1, D_2, D_3), and also includes: a first microstrip line 10 , the second microstrip line 20, the third microstrip line 30, the fourth microstrip line 40, the fifth microstrip line 50, and the power divider 100.
  • the power divider 100 includes a first output terminal out1 and a second output terminal.
  • the first output terminal out1 is connected to the gate of the first high electron mobility transistor HEMT1 (that is, the gates of the first amplifier tube D_1 and the third amplifier tube D_3) through the first microstrip line 10, and the second output terminal out2 is connected to The gate of the second high electron mobility transistor HEMT2 (that is, the gate of the second amplifier tube D_2) is connected.
  • the drain of the first amplifier tube D_1 ie, the first drain
  • the drain of the second amplifier tube D_2 is connected to the combining point O through the third microstrip line 30 and the fourth microstrip line 40 in sequence.
  • the drain electrode (ie, the second drain electrode) of the third amplifier tube D_3 is connected between the third microstrip line 30 and the fourth microstrip line 40 .
  • the combining point O is connected to the output terminal OUT of the Doherty power amplifier through the fifth microstrip line 50 .
  • the sources of the gates of the first high electron mobility transistor HEMT1 and the second high electron mobility transistor HEMT2 are both connected to the ground terminal.
  • the input terminal can be related to the circuit connection through the input matching circuit, and the output terminal
  • the terminals can be connected to relevant circuits through the output matching circuit.
  • the first amplification tube D_1 and the third amplification tube D_3 should have input signals of the same phase, thereby ensuring that the use of the first high electron mobility transistor HEMT1 can satisfy the two amplification requirements.
  • the gate of the first high electron mobility transistor HEMT1 is connected to the same output terminal (first output terminal out1) of the power divider 100, and the gate of the second high electron mobility transistor HEMT2 is connected to the same output terminal of the power divider 100.
  • the other output terminal (the second output terminal out2) of the device 100 is connected.
  • the output signal of the first output terminal out1 is phase compensated through the first microstrip line 10 to ensure the total phase of the main power amplifier circuit 1, the total phase of the first auxiliary power amplifier circuit 2, and the second auxiliary power amplifier circuit 2.
  • the total phase of the power amplifier circuit 3 is basically the same; the second microstrip line 20, the third microstrip line 30, the fourth microstrip line 40 and the fifth microstrip line 50 are used for impedance transformation to realize the Doherty impedance pulling function.
  • Figure 4 is a schematic structural diagram of a traditional single-channel electron mobility transistor (HEMT).
  • HEMT single-channel electron mobility transistor
  • a channel layer and a barrier layer are provided in a single-channel HEMT, and a two-dimensional electron gas is generated at the interface between the channel layer and the barrier layer (ie, the heterojunction interface) (2-dimension electron gas, 2DEG) forms channel 100.
  • 2DEG 2-dimension electron gas
  • the dual-channel HEMT used in the embodiment of the present application forms multiple channels (such as 101, 102) by repeatedly growing channel layers and barrier layers in the epitaxial structure. , thereby breaking through the theoretical limit of single-channel devices, increasing the two-dimensional electron gas (2DEG) surface density in the channel while maintaining high electron mobility. Compared with the traditional single-channel structure, this multi-channel HEMT can effectively Reduce on-resistance and increase device power density.
  • multiple channels such as 101, 102
  • the embodiment of the present application provides a dual-channel HEMT (ie, the first high electron mobility transistor HEMT1).
  • the transistor includes a substrate 11 (substrate) and a plurality of transistors disposed on the substrate 11 in sequence.
  • Nucleation layer 12 nucleation
  • buffer layer 13 buffer
  • first channel layer 21 channel
  • first barrier layer 31 barrier
  • second channel layer 22 channel
  • second barrier layer 32 barrier
  • cap layer 40 cap
  • the transistor also includes a gate G, a source S, a first drain D1, and a second drain D2.
  • the first drain D1 is electrically connected to the first channel layer 21
  • the second drain D2 is electrically connected to the second channel layer 22 .
  • the first drain electrode D1 may be disposed on the first channel layer 21 to form an electrical connection with the first channel layer 21 .
  • the gate G, the source S, and the second drain D2 may be disposed on the cap layer 40 , and the second drain D2 and the second channel layer 22 are electrically connected through ion implantation.
  • the source S is electrically connected to the first channel layer 21 and the second channel layer 22 through ion implantation.
  • the voltage between the two drains (D1, D2) and the source S makes the voltage between the two channels (101, 102)
  • a lateral electric field is generated within the device, and under the action of the lateral electric field, the two-dimensional electron gas (2DEG) is transported along the two heterojunction interfaces to form a drain output current (as indicated by the arrow in Figure 5).
  • the depth of the potential well in the heterojunction can be controlled, and the surface density of the two-dimensional electron gas (2DEG) in the channel (101, 102) can be changed, thereby controlling the two drains (D1, D2) output current.
  • the first drain D1 is equivalent to the drain of the first amplifier tube D_1
  • the second drain D2 is equivalent to The drain of the third amplifier tube D_3.
  • This dual-channel HEMT can transform the traditional planar layout into a vertical layout.
  • the dual-channel HEMT can replace the two amplifier tubes (D_1, D_3). In this way, One bare chip can meet the needs of two amplifier tubes (D_1, D_3). It also avoids the need to separately configure the gate voltage for the two power amplifier circuits, simplifying the circuit complexity of the Doherty power amplifier and reducing the production cost.
  • the first amplifier tube D_1 in the main power amplifier circuit 1 is turned on before the third amplifier tube D_3 in the second auxiliary power amplifier circuit 3. Therefore, for the first high electron mobility transistor HEMT1, By setting the first drain D1 to be electrically connected to the first channel 101 (i.e., the lower channel), and the second drain D2 to be electrically connected to the second channel 102 (the upper channel), the first channel precedes the second channel. channel is turned on, and by reasonably setting the distance between adjacent channels, the needs of the main power amplifier circuit 1 (main) and the second auxiliary power amplifier circuit 3 (peak2) can be met.
  • the turn-on voltage of the second auxiliary power amplifier circuit 3 can be adjusted by reasonably setting the distance between the first channel and the second channel, thereby forming two signal paths that do not interfere with each other to meet the main requirements. Requirements for power amplifier circuit 1 (main) and second auxiliary power amplifier circuit 3 (peak2).
  • first drain D1 and the first channel layer 21 may be arranged to form an ohmic contact, thereby ensuring the electrical connection between the first drain D1 and the first channel 101 .
  • second drain electrode D2 can be arranged to form ohmic contact with the second channel layer 22
  • the source electrode S can form ohmic contact with the first channel layer 21 and the second channel layer 22 .
  • the method of realizing ohmic contact between the source S, the drain (D1, D2) and the channel layer (21, 22) may include but is not limited to etching ohms, implanting ohms, and high-temperature metal ohms.
  • the first drain electrode D1 can be connected to the surface of the first channel layer 21 in an etched ohmic contact manner, and the second drain electrode D2 can be connected to the second drain electrode D2 by etching ohmic contact.
  • the surface of the channel layer 22 is connected by implanting ohmic contact, and the source S is connected with the first channel layer 21 and the second channel layer 22 by implanting ohmic contact.
  • an etching process can be used to remove the film layer above the first channel layer 21 to leak the surface of the first channel layer 21 , and perform the first drain electrode in the leakage area of the first channel layer 21 .
  • the fabrication of D1 ensures ohmic contact between the first drain electrode D1 and the surface of the first channel layer 21 .
  • An implantation process is used to perform ion implantation at a position below the source S to form an implantation region a1.
  • the source S forms ohmic contact with the first channel layer 21 and the second channel layer 22 in the implantation region a1.
  • An implantation process is used to perform ion implantation at a position below the second drain electrode D2 to form an implantation region a2.
  • the second drain electrode D2 forms an ohmic contact with the second channel layer 22 through the implantation region a2.
  • a first insertion layer n1 may be provided between the first channel layer 21 and the first barrier layer 31 , and between the second channel layer 22 and the second A second insertion layer n2 is provided between the barrier layers 32.
  • the electron mobility of the 2DEG generated at the channel (101, 102) can be improved by the arrangement of the insertion layer (n1, n2).
  • this application does not impose restrictions on the materials used for the above-mentioned substrate 11 and other related film layers in the transistor. In practice, they can be set as needed.
  • the substrate 11 can be made of materials including but not limited to SiC, Si, GaN, GaAs, InP, etc.
  • the nucleation layer 12 can be made of materials including but not limited to AlN, InAlN, InGaN, ScAlN and the like.
  • the buffer layer 13 may be made of materials including but not limited to AlN, GaN, InAlN, InGaN, ScAlN, etc.
  • the channel layers (21, 22) can use materials including but not limited to AlN, GaN, InAlN, InGaN, ScAlN and the like.
  • the high electron mobility transistors (HEMT1, HEMT2) involved in the aforementioned embodiments may both be GaNHEMTs, and the channel layers (21, 22) may be GaN.
  • the barrier layers (31, 32) can use materials including but not limited to AlN, GaN, InAlN, InGaN, ScAlN and the like.
  • the insertion layer (n1, n2) can use materials including but not limited to AlN, GaN, InAlN, InGaN, ScAlN and other materials.
  • the cap layer 40 may be made of materials including but not limited to SiN, GaN, AIN, InAlN, InGaN, ScAlN, and the like.
  • the aforementioned second high electron mobility transistor HEMT2 may be the single-channel HEMT shown in FIG. 4 , but the present application is not limited thereto.
  • a single HEMT structure can use multiple transistor units (cells) arranged in parallel.
  • multiple transistor cells arranged in parallel are used. (i.e., cellular structure) distribution method is not limited.
  • the HEMT may include multiple transistor units (such as C1, C2, C3) arranged in parallel, and two adjacent transistor units are arranged symmetrically.
  • the plurality of transistor units include a first transistor unit C1, a second transistor unit C2, and a third transistor unit C3 that are arranged adjacently in sequence.
  • the first transistor unit C1 and the second transistor unit C2 use the same source S, that is, the first transistor unit C1 and the second transistor unit C2 use the same source pattern; and the first transistor unit C1 and the second transistor unit C2 is placed symmetrically along this source.
  • the second transistor unit C2 and the third transistor unit C3 share the first drain D1, that is, the second transistor unit C2 and the third transistor unit C3 adopt a common first drain pattern, and the second transistor unit C2 and the third transistor unit C3 share the first drain pattern.
  • C3 is arranged symmetrically along the first drain D1.
  • the second drain D2 is located in the area between the source S and the first drain D1
  • the gate G is located in the source S and the second drain D2 the area between.
  • the sources S of all transistor units are connected to the same conductive pattern as the source of the transistor, and all the first drains D1 are connected to the same conductive pattern through leads as One output pin of the transistor, and all the second drain D2 are connected to the same conductive pattern as another output pin of the transistor through leads to connect with the subsequent circuit through the two output pins.
  • the lead connected to the first drain D1 and the lead connected to the second drain D2 can be isolated by a dielectric bridge or an air bridge to ensure the normal operation of the two output pins.
  • first transistor unit C1, second transistor unit C2, and third transistor unit C3 do not specifically refer to the three fixed transistor units in the first high electron mobility transistor HEMT1. They are only relative concepts and can be It is three transistor units arranged adjacently in any order among multiple transistor units.
  • the second drain electrode D2 can be omitted in the transistor unit of the aforementioned first high electron mobility transistor HEMT1. Layout.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

本申请提供了一种Doherty功率放大器及电子设备，涉及功率放大器领域，能够减少Doherty功率放大器采用裸片(die)的数量。该Doherty功率放大器中，主功放电路包括第一放大管，第一辅功放电路包括第二放大管，第二辅功放电路包括第三放大管。Doherty功率放大器包括高电子迁移率晶体管；该晶体管包括源极、栅极、第一沟道层、第二沟道层、第一漏极、第二漏极；第一漏极与第一沟道层电连接，第二漏极与第二沟道层电连接。第一放大管和第三放大管复用高电子迁移率晶体管的源极。第一放大管和第三放大管复用高电子迁移率晶体管的栅极。高电子迁移率晶体管的第一漏极作为第一放大管的漏极。高电子迁移率晶体管的第二漏极作为第三放大管的漏极。

Description

Doherty功率放大器及电子设备 技术领域
本申请涉及功率放大器领域，尤其涉及一种Doherty功率放大器及电子设备。
背景技术
多赫尔蒂(Doherty)功率放大器是无线通信系统目前广泛应用的一种高功率放大器。其中，3路(way)Doherty功率放大器相对于2路Doherty功率放大器具有更大的回退范围，但是目前在Doherty功率放大器中，针对不同功放电路中的放大管需要设置不同的裸片(die)，并需要单独配置栅压，从而导致周边电路复杂、量产一致性差、成本高等一系列问题，导致3way-Doherty功率放大器在实际产品中很难应用。
发明内容
本申请实施例提供一种Doherty功率放大器及电子设备，能够减少Doherty功率放大器采用裸片(die)的数量。
本申请提供一种Doherty功率放大器，包括主功放电路、第一辅功放电路、第二辅功放电路。主功放电路包括第一放大管，该第一放大管用于对输入至主功放电路的信号进行放大。第一辅功放电路包括第二放大管，该第二放大管用于对输入至第一辅功放电路的信号进行放大。第二辅功放电路包括第三放大管，该第三放大管用于对输入至第二辅功放电路的信号进行放大。Doherty功率放大器包括高电子迁移率晶体管(第一高电子迁移率晶体管)；该高电子迁移率晶体管包括源极、栅极、第一沟道层、第二沟道层、第一漏极、第二漏极。第一漏极与第一沟道层电连接，第二漏极与第二沟道层电连接。第一放大管的源极和第三放大管的源极相同，复用高电子迁移率晶体管的源极。第一放大管的栅极和第三放大管的栅极相同，复用高电子迁移率晶体管的栅极。高电子迁移率晶体管的第一漏极作为第一放大管的漏极。高电子迁移率晶体管的第二漏极作为第三放大管的漏极。
本申请实施例提供的Doherty功率放大器中，采用多沟道高电子迁移率晶体管作为上述主功放电路、第二辅功放电路中的两个放大管，在此情况下，主功放电路和第二辅功放电路中的放大管采用一个裸片即可满足需求，第一辅功放电路采用一个裸片即可满足需求；同时还避免了针对第一放大管和第三放大管单独配置栅压，从而简化了Doherty功率放大器的电路复杂度，降低了成本。
在一些可能实现的方式中，第二放大管的开启电压大于第三放大管的开启电压。
在一些可能实现的方式中，高电子迁移率晶体管的源极与接地端连接；高电子迁移率晶体管的栅极的输入信号经第一放大管和第三放大管进行放大后，分别通过第一漏极和第二漏极进行输出。
在一些可能实现的方式中，该Doherty功率放大器还包括：第一微带线、第二微带线、第三微带线、第四微带线、第五微带线、功分器。功分器包括第一输出端和第二输出端。第一输出端通过第一微带线连接到高电子迁移率晶体管的栅极。第二输出端与第二放大管 的栅极连接。第一漏极通过第二微带线连接到合路点；第二放大管的漏极依次通过第三微带线、第四微带线连接到合路点；第二漏极连接到第三微带线和第四微带线之间；合路点通过第五微带线连接到Doherty功率放大器的输出端。在此情况下，通过第一微带线对第一输出端的输出信号进行相位补偿，以保证主功放电路的总相位、第一辅功放电路的总相位、第二辅功放电路的总相位基本相同；第二微带线、第三微带线、第四微带线以及第五微带线用于进行阻抗变换，以实现Doherty阻抗牵引的功能。
在一些可能实现的方式中，上述高电子迁移率晶体管包括衬底；在衬底上层叠设置的第一沟道层和第一势垒层，第一势垒层位于第一沟道层远离衬底的一侧。在第一势垒层上层叠设置的第二沟道层和第二势垒层，第二势垒层位于第二沟道层远离衬底的一侧。设置在第二势垒层远离衬底的一侧的帽层。第一漏极设置在第一沟道层上、且与第一沟道层电连接。源极、栅极、第二漏极设置在帽层上的，第二漏极与第二沟道层电连接，源极与第一沟道层、第二沟道层均电连接。
在一些可能实现的方式中，第一漏极与第一沟道层欧姆接触；第二漏极与第二沟道层欧姆接触，源极与第一沟道层、第二沟道层欧姆接触。其中，实现欧姆接触方式可以包括为刻蚀欧姆接触、注入欧姆接触及高温金属欧姆接触等。
在一些可能实现的方式中，第一沟道层和第一势垒层之间设置有第一插入层；第二沟道层和第二势垒层之间设置有第二插入层。通过插入层的设置能够提高沟道处产生的二维电子气的电子迁移率。
在一些可能实现的方式中，衬底与第一沟道层之间设置有成核层、缓冲层；成核层相对于缓冲层靠近衬底。
在一些可能实现的方式中，高电子迁移率晶体管包括依次并列、且并联设置的多个晶体管单元。多个晶体管单元中包括依次相邻设置的第一晶体管单元、第二晶体管单元、第三晶体管单元。第一晶体管单元和第二晶体管单元共用同一源极，且第一晶体管单元和第二晶体管单元沿源极对称设置。第二晶体管单元和第三晶体管单元共用同一第一漏极，且第二晶体管单元和第三晶体管单元沿第一漏极对称。在每一晶体管单元中，第二漏极位于源极和第一漏极之间的区域，栅极位于源极与第二漏极之间的区域。
在一些可能实现的方式中，高电子迁移率晶体管为GaNHEMT。
本申请实施例还提供一种电子设备，包括发射机；该发射机中采用如前述任一种可能实现的方式中提供的Doherty功率放大器。
附图说明
图1为本申请实施例提供的一种Doherty功率放大器的电路示意图；
图2为本申请实施例提供的一种Doherty功率放大器的电路示意图；
图3为图1的Doherty功率放大器的工作效率曲线；
图4为现有技术中提供的一种高电子迁移率晶体管的结构示意图；
图5为本申请实施例提供的一种高电子迁移率晶体管的结构示意图；
图6为本申请实施例提供的一种高电子迁移率晶体管的结构示意图；
图7为本申请实施例提供的一种Doherty功率放大器中采用的高电子迁移率晶体管的布图设计示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。“安装”、“连接”、“相连”等应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或者一体地连接；可以是直接连接，也可以是通过中间媒介间接，也可以是两个元件内部的连通。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”、“左”、“右”、“顶”、“底”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种电子设备，该电子设备中设置有发射机，并且该发射机中设置有Doherty功率放大器，该Doherty功率放大器中包括至少三路功放电路，该Doherty功率放大器将多路功放电路中的放大管采用一个新型的多沟道高电子迁移率晶体管(high electron mobility transistor，HEMT)进行替代，相当于采用一个裸片可以满足多个放大管的需求，同时还避免了针对多个放大管单独配置栅压，从而简化了Doherty功率放大器的电路复杂度，降低了成本。
本申请对于上述电子设备的设置形式不做限制。示意的，该电子设备可以为手机、平板电脑、笔记本、车载电脑、智能手表、智能手环、雷达、基站等电子产品。
以下对本申请实施例中提供的Doherty功率放大器的具体结构进行示意的说明。
图1为本申请实施例提供的一种3way-Doherty功率放大器的电路示意图。如图1所示，该3way-Doherty功率放大器包括主功放电路1(main)、第一辅功放电路2(peak1)、第二辅功放电路3(peak2)。其中，主功放电路1中包括第一放大管D_1，通过该第一放大管D_1能够对输入至主功放电路的信号进行放大。第一辅功放电路2包括第二放大管D_2，通过该第二放大管D_2能够对输入至第一辅功放电路2的信号进行放大。第二辅功放电路2包括第三放大管D_3，通过该第三放大管D_3能够对输入至第二辅功放电路3的信号进行放大。
此处可以理解的是，Doherty功率放大器中的多路功放电路通常包括一个主功放电路 (main)，以及除主功放电路(main)以外的至少一个辅功放电路(peak)。本申请实施例是以主功放电路(main)和两个辅功放电路2为例进行说明的。在另一些可能实现的方式中，Doherty功率放大器可以包括3路或3路以上的辅功放电路(peak)。
在此基础上，本申请还提供一种新型的双沟道高电子迁移率晶体管(HEMT)，具体结构可以参考图5以及下文的相关说明。参考图1、图2、图5所示，采用该双沟道晶体管(HEMT)对上述第一放大管D_1和第三放大管D_3进行替代，也即第一放大管D_1和第三放大管D_3复用该双沟道晶体管(HEMT)。该双沟道晶体管(HEMT)包括栅极G、源极S、第一沟道层21、第二沟道层22、第一漏极D1、第二漏极D2。第一漏极D1与第一沟道层21电连接，第二漏极D2与第二沟道层22电连接，也即第一漏极D1和第二漏极D2分别连接两个不同的沟道(101、102)。该双沟道晶体管(HEMT)的第一漏极D1作为第一放大管D_1的漏极；该双沟道晶体管(HEMT)的第二漏极D2作为第三放大管D_3的漏极。该双沟道晶体管(HEMT)的栅极G作为第一放大管D_1和第三放大管D_3的栅极，双沟道晶体管(HEMT)的源极S作为第一放大管D_1和第三放大管D_3的源极；也即第一放大管D_1的栅极和第三放大管D_3的栅极相同，复用该双沟道晶体管(HEMT)的栅极；第一放大管D_1的源极和第三放大管D_3的源极相同，复用该双沟道晶体管(HEMT)的源极。
示意的，在该Doherty功率放大器中，可以将双沟道晶体管(HEMT)的源极与接地端连接，栅极连接到该Doherty功率放大器的输入端IN，第一漏极D1和第二漏极D2通过相关电路连接到Doherty功率放大器的输出端OUT。这样一来，输入端IN输入信号经第一放大管D_1和第三放大管D_3进行放大后，分别通过第一漏极D1和第二漏极D2输出至输出端OUT。
综上所述，相比于现有技术中，不同的功放电路中的放大管分别采用不同的裸片而言，在本申请实施例提供的Doherty功率放大器中，参考图1和图2所示，采用第一高电子迁移率晶体管HEMT1(多沟道高电子迁移率晶体管)作为上述主功放电路1、第二辅功放电路3中的两个放大管(D_1、D_3)，在此情况下，主功放电路1和第二辅功放电路3中的放大管采用一个裸片(HEMT1)即可满足需求，第一辅功放电路2采用一个裸片(HEMT2)即可满足需求；同时还避免了针对第一放大管D_1和第三放大管D_3单独配置栅压，从而简化了Doherty功率放大器的电路复杂度，降低了成本。
当然，对于第二辅功放电路3中的第二放大管D_2可以采用单沟道的第二高电子迁移率晶体管HEMT2，在此情况下，采用2个裸片即可实现3路功放电路(1、2、3)的需求。
另外，可以理解的是，在Doherty功率放大器的多路功放电路(1、2、3)中，放大管的开启顺序不同，通常可以是主功放电路(main)中的放大管先开启，辅功放电路(peak)中的放大管后开启。
示意的，在本申请实施例中，可以是第一放大管D_1、第二放大管D_2、第三放大管D_3依次开启，也即第三放大管D_3的开启电压(即栅源电压Vgs_main)大于第二放大管D_2的开启电压(Vgs_peak2)，第二放大管D_2的开启电压大于第一放大管D_1的开启电压(Vgs_peak1)，即Vgs_main＞Vgs_peak1＞Vgs_peak2。以下实施例均是以此为例进行说明的。
示意的，以下对该Doherty功率放大器的工作状态进行简单的说明。
参考图1、图2、图3所示，在一些可能实现的方式中，第一放大管D_1偏置在AB类状态，第二放大管D_2和第三放大管D_3偏置在C类状态，随着输入功率的不同，三路功放电路(1、2、3)的工作状态也会发生变化。
参考图1和图3(对应图1的工作效率曲线)所示，在状态1，输入功率很小，仅第一放大管D_1开启工作，设计电路匹配使第一放大管D_1工作在高阻高效率状态，此时第二放大管D_2和第三放大管D_3因输入功率太小，C类偏置下还没有打开，阻抗呈现开路状态。随着输入功率逐渐增加，到达第一放大管D_1高阻状态下的饱和点时，第一放大管D_1的效率到达最大值，通过合理设置第二放大管D_2的栅压偏置，使得第二放大管D_2在此时临界开启，而第三放大管D_3仍然处于关断状态。此时电路相对于饱和状态回退值α2＝20*log{P_main/(P_main+P_peak1+P_peak2)}。在状态2，第二放大管D_2(peak1)逐渐打开，并对第一放大管D_1(main)的阻抗进行牵引。第二放大管D_2(peak1)到达其效率最大值时，电路达到了第二个峰值效率点，通过合理设置第三放大管D_3(peak2)的栅压偏置，使得第三放大管D_3(peak2)临界开启。此时电路相对于饱和状态回退值α1＝20*log{P_peak1/(P_peak1+P_peak2)}。在状态3，第三放大管D_3(peak2)逐渐打开，而随着第三放大管D_3(peak2)的开启，对第二放大管D_2(peak1)和第一放大管D_1(main)的阻抗进行牵引，当第三放大管D_3(peak2)到达饱和点时，第二放大管D_2(peak1)和第一放大管D_1(main)也到达了功率饱和点，全电路达到饱和功率和第三个峰值效率点。
前述实施例仅是示意的以第一高电子迁移率晶体管HEMT1为双沟道晶体管作为两路功放电路(1、3)中的放大管为例进行示意说明的，但本申请并不限制于此，在一些可能实现的方式中，Doherty功率放大器还可以包括第四功放电路、第五功放电路等；第一高电子迁移率晶体管HEMT1也可以包括三个或三个以上的沟道，从而实现对Doherty功率放大器中具有同相位输入信号的多个放大管进行替代。本申请实施例中均是以3way-Doherty功率放大器为例进行示意说明的。
本申请中对于上述3way-Doherty功率放大器的具体架构不作限制。如图1和图2所示，在一些可能实现的方式中，该Doherty功率放大器中在包括前述的三个放大管(D_1、D_2、D_3)的基础上，还包括：第一微带线10、第二微带线20、第三微带线30、第四微带线40、第五微带线50、功分器100。其中，功分器100包括第一输出端out1和第二输出端。第一输出端out1通过第一微带线10连接到第一高电子迁移率晶体管HEMT1的栅极(也即第一放大管D_1和第三放大管D_3的栅极)，第二输出端out2与第二高电子迁移率晶体管HEMT2的栅极(也即第二放大管D_2的栅极)连接。第一放大管D_1的漏极(即第一漏极)通过第二微带线20连接到合路点O。第二放大管D_2的漏极依次通过第三微带线30、第四微带线40连接到合路点O。第三放大管D_3的漏极(即第二漏极)连接到第三微带线30和第四微带线40之间。合路点O通过第五微带线50连接到Doherty功率放大器的输出端OUT。第一高电子迁移率晶体管HEMT1和第二高电子迁移率晶体管HEMT2的栅极的源极均与接地端连接。
此处可以理解的是，对于上述放大器(D_1、D_2、D_3)的输入端(栅极)和输出端(漏极)连接而言，输入端可以是通过输入匹配电路进行相关的电路连接，输出端可以是通过输出匹配电路进行相关的电路连接。
此处还可以理解的是，在上述Doherty功率放大器中，第一放大管D_1和第三放大管D_3应具有同相相位的输入信号，从而保证采用第一高电子迁移率晶体管HEMT1能够满足两个放大管(D_1、D_3)对输入信号的需求。在此情况下，将第一高电子迁移率晶体管HEMT1的栅极与功分器100的同一输出端(第一输出端out1)连接，而第二高电子迁移率晶体管HEMT2的栅极与功分器100的另一输出端(第二输出端out2)连接。
在上述Doherty功率放大器中，通过第一微带线10对第一输出端out1的输出信号进行相位补偿，以保证主功放电路1的总相位、第一辅功放电路2的总相位、第二辅功放电路3的总相位基本相同；第二微带线20、第三微带线30、第四微带线40以及第五微带线50用于进行阻抗变换，以实现Doherty阻抗牵引的功能。
以下结合上述3way-Doherty功率放大器，对本申请实施例提供的多沟道高电子迁移率晶体管的具体结构做进一步的说明。
图4为传统的单沟道电子迁移率晶体管(HEMT)的结构示意图。参考图4所示，在单沟道HEMT中设置有一个沟道层和一个势垒层，并且在沟道层和势垒层之间的界面(即异质结界面)处产生二维电子气(2-dimension electron gas，2DEG)形成沟道100。
相比之下，参考图5所示，本申请实施例中采用的双沟道HEMT，通过在外延结构中反复生长沟道层和势垒层，从而形成多个沟道(如101、102)，从而突破单沟道器件的理论极限，在保持高电子迁移率的同时增加沟道中的二维电子气(2DEG)面密度，相对于传统的单沟道结构，此种多沟道HEMT能够有效降低导通电阻，提升器件功率密度。
示意的，如图5所示，本申请实施例提供一种双沟道HEMT(即第一高电子迁移率晶体管HEMT1)，该晶体管包括衬底11(substrate)以及依次设置在衬底11上的成核层12(nucleation)、缓冲层13(buffer)、第一沟道层21(channel)、第一势垒层31(barrier)、第二沟道层22(channel)、第二势垒层32(barrier)、帽层40(cap)。其中，第一沟道层21与第一势垒层31之间的界面形成第一沟道101，第二沟道层22与第二势垒层32之间的界面形成第二沟道102。
在此基础上，该晶体管还包括栅极G、源极S、第一漏极D1、第二漏极D2。其中，第一漏极D1与第一沟道层21电连接，第二漏极D2与第二沟道层22电连接。第一漏极D1可以设置在第一沟道层21上，与第一沟道层21之间形成电连接。栅极G、源极S、第二漏极D2可以设置在帽层40上，并且第二漏极D2与第二沟道层22之间通过离子注入的方式形成电连接。源极S与第一沟道层21、第二沟道层22之间过离子注入的方式形成电连接。
上述双沟道HEMT的工作原理而言：两个漏极(D1、D2)与源极S之间的电压(即漏源电压V D1S、V D2S)使得在两个沟道(101、102)内产生横向电场，并在横向电场作用下，二维电子气(2DEG)沿两个异质结界面进行传输形成漏极输出电流(如图5中的箭头示意)。通过控制栅极G输入的电压大小能够控制异质结中势阱的深度，改变沟道(101、102)中二维电子气(2DEG)面密度的大小，从而控制两个漏极(D1、D2)的输出电流。
在此情况下，在将上述双沟道HEMT应用至本申请前述的3way-Doherty功率放大器中时，第一漏极D1相当于前述第一放大管D_1的漏极，第二漏极D2相当于第三放大管D_3的漏极，该双沟道HEMT能够将传统的平面型布局转变为垂直型布局，通过双沟道HEMT实现对两个放大管(D_1、D_3)的替代，这样一来，采用一个裸片即可满足两个 放大管(D_1、D_3)的需求，同时还避免了针对两路功放电路单独配置栅压，简化了Doherty功率放大器的电路复杂度，降低了制作成本。
在前述3way-Doherty功率放大器中，主功放电路1中的第一放大管D_1先于第二辅功放电路3中的第三放大管D_3开启，因此对于第一高电子迁移率晶体管HEMT1而言，通过设置第一漏极D1与第一沟道101(即下沟道)电连接，第二漏极D2与第二沟道102(上沟道)电连接，第一沟道先于第二沟道开启，通过合理的设置相邻沟道之间的距离，从而可以满足主功放电路1(main)和第二辅功放电路3(peak2)的需求。实际中，可以通过合理设置第一沟道和第二沟道之间的距离，来调整第二辅功放电路3(peak2)的开启电压，从而形成互不干扰的两个信号通路，以满足主功放电路1(main)和第二辅功放电路3(peak2)的需求。
本申请对于上述第一漏极D1与第一沟道层21的电连接方式不作限制。示意的，在一些可能实现的方式中，可以设置第一漏极D1与第一沟道层21形成欧姆接触，从而保证第一漏极D1与第一沟道101之间的电连接。类似的可以设置第二漏极D2与第二沟道层22形成欧姆接触，以及源极S与第一沟道层21、第二沟道层22形成欧姆接触。其中，实现源极S、漏极(D1、D2)与沟道层(21、22)之间的欧姆接触方式可以包括但不限于刻蚀欧姆、注入欧姆及高温金属欧姆等。
示意的，在一些可能实现的方式中，如图5所示，可以设置第一漏极D1与第一沟道层21的表面以刻蚀欧姆接触的方式连接，第二漏极D2与第二沟道层22的表面以注入欧姆接触的方式连接，源极S与第一沟道层21、第二沟道层22之间以注入欧姆接触的方式连接。在此情况下，可以采用刻蚀工艺将第一沟道层21上方的膜层去除，从而漏出第一沟道层21的表面，并在第一沟道层21的漏出区域进行第一漏极D1的制作，保证第一漏极D1与第一沟道层21的表面欧姆接触。采用注入工艺在源极S下方的位置进行离子注入形成注入区a1，源极S在该注入区a1与第一沟道层21和第二沟道层22形成欧姆接触。采用注入工艺在第二漏极D2下方的位置进行离子注入形成注入区a2，第二漏极D2通过该注入区a2与第二沟道层22形成欧姆接触。
另外，如图6所示，在一些可能实现的方式中，可以在第一沟道层21与第一势垒层31之间设置第一插入层n1，在第二沟道层22和第二势垒层32之间设置第二插入层n2，通过插入层(n1、n2)的设置能够提高沟道(101、102)处产生的2DEG的电子迁移率。
另外，本申请对于上述衬底11以及晶体管中的其他相关膜层采用的材料不做限制，实际中可以根据需要进行设置即可。
示意的，衬底11可以采用包括但不限于SiC，Si，GaN，GaAs，InP等材料。
示意的，成核层12可以采用包括但不限于AlN，InAlN，InGaN，ScAlN等材料。
示意的，缓冲层13可以采用包括但不限于AlN，GaN，InAlN，InGaN，ScAlN等材料。
示意的，沟道层(21、22)可以采用包括但不限于AlN，GaN，InAlN，InGaN，ScAlN等材料。例如，在一些实施例中，前述实施例中涉及的高电子迁移率晶体管(HEMT1、HEMT2)可以均为GaNHEMT，沟道层(21、22)可以采用GaN。
示意的，势垒层(31、32)可以采用包括但不限于AlN，GaN，InAlN，InGaN，ScAlN等材料。
示意的，插入层(n1、n2)可以采用包括但不限于AlN，GaN，InAlN，InGaN，ScAlN等材料。
示意的，帽层40可以采用包括但不限于SiN，GaN，AlN，InAlN，InGaN，ScAlN等材料。
前述第二高电子迁移率晶体管HEMT2可以采用图4中示出的单沟道HEMT，但本申请并不限制于此。
此外，本领域的技术人员应当理解的是，在实际的布图设计(layout)中，单个HEMT结构可以采用多个并联设置的晶体管单元(cell)，本申请中对多个并联设置的晶体管单元(也即元胞结构)的分布方式不做限制。
示意的，以下图6中的双沟道HEMT为例，以下对第一高电子迁移率晶体管HEMT1中多个晶体管单元的布图设计进行说明。如图7所示，在一些可能实现的方式中，HEMT中可以包括依次并列、且并联设置的多个晶体管单元(如C1、C2、C3)，并且相邻的两个晶体管单元对称设置。具体的，多个晶体管单元中包括依次相邻设置的第一晶体管单元C1、第二晶体管单元C2、第三晶体管单元C3。其中，第一晶体管单元C1和第二晶体管单元C2同用同一源极S，也即第一晶体管单元C1和第二晶体管单元C2采用同一源极图案；并且第一晶体管单元C1和第二晶体管单元C2沿该源极对称设置。第二晶体管单元C2和第三晶体管单元C3共用第一漏极D1，也即第二晶体管单元C2和第三晶体管单元C3采用共用第一漏极图案，且第二晶体管单元C2和第三晶体管单元C3沿第一漏极D1对称设置。另外，在每一晶体管单元(如C1、C2、C3)中，第二漏极D2位于源极S与第一漏极D1之间的区域，栅极G位于源极S与第二漏极D2之间的区域。
当然，在第一高电子迁移率晶体管HEMT1中，所有的晶体管单元的源极S均连接至同一导电图案作为该晶体管的源极，所有的第一漏极D1通过引线均连接至同一导电图案作为该晶体管的一个输出引脚，所有的第二漏极D2通过引线均连接至同一导电图案作为该晶体管的另一个输出引脚，以通过两个输出引脚与后级电路进行连接。其中，连接第一漏极D1的引线与连接第二漏极D2的引线之间可以通过介质桥或空气桥隔离，以保证两个输出引脚的正常工作。
可以理解的是，上述第一晶体管单元C1、第二晶体管单元C2、第三晶体管单元C3并不特指第一高电子迁移率晶体管HEMT1中固定的三个晶体管单元，其仅为相对概念，可以是多个晶体管单元中任意依次相邻设置的三个晶体管单元。
另外，对于单沟道的第二高电子迁移率晶体管HEMT2中多个晶体管单元的布图设计而言，可以在前述第一高电子迁移率晶体管HEMT1的晶体管单元中省去第二漏极D2的布图。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种Doherty功率放大器，其特征在于，包括主功放电路、第一辅功放电路、第二辅功放电路；
    所述主功放电路包括第一放大管，所述第一放大管用于对输入至所述主功放电路的信号进行放大；
    所述第一辅功放电路包括第二放大管，所述第二放大管用于对输入至所述第一辅功放电路的信号进行放大；
    所述第二辅功放电路包括第三放大管，所述第三放大管用于对输入至所述第二辅功放电路的信号进行放大；
    所述Doherty功率放大器包括高电子迁移率晶体管；所述高电子迁移率晶体管包括源极、栅极、第一沟道层、第二沟道层、第一漏极、第二漏极；所述第一漏极与所述第一沟道层电连接，所述第二漏极与所述第二沟道层电连接；
    所述第一放大管的源极和所述第三放大管的源极相同，复用所述高电子迁移率晶体管的源极；
    所述第一放大管的栅极和所述第三放大管的栅极相同，复用所述高电子迁移率晶体管的栅极；
    所述高电子迁移率晶体管的第一漏极作为所述第一放大管的漏极；
    所述高电子迁移率晶体管的第二漏极作为所述第三放大管的漏极。
  2. 根据权利要求1所述的Doherty功率放大器，其特征在于，
    所述第二放大管的开启电压大于所述第三放大管的开启电压。
  3. 根据权利要求1或2所述的Doherty功率放大器，其特征在于，
    所述高电子迁移率晶体管的源极与接地端连接；
    所述高电子迁移率晶体管的栅极的输入信号经所述第一放大管和所述第三放大管进行放大后，分别通过所述第一漏极和所述第二漏极进行输出。
  4. 根据权利要求1-3任一项所述的Doherty功率放大器，其特征在于，
    所述Doherty功率放大器还包括：第一微带线、第二微带线、第三微带线、第四微带线、第五微带线、功分器；所述功分器包括第一输出端和第二输出端；
    所述第一输出端通过所述第一微带线连接到所述高电子迁移率晶体管的栅极；
    所述第二输出端与所述第二放大管的栅极连接；
    所述第一漏极通过所述第二微带线连接到合路点；
    所述第二放大管的漏极依次通过所述第三微带线、所述第四微带线连接到所述合路点；
    所述第二漏极连接到所述第三微带线和所述第四微带线之间；
    所述合路点通过所述第五微带线连接到所述Doherty功率放大器的输出端。
  5. 根据权利要求1-4任一项所述的Doherty功率放大器，其特征在于，
    所述高电子迁移率晶体管包括：
    衬底；
    在所述衬底上层叠设置的所述第一沟道层和第一势垒层，所述第一势垒层位于所述第一沟道层远离所述衬底的一侧；
    在所述第一势垒层上层叠设置的所述第二沟道层和第二势垒层，所述第二势垒层位于所述第二沟道层远离所述衬底的一侧；
    帽层，所述帽层设置在所述第二势垒层远离所述衬底的一侧；
    第一漏极，所述第一漏极设置在所述第一沟道层上、且与所述第一沟道层电连接；
    设置在所述帽层上的源极、栅极、第二漏极，所述第二漏极与所述第二沟道层电连接，所述源极与所述第一沟道层、所述第二沟道层均电连接。
  6. 根据权利要求5所述的Doherty功率放大器，其特征在于，
    所述第一漏极与所述第一沟道层欧姆接触；
    所述第二漏极与所述第二沟道层欧姆接触；
    所述源极与所述第一沟道层、所述第二沟道层欧姆接触。
  7. 根据权利要求5或6所述的Doherty功率放大器，其特征在于，
    所述第一沟道层和所述第一势垒层之间设置有第一插入层；
    所述第二沟道层和所述第二势垒层之间设置有第二插入层。
  8. 根据权利要求5-7任一项所述的Doherty功率放大器，其特征在于，
    所述衬底与所述第一沟道层之间设置有成核层、缓冲层；
    所述成核层相对于所述缓冲层靠近所述衬底。
  9. 根据权利要求5-8任一项所述的Doherty功率放大器，其特征在于，
    所述高电子迁移率晶体管包括依次并列、且并联设置的多个晶体管单元；
    所述多个晶体管单元中包括依次相邻设置的第一晶体管单元、第二晶体管单元、第三晶体管单元；
    所述第一晶体管单元和所述第二晶体管单元共用源极、且沿所述源极对称设置；
    所述第二晶体管单元和所述第三晶体管单元共用第一漏极、且沿所述第一漏极对称；
    在每一所述晶体管单元中，第二漏极位于所述源极和所述第一漏极之间的区域，所述栅极位于所述源极与所述第二漏极之间的区域。
  10. 根据权利要求1-9任一项所述的Doherty功率放大器，其特征在于，所述高电子迁移率晶体管为GaNHEMT。
  11. 一种电子设备，其特征在于，包括发射机；所述发射机中采用如权利要求1-10任一项所述的Doherty功率放大器。
PCT/CN2022/083157 2022-03-25 2022-03-25 Doherty功率放大器及电子设备 WO2023178682A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/083157 WO2023178682A1 (zh) 2022-03-25 2022-03-25 Doherty功率放大器及电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/083157 WO2023178682A1 (zh) 2022-03-25 2022-03-25 Doherty功率放大器及电子设备

Publications (1)

Publication Number Publication Date
WO2023178682A1 true WO2023178682A1 (zh) 2023-09-28

Family

ID=88099608

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/083157 WO2023178682A1 (zh) 2022-03-25 2022-03-25 Doherty功率放大器及电子设备

Country Status (1)

Country Link
WO (1) WO2023178682A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037521A1 (en) * 2009-08-14 2011-02-17 Electronics And Telecommunications Research Institute Power amplifier having depletion mode high electron mobility transistor
CN102158184A (zh) * 2011-04-29 2011-08-17 中兴通讯股份有限公司 一种功率放大管以及功率放大方法
CN102460692A (zh) * 2009-06-29 2012-05-16 高通股份有限公司 具有位于集成电路裸片下的负载电感器的集成式功率放大器
CN103178786A (zh) * 2011-12-26 2013-06-26 瑞典爱立信有限公司 多路Doherty放大器
CN105932969A (zh) * 2015-12-30 2016-09-07 苏州能讯高能半导体有限公司 一种高效率功率放大器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102460692A (zh) * 2009-06-29 2012-05-16 高通股份有限公司 具有位于集成电路裸片下的负载电感器的集成式功率放大器
US20110037521A1 (en) * 2009-08-14 2011-02-17 Electronics And Telecommunications Research Institute Power amplifier having depletion mode high electron mobility transistor
CN102158184A (zh) * 2011-04-29 2011-08-17 中兴通讯股份有限公司 一种功率放大管以及功率放大方法
CN103178786A (zh) * 2011-12-26 2013-06-26 瑞典爱立信有限公司 多路Doherty放大器
CN105932969A (zh) * 2015-12-30 2016-09-07 苏州能讯高能半导体有限公司 一种高效率功率放大器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GREBENNIKOV ANDREI, WONG JAMES, DEGUCHI HIROAKI: "High-Power High-Efficiency GaN HEMT Doherty Amplifiers for Base Station Applications", IEICE TRANSACTIONS ON ELECTRONICS, INSTITUTE OF ELECTRONICS, TOKYO, JP., vol. E104.C, no. 10, 1 October 2021 (2021-10-01), Tokyo, JP. , pages 488 - 495, XP093094302, ISSN: 0916-8524, DOI: 10.1587/transele.2021MMI0003 *

Similar Documents

Publication Publication Date Title
EP2447998A1 (en) Semiconductor device
US11515842B2 (en) Doherty power amplifiers and devices with low voltage driver stage in carrier-path and high voltage driver stage in peaking-path
CN101894863B (zh) 场效应晶体管
Santhakumar et al. Two-stage high-gain high-power distributed amplifier using dual-gate GaN HEMTs
US11594628B2 (en) Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors
KR101011591B1 (ko) 다수의 전압 제어 커패시터를 갖는 반도체 장치 및 회로
KR102055839B1 (ko) 질화계 반도체 소자
US8106503B2 (en) High frequency semiconductor device
JP2010278280A (ja) 高周波半導体装置
US20220376105A1 (en) Field effect transistor with selective channel layer doping
WO2023178683A1 (zh) 高电子迁移率晶体管、Doherty功率放大器及电子设备
US8809907B2 (en) Leakage barrier for GaN based HEMT active device
CN113647015A (zh) 晶体管内负载调制
KR20110020162A (ko) 멀티 칩 모듈 구조를 갖는 고주파 회로
WO2023178682A1 (zh) Doherty功率放大器及电子设备
Ueda et al. GaN transistors for power switching and millimeter-wave applications
US20220406925A1 (en) Hemt transistor
Koudymov et al. Monolithically integrated high-power broad-band RF switch based on III-N insulated gate transistors
EP4052300B1 (en) Field-effect transistor having improved layout
CN114843335A (zh) 一种基于非对称欧姆再生长区域的高线性GaN HEMT器件及其制备方法
JP2010245351A (ja) 半導体装置
CN207068796U (zh) 具有石墨烯掩埋散热层和源接地的GaNMMIC器件
Neininger et al. Advances in GaN Devices and Circuits at Higher mm-Wave Frequencies
Joshin et al. Recent progress of high power GaN-HEMT for wireless application
EP4333296A1 (en) Digital rf amplifier

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22932743

Country of ref document: EP

Kind code of ref document: A1