WO2023173999A1 - 一种数据读取方法及装置 - Google Patents

一种数据读取方法及装置 Download PDF

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Publication number
WO2023173999A1
WO2023173999A1 PCT/CN2023/076926 CN2023076926W WO2023173999A1 WO 2023173999 A1 WO2023173999 A1 WO 2023173999A1 CN 2023076926 W CN2023076926 W CN 2023076926W WO 2023173999 A1 WO2023173999 A1 WO 2023173999A1
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Prior art keywords
memory
data
information
valid
processor
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PCT/CN2023/076926
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English (en)
French (fr)
Inventor
黎燕
张箭
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华为技术有限公司
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Publication of WO2023173999A1 publication Critical patent/WO2023173999A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

Definitions

  • the present application relates to the field of data storage technology, and in particular, to a data reading method and device.
  • SSD Solid state disk
  • SSD uses flash NAND as a storage medium to store data.
  • SSD includes flash translation layer (FTL) and FTL mapping table.
  • FTL flash translation layer
  • PBA physical block address
  • the controller reads and writes data based on the converted PBA.
  • the FTL mapping table can be used to record the conversion relationship between logical block addresses and physical block addresses in SSD.
  • SSDs Compared with mechanical hard drives, SSDs have the characteristics of fast reading and writing, light weight, low energy consumption and small size, so they are widely used.
  • the host traverses and reads the data in the SSD, it accesses all the LBAs in the SSD once to read the data in the SSD.
  • the flash NAND of SSD includes some space that does not store data, it can also be called free space.
  • the free space has a corresponding LBA.
  • this part of the LBA does not have a corresponding PBA in the FTL mapping table.
  • the processor accesses an LBA that does not have a corresponding PBA, the SSD feeds back invalid data to the processor. Therefore, the processor also needs to perform magic word magic check or cyclic redundancy check (CRC) on the data read through the traversal to filter out invalid data in the data to obtain valid data.
  • CRC cyclic redundancy check
  • the processor traverses and reads the data in the SSD, the reading of the free space takes up extra time, resulting in inefficient traversal reading; on the other hand, the data read by the processor includes invalid data, which also requires Only valid data can be obtained by verifying the read data, which reduces the accuracy of the data.
  • This application provides a data reading method and device, which relate to the field of data storage technology and are used to improve the efficiency of traversal reading and the accuracy of data.
  • a data reading method includes: a processor sends a query command to a memory.
  • the query command is used to query the valid information of the data stored in the memory.
  • the valid information is used to indicate whether the data is Valid data;
  • the processor receives the valid information from the memory, and when the valid information indicates that the data is valid data, the processor sends an access request to the memory, where the access request includes the address information of the valid data;
  • the processor receives data information from the memory, the data information including the valid data.
  • the processor when the processor traverses and reads the data in the memory, the processor first sends a query command to the memory.
  • the query command is used to query the valid information of the data stored in the memory.
  • the valid information is used to indicate the data. Whether it is valid data, the processor receives the valid information from the memory, and when the valid information indicates When indicating that the data is valid data, the processor sends an access request to the memory.
  • the access request includes the address information of the valid data to traverse and read the valid data stored in the memory.
  • the processor receives the data information from the memory, The data information includes the valid data, thereby obtaining the valid data stored in the memory.
  • the processor only accesses the storage space where the valid data is stored in the memory, instead of accessing all the storage spaces in the memory. All have been accessed.
  • the processor traverses and reads the data in the memory, it accesses all the storage spaces in the memory once. That is, the processor accesses the storage spaces in the memory that store valid data and the storage spaces that do not store data.
  • this technical solution improves the efficiency of traversal reading; in addition, in this solution, the processor accesses the memory according to the address of the valid data in the memory to read the memory There is no need to verify the read data to obtain valid data.
  • the processor needs to verify the read data to obtain valid data, which improves the accuracy of the data. sex.
  • the query command is a Non-Volatile Memory Host Controller Interface Specification NVME command, a Serial Attached SCSI SAS command or a Serial Advanced Technology Attachment SATA command.
  • the query command can be an NVME command, a SAS command or a SATA command, which increases the diversity of choices.
  • the valid information is address information indicating the valid data in the form of a bitmap or a linked list.
  • the method further includes: the processor sending a deletion command to the memory, where the deletion command is used to delete the target data.
  • the processor deletes the target data stored in the memory by sending a delete command to the memory.
  • the processor traverses and reads the data in the memory, it avoids returning valid information of the target data, that is, it avoids returning
  • the address information of the target data improves the traversal reading rate and further improves the accuracy of the effective data.
  • a data reading method includes: the memory receives a query command from the processor, the query command is used to query the valid information of the data stored in the memory, and the valid information is used to indicate whether the data is is valid data; the memory sends the valid information to the processor; the memory receives an access request from the processor, where the access request includes the address information of the valid data; the memory sends data information to the processor, the The data information includes the valid data.
  • the memory when the processor traverses and reads the data in the memory, the memory receives a query command from the processor.
  • the query command is used to query the valid information of the data stored in the memory, and the valid information is used to indicate the data.
  • the memory sends the valid information to the processor, the memory receives an access request from the processor, where the access request includes the address information of the valid data, and the memory sequentially performs operations based on the address information of the valid data.
  • Read valid data and send the read valid data to the processor.
  • the memory only reads the valid data based on the address information of the valid data.
  • the storage space storing valid data in the memory is read, instead of reading every storage space in the memory.
  • the memory will all Compared with reading the entire storage space once, the efficiency of traversal reading is improved; in addition, the memory reads valid data according to the address of the valid data, and valid data can be obtained without verifying the read data.
  • the memory will traverse the read data to verify the ability to effectively Compared with the data, the accuracy of the data is improved.
  • the method further includes: the memory queries address mapping information according to the logical block address of the memory to determine the location of the valid data. Physical block address, the address mapping information is used to indicate the mapping relationship between the logical block address and the physical block address of the data stored in the memory.
  • the address mapping information is queried according to the logical block address of the memory to determine the physical block address of the valid data, thereby determining the address information of the valid data in the memory, and the memory stores the address of the valid data.
  • the information is sent to the processor, and the processor sends an access request based on the address information of the valid data to read the valid data in the memory. That is, the memory only performs an access request on the storage space where the valid data is stored in the memory based on the address information of the valid data.
  • Reading instead of reading every storage space in the memory, compared with the existing technology, when the processor traverses and reads the data in the memory, the memory reads all the storage spaces once , improving the efficiency of traversal reading; in addition, the memory reads valid data according to the address of the valid data, and valid data can be obtained without verifying the read data. Unlike the existing technology, the memory will Traversing the read data for verification improves the accuracy of the data compared with valid data.
  • the method further includes: the memory reads the valid data from the memory according to the address information of the valid data.
  • the memory reads the valid data from the memory according to the address of the valid data.
  • the memory accesses each storage space once to read the data in the memory. Compared with this, the efficiency of traversal reading is improved.
  • the memory reads valid data according to the address of the valid data, and valid data can be obtained without verifying the read data.
  • the memory Comparing the read data with valid data for verification the accuracy of the data is improved.
  • the method further includes: the memory receiving a deletion command from the processor, and deleting the target data according to the deletion command.
  • the memory receives a delete command from the processor and deletes the target data according to the delete command.
  • the processor traverses and reads the data in the memory, it avoids returning valid information of the target data, that is, it avoids Returning the address information of the target data improves the rate of traversal reading and further improves the accuracy of effective data.
  • the memory also stores address information of the target data
  • the method further includes: deleting the address information of the target data from the memory.
  • the memory deletes the address information of the target data, preventing the address information of the target data from occupying the storage space of the memory, and improving the utilization of the storage space in the memory.
  • the query command is a Non-Volatile Memory Host Controller Interface Specification NVME command, a Serial Attached SCSI SAS command or a Serial Advanced Technology Attachment SATA command.
  • the query command can be an NVME command, a SAS command or a SATA command, which increases the diversity of choices.
  • the valid information is address information indicating the valid data in the form of a bitmap or a linked list.
  • a processor configured to send a query command to a memory.
  • the query command is used to query the valid information of the data stored in the memory.
  • the valid information is used to indicate the data. Whether it is valid data; the receiving unit is used to receive valid information from the memory; when the valid information indicates that the data is valid data, the sending unit is also used to send an access request to the memory, where the access request includes The address information of the valid data; the receiving unit is also used to receive data information from the memory, where the data information includes the valid data.
  • the query command is a Non-Volatile Memory Host Controller Interface Specification NVME command, a Serial Attached SCSI SAS command or a Serial Advanced Technology Attachment SATA command.
  • the valid information is address information indicating the valid data in the form of a bitmap or a linked list.
  • the sending unit is further configured to: send a deletion command to the memory, where the deletion command is used to delete the target data.
  • a fourth aspect provides a memory, the memory including: a receiving unit for receiving a query command from a processor, the query command is used to query the address information of data stored in the memory, and the valid information is used to indicate the data Whether it is valid data; the sending unit is used to send the valid information to the processor; the receiving unit is also used to receive an access request from the processor, where the access request includes the address information of the valid data; the sending unit The unit is also used to send data information to the processor, where the data information includes the valid data.
  • the memory further includes a query unit: after the receiving unit receives the query command from the processor, the query unit is used to query address mapping information according to the logical block address of the memory. to determine the physical block address of the valid data, and the address mapping information is used to indicate the mapping relationship between the logical block address and the physical block address of the data stored in the memory.
  • the memory further includes a reading unit: after the receiving unit receives the access request from the processor, the reading unit is configured to read from the address information of the valid data according to the address information of the valid data. Read the valid data from the memory.
  • the query command is a Non-Volatile Memory Host Controller Interface Specification NVME command, a Serial Attached SCSI SAS command or a Serial Advanced Technology Attachment SATA command.
  • the valid information is address information indicating the valid data in the form of a bitmap or a linked list.
  • the memory further includes a deletion unit: the receiving unit is also used to receive a deletion command from the processor, and the deletion unit is used to delete the target data according to the deletion command.
  • the memory also stores address information of the target data
  • the deletion unit is further configured to delete the address information of the target data.
  • an electronic device in a fifth aspect, includes: a processor and a memory.
  • the processor is the processor provided by the above third aspect or any possible implementation of the third aspect.
  • the memory is the above processor.
  • the memory provided by the fourth aspect or any possible implementation manner of the fourth aspect.
  • a computer-readable storage medium includes computer instructions.
  • the computer instructions When the computer instructions are run on a processor, the computer instructions execute the above-mentioned first aspect or any one of the first aspects. Relevant steps in possible implementation methods.
  • a computer-readable storage medium includes computer instructions.
  • the computer instructions When the computer instructions are run on a memory, the computer instructions execute the above second aspect or any one of the second aspects. Relevant steps in possible implementations.
  • a computer program product containing instructions is provided.
  • the computer program product When the computer program product is run on a computer device, it causes the processor to execute the above-mentioned first aspect or any possible implementation of the first aspect. related steps.
  • a computer program product containing instructions is provided, which when the computer program product is run on a computer device, causes the memory to execute the above second aspect or any possible implementation manner of the second aspect. related steps.
  • processor, memory, electronic device, computer-readable storage medium and computer program product provided above can be used to execute the corresponding method provided above. Therefore, the beneficial effects it can achieve can be referred to the above. The beneficial effects of the corresponding methods provided in this article will not be repeated here.
  • Figure 1 is a schematic structural diagram of an SSD provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a flash memory particle provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a terminal device provided by an embodiment of the present application.
  • Figure 5 is a flow chart of a data reading method provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of a mapping table provided by an embodiment of the present application.
  • Figure 7 is a schematic diagram of a processor and SSD provided by an embodiment of the present application.
  • Figure 8 is a flow chart of another data reading method provided by an embodiment of the present application.
  • Figure 9 is a flow chart of a data deletion method provided by an embodiment of the present application.
  • Figure 10 is a schematic structural diagram of a processor provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • At least one refers to one or more, and “plurality” refers to two or more.
  • “And/or” describes the association of associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the related objects are in an “or” relationship.
  • “At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • At least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.
  • the embodiments of this application use words such as “first” and “second” to distinguish identical or similar items that have basically the same functions and effects.
  • the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as “first” and “second” do not limit the number and execution order.
  • SSD solid state disk
  • Figure 1 is a schematic structural diagram of an SSD, including: a controller 01, a memory 02 and multiple flash memory particles 03.
  • the controller 01 is the control center of the SSD, using various interfaces and lines to connect various parts of the entire SSD.
  • the controller 01 can be used to control the reading and writing of the memory 02 and the multiple flash memory particles 03.
  • the controller 01 It can be used to receive traversal access requests from the processor to traverse read multiple flash memory particles 03.
  • the controller 01 is also used to manage address information in the SSD, which may include a logical block address (logical block address, LBA) and a physical block address (physics block address, PBA).
  • the controller 01 is also used to send information to the processor.
  • the information may include valid information and data information in the method embodiments provided below.
  • Memory 02 is the internal memory that directly exchanges data with the controller 01. It can be used to store temporary data of the operating system or other running programs and information created during SSD use.
  • Multiple flash memory particles 03 serve as storage media for storing data and address information corresponding to the data.
  • the address information may include the logical block address (LBA) and physical block address (physics block address) of the data. PBA).
  • LBA logical block address
  • PBA physical block address
  • the flash memory particle 03 includes a plurality of memory chips Die, each memory chip among the plurality of memory chips includes a plurality of memory blocks Block, and each of the plurality of memory blocks A storage block includes multiple storage pages.
  • the flash memory particles may be flash memory NAND particles.
  • FIG. 2 is a schematic structural diagram of a flash memory NAND particle.
  • the flash memory NAND particle includes four memory chips and can be represented as D1 to D4.
  • the chip includes two memory blocks and can be represented as B1 and B2, each memory block in B1 and B2 includes 10 memory pages and can be represented as P1 to P10.
  • a flash memory particle includes 4 memory chips, each memory chip includes 2 memory blocks, and each memory block includes 10 memory pages as an example.
  • the storage capacity of flash NAND particles is related to the number of storage chips included in the flash NAND particles and the capacity of the memory chips.
  • the capacity of a single memory chip is generally 8 gigabytes (GB), 16GB, 32GB or larger. If a single flash NAND particle has 8 memory chips, the capacity of a single flash NAND particle can be 64GB. , 128GB, 256GB or larger.
  • This application provides a data reading method.
  • the data reading method is applied in electronic equipment.
  • the processor traverses and reads the data in the memory, it queries the effective information of the data stored in the memory by sending a query command to the memory.
  • the valid information is used to indicate whether the data is valid data.
  • the processor sends an access request based on the address information of the valid data, that is, the processor only stores valid data in the memory. Space is accessed to obtain the data in the memory.
  • the processor traverses and reads the data in the memory, it accesses each storage space in the memory (the storage space that stores valid data and the space that does not store data). Compared with one time, it improves the efficiency of traversal reading and further improves the accuracy of data.
  • the electronic device includes a server and a memory.
  • the electronic device may also include a terminal device, where the memory may be an external memory.
  • FIG. 3 is a schematic structural diagram of an electronic device.
  • the electronic device may include a server 10 and an external storage.
  • Device 11 may include a server 10 and an external storage.
  • the server 10 can be used to query and access the external memory 11.
  • the server 10 can include a processor, and the processor can query the external memory 11 by sending query commands and access requests to the external memory 11. Inquiries and visits.
  • the server 10 is also used to receive information from the external memory 11, and the information may include valid information and data information.
  • the external memory 11 can be used to receive query commands and access requests sent by the server 10 .
  • the external memory 11 can include a controller, and the controller can be used to receive query commands and access requests sent by the server 10 .
  • the controller is also used to send information to the server 10, and the information may include valid information and data information.
  • the external memory 11 may be an SSD, and the SSD may be the SSD shown in FIG. 1 above.
  • the processor in the server 10 can communicate with the external memory 11 using different protocols, and when different protocols are used, the connection methods between the server 10 and the external memory 11 are different. Three different communication protocols between the processor and the external memory 11 will be described below.
  • the processor can communicate with the external memory 11 using a non-volatile memory controller interface specification (non-volatile memory express, NVME) protocol.
  • NVME non-volatile memory express
  • the server 10 communicates with the external memory 11.
  • the external memories 11 are connected through the PCI-E bus.
  • the processor can communicate with the external memory 11 using the serial attached SCSI (SAS) protocol.
  • SAS serial attached SCSI
  • the server 10 and the external memory 11 communicate through SAS. bus connection.
  • the processor can communicate with the external memory 11 using a serial advanced technology attachment (SATA) protocol. At this time, the connection between the server 10 and the external memory 11 Connected via ATA bus.
  • SAS serial attached SCSI
  • SATA serial advanced technology attachment
  • the query commands and access requests sent by the processor to the external memory 11 will also be encapsulated into a format corresponding to the communication protocol, and the memory 11 will The information sent will also be encapsulated into a format corresponding to the communication protocol.
  • the query command sent by the processor to the memory 11 may be an NVME command, a SAS command or a SATA command.
  • the terminal device may include but is not limited to a personal computer, a server computer, a mobile device (such as a mobile phone, a tablet computer, a media player, etc.), a wearable device, a vehicle-mounted device, a consumer terminal device, Mobile robots and drones, etc.
  • a mobile device such as a mobile phone, a tablet computer, a media player, etc.
  • a wearable device such as a wearable device, a vehicle-mounted device, a consumer terminal device, Mobile robots and drones, etc.
  • FIG. 4 is a schematic structural diagram of a terminal device provided by an embodiment of the present application.
  • the terminal device includes a processor 101, a memory 102, a sensor component 103, a multimedia component 104, a power supply 105, and an input/output interface 106.
  • the processor 101 can also be the control center of the terminal device, using various interfaces and lines to connect various parts of the entire device, by running or executing software programs and/or software modules stored in the memory 102, and calling the software stored in the memory 102.
  • the data in 102 performs various functions of the terminal device and processes data, thereby overall monitoring the terminal device.
  • the processor 101 may include one or more processing units.
  • the processor 101 may include a central processing unit (CPU), an application processor (AP), and a modem processor. , graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor and/or Neural Networks Processor (neural-network processing unit, NPU), etc.
  • CPU central processing unit
  • AP application processor
  • modem processor graphics processing unit
  • ISP image signal processor
  • DSP digital signal processor
  • NPU Neural Networks Processor
  • different processing units can be independent devices or integrated in one or more processors.
  • the processor 101 can be used to send instructions to the memory 102, and the instructions can include query commands, access requests, and deletion commands.
  • the processor 101 is also used to receive information from the memory 102, which information may include data information and valid information.
  • the memory 102 can be used to store data, software programs and software modules; it mainly includes a stored program area and a stored data area, wherein the stored program area can store an operating system and at least one application program required for a function, such as a sound playback function or an image playback function. etc.; the storage data area can store data created based on the use of the terminal device, such as audio data, image data, or table data, etc.
  • the memory 102 may include internal memory, high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.
  • the internal memory may be internal memory.
  • the memory 102 may include an external memory, and the external memory may be used to receive instructions sent by the processor 101.
  • the external memory may include a controller, and the controller may be used to receive instructions sent by the processor 101. instructions.
  • the controller is also used to send information to the processor 101, and the information may include valid information and data information.
  • the external memory may be an SSD, and the SSD may be the SSD shown in Figure 1 above.
  • the sensor component 103 includes one or more sensors for providing various aspects of status assessment for the terminal device.
  • the sensor component 103 may include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor or a temperature sensor. Through the sensor component 103, the acceleration/deceleration, orientation, open/closed status, relative positioning or terminal of the terminal device can be detected. Temperature changes of equipment, etc.
  • the sensor component 103 may also include a light sensor.
  • the sensor component 103 may also include a light sensor for detecting light in the surrounding environment.
  • the multimedia component 104 provides a screen for an output interface between the terminal device and the user.
  • the screen may be a touch panel, and when the screen is a touch panel, the screen may be implemented as a touch screen to receive input signals from the user.
  • the touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide action.
  • the multimedia component 104 also includes at least one camera.
  • the multimedia component 104 includes a front camera and/or a rear camera. When the terminal device is in an operating mode, such as a shooting mode or a video mode, the front camera and/or the rear camera can receive external multimedia data.
  • Each front-facing camera and rear-facing camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.
  • the power supply 105 is used to provide power to various components of the terminal device.
  • the power supply 105 may include a power management system, one or more power supplies, or other components associated with generating, managing, and distributing power to the terminal device.
  • the input/output interface 106 provides an interface between the processor 101 and a peripheral interface module.
  • the peripheral interface module can be a keyboard, a mouse, or a universal serial bus (universal serial bus, USB) device.
  • the terminal device and the external memory communicate through the input/output interface 106 .
  • the data reading method provided by the embodiment of the present application will be introduced below with reference to the electronic device shown in Figure 3 and the terminal device shown in Figure 4 .
  • the memory in the following embodiments may refer to the external memory in Figure 3 above. memory.
  • Figure 5 is a flow chart of a data reading method provided by an embodiment of the present application.
  • the data reading method includes:
  • S501 The processor sends a query command to the memory.
  • the query command is used to query the valid information of the data stored in the memory.
  • the valid information is used to indicate whether the data is valid data.
  • the memory may include at least one flash memory particle, each of the at least one flash memory particle may include a plurality of memory chips, and each of the plurality of memory chips may include a plurality of memory blocks, and the plurality of memory chips may include a plurality of memory blocks.
  • Each of the memory blocks may include a plurality of memory pages, and each of the plurality of memory pages may include a plurality of memory units.
  • the following description takes the memory including one flash memory particle N1 as an example.
  • the flash memory particle N1 includes a first memory chip D1 and a second memory chip D2.
  • the memory chip may include a first memory block B1 and a second memory block B2.
  • Any memory block includes 10 memory pages P1 to P10.
  • Each of the memory pages P1 to P10 may include at least one memory unit. That is, the flash memory particle includes multiple memory units, and each of the multiple memory units Storage units can be used to store data.
  • the memory includes the above-mentioned flash memory particle N1 as an example for description.
  • the query command may include all logical block addresses of the memory, and the query command may also include partial logical block addresses of the memory. The above two situations are explained below respectively.
  • the query command includes a partial logical block address of the memory.
  • the partial logical block address is used to indicate part of the storage space in the memory.
  • the part of the storage space can be part of the flash memory granule, part of the storage block in the same flash memory granule, part of the storage page in the same storage block, or the same storage space. Part of the page storage unit.
  • the query command includes a partial logical block address of the memory
  • the partial logical block address is continuous.
  • the flash memory particle N1 includes 10 storage units, and each storage unit corresponds to a logical block address. That is, the flash memory particle N1 includes 10 logical block addresses.
  • the query command can include 5 logical areas in the flash memory particle N1. Block address.
  • the LBAs corresponding to the five storage units are continuous and can be expressed as LBA0 to LBA4.
  • the query command includes all logical block addresses of the memory, and all the logical block addresses can be used to indicate the entire storage space of the memory.
  • the query command may include the first logical block address and address length of the memory, and the address length is the length of all logical block addresses in the memory except the first logical block address; or the query command may also include Including the last logical block address and address length of the memory. The address length is the length of all logical block addresses in the memory except the last logical block address.
  • the query command may also include the first logical block address of the memory. Block address and tail logical block address.
  • the query command including the first logical block address and address length of the memory
  • the query command is LBA0 and Address length 10.
  • the query command includes the first logical block address and address length of the memory, and the query command includes all logical block addresses of the memory.
  • the query command is also encapsulated into different formats.
  • the three formats of this query command are described below.
  • the NVME protocol is used to communicate between the processor and the memory, and the query command is encapsulated into an NVME command.
  • the SAS protocol is used to communicate between the processor and the memory.
  • the query command is encapsulated into a SAS command.
  • the SATA protocol is used for communication between the processor and the memory, and the query command is encapsulated into a SATA command.
  • the valid information may include address mapping information indicating a mapping relationship between a logical block address and a physical block address of data stored in the memory.
  • the valid information can be stored in the memory.
  • the valid information can be stored in the flash memory particles of the memory.
  • the valid information can also be stored in a storage device outside the memory.
  • the valid information can be stored in the processing unit. in the processor's memory.
  • the effective information is stored in the memory as an example for description.
  • the multiple storage units included in the memory there may be data stored in some storage units (or the stored data is valid data), and there may be no data stored in some storage units (or the stored data is said to be valid data). invalid data).
  • the data stored in the above-mentioned memory may include all valid data stored in the memory.
  • the memory receives a query command from the processor.
  • the query command is used to query the valid information of the data stored in the memory.
  • the valid information is used to indicate whether the data is valid data.
  • the memory queries the address mapping information (ie, valid information) of the data stored in the memory according to the LBA of the memory to determine whether the LBA has a corresponding PBA. If the LBA has a corresponding PBA, then the Data is stored in the storage unit corresponding to the LBA. The data is valid data. The PBA is the physical block address of the valid data. Therefore, the address mapping information of the data stored in the memory can be queried to determine the location of the valid data stored in the memory. Physical block address.
  • the effective information can be stored in a table, which can also be called a mapping table.
  • the mapping table can be a flash translation layer (FTL) mapping table.
  • the mapping table may include at least one sub-mapping table.
  • the at least one sub-mapping table may include one sub-mapping table or multiple sub-mapping tables. Different sub-mapping tables may be used to indicate address mapping information of different storage spaces.
  • the granularity of the storage space may be a memory chip, a memory block, a memory page, etc., and the embodiment of the present application does not specifically limit this.
  • the mapping table may include a first sub-mapping table.
  • the first sub-mapping table stores address mapping information of valid data in the flash memory particle N1; or the mapping table may include a first sub-mapping table and The second sub-mapping table, the first sub-mapping table and the second sub-mapping table can respectively store the address mapping information of the valid data in the storage chip D1 and the address mapping information of the valid data in the storage chip D2 in the memory.
  • FIG. 6 is a schematic diagram of a mapping table provided by an embodiment of the present application.
  • the mapping table includes sub-mapping table 0 and sub-mapping table 1.
  • the memory includes a first storage block and a second storage block. example.
  • the mapping table 0 is used to represent the address mapping information of the data area 0 stored in the first storage block.
  • the data area 0 may include valid data in the first storage block.
  • the logical block address of the data area 0 is LBA0 to LBAX
  • the physical block address of data area 0 is LBA0 to PBAX, where X is a positive integer greater than or equal to 1.
  • the mapping table 1 is used to represent the address mapping information of the data area 1 stored in the second storage block.
  • the data area 1 can include valid data in the second storage block.
  • the logical block address of the data area 1 is LBAX to LBAY.
  • the physical block addresses of data area 1 are LBA1 to PBAY, where Y is a positive integer greater
  • the LBA of the storage unit in the address mapping information has a corresponding PBA.
  • PBA is the physical block address of the data stored in the storage unit, and the data is valid data; if there is no valid data stored in the storage unit, the LBA of the storage unit in the address mapping information does not have a corresponding PBA or There is no LBA for this storage unit.
  • the memory includes 5 storage units, and the logical block addresses of the 5 storage units can be expressed as LBA0 to LBA4.
  • the memory queries the address mapping information based on LBA0. If in the address mapping information, the LBA0 If there is a corresponding PBA, then the PBA is the physical block address of the valid data.
  • LBA1 to LBA4 follows the above steps to query LBA1 to LBA4 in order to determine the logical block address of the valid data in the five storage units.
  • S503 The memory sends valid information to the processor, and the valid information is used to indicate the address of the valid data.
  • the valid information may include the logical block address of the valid data, or the valid information may include indication information of the logical block address of the valid data.
  • the valid information is encapsulated into different forms and sent to the processor. The two forms of this effective information are described below respectively.
  • the valid information includes the logical block address of the valid data.
  • the valid information is encapsulated into a linked list and sent to the processor.
  • the valid data includes first valid data and second valid data.
  • the logical block address of the first valid data is LBA1
  • the logical block address of the second valid data is LBA2. Connect the LBA1 and LBA2 together. Finally, it is sent to the processor in the form of "LBA1-LBA2".
  • the valid information includes indication information of the logical block address of the valid data.
  • the valid information is encapsulated into a bitmap and sent to the processor.
  • the memory includes three storage units, and the logical block addresses of the three storage units can be expressed as LBA1 to LBA3, where LBA1 and LBA2 have corresponding PBAs respectively, and LBA3 does not have a corresponding PBA.
  • the indication information of LBA1 and LBA2 is both 1, the indication information of LBA3 is 0, and the indication information "110" is sent to the processor, where 1 is used to indicate that the logical block address has a corresponding physical area.
  • Block address, 0 is used to indicate that the logical block address does not have a corresponding physical block address.
  • S504 The processor receives valid information from the memory, and the valid information is used to indicate the address of the valid data.
  • the processor parses the valid information to obtain the logical block address of the valid data.
  • the following describes the process of the processor parsing the valid information based on the two possible forms of the valid information in S503.
  • the valid information includes the logical block address of the valid data.
  • the valid information may include "LBA1-LBA2", which is obtained by the processor after disassembling "LBA1-LBA2" Logical block address LBA1 and logical block address LBA2, where LBA1 is the logical block address of the first valid data, and LBA2 is the logical block address of the second valid data, thereby obtaining the logical block address of the valid data in the memory. for LBA1 and LBA2.
  • the valid information includes indication information of the logical block address of the valid data.
  • the valid information may include "110”
  • the processor converts the indication information of the logical block address of the valid data to Comparing "110" with the logical block address in the memory, it can be seen that the valid information of logical block address LBA1 and logical block address LBA2 is both 1, which means that logical block address LBA1 and logical block address LBA2 have respectively
  • the corresponding physical block address and the indication information of the logical block address LBA3 are 0, which means that the logical block address LBA3 does not have a corresponding physical block address, that is, there is no data stored in the logical block address LBA3, so
  • the logical block addresses of the valid data in the memory are LBA1 and LBA2.
  • S505 The processor sends an access request to the memory, where the access request includes the address information of the valid data.
  • the access request for accessing all valid data in the memory may be sent once or multiple times.
  • the two access forms of the processor are described below.
  • the memory includes multiple valid data as an example for description.
  • the processor accesses the memory once. Specifically, the processor sends an access request to the memory.
  • the access request includes the multiple logical block addresses.
  • the multiple logical areas The block address is the logical block address of all valid data in this memory.
  • the processor accesses the multiple logical block addresses of the multiple valid data one by one. Specifically, the processor sends multiple access requests to the memory.
  • the multiple access requests Each access request in includes a logical block address, which is the logical block address of a valid data in the memory, until the logical block addresses of all valid data in the memory are sent to the memory. .
  • S506 The memory receives an access request from the processor, the access request is used to access the valid data, where the access request includes the address information of the valid data.
  • the memory only receives one access request, the access request includes multiple logical block addresses, and the memory sequentially determines each logical block address of the multiple logical block addresses. The corresponding physical block address is read, and the valid data in the physical block address is read, thereby obtaining multiple valid data in the memory.
  • the memory receives an access request each time, and the access request includes a logical block address.
  • the memory determines the physical block address corresponding to the logical block address and reads the Valid data in the physical block address, the memory receives an access request to read a valid data until multiple valid data in the memory are obtained.
  • S507 The memory sends data information to the processor, and the data information includes the valid data.
  • the multiple valid data are sent at one time.
  • the memory sends the multiple valid data in the memory to the processor at one time, that is, the memory reads the multiple valid data at one time. Complete multiple valid data in the memory and send the multiple valid data to the processor at one time.
  • the plurality of valid data are sent one by one.
  • the storage The memory sends valid data in the memory to the processor one by one, that is, the memory reads a valid data and sends a valid data to the processor.
  • S508 The processor receives data information from the memory, and the data information includes the valid data.
  • the method further includes: the processor sending a deletion command to the memory, where the deletion command is used to delete the target data.
  • the processor before the processor sends a deletion command to the memory, the processor receives a deletion instruction from the user, and the deletion instruction may include target data. After receiving the deletion instruction, the processor performs deletion according to the target data included in the deletion instruction. Determine the LBA for this target data. This target data may also be called invalid data.
  • the method further includes: the memory receiving a deletion command from the processor, and deleting the target data according to the deletion command.
  • the deletion command includes the physical block address of the target data.
  • the memory deletes the target data stored in the physical block address according to the physical block address of the target data.
  • the memory also stores the address information of the target data.
  • the method also includes: after the memory deletes the target data, the memory also deletes the address information of the target data.
  • the address information includes the address stored in the memory. PBA, or LBA and PBA in the mapping information.
  • the valid information, the access request, the data information, and the deletion command can be transmitted through any one of the NVME protocol, the SAS protocol, or the SATA protocol.
  • the embodiments of this application do not specifically limit this.
  • the processor includes: I/O module 701, feature traversal module 702, I/O delivery module 703 and driver module 704.
  • the I/O module 701 can be used to send a delete command to the I/O issuing module 703, and the characteristic traversal module 702 can be used to send query commands and access requests to the I/O issuing module 703, and receive information sent by the memory.
  • the /O issuing module 703 can be used to encapsulate deletion commands, query commands and access requests, and parse the information sent by the memory.
  • the driving module 704 can be used to issue the encapsulated deletion commands, query commands and access requests.
  • the driving module 704 is connected to the SSD, and the processor communicates with the SSD through the driver module 704.
  • the I/O module 701, the characteristic traversal module 702, the I/O delivery module 703 and the driver module 704 in Figure 7 can all be the processors in Figure 4 mentioned above.
  • the method includes: S1.
  • the characteristic traversal module sends a query command to the I/O issuing module.
  • the query command is used to query the address information of the valid data stored in the memory of the SSD (sending the query command);
  • S2 the I/O delivery module encapsulates the query command (encapsulates the query command);
  • S3, the I/O delivery module sends the encapsulated query command to the driver module (sends the encapsulated query command);
  • S4 the driver
  • the module receives the encapsulated query command and sends the encapsulated query command to SSD (receives and sends the encapsulated query command);
  • S5, SSD receives the encapsulated query command and parses the query command;
  • S7 SSD encapsulates the logical block address of the valid data into a bitmap or linked list and sends it to the feature
  • the characteristic traversal module sends an access request to the I/O issuing module, and the access request includes the logical block address of the valid data (sending an access request); S10.
  • I The /O issuing module encapsulates the access request (encapsulates the access request); S11 and the I/O issuing module encapsulate the encapsulated access request.
  • the access request is sent to the driver module (sends the encapsulated access request); S12.
  • the driver module receives the encapsulated access request and sends the encapsulated access request to the solid state drive (receives and sends the encapsulated access request); S13.
  • the SSD receives the access request and reads the valid data; S14.
  • the SSD sends the read valid data to the feature traversal module; S15.
  • the feature traversal module receives the valid data sent by the SSD.
  • the I/O module detects invalid data; S2.
  • the I/O module sends a delete command to the I/O issuing module.
  • the delete command includes the invalid data and the logical block address of the invalid data (sending the delete command); S3.
  • the I/O delivery module encapsulates the delete command; S4, the I/O delivery module sends the encapsulated delete command to the driver module; S5, the driver module receives the encapsulated delete command; S6, the driver module sends the encapsulated delete command
  • the delete command is sent to the SSD; S7, SSD receives the encapsulated delete command and parses it; S8, SSD deletes the invalid data stored in the SSD; S9, the SSD deletes the logical block address of the invalid data stored in the SSD. and physical block address.
  • the processor when the processor traverses and reads the data in the memory, the processor sends a query command to the memory, and the memory queries the effective information of the data stored in the memory according to the query command, that is, the memory This query command queries the address mapping information of the data stored in the memory to determine the address information of the valid data stored in the memory.
  • the memory sends the address information of the valid data to the processor, and the processor determines the address of the valid data according to the address of the valid data.
  • Information traverses and reads the memory to obtain valid data in the memory.
  • the processor only accesses the storage space that stores valid data in the memory, instead of accessing all the storage spaces in the memory.
  • the processor traverses and reads the memory. Compared with accessing all storage spaces in the memory once, the efficiency of traversing and reading data is improved; on the other hand, the memory reads valid data based on the address information of the valid data, without the need to read out the data. Valid data can be obtained by verifying the data. Compared with the prior art, valid data can only be obtained by verifying the read data, thus improving the accuracy of the data.
  • the processor and the memory include corresponding hardware structures and/or software modules for executing each function.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is performed by hardware or computer software driving the hardware depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each specific application, but such implementations should not be considered beyond the scope of this application.
  • Embodiments of the present application can divide the processor and memory into functional modules according to the above method examples.
  • each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module.
  • the above integrated modules can be implemented in the form of hardware or software function modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. In actual implementation, there may be other division methods.
  • FIG. 10 shows a possible structural diagram of the processor involved in the above embodiment.
  • the processor includes: a sending unit 01 and a receiving unit 02,
  • the sending unit 01 is used to support the processor to perform one or more steps of S501 and S505 in the above method embodiment.
  • the receiving unit 02 is used to support the processor to perform S504 and S508 in the above method embodiment. one or more steps in .
  • the sending unit 01 and the receiving unit 02 may be the processor shown in Figure 4.
  • the processor shown in Figure 4.
  • the specific description in Figure 4 please refer to the specific description in Figure 4, and the embodiments of the present application will not be repeated here.
  • FIG 11 shows a possible structural diagram of the memory involved in the above embodiment.
  • the memory includes: a receiving unit 101 and a sending unit 102.
  • the receiving unit 101 The sending unit 102 is used to support the memory to perform one or more steps of S502 and S506 in the above method embodiment, and the sending unit 102 is used to support the memory to perform one or more steps of S503 and S507 in the above method embodiment.
  • the memory also includes: a query unit 103 and a reading unit 104.
  • the query unit 103 is used to query valid information according to the logical block address of the memory to determine the physical block address of the valid data.
  • the address The mapping information is used to indicate the mapping relationship between the logical block address and the physical block address of the valid data stored in the memory.
  • the reading unit 104 is used to read from the memory according to the address information of the valid data. the valid data.
  • the receiving unit 101, the sending unit 102, the query unit 103 and the reading unit 104 can be the controller shown in Figure 1.
  • the controller shown in Figure 1.
  • This application implements The example will not be repeated here.
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of modules or units is only a logical function division.
  • there may be other division methods for example, multiple units or components may be The combination can either be integrated into another device, or some features can be omitted, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software functional units.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a readable storage medium.
  • the technical solutions of the embodiments of the present application are essentially or contribute to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the software product is stored in a storage medium includes several instructions to cause the device to execute all or part of the steps of the methods described in various embodiments of this application.
  • the aforementioned storage media include: U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk and other media that can store program codes.
  • the electronic device includes a processor and a memory.
  • the processor and the memory can be used to perform relevant steps in the above method embodiment.
  • the processor can be the above-mentioned Figure 3, Figure 3. 4.
  • the memory can be the memory provided in Figures 2, 3, 7 and 11 above.
  • a computer-readable storage medium includes computer instructions.
  • the processor is caused to execute the above method. Relevant steps in the example.
  • a computer-readable storage medium includes computer instructions.
  • the computer instructions When the computer instructions are run on a memory, the memory is caused to perform relevant steps in the above method embodiments.
  • a computer program product containing instructions is provided, which when the computer program product is run on a computer device, causes the processor to perform the relevant steps in the above method embodiment.
  • a computer program product containing instructions is provided, which when the computer program product is run on a computer device, causes the memory to perform the relevant steps in the above method embodiment.

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Abstract

本申请提供一种数据读取方法及装置，涉及数据存储技术领域，用于提高遍历读取的效率。该数据读取方法包括：处理器向存储器发送查询命令，该查询命令用于查询该存储器中存储的数据的有效信息，该有效信息用于指示该数据是否为有效数据；该处理器接收来自该存储器的该有效信息，当该有效信息指示该数据为有效数据时，该处理器向该存储器发送访问请求，其中，该访问请求包括该有效数据的地址信息；该处理器接收来自该存储器的数据信息，该数据信息包括该有效数据。

Description

一种数据读取方法及装置
本申请要求于2022年03月18日提交国家知识产权局、申请号为202210273203.2，申请名称为“一种数据读取方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据存储技术领域，尤其涉及一种数据读取方法及装置。
背景技术
固态硬盘(solid state disk，SSD)采用闪存NAND作为存储介质来存储数据，SSD包括闪存转换层(flash translation layer，FTL)和FTL映射表，当SSD的控制器接收到主机的数据读写请求，进行数据的读写时，FTL可用于将数据的逻辑区块地址(logical block address，LBA)转换为物理区块地址(physics block address，PBA)，控制器根据转换后的PBA进行数据的读写，其中，FTL映射表可以用于记录SSD中逻辑区块地址和物理区块地址的转换关系。与机械硬盘相比，SSD具有快速读写、质量轻、能耗低以及体积小等特点，因此被广泛应用。
现有技术中，主机遍历读取SSD中的数据时，将SSD中所有的LBA均访问一次，以读取SSD中的数据。由于，SSD的闪存NAND中包括部分未存储数据的空间，也可以称为空闲空间，空闲空间有对应的LBA，但是，在FTL映射表中这部分LBA没有对应的PBA。当处理器访问到没有对应的PBA的LBA时，SSD向处理器反馈一个无效的数据。因此，处理器还需要将遍历读取到的数据进行魔术字Magic检验或者循环冗余校验(cyclic redundancy check，CRC)，筛选出数据中的无效数据，从而得到有效数据。
但是，处理器遍历读取SSD中的数据时，空闲空间的读取占用了额外的时间，导致遍历读取的效率不高；另一方面，处理器读取的数据中包括无效数据，还需要对读取的数据进行校验才能得到有效数据，降低了数据的准确性。
发明内容
本申请提供一种数据读取方法及装置，涉及数据存储技术领域，用于提高遍历读取的效率和数据的准确性。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种数据读取方法，该方法包括：处理器向存储器发送查询命令，该查询命令用于查询该存储器中存储的数据的有效信息，该有效信息用于指示该数据是否为有效数据；该处理器接收来自该存储器的该有效信息，当该有效信息指示该数据为有效数据时，该处理器向该存储器发送访问请求，其中，该访问请求包括该有效数据的地址信息；该处理器接收来自该存储器的数据信息，该数据信息包括该有效数据。
上述技术方案中，当处理器遍历读取存储器中的数据时，处理器先向存储器发送查询命令，该查询命令用于查询该存储器中存储的数据的有效信息，该有效信息用于指示该数据是否为有效数据，处理器接收来自存储器的该有效信息，当该有效信息指 示该数据为有效数据时，处理器向存储器发送访问请求，该访问请求包括该有效数据的地址信息，以对该存储器中存储的有效数据进行遍历读取，处理器接收来自存储器的数据信息，该数据信息包括该有效数据，从而得到该存储器中存储的有效数据，在此过程中，处理器只对该存储器中存储有效数据的存储空间进行了访问，而不是将该存储器中的所有存储空间均进行了访问，现有技术中，处理器在遍历读取存储器中的数据时，将存储器中的所有存储空间均访问一次，即处理器将存储器中存储有效数据的存储空间和没有存储数据的空间均进行了访问，与现有技术中相比，本技术方案提高了遍历读取的效率；此外，本方案中该处理器根据存储器中有效数据的地址对存储器进行访问，以读取该存储器中的有效数据，无需对读取出的数据进行校验即可得到有效数据，与现有技术中，处理器需要对读取出的数据进行检验才能得到有效数据相比，提高了数据的准确性。
在第一方面的一种可能的实现方式中，该查询命令为非易失性内存主机控制器接口规范NVME命令、串行连接SCSI SAS命令或串行高级技术附件SATA命令。
上述可能的实现方式中，该查询命令可以为NVME命令、SAS命令或SATA命令，增加了选择的多样性。
在第一方面的一种可能的实现方式中，该有效信息是以位图或者链表的形式指示该有效数据的地址信息。上述可能的实现方式中，增加了选择的多样性。
在第一方面的一种可能的实现方式中，该方法还包括：该处理器向该存储器发送删除命令，该删除命令用于删除目标数据。
上述可能的实现方式中，该处理器通过向存储器发送删除命令来删除存储在存储器中的目标数据，在处理器遍历读取存储器中的数据时，避免返回该目标数据的有效信息，即避免返回该目标数据的地址信息，提高了遍历读取的速率，进一步，提高了有效数据的准确性。
第二方面，提供一种数据读取方法，该方法包括：存储器接收来自处理器的查询命令，该查询命令用于查询该存储器中存储的数据的有效信息，该有效信息用于指示该数据是否为有效数据；该存储器向该处理器发送该有效信息；该存储器接收来自该处理器的访问请求，其中，该访问请求包括该有效数据的地址信息；该存储器向该处理器发送数据信息，该数据信息包括该有效数据。
上述技术方案中，在处理器遍历读取存储器中的数据时，存储器接收来自处理器的查询命令，该查询命令用于查询该存储器中存储的数据的有效信息，该有效信息用于指示该数据是否为有效数据，该存储器向该处理器发送该有效信息，该存储器接收来自处理器的访问请求，其中，该访问请求包括该有效数据的地址信息，该存储器根据该有效数据的地址信息依次进行有效数据的读取，并将读取到的有效数据发送给处理器，在此过程中，该处理器在遍历读取该存储器中的数据时，该存储器只根据有效数据的地址信息对该存储器中存储有效数据的存储空间进行了读取，而不是将该存储器中的每个存储空间都进行了读取，与现有技术中，处理器在遍历读取存储器中的数据时，存储器将所有的存储空间均读取一次相比，提高了遍历读取的效率；此外，该存储器根据该有效数据的地址进行有效数据的读取，无需将读取到的数据进行校验既可得到有效数据，与现有技术中，存储器将遍历读取出的数据进行检验才能的带有效 数据相比，提高了数据的准确性。
在第二方面的一种可能的实现方式中，该存储器接收来自处理器的查询命令之后，该方法还包括：该存储器根据该存储器的逻辑区块地址查询地址映射信息，以确定该有效数据的物理区块地址，该地址映射信息用于指示该存储器中存储的数据的逻辑区块地址与物理区块地址之间的映射关系。
上述可能的实现方式中，根据该存储器的逻辑区块地址查询地址映射信息，以确定该有效数据的物理区块地址，从而确定了该存储器中有效数据的地址信息，存储器将该有效数据的地址信息发送给处理器，处理器根据有效数据的地址信息发送访问请求，以读取该存储器中的有效数据，即该存储器只根据有效数据的地址信息对该存储器中存储有效数据的存储空间进行了读取，而不是将该存储器中的每个存储空间都进行了读取，与现有技术中，处理器在遍历读取存储器中的数据时，存储器将所有的存储空间均读取一次相比，提高了遍历读取的效率；此外，该存储器根据该有效数据的地址进行有效数据的读取，无需将读取到的数据进行校验既可得到有效数据，与现有技术中，存储器将遍历读取出的数据进行检验才能的带有效数据相比，提高了数据的准确性。
在第二方面的一种可能的实现方式中，该存储器接收来自该处理器的访问请求之后，该方法还包括：该存储器根据该有效数据的地址信息，从该存储器中读取该有效数据。
上述可能的实现方式中，该存储器根据有效数据的地址，从该存储器中读取该有效数据，与现有技术中，存储器对每个存储空间都进行一次访问，以读取存储器中的数据相比，提高了遍历读取的效率，此外，该存储器根据该有效数据的地址进行有效数据的读取，无需将读取到的数据进行校验既可得到有效数据，与现有技术中，存储器将遍历读取出的数据进行检验才能的带有效数据相比，提高了数据的准确性。
在第二方面的一种可能的实现方式中，该方法还包括：该存储器接收来自该处理器的删除命令，并根据该删除命令删除目标数据。
上述可能的实现方式中，该存储器接收来自该处理器的删除命令，并根据该删除命令删除目标数据，在处理器遍历读取存储器中的数据时，避免返回该目标数据的有效信息，即避免返回该目标数据的地址信息，提高了遍历读取的速率，进一步，提高了有效数据的准确性。
在第二方面的一种可能的实现方式中，该存储器中还存储有该目标数据的地址信息，该方法还包括：该存储器删除该目标数据的地址信息。
上述可能的实现方式中，存储器删除目标数据的地址信息，避免目标数据的地址信息占用存储器的存储空间，提高了存储器中存储空间的利用率。
在第二方面的一种可能的实现方式中，该查询命令为非易失性内存主机控制器接口规范NVME命令、串行连接SCSI SAS命令或串行高级技术附件SATA命令。
上述可能的实现方式中，该查询命令可以为NVME命令、SAS命令或SATA命令，增加了选择的多样性。
在第二方面的一种可能的实现方式中，该有效信息是以位图或者链表的形式指示该有效数据的地址信息。上述可能的实现方式中，增加了选择的多样性。
第三方面，提供一种处理器，该处理器包括：发送单元，用于向存储器发送查询命令，该查询命令用于查询该存储器中存储的数据的有效信息，该有效信息用于指示该数据是否为有效数据；接收单元，用于接收来自该存储器的有效信息；当该有效信息指示该数据为有效数据时，该发送单元，还用于向该存储器发送访问请求，其中，该访问请求包括该有效数据的地址信息；该接收单元，还用于接收来自该存储器的数据信息，该数据信息包括该有效数据。
在第三方面的一种可能的实现方式中，该查询命令为非易失性内存主机控制器接口规范NVME命令、串行连接SCSI SAS命令或串行高级技术附件SATA命令。
在第三方面的一种可能的实现方式中，该有效信息是以位图或者链表的形式指示该有效数据的地址信息。
在第三方面的一种可能的实现方式中，该发送单元还用于：向该存储器发送删除命令，该删除命令用于删除目标数据。
第四方面，提供一种存储器，该存储器包括：接收单元，用于接收来自处理器的查询命令，该查询命令用于查询该存储器中存储的数据的地址信息，该有效信息用于指示该数据是否为有效数据；发送单元，用于向该处理器发送该有效信息；该接收单元，还用于接收来自该处理器的访问请求，其中，该访问请求包括该有效数据的地址信息；该发送单元，还用于向该处理器发送数据信息，该数据信息包括该有效数据。
在第四方面的一种可能的实现方式中，该存储器还包括查询单元：该接收单元接收来自处理器的查询命令之后，该查询单元，用于根据该存储器的逻辑区块地址查询地址映射信息，以确定该有效数据的物理区块地址，该地址映射信息用于指示该存储器中存储的数据的逻辑区块地址与物理区块地址之间的映射关系。
在第四方面的一种可能的实现方式中，该存储器还包括读取单元：该接收单元接收来自该处理器的访问请求之后，该读取单元，用于根据该有效数据的地址信息，从该存储器中读取该有效数据。
在第四方面的一种可能的实现方式中，该查询命令为非易失性内存主机控制器接口规范NVME命令、串行连接SCSI SAS命令或串行高级技术附件SATA命令。
在第四方面的一种可能的实现方式中，该有效信息是以位图或者链表的形式指示该有效数据的地址信息。
在第四方面的一种可能的实现方式中，该存储器还包括删除单元：该接收单元，还用于接收来自该处理器的删除命令，该删除单元，用于根据该删除命令删除目标数据。
在第四方面的一种可能的实现方式中，该存储器中还存储有该目标数据的地址信息，该删除单元还用于：删除该目标数据的地址信息。
第五方面，提供一种电子设备，该电子设备包括：处理器和存储器，该处理器为上述第三方面或者第三方面的任一种可能的实现方式所提供的处理器，该存储器为上述第四方面或者第四方面的任一种可能的实现方式所提供的存储器。
本申请的又一方面，提供一种计算机可读存储介质，该计算机可读存储介质包括计算机指令，当该计算机指令在处理器上运行时，执行如上述第一方面或者第一方面的任一种可能的实现方式中的相关步骤。
本申请的又一方面，提供一种计算机可读存储介质，该计算机可读存储介质包括计算机指令，当该计算机指令在存储器上运行时，执行如上述第二方面或者第二方面的任一种可能的实现方式中的相关步骤。
在本申请的又一方面，提供一种包含指令的计算机程序产品，当计算机程序产品在计算机上设备运行时，使得处理器执行如上述第一方面或者第一方面的任一种可能的实现方式中的相关步骤。
在本申请的又一方面，提供一种包含指令的计算机程序产品，当计算机程序产品在计算机设备上运行时，使得存储器执行如上述第二方面或者第二方面的任一种可能的实现方式中的相关步骤。
可以理解地，上述提供的一种处理器、存储器、电子设备、计算机可读存储介质和计算机程序产品可用于执行上文所提供的对应的方法，因此，其所能达到的有益效果可参考上文所提供的对应的方法中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种SSD的结构示意图；
图2为本申请实施例提供的一种闪存颗粒的结构示意图；
图3为本申请实施例提供的一种电子设备的结构示意图；
图4为本申请实施例提供的一种终端设备的结构示意图；
图5为本申请实施例提供的一种数据读取方法的流程图；
图6为本申请实施例提供的一种映射表的示意图；
图7为本申请实施例提供的一种处理器和SSD的示意图；
图8为本申请实施例提供的另一种数据读取方法的流程图；
图9为本申请实施例提供的一种数据删除取方法的流程图；
图10为本申请实施例提供的一种处理器的结构示意图；
图11为本申请实施例提供的一种存储器的结构示意图。
具体实施方式
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a、b、或c中的至少一项(个)，可以表示：a、b、c、a和b、a和c、b和c、或a和b和c，其中a、b、c可以是单个，也可以是多个。另外，本申请实施例采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。例如，第一阈值和第二阈值仅仅是为了区分不同的阈值，并不对其先后顺序进行限定。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在介绍本申请实施例之前，首先对固态硬盘(solid state disk，SSD)的相关知识进行介绍说明。
图1为一种SSD的结构示意图，包括：控制器01、内存02和多个闪存颗粒03。
其中，控制器01是SSD的控制中心，利用各种接口和线路连接整个SSD的各个部分，该控制器01可用于控制内存02和该多个闪存颗粒03的读写，比如，该控制器01可用于接收处理器的遍历访问请求，以对多个闪存颗粒03进行遍历读取。该控制器01还用于管理该SSD中的地址信息，该地址信息可以包括逻辑区块地址(logical block address，LBA)和物理区块地址(physics block address，PBA)。该控制器01还用于向处理器发送信息，比如，该信息可以包括下文所提供的方法实施例中的有效信息和数据信息。
内存02是与控制器01直接交换数据的内部存储器，可用于存储操作系统或其他正在运行中的程序的临时数据和SSD使用中所创建的信息。
多个闪存颗粒03作为存储介质，用于存储数据以及数据相应的地址信息，比如，该地址信息可以包括数据的逻辑区块地址(logical block address，LBA)和物理区块地址(physics block address，PBA)。对于多个闪存颗粒03中的每个闪存颗粒03，该闪存颗粒03包括多个存储芯片Die，多个存储芯片中的每个存储芯片包括多个存储块Block，多个存储块中的每个存储块包括多个存储页Page。在一种可能的实现方式中，该闪存颗粒可以为闪存NAND颗粒。
图2为一种闪存NAND颗粒结构示意图，该闪存NAND颗粒包括4个存储芯片且可以表示为D1至D4，对于D1至D4中的每个存储芯片，该芯片包括两个存储块且可以表示为B1和B2，该B1和B2中的每个存储块包括10个存储页且可以表示为P1至P10。图2中以一个闪存颗粒包括4个存储芯片，每个存储芯片包括2个存储块，每个存储块包括10个存储页为例进行说明。
其中，闪存NAND颗粒的存储容量与闪存NAND颗粒中包括的储存处芯片的数量和存储芯片的容量有关。比如，在实际应用中，单个存储芯片的容量一般为8吉字节(GB)、16GB、32GB或更大，如果单个闪存NAND颗粒有8个存储芯片，则单个闪存NAND颗粒的容量可以为64GB、128GB、256GB或更大。
本申请提供一种数据读取方法，该数据读取方法应用于电子设备中，当处理器遍历读取存储器中的数据时，通过向存储器发送查询命令，查询存储器中存储的数据的有效信息，该有效信息用于指示该数据是否为有效数据，当该有效信息指示该数据为有效数据时，处理器根据有效数据的地址信息发送访问请求，即处理器只对存储器中存储有有效数据的存储空间进行访问，从而得到存储器中的数据，与现有技术中处理器遍历读取存储器中数据时，将存储器中的每个存储空间(存储有效数据的存储空间和未存储数据的空间)均访问一次相比，提高了遍历读取的效率，进一步，提高了数据的准确性。
下面首先对电子设备的结构进行介绍说明。该电子设备包括服务器和存储器，该电子设备也可包括终端设备，其中，该存储器可以为外部存储器。
图3为一种电子设备的结构示意图，该电子设备可以包括服务器10和外部存储 器11。
其中，该服务器10可用于对该外部存储器11进行查询和访问，比如，服务器10可以包括处理器，该处理器可以通过向该外部存储器11发送查询命令和访问请求，以对该外部存储器11进行查询和访问。该服务器10还用于接收来自该外部存储器11的信息，该信息可以包括有效信息和数据信息。
该外部存储器11可用于接收该服务器10发送的查询命令和访问请求，比如，该外部存储器11可以包括控制器，该控制器可用于接收该服务器10发送的查询命令和访问请求。该控制器还用于向该服务器10发送信息，该信息可以包括有效信息和数据信息。在一种可能的实现方式中，该外部存储器11可以为SSD，该SSD可以为上述图1中所示的SSD。
可选的，该服务器10中的处理器可以采用不同的协议与该外部存储器11进行通信，且采用不同的协议时，该服务器10与该外部存储器11之间的连接方式不同。下面分别将该处理器和该外部存储器11之间的三种不同的通信协议进行说明。
在第一种可能的实现方式中，该处理器可以采用非易失性内存控制器接口规范(non-volatile memory express，NVME)协议与该外部存储器11进行通信，此时，该服务器10与该外部存储器11之间通过PCI-E总线连接。在第二种可能的实现方式中，该处理器可以采用串行连接SCSI(serial attached scsi，SAS)协议与该外部存储器11进行通信，此时，该服务器10与该外部存储器11之间通过SAS总线连接。在第三种可能的实现方式中，该处理器可以采用串行高级技术附件(serial advanced technology attachment，SATA)协议与该外部存储器11进行通信，此时，该服务器10与该外部存储器11之间通过ATA总线连接。当该处理器与该外部存储器11之间采用不同的协议进行通信时，该处理器向该外部存储器11发送的查询命令和访问请求也会被封装成与通信协议相对应的格式，存储器11向发送的信息也会被封装成与通信协议相对应的格式。例如，该处理器向存储器11发送的查询命令可以为NVME命令、SAS命令或SATA命令。
当该电子设备包括终端设备时，该终端设备可以包括但不限于个人计算机、服务器计算机、移动设备(比如手机、平板电脑、媒体播放器等)、可穿戴设备、车载设备、消费型终端设备、移动机器人和无人机等。
图4为本申请实施例提供的一种终端设备的结构示意图，该终端设备包括处理器101、存储器102、传感器组件103、多媒体组件104、电源105以及输入/输出接口106。
其中，处理器101也可以是终端设备的控制中心，利用各种接口和线路连接整个设备的各个部分，通过运行或执行存储在存储器102内的软件程序和/或软件模块，以及调用存储在存储器102内的数据，执行终端设备的各种功能和处理数据，从而对终端设备进行整体监控。可选地，处理器101可以包括一个或多个处理单元，比如，上述处理器101可以包括中央处理器(central processing unit，CPU)、应用处理器(application processor，AP)、调制解调处理器、图形处理器(graphics processing unit，GPU)、图像信号处理器(image signal processor，ISP)、控制器、视频编解码器、数字信号处理器(digital signal processor，DSP)、基带处理器和/或神经网络 处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。在本申请实施例中，该处理器101可用于向存储器102发送指令，该指令可以包括查询命令、访问请求和删除命令。该处理器101还用于接收来自该存储器102的信息，该信息可以包括数据信息和有效信息。
存储器102可用于存储数据、软件程序以及软件模块；主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统和至少一个功能所需的应用程序，比如声音播放功能或图像播放功能等；存储数据区可存储根据终端设备的使用所创建的数据，比如音频数据、图像数据、或表格数据等。该存储器102可以包括内部存储器、高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。该内部存储器可以为内存。在本申请实施例中，该存储器102可以包括外部存储器，该外部存储器可用于接收该处理器101发送的指令，比如，该外部存储器可以包括控制器，该控制器可用于接收该处理器101发送的指令。该控制器还用于向该处理器101发送信息，该信息可以包括有效信息和数据信息。在一种可能的实现方式中，该外部存储器可以为SSD，该SSD可以为上述图1中所示的SSD。
传感器组件103包括一个或多个传感器，用于为终端设备提供各个方面的状态评估。其中，传感器组件103可以包括加速度传感器、陀螺仪传感器、磁传感器、压力传感器或温度传感器，通过传感器组件103可以检测到终端设备的加速/减速、方位、打开/关闭状态、组件的相对定位或终端设备的温度变化等。此外，传感器组件103还可以包括光传感器，此外，传感器组件103还可以包括光传感器，用于检测周围环境的灯光。
多媒体组件104在终端设备和用户之间的提供一个输出接口的屏幕，该屏幕可以为触摸面板，且当该屏幕为触摸面板时，屏幕可以被实现为触摸屏，以接收来自用户的输入信号。触摸面板包括一个或多个触摸传感器以感测触摸、滑动和触摸面板上的手势。所述触摸传感器可以不仅感测触摸或滑动动作的边界，而且还检测与所述触摸或滑动操作相关的持续时间和压力。此外，多媒体组件104还包括至少一个摄像头，比如，多媒体组件104包括一个前置摄像头和/或后置摄像头。当终端设备处于操作模式，如拍摄模式或视频模式时，前置摄像头和/或后置摄像头可以接收外部的多媒体数据。每个前置摄像头和后置摄像头可以是一个固定的光学透镜系统或具有焦距和光学变焦能力。
电源105用于为该终端设备的各个组件提供电源，电源105可以包括电源管理系统，一个或多个电源，或其他与该终端设备生成、管理和分配电力相关联的组件。
输入/输出接口106为处理器101和外围接口模块之间提供接口，比如，外围接口模块可以键盘、鼠标、或通用串行总线(universal serial bus，USB)设备等。在本申请实施例中，当该存储器102包括外部存储器时，该终端设备和该外部存储器之间通过该输入/输出接口106进行通信。
下面结合图3中所示的电子设备以及图4中所示的终端设备，对本申请实施例提供的数据读取方法进行介绍说明。以下实施例中的存储器可以是指上述图3中的外部 存储器。
图5为本申请实施例提供的一种数据读取方法的流程图，该数据读取方法包括：
S501：处理器向存储器发送查询命令，该查询命令用于查询该存储器中存储的数据的有效信息，该有效信息用于指示该数据是否为有效数据。
其中，该存储器可以包括至少一个闪存颗粒，该至少一个闪存颗粒中的每个闪存颗粒可以包括多个存储芯片，该多个存储芯片中的每个存储芯片可以包括多个存储块，该多个存储块中的每个存储块可以包括多个存储页，该多个存储页中的每个存储页可以包括多个存储单元。为了便于理解，下面以该存储器包括一个闪存颗粒N1为例进行说明。示例性的，该闪存颗粒N1包括第一存储芯片D1和第二存储芯片D2，对于D1和D2中的任意一个存储芯片可以包括第一存储块B1和第二存储块B2，对于B1和B2中的任意一个存储块包括10个存储页P1至P10，对于该P1至P10中的每个存储页可以包括至少一个存储单元，即该闪存颗粒包括多个存储单元，该多个存储单元中的每个存储单元可用于存储数据。以下实施例中均以该存储器包括上述闪存颗粒N1为例进行说明。
其次，该查询命令可以包括该存储器的所有逻辑区块地址，该查询命令也可以包括该存储器部分逻辑区块地址。下面分别将上述两种情况进行说明。
第一种可能的实施例中，该查询命令包括该存储器的部分逻辑区块地址。该部分逻辑区块地址用于指示该存储器中的部分存储空间，比如，该部分存储空间可以是部分闪存颗粒、同一闪存颗粒中的部分存储块、同一存储块中的部分存储页、或者同一存储页的部分存储单元。当该查询命令包括该存储器的部分逻辑区块地址时，该部分逻辑区块地址是连续的。比如，该闪存颗粒N1包括10个存储单元，每个存储单元对应一个逻辑区块地址，即该闪存颗粒N1包括10个逻辑区块地址，该查询命令可以包括闪存颗粒N1中的5个逻辑区块地址，此时，该5个存储单元对应的LBA是连续的，且可以表示为LBA0至LBA4。
第二种可能的实施例中，该查询命令包括该存储器的所有逻辑区块地址，该所有的逻辑区块地址可用于指示该存储器的全部存储空间。比如，该查询命令可以包括该存储器的首逻辑区块地址和地址长度，该地址长度为该存储器中除该首逻辑区块地址外的所有逻辑区块地址的长度；或者，该查询命令也可以包括该存储器的尾逻辑区块地址和地址长度，该地址长度为该存储器中除该尾逻辑区块地址外的所有逻辑区块地址的长度；或者，该查询命令还可以包括该存储器的首逻辑区块地址和尾逻辑区块地址。以该查询命令包括该存储器的首逻辑区块地址和地址长度为例，当该存储器包括10个存储单元，且该10个存储单元的首逻辑区块地址为LBA0时，该查询命令为LBA0以及地址长度10。以下实施例中以该查询命令包括该存储器的首逻辑区块地址和地址长度，该查询命令包括该存储器的所有的逻辑区块地址为例进行说明。
可选的，当处理器与存储器之间采用不同的协议进行通信时，该查询命令也被封装成不同的格式。下面分别将该查询命令的三种格式进行说明。
在第一种可能的实现方式中，该处理器与该存储器之间采用NVME协议进行通信，则该查询命令被封装成NVME命令。
在第二中可能的实现方式中，该处理器与该存储器之间采用SAS协议进行通 信，则该查询命令被封装成SAS命令。
在第三种可能的实现方式中，该处理器与该存储器之间采用SATA协议进行通信，则该查询命令被封装成SATA命令。
此外，该有效信息可以包括地址映射信息，该地址映射信息于指示存储器中存储的数据的逻辑区块地址与物理区块地址之间的映射关系。该有效信息可以存储在该存储器中，比如，该有效信息可以存储在该存储器的闪存颗粒中，该有效信息也可以存储在该存储器外的存储设备中，比如，该有效信息可以存储在该处理器的内存中。以下实施例中，以该有效信息存储在该存储器中为例进行说明。
另外，在该存储器所包括的多个存储单元中，可能存在一部分存储单元中存储有数据(或者称为存储的数据为有效数据)，一部分存储单元中没有存储数据(或者称为存储的数据为无效数据)。上述存储器中存储的数据可以包括该存储器中存储的所有的有效数据。
S502：存储器接收来自处理器的查询命令，该查询命令用于查询该存储器中存储的数据的有效信息，该有效信息用于指示该数据是否为有效数据。
进一步的，该存储器根据该存储器的LBA查询存储在存储器中数据的地址映射信息(即有效信息)，以确定该LBA是否有与之对应的PBA，若该LBA有与之对应的PBA，则该LBA对应的存储单元中存储有数据，该数据为有效数据，该PBA为有效数据的物理区块地址，从而可以通过查询存储在存储器中数据的地址映射信息，确定该存储器中存储的有效数据的物理区块地址。在一种可能的实现方式中，该有效信息可以存储在表格中，也可以称为映射表，比如，该映射表可以为闪存转换层(flash translation layer，FTL)映射表。
其中，该映射表可以包括至少一个子映射表，该至少一个子映射表可以包括一个子映射表，也可以包括多个子映射表，不同的子映射表可以用于指示不同存储空间的地址映射信息，该存储空间的粒度可以是存储芯片、存储块或者存储页等，本申请实施例对此不作具体限制。比如，该映射表可以包括第一子映射表，此时，该第一子映射表中存储该闪存颗粒N1中的有效数据的地址映射信息；或者，该映射表可以包括第一子映射表和第二子映射表，该第一子映射表和该第二子映射表可以分别存储该存储器中存储芯片D1中的有效数据的地址映射信息，以及存储芯片D2中的有效数据的地址映射信息。
示例性的，图6为本申请实施例提供的一种映射表的示意图，图6中以该映射表包括子映射表0和子映射表1，该存储器包括第一存储块和第二存储块为例。其中，映射表0用于表示第一存储块中存储的数据区0的地址映射信息，该数据区0可以包括第一存储块中的有效数据，该数据区0的逻辑区块地址为LBA0至LBAX，该数据区0的物理区块地址为LBA0至PBAX，其中X为大于等于1的正整数。映射表1用于表示第二存储块中存储的数据区1的地址映射信息，该数据区1可以包括第二存储块中的有效数据，该数据区1的逻辑区块地址为LBAX至LBAY，该数据区1的物理区块地址为LBA1至PBAY，其中，Y为大于X的正整数。
其中，对于该存储器包括的多个存储单元中的每个存储单元，若该存储单元中存储有有效数据，则在该地址映射信息中该存储单元的LBA有与之对应的PBA，该 PBA为该存储单元中存储的数据的物理区块地址，该数据为有效数据；若该存储单元中没有存储有效数据，则在该地址映射信息中该存储单元的LBA没有与之对应的PBA或者没有该存储单元的LBA。因此，可以通过查询地址映射信息，确定该存储器中的每个存储单元的LBA是否有与之对应的PBA，从而确定该存储器中存储的有效数据的逻辑区块地址；或者，通过查询地址映射信息，确定该存储器中的每个存储单元是否有相应的LBA，从而确定该存储器中存储的有效数据的逻辑区块地址。
具体的，以该存储器包括5个存储单元，该5个存储单元的逻辑区块地址可以表示为LBA0至LBA4为例，该存储器根据LBA0查询地址映射信息，若在该地址映射信息中，该LBA0有与之对应的PBA，则该PBA为有效数据的物理区块地址，按照上述步骤，依次查询LBA1至LBA4，从而确定该5个存储单元中有效数据的逻辑区块地址。
S503：该存储器向该处理器发送有效信息，该有效信息用于指示该有效数据的地址。
其中，该有效信息可以包括该有效数据的逻辑区块地址，或者该有效信息可以包括该有效数据的逻辑区块地址的指示信息。当该有效信息包括不同的内容时，该有效信息被封装成不同的形式发送给处理器。下面分别将该有效信息的两种形式进行说明。
在第一种可能的实施例中，该有效信息包括该有效数据的逻辑区块地址，此时，该有效信息被封装成链表发送给处理器。比如，该有效数据包括第一有效数据和第二有效数据，该第一有效数据的逻辑区块地址为LBA1，该第二有效数据的逻辑区块地址为LBA2，将该LBA1与LBA2连接在一起后，以“LBA1-LBA2”的形式发送给处理器。
在第二种可能的实施例中，该有效信息包括该有效数据的逻辑区块地址的指示信息，此时，该有效信息被封装成位图发送给处理器。示例性的，该存储器包括3个存储单元，该三个存储单元的逻辑区块地址可以表示为LBA1至LBA3，其中，LBA1和LBA2分别有与之对应的PBA，LBA3中没有与之对应的PBA，此时，该LBA1和LBA2的指示信息均为1，LBA3的指示信息为0，将指示信息“110”发送给处理器，其中，1用于指示逻辑区块地址有与之对应的物理区块地址，0用于指示逻辑区块地址没有与之对应的物理区块地址。
S504：该处理器接收来自该存储器的有效信息，该有效信息用于指示该有效数据的地址。
进一步的，该处理器接收来自该存储器的有效信息之后，将该有效信息进行解析，以得到该有效数据的逻辑区块地址。下面基于S503中有效信息的两种可能的形式，将该处理器解析该有效信息的过程进行说明。
在第一种可能的实施例中，该有效信息包括该有效数据的逻辑区块地址，比如，该有效信息可以包括“LBA1-LBA2”，该处理器将“LBA1-LBA2”进行拆解后得到逻辑区块地址LBA1和逻辑区块地址LBA2，该LBA1为第一有效数据的逻辑区块地址，该LBA2第二有效数据的逻辑区块地址，从而得到该存储器中的有效数据的逻辑区块地址为LBA1和LBA2。
在第二种可能的实施例中，该有效信息包括有效数据的逻辑区块地址的指示信息，比如，该有效信息可以包括“110”，该处理器将有效数据的逻辑区块地址的指示信息“110”与该存储器中的逻辑区块地址进行对比解析，可知逻辑区块地址LBA1和逻辑区块地址LBA2的有效信息均为1，则表示逻辑区块地址LBA1和逻辑区块地址LBA2分别有与之对应的物理区块地址，逻辑区块地址LBA3的指示信息为0，则表示逻辑区块地址LBA3没有与之对应的物理区块地址，即该逻辑区块地址LBA3中没有存储数据，从而得到该存储器中的有效数据的逻辑区块地址为LBA1和LBA2。
S505：该处理器向该存储器发送访问请求，其中，该访问请求包括该有效数据的地址信息。
其中，用于访问存储器中所有的有效数据的访问请求可以是一次性发送的，也可以是通过多次发送的。下面分别将处理器的两种访问形式进行说明。以下实施例中，以该存储器中包括多个有效数据为例进行说明。
第一种可能的实施例中，该处理器一次性访问该存储器，具体的，该处理器向该存储器发送一次访问请求，该访问请求中包括该多个逻辑区块地址，该多个逻辑区块地址为该存储器中所有有效数据的逻辑区块地址。
第二种可能的实施例中，该处理器根据该多个有效数据的多个逻辑区块地址一个一个地进行访问，具体的，该处理器向该存储器发送多次访问请求，多次访问请求中的每次访问请求中包括一个逻辑区块地址，该逻辑区块地址为该存储器中一个有效数据的逻辑区块地址，直到将该存储器中所有的有效数据的逻辑区块地址均发送给存储器。
S506：该存储器接收来自该处理器的访问请求，该访问请求用于访问该有效数据，其中，该访问请求包括该有效数据的地址信息。
下面基于S505中处理器两种可能的访问形式，对该存储器读取有效数据的两种不同的方式程进行详细的说明。
在第一种可能的实施例中，该存储器只接收到一个访问请求，该访问请求中包括多个逻辑区块地址，该存储器依次确定该多个逻辑区块地址中的每个逻辑区块地址对应的物理区块地址，并读取该物理区块地址中的有效数据，从而得到该存储器中的多个有效数据。
在第二种可能的实施例中，该存储器每次接收一个访问请求，该访问请求包括该一个逻辑区块地址，该存储器根据确定该逻辑区块地址对应的物理区块地址，并读取该物理区块地址中的有效数据，该存储器接收一个访问请求读取一个有效数据，直到得到该存储器中的多个有效数据。
S507：该存储器向该处理器发送数据信息，该数据信息包括该有效数据。
下面基于S506中存储器的两种有效数据读取方式，对该存储器发送有效数据的两种形式进行说明。
在第一种可能的实施例中，该多个有效数据是一次性发送的，具体的，该存储器将该存储器中的多个有效数据一次性发送给该处理器，即该存储器一次性读取完该存储器中的多个有效数据，并将该多个有效数据一次性发送给该处理器。
在第一种可能的实施例中，该多个有效数据是一个一个发送的，具体的，该存储 器将该存储器中的有效数据一个一个的发送给处理器，即该存储器读取一个有效数据，向处理器发送一个有效数据。
S508：该处理器接收来自该存储器的数据信息，该数据信息包括该有效数据。
进一步的，该方法还包括：该处理器向该存储器发送删除命令，该删除命令用于删除目标数据。
其中，在该处理器向该存储器发送删除命令之前，该处理器接收来自用户的删除指令，该删除指令可以包括目标数据，该处理器接收到该删除指令后，根据该删除指令包括的目标数据确定该目标数据的LBA。该目标数据也可以称为无效数据。
进一步的，该方法还包括：该存储器接收来自该处理器的删除命令，并根据该删除命令删除目标数据。具体的，该删除命令中包括该目标数据的物理区块地址，该存储器接收到删除命令后，根据该目标数据的物理区块地址，并删除该物理区块地址中存储的目标数据。
进一步的，该存储器中还存储有该目标数据的地址信息，该方法还包括：在存储器删除该目标数据之后，该存储器还删除该目标数据的地址信息，该地址信息包括存储在该存储器的地址映射信息中的PBA、或者LBA和PBA。
可选的，该有效信息、该访问请求、数据信息，删除命令可以通过NVME协议、SAS协议或者SATA协议中的任意一种协议进行传输。本申请实施例对此不做具体限定。
为便于理解，下面以图7所示的处理器和SSD的结构示意图为例，对处理器和SSD的具体结构进行说明。如图7所述，该处理器包括：I/O模块701、特性遍历模块702、I/O下发模块703和驱动模块704。其中，I/O模块701可用于向I/O下发模块703发送删除命令，特性遍历模块702可用于向I/O下发模块703发送查询命令和访问请求，以及接收存储器发送的信息，I/O下发模块703可用于对删除命令、查询命令和访问请求进行封装，以及解析存储器发送的信息，驱动模块704可用于下发封装后的删除命令、查询命令和访问请求，其中，驱动模块704与SSD连接，该处理器通过驱动模块704与SSD进行通信。图7中的I/O模块701、特性遍历模块702、I/O下发模块703和驱动模块704均可以为上述图4中的处理器。
为便于理解，下面以图8所示的流程图为例，对本申请提供的技术方案进行举例说明。如图8所示，该方法包括：S1、特性遍历模块向I/O下发模块发送查询命令，所述查询命令用于查询SSD的存储器中存储的有效数据的地址信息(发送查询命令)；S2、I/O下发模块对该查询命令进行封装(封装查询命令)；S3、I/O下发模块将封装后的查询命令发送给驱动模块(发送封装后的查询命令)；S4、驱动模块接收封装后的查询命令，并将封装后的查询命令发送给SSD(接收并发送封装后的查询命令)；S5、SSD接收到封装后的查询命令，并对查询命令进行解析；S6、SSD查询映射表，以确定有效数据的逻辑区块地址；S7、SSD将有效数据的逻辑区块地址封装成位图或者链表的形式发送给特性遍历模块；S8、特性遍历模块接收并解析位图或者链表，以得到有效数据的逻辑区块地址；S9、特性遍历模块向I/O下发模块发送访问请求，该访问请求中包括该有效数据的逻辑区块地址(发送访问请求)；S10、I/O下发模块对该访问请求进行封装(封装访问请求)；S11、I/O下发模块将封装后的 访问请求发送给驱动模块(发送封装后的访问请求)；S12、驱动模块接收封装后的访问请求，并将封装后的访问请求发送给固态硬盘(接收并发送封装后的访问请求)；S13、SSD接收访问请求，读取有效数据；S14、SSD将读取到的有效数据发送给特性遍历模块；S15、特性遍历模块接收SSD发送的有效数据。
为便于理解，下面以图9所示的流程图为例，对本申请提供的技术方案中的目标数据的删除过程进行举例说明。S1、I/O模块检测到无效数据；S2、I/O模块向I/O下发模块发送删除命令，该删除命令包括无效数据和无效数据的逻辑区块地址(发送删除命令)；S3、I/O下发模块对该删除命令进行封装；S4、I/O下发模块将封装后的删除命令发送给驱动模块；S5、驱动模块接收封装后的删除命令；S6、驱动模块将封装后的删除命令发送发给SSD；S7、SSD接收封装后的删除命令，并进行解析；S8、SSD删除存储在SSD中的无效数据；S9、SSD删除存储在SSD中的无效数据的逻辑区块地址和物理区块地址。
本申请实施例提供的数据读取方法，在处理器遍历读取存储器中的数据时，处理器向存储器发送查询命令，存储器根据该查询命令来查询存储器中存储的数据的有效信息，即存储器根据该查询命令来查询该存储器中存储的数据的地址映射信息，以确定该存储器中存储的有效数据的地址信息，存储器将该有效数据的地址信息发送给处理器，处理器根据该有效数据的地址信息对该存储器进行遍历读取，以得到该存储器中的有效数据。该技术方案中，该处理器只对该存储器中存储有效数据的存储空间进行了访问，而不是将该存储器中的所有存储空间均进行访问，与现有技术中，处理器在遍历读取存储器中的数据时，将存储器中的所有存储空间均访问一次相比，提高了遍历读取数据的效率；另一方面，该存储器根据有效数据的地址信息读取有效数据，无需对读取出的数据进行校验即可得到有效数据，与现有技术中，将遍历读取出的数据进行检验才能得到有效数据相比，提高了数据的准确性。
可以理解的是，该处理器和存储器为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中实施例描述的各示例的数据读取方法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对处理器和存储器进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图10示出了一种上述实施例中所涉及的处理器的一种可能的结构示意图，该处理器包括：发送单元01和接收单元02，该发送单元01，用于支持该处理器执行上述方法实施例中的S501和S505中的一个或多个步骤，该接收单元02，用于支持该处理器执行上述方法实施例中的S504和S508中的一个或多个步骤。
在硬件实现上，发送单元01和接收单元02可以是图4所示的处理器，关于该处理器的具体描述可以参见图4中的具体描述，本申请实施例在此不再赘述。
在采用对应各个功能划分各个功能模块的情况下，图11示出了上述实施例中所涉及的存储器的一种可能的结构示意图，该存储器包括：接收单元101和发送单元102，该接收单元101用于支持该存储器执行上述方法实施例中的S502和S506中的一个或多个步骤，该发送单元102用于支持该存储器执行上述方法实施例中的S503和S507中的一个或多个步骤。
可选的，该存储器还包括：查询单元103和读取单元104，该查询单元103，用于根据该存储器的逻辑区块地址查询有效信息，以确定该有效数据的物理区块地址，该地址映射信息用于指示该存储器中存储的有效数据的逻辑区块地址与物理区块地址之间的映射关系，该读取单元104，用于根据该有效数据的地址信息，从该存储器中读取该有效数据。
在硬件实现上，接收单元101、发送单元102、查询单元103和读取单元104可以是图1所示的控制器，关于该控制器的具体描述可以参见图1中的具体描述，本申请实施例在此不再赘述。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。本申请实施例提供的处理器和存储器，用于执行上述实施例中对应的功能，因此可以达到与上述控制方法相同的效果。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该软件产品存储在一个存储介质中，包括若干指令用以使得装置执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
本申请的另一方面，提供一种电子设备，该电子设备包括处理器和存储器，该处理器和该存储器可用于执行上述方法实施例中的相关步骤，该处理器可以为上述图3、图4、图7和图10中所提供的处理器，该存储器可以为上述图2、图3、图7和图11中所提供的存储器。
在本申请的又一方面，提供一种计算机可读存储介质，该计算机可读存储介质包括计算机指令，当该计算机指令在处理器上运行时，使得该处理器执行上述方法实施 例中的相关步骤。
在本申请的又一方面，提供一种计算机可读存储介质，该计算机可读存储介质包括计算机指令，当该计算机指令在存储器上运行时，使得该存储器执行上述方法实施例中的相关步骤。
在本申请的又一方面，提供一种包含指令的计算机程序产品，当计算机程序产品在计算机设备上运行时，使得处理器执行上述方法实施例中的相关步骤。
在本申请的又一方面，提供一种包含指令的计算机程序产品，当计算机程序产品在计算机设备上运行时，使得存储器执行上述方法实施例中的相关步骤。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种数据读取方法，其特征在于，所述方法包括：
    处理器向存储器发送查询命令，所述查询命令用于查询所述存储器中存储的数据的有效信息，所述有效信息用于指示所述数据是否为有效数据；
    所述处理器接收来自所述存储器的所述有效信息，当所述有效信息指示所述数据为有效数据时，所述处理器向所述存储器发送访问请求，其中，所述访问请求包括所述有效数据的地址信息；
    所述处理器接收来自所述存储器的数据信息，所述数据信息包括所述有效数据。
  2. 根据权利要求1所述的数据读取方法，其特征在于，所述查询命令为非易失性内存主机控制器接口规范NVME命令、串行连接SCSI SAS命令或串行高级技术附件SATA命令。
  3. 根据权利要求1或2所述的数据读取方法，其特征在于，所述有效信息是以位图或者链表的形式指示所述有效数据的地址信息。
  4. 根据权利要求1-3任一项所述的数据读取方法，其特征在于，所述方法还包括：
    所述处理器向所述存储器发送删除命令，所述删除命令用于删除目标数据。
  5. 一种数据读取方法，其特征在于，所述方法包括：
    存储器接收来自处理器的查询命令，所述查询命令用于查询所述存储器中存储的数据的有效信息，所述有效信息用于指示所述数据是否为有效数据；
    所述存储器向所述处理器发送所述有效信息；
    所述存储器接收来自所述处理器的访问请求，其中，所述访问请求包括所述有效数据的地址信息；
    所述存储器向所述处理器发送数据信息，所述数据信息包括所述有效数据。
  6. 根据权利要求5所述的数据读取方法，其特征在于，所述存储器接收来自处理器的查询命令之后，所述方法还包括：
    所述存储器根据所述存储器的逻辑区块地址查询地址映射信息，以确定所述有效数据的物理区块地址，所述地址映射信息用于指示所述存储器中存储的所述数据的逻辑区块地址与物理区块地址之间的映射关系。
  7. 根据权利要求5或6所述的数据读取方法，其特征在于，所述存储器接收来自所述处理器的访问请求之后，所述方法还包括：
    所述存储器根据所述有效数据的地址信息，从所述存储器中读取所述有效数据。
  8. 根据权利要求5-7任一项所述的数据读取方法，其特征在于，所述查询命令为非易失性内存主机控制器接口规范NVME命令、串行连接SCSI SAS命令或串行高级技术附件SATA命令。
  9. 根据权利要求5-8任一项所述的数据读取方法，其特征在于，所述有效信息是以位图或者链表的形式指示所述有效数据的地址信息。
  10. 根据权利要求5-9任一项所述的数据读取方法，其特征在于，所述方法还包括：
    所述存储器接收来自所述处理器的删除命令，并根据所述删除命令删除目标数据。
  11. 根据权利要求10所述的数据读取方法，其特征在于，所述存储器中还存储有 所述目标数据的地址信息，所述方法还包括：
    所述存储器删除所述目标数据的地址信息。
  12. 一种处理器，其特征在于，所述处理器包括：
    发送单元，用于向存储器发送查询命令，所述查询命令用于查询所述存储器中存储的数据的有效信息，所述有效信息用于指示所述数据是否为有效数据；
    接收单元，用于接收来自所述存储器的有效信息；
    当所述有效信息指示所述数据为有效数据时，所述发送单元，还用于向所述存储器发送访问请求，其中，所述访问请求包括所述有效数据的地址信息；
    所述接收单元，还用于接收来自所述存储器的数据信息，所述数据信息包括所述有效数据。
  13. 根据权利要求12所述的处理器，其特征在于，所述查询命令为非易失性内存主机控制器接口规范NVME命令、串行连接SCSI SAS命令或串行高级技术附件SATA命令。
  14. 根据权利要求12或13所述的处理器，其特征在于，所述有效信息是以位图或者链表的形式指示所述有效数据的地址信息。
  15. 根据权利要求12-14任一项所述的处理器，其特征在于，所述发送单元还用于：
    向所述存储器发送删除命令，所述删除命令用于删除目标数据。
  16. 一种存储器，其特征在于，所述存储器包括：
    接收单元，用于接收来自处理器的查询命令，所述查询命令用于查询所述存储器中存储的数据的有效信息，所述有效信息用于指示所述数据是否为有效数据；
    发送单元，用于向所述处理器发送所述有效信息；
    所述接收单元，还用于接收来自所述处理器的访问请求，其中，所述访问请求包括所述有效数据的地址信息；
    所述发送单元，还用于向所述处理器发送数据信息，所述数据信息包括所述有效数据。
  17. 根据权利要求16所述的存储器，其特征在于，所述存储器还包括查询单元；
    所述查询单元，用于根据所述存储器的逻辑区块地址查询地址映射信息，以确定所述有效数据的物理区块地址，所述地址映射信息用于指示所述存储器中存储的所述数据的逻辑区块地址与物理区块地址之间的映射关系。
  18. 根据权利要求16或17所述的存储器，其特征在于，所述存储器还包括读取单元；
    所述读取单元，用于在所述接收单元接收到所述处理器的访问请求之后，根据所述有效数据的地址信息，从所述存储器中读取所述有效数据。
  19. 根据权利要求16-18任一项所述的存储器，其特征在于，所述查询命令为非易失性内存主机控制器接口规范NVME命令、串行连接SCSI SAS命令或串行高级技术附件SATA命令。
  20. 根据权利要求16-19任一项所述的存储器，其特征在于，所述有效信息是以位图或者链表的形式指示所述有效数据的地址信息。
  21. 根据权利要求16-20任一项所述的存储器，其特征在于，所述存储器还包括删除单元：
    所述接收单元，还用于接收来自所述处理器的删除命令；
    所述删除单元，用于根据所述删除命令删除目标数据。
  22. 根据权利要求21所述的存储器，其特征在于，所述存储器中还存储有所述目标数据的地址信息，所述删除单元还用于：
    删除所述目标数据的地址信息。
  23. 一种电子设备，其特征在于，所述终端设备包括处理器和存储器，所述处理器为如权利要求12-15任一项所述的处理器，所述存储器为如权利要求16-22任一项所述的存储器。
  24. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有指令，当所述指令在处理器上运行时，使得所述处理器执行如权利要求1-4任一项所述的方法。
  25. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有指令，当所述指令在存储器上运行时，使得所述存储器执行如权利要求5-11任一项所述的方法。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112181280A (zh) * 2019-07-04 2021-01-05 爱思开海力士有限公司 传送存储器系统中的映射信息和读取计数的设备和方法
CN113220693A (zh) * 2021-06-02 2021-08-06 北京字节跳动网络技术有限公司 计算存储分离系统及其数据访问方法、介质和电子设备
CN113535068A (zh) * 2020-04-21 2021-10-22 华为技术有限公司 数据读取方法和系统

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112181280A (zh) * 2019-07-04 2021-01-05 爱思开海力士有限公司 传送存储器系统中的映射信息和读取计数的设备和方法
CN113535068A (zh) * 2020-04-21 2021-10-22 华为技术有限公司 数据读取方法和系统
CN113220693A (zh) * 2021-06-02 2021-08-06 北京字节跳动网络技术有限公司 计算存储分离系统及其数据访问方法、介质和电子设备

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