WO2023172731A1 - Concentrateur usb3 automatique pour détecter et modifier la vitesse de liaison - Google Patents

Concentrateur usb3 automatique pour détecter et modifier la vitesse de liaison Download PDF

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Publication number
WO2023172731A1
WO2023172731A1 PCT/US2023/014967 US2023014967W WO2023172731A1 WO 2023172731 A1 WO2023172731 A1 WO 2023172731A1 US 2023014967 W US2023014967 W US 2023014967W WO 2023172731 A1 WO2023172731 A1 WO 2023172731A1
Authority
WO
WIPO (PCT)
Prior art keywords
usb
connection
port
errors
detector circuit
Prior art date
Application number
PCT/US2023/014967
Other languages
English (en)
Inventor
Andrew Rogers
Original Assignee
Microchip Technology Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/077,385 external-priority patent/US20230289312A1/en
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Priority to CN202380013933.1A priority Critical patent/CN118076949A/zh
Publication of WO2023172731A1 publication Critical patent/WO2023172731A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823—Errors, e.g. transmission errors
    • H04L43/0847—Transmission error
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/25—Flow control; Congestion control with rate being modified by the source upon detecting a change of network conditions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3812—USB port controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/16—Threshold monitoring

Definitions

  • the present application relates to USB3 link operations, and in particular, relates to systems and methods to detect marginal USB3 link operation and change link connection speed to improve overall performance.
  • USB 1.0 supports speeds up to 1.5 Mbps and USB 1.1 supports speeds up to 12 Mbps. Since then, USB has progressed into versions 2.0 and 3.0 and became ubiquitous in computers as well as portable devices, such as smartphones, tablet computers, and MP3 players. USB 2.0 supports speeds up to 480 Mbps. Later, USB 3.0 became a universal standard and supports speeds up to 5 Gbps. USB 3.0 and/or USB 3.1 came to have Gen 1 and Gen 2 capabilities. The difference between USB 3.1 Gen 1 and USB 3.1 Gen 2 is only in terms of speed.
  • USB 3.1 Gen 1 supports speeds of up to 5 Gbps, while USB 3.1 Gen 2 supports speeds of up to 10 Gbps. Still later, USB 3.2 became a universal standard. Similarly, the difference between USB 3.2 Gen 1 and USB 3.2 Gen 2 is only in terms of speed. USB 3.2 Gen 1 supports speeds of up to 5 Gbps, while USB 3.2 Gen 2 supports speeds of up to 10 Gbps.
  • USB communication In general, in USB communication, a host is defined, and another peripheral acts as a device, connected to the host over a bus.
  • the host powers the bus, issues commands, and generally maintains control over the connection.
  • the peripheral device usually does not initiate any activity for control of the bus.
  • a personal computer acts as a host to a USB “thumb drive” device.
  • a USB hub is a device that expands a single USB port into several USB ports, so that there are more ports available to connect devices to the host.
  • the USB Type-C connector has been developed to help enable thinner and sleeker product designs, enhance usability and provide a growth path for performance enhancements for future versions of USB.
  • the Type-C connector is built on existing USB 3.1 and USB 2.0 technologies.
  • USB Type-C is a 24-pin USB connector system with a rotationally symmetrical connection. The designation C refers only to the connector’s physical configuration or form factor and should not be confused with the connector’s specific capabilities, which are designated by its transfer specifications.
  • USB devices When USB devices are connected to a host via USB cable connections, poor quality communications are sometimes encountered.
  • the current USB specifications do not provide a solution for poor quality connections and assumes USB devices and hosts will act to mitigate data loss issues.
  • Current USB devices, hosts, and hubs do little to address poor data transmission.
  • the current USB specification does not envision the USB hub taking an active role in error detection and mitigation. No mechanisms exist today, and this type of functionality has not been observed in currently available USB hubs.
  • USB hub, host, or device that can automatically detect significant or critical data loss in a USB connection and take corrective action so the impact to the end user can be reduced.
  • An apparatus includes a non-transitory, machine-readable medium including instructions.
  • the instructions when loaded and executed by a processor, cause the processor to perform automatic USB hub poor link quality detection and speed roll-back.
  • a USB host may force individual USB hub ports to specified USB speeds (i.e., force a USB port operating at Gen2 speeds to switch to Genl speed due to excessive errors detected when operating at Gen2 speeds).
  • a method comprising: counting errors encountered by a USB connection; comparing a number of counted errors to an error count threshold within a set time frame; identifying a port speed configuration for the USB connection; and changing the port speed configuration for the USB connection to a slower port speed configuration than the identified port speed configuration
  • a further aspect provides an apparatus having a connection detector circuit that counts errors encountered by a USB connection operating at an initial speed, compares a number of counted errors to a preset threshold number of errors, and identifies a port speed configuration for the USB connection, and a control circuit that changes the port speed configuration of the USB connection to a speed slower than the initial speed.
  • a system having a USB hub with an upstream port, a downstream port, and a switch in electrical communication with the upstream port and the downstream port, a USB host in electrical communication with the upstream port via a first USB connection, a USB device in electrical communication with the downstream port via a second USB connection, a connection detector circuit that counts errors encountered by either the first or second USB connection, compares a number of counted errors to a preset threshold number of errors, and identifies a port speed configuration for either the first or second USB connection, and a control circuit that changes the port speed configuration of either the first or second USB connection to a slower speed.
  • the figures illustrate example flows and systems for detecting marginal USB3 link operation and throttle connection speed to improve overall performance and prevent disconnect.
  • Various error counters for each port may be implemented and specific actions may be taken to throttle connection speed when a counter exceeds a configured threshold.
  • FIGURE l is a diagram illustrating an example USB environment that includes a USB hub, a USB host, and a USB device, wherein the USB hub has a connection detector circuit and a speed circuit.
  • FIGURE 2 shows a flow chart algorithm for the connection detector and speed circuits of FIGURE 1 whereby the USB hub may detect a poor quality USB connection and throttle the connection to improve performance.
  • FIGURE 3 is a diagram illustrating an example USB environment that includes a hub, a USB host, and a USB device, wherein the USB host has a connection detector circuit and the USB hub has a speed circuit.
  • FIGURE 4 shows a flow chart algorithm for the connection detector and speed circuits of FIGURE 3 whereby the USB host may detect a poor quality USB connection and throttle the connection to improve performance.
  • FIGURE 5 is a diagram illustrating an example USB environment that includes a hub, a USB host, and a USB device, wherein the USB device has a connection detector circuit and the USB hub has a speed circuit.
  • FIGURE 6 shows a flow chart algorithm for the connection detector and speed circuits of FIGURE 5 whereby the USB device may detect a poor quality USB connection and the speed circuit may throttle the connection to improve performance.
  • FIGURE 7 shows a schematic diagram for a software implementation of a connection detection circuit.
  • FIGURE 8 shows a schematic diagram for detecting a poor quality USB connection and throttling the connection to improve performance, comprising a connection detection circuit and a speed circuit.
  • Automatic USB hosts, automatic USB hubs, and automatic USB devices are described herein for poor link quality detection and speed roll-back. Automatic connections are made either when the user plugs a USB device in to a USB host or a USB hub and the ports and speeds are configured according to policy settings. Further, automatic USB hosts, automatic USB hubs, and automatic USB devices may be used in USB3 interfaces with Type-C functionality by implementing various error counters for each port, and taking specific actions to throttle connection speed when a counter exceeds a configured threshold. For example, USB hubs may allow poor quality devices or devices connected with poor quality cables to operate at a reduced signal rate in order to prevent total failure. USB hubs may fine tune the functionality to meet custom specifications. USB hubs may be compatible for USB devices and cables to operate together. Of course, the USB hub functionality may be implemented with firmware of the USB hub and may not have a new hardware design, but hardware implementations are possible and reduce the burden on firmware and improve reliability.
  • USB hubs may fine tune the functionality to meet the specifications/needs of the host/hub/device environment.
  • Devices plus cables which would simply not work at the set signal rate may be configured to operate at a slower signal rate with connection detector circuits as disclosed herein. Examples may be implemented within firmware of the host, hub or device, and may not have new hardware design. Alternatively, a hardware implementation may also reduce the burden on firmware development and improve reliability if implemented with hardware.
  • USB3.2 device i.e. a device that meets the USB 3.2 standard released by the USB Implemented Forum (USB-IF)
  • USB-IF USB Implemented Forum
  • a USB3 Gen2 device supporting lOGbit/second with a poor quality cable may have lower overall data throughput than the same device and cable when connected to a USB3 Genl port, which USB3 Genl port supports 5Gbit/second.
  • Poor data communication can also happen on a USB hub upstream port as well, e.g., between the USB hub and the USB host, causing connections to all devices on the downstream ports to suffer.
  • Detection of a poor quality USB connection may be implemented via various firmware or hardware-based error counters. Types of errors counted may include: number of entries to link recovery; number of warm resets received; number of retries detected; and number of LBAD (link bad) link commands received. For example, for any of these types of errors, if fifteen errors are counted in one second, the USB connection may be determined to be poor quality. End system integrator configurable parameters may include: mask operation on error type; error counter thresholds (1 per error type), wherein a user may set a threshold to define what “excessive” means; mode select an infinite error count persistence mode or a rolling window mode; and rolling window timing.
  • a threshold for detecting an error condition indicative of a poor quality USB connection may be based on a single error type, or it may be based on a combination of error types, and it may also be based on the number of errors counted per unit time. For a combination example, a threshold may be preset for a first error type and another threshold may be set for a second error type, and both thresholds would be met before the quality of the USB connection would be determined to be poor. New hardware or USB devices may be run in the port to implement error counters. The connection quality may be detected/throttled by the USB hub, the USB host, or the USB device.
  • the system 100 includes a USB hub 102, a USB host 112, and a USB device 114.
  • the USB hub 102 has an upstream port 108 and four downstream ports 110a, 110b, 110c, 1 lOd.
  • a switching hub 104 switches between the downstream ports 110a, 110b, 110c, HOd.
  • a control circuit 105 functions to receive and process signals over the USB port(s) and controls the switching hub 104.
  • the control circuit 105 may be implemented by instructions in a medium for execution by a processor, a function, library call, subroutine, shared library, software as a service, analog circuitry, digital circuitry, control logic, digital logic circuits programmed through hardware description language, application-specific integrated circuit (ASIC), field- programmable gate array (FPGA), programmable logic device (PLD), or any suitable combination thereof, or any other suitable mechanism, whether in a unitary device or spread over several devices.
  • a connection detector circuit 106 detects errors per unit of time and identifies port speeds.
  • a speed circuit 103 changes the port to a slower speed configuration.
  • connection detector circuit 106 and the speed circuit 103 may be implemented by instructions in a medium for execution by a processor, a function, library call, subroutine, shared library, software as a service, analog circuitry, digital circuitry, control logic, digital logic circuits programmed through hardware description language, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), or any suitable combination thereof, or any other suitable mechanism, whether in a unitary device or spread over several devices.
  • the USB hub 102 may be implemented as a USB46x4 hub available from Microchip Technology Incorporated, of Chandler, Arizona, if modified to include a connection detector circuit 106 and speed circuit 103, as described herein.
  • the USB host 112 is connected to the USB hub 102 via a cable 109.
  • the USB device 114 may also be connected to the hub 102 via one of the downstream ports 110a, 110b, 110c, HOd, wherein a Type-C connector may be used for the connection.
  • the USB hub 102 has a connection detector circuit 106 that includes hardware based error counters, firmware, or both, to throttle connections.
  • connection detector circuit 106 may be implemented by instructions in a medium for execution by a processor, a function, library call, subroutine, shared library, software as a service, analog circuitry, digital circuitry, control logic, digital logic circuits programmed through hardware description language, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), or any suitable combination thereof, or any other suitable mechanism, whether in a unitary device or spread over several devices.
  • ASIC application-specific integrated circuit
  • FPGA field-programmable gate array
  • PLD programmable logic device
  • FIGURE 2 shows a flow chart algorithm for the connection detector circuit 106 of FIGURE 1 whereby the USB hub 102 detects a poor quality USB connection and throttles the connection to improve performance.
  • the USB hub 102 monitors the USB connection through upstream port 108 and cable 109 as well as the downstream ports 110a - HOd, and checks whether these connections are to a USB host or to USB devices.
  • the algorithm starts by clearing 202 all error counters. Errors are then counted 204 and a determination is made whether the error count has exceeded an error count threshold within a set time frame. If the error counter threshold is not exceeded within the set time frame, the algorithm waits 206, clears 202 the error counters, and again begins another count 204 of error within a new set time frame.
  • the algorithm next determines the port speed 208 for the connection for which the error counter threshold is exceeded within the set time frame: e.g., USB3.2 Gen2 (10G) or USB3.2 Genl (5G). In both cases, the algorithm next determines 210A and 210B the port type: (1) upstream (e.g., connection to USB host 112); or (2) downstream (e.g. connection to USB device 114).
  • the port speed 208 for the connection for which the error counter threshold is exceeded within the set time frame: e.g., USB3.2 Gen2 (10G) or USB3.2 Genl (5G).
  • the algorithm next determines 210A and 210B the port type: (1) upstream (e.g., connection to USB host 112); or (2) downstream (e.g. connection to USB device 114).
  • the connection detector circuit 106, or control circuit 105, or both temporarily disconnects 212 the upstream port USB3 interface and reconnects with Gen2 capability masked, thereby enforcing a lower data speed, i.e. the throughput of USB3 Genl.
  • This action causes the upstream connection to drop to a USB3 Gen 1 (5G) port speed connection, by a respective action of the USB host 112.
  • the connection detector circuit 106 disconnects 214 the upstream port USB3 interface and issues a USB3 warm reset to all of the downstream ports with USB3 devices attached and then disconnects/deactivates all of the downstream USB3 interface(s). This action causes the downstream connection to reconfigure for USB2.
  • an upstream port e.g., connection to USB host 112 configured for USB3 Gen 1 (5g) speed
  • the connection detector circuit 106 disconnects 214 the upstream port USB3 interface and issues a USB3 warm reset to all of the downstream ports with USB3 devices attached and then disconnects/deactivates all of the downstream USB3 interface(s). This action causes the downstream connection to reconfigure for USB2.
  • the connection detector circuit 106, or control circuit 105, or both issues a ware reset 216 to the downstream port, and masks Gen2 capability bits, and then reconnects the port with Gen2 capability bits masked. This action causes the connection to reconfigure for USB3 Genl (5G) speeds. If the port for which the error counter threshold is exceeded within the set time frame is on a downstream port configured for USB3.2 Genl (5G) speeds, the connection detector circuit 106, or control circuit 105, or both, issues a warm reset to the port, and disconnects/deactivates the USB3 interface. This action causes the connection to reconfigure for USB2 speeds.
  • This functionality may be implemented in the USB hub’s firmware or hardware.
  • FIGURE 3 illustrates a diagram of an example USB hub environment similar to the environment shown in FIGURE 1 except that the connection detector circuit 106 and speed circuit 103 are in the USB host 112.
  • the USB Host 112 has a connection detector circuit 106 that may include hardware based error counters, or firmware, or both, to determine the quality of the throughput and the speed circuit 103 may include hardware, or firmware, or both to the throttle connections.
  • the USB host 112 is connected to the hub 102 via a cable 109 through upstream port 108.
  • the connection detector circuit 106 may be in the USB Host 112 and the speed circuit 103 may be in the USB Hub 102.
  • the connection detector circuit 106 may be in the USB Hub 102 and the speed circuit 103 may be in the USB Host 112.
  • FIGURE 4 shows a flow chart algorithm for the connection detector circuit 106 of FIGURE 3 whereby the USB host 112 detects a poor quality USB connection (cable 109 and upstream port 108) and throttles the connection to improve performance.
  • the connection detector circuit 106 starts by clearing 402 all error counters. Errors are then counted 404 and a determination is made whether the error count has exceeded an error count threshold within a set time frame. If the error counter threshold is not exceeded within the set time frame, the algorithm waits 406, clears the error counters 402, and begins another count 404 of error within the set time frame, i.e. within a next set time frame.
  • the algorithm next determines 408 the port speed for the connection: USB3.2 Gen2 (10G) or USB3.2 Genl (5G). If the error counter threshold is exceeded within the set time frame for a USB connection 109, the algorithm of the speed circuit 103 configures for USB3 Gen2 (10G) speeds, wherein the speed circuit 103 issues a USB3 warm reset to the port and reconnects with Gen2 capability bits masked. This action causes the connection to reconfigure for USB3 Genl (5G) speeds. If the error counter threshold is exceeded within the set time frame for a USB connection 109 configured for USB3.2 Genl (5G) speeds, the speed circuit 103 issues a USB3 warm reset 414 to the port and disconnects/deactivates the USB3 interface. This action causes the connection to reconfigure for USB2 speed, since USB3 capability has been disconnected/deactivated.
  • This functionality may be implemented in the USB host’s firmware or hardware.
  • FIGURE 5 shows a diagram where the connection detector circuit 106 is in the USB device 114 in the example USB hub environment.
  • the system 100 includes a hub 102, one or more control circuits 105, a USB host 112, and a USB device 114, wherein a number of USB devices 114 may be connected to the hub 102 via downstream ports 1 Wal l Od.
  • the USB device 114 has a connection detector circuit 106 that includes hardware based error counters, or firmware based error counters, or both, and a speed circuit 103 to throttle connections.
  • FIGURE 6 shows a flow chart algorithm for the connection detector circuit 106 and speed circuit 103 of FIGURE 5 whereby the USB device 114 detects a poor quality USB connection and throttles the connection to improve performance.
  • the USB device 114 monitors the USB connection.
  • the connection detector circuit 106 starts by clearing 602 all error counters. Errors are then counted 604 and a determination is made whether the error count has exceeded an error count threshold within a set time frame. If the error counter threshold is not exceeded with the set time frame, the algorithm waits 606, clears the error counters 602, and begins another count 604 of errors within the set time frame, i.e. a subsequent instance of the set time frame.
  • the algorithm next determines 608 the port speed for the connection: USB3 Gen2 (10G) or USB3 Genl (5G). If the error counter threshold is exceeded within the set time frame where the USB connection is configured for USB3.2 Gen2 (10G) speeds, the speed circuit 103 temporarily disconnects 612 the USB 3 interface, and reconnects with Gen2 capability bits masked. This action causes the connection to drop to a USB3 Gen 1 (5G) port speed connection. If the error counter threshold is exceeded within the set time frame where the USB connection is configured for USB3.2 Gen 1 (5g) speeds, the speed circuit 103 disconnects/deactivate 614 USB3 interface and issues a USB3 Warm Reset to the port. This action causes the connection to reconfigure for USB2.
  • This functionality may be implemented in the USB device’s 114 firmware or hardware.
  • Connection detectors 106 or speed circuit 103 as disclosed herein may be implemented in USB3 hubs, USB hosts, and USB devices designed for the automotive industry, in particular, which almost universally adopts USB Type-C ports with USB power delivery.
  • FIGURE 7 illustrates a schematic diagram of a connection detector and speed circuit 706 which may be an example of connection detector circuit 106 or speed circuit 103. See FIGURES 1, 3, and 5.
  • This example of the connection detector and speed circuit 706 has a processor 702 and a non-transitory, machine-readable medium 704 including instructions 708.
  • the instructions include: counting errors encountered by a USB connection; comparing a number of counted errors to a preset threshold number of errors; identifying a port speed configuration for the USB connection; and changing the port speed configuration for the USB connection to a slower speed. These functions may also be programed to be performed by the speed circuit 103. See FIGURES 1, 3, and 5.
  • FIGURE 8 shows a schematic diagram for detecting a poor quality USB connection and throttling the connection to improve performance, comprising a connection detection circuit 806 and a speed circuit 803.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Environmental & Geological Engineering (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)

Abstract

L'invention concerne un procédé de commande USB qui comprend : le comptage d'erreurs rencontrées par une connexion USB; la comparaison d'un nombre d'erreurs comptées à un seuil de comptage d'erreurs dans une période définie (404); l'identification d'une configuration de vitesse de port pour la connexion USB (408); et le changement de la configuration de vitesse de port pour la connexion USB à une configuration de vitesse de port plus lente que la configuration de vitesse de port identifiée (414)
PCT/US2023/014967 2022-03-11 2023-03-10 Concentrateur usb3 automatique pour détecter et modifier la vitesse de liaison WO2023172731A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202380013933.1A CN118076949A (zh) 2022-03-11 2023-03-10 用于检测和改变链路速度的自动usb3集线器

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202263319002P 2022-03-11 2022-03-11
US63/319,002 2022-03-11
US18/077,385 2022-12-08
US18/077,385 US20230289312A1 (en) 2022-03-11 2022-12-08 Automatic USB3 Hub for Detecting and Changing Link Speed

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WO2023172731A1 true WO2023172731A1 (fr) 2023-09-14

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0952700A2 (fr) * 1998-02-27 1999-10-27 Advanced Micro Devices, Inc. Equipement de réseau comme un répéteur et méthode d'essai
US20120110220A1 (en) * 2010-10-27 2012-05-03 Miyano Takahiko Communication speed control apparatus and communication speed control method
US20180232323A1 (en) * 2017-02-13 2018-08-16 Microchip Technology Incorporated Host-Detecting USB Hub

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0952700A2 (fr) * 1998-02-27 1999-10-27 Advanced Micro Devices, Inc. Equipement de réseau comme un répéteur et méthode d'essai
US20120110220A1 (en) * 2010-10-27 2012-05-03 Miyano Takahiko Communication speed control apparatus and communication speed control method
US20180232323A1 (en) * 2017-02-13 2018-08-16 Microchip Technology Incorporated Host-Detecting USB Hub

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