WO2023165543A1 - 共享缓存的管理方法、装置及存储介质 - Google Patents

共享缓存的管理方法、装置及存储介质 Download PDF

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Publication number
WO2023165543A1
WO2023165543A1 PCT/CN2023/079164 CN2023079164W WO2023165543A1 WO 2023165543 A1 WO2023165543 A1 WO 2023165543A1 CN 2023079164 W CN2023079164 W CN 2023079164W WO 2023165543 A1 WO2023165543 A1 WO 2023165543A1
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requests
cache
request
shared cache
category
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PCT/CN2023/079164
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English (en)
French (fr)
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陈泽晖
董如良
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华为技术有限公司
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Priority claimed from CN202210908210.5A external-priority patent/CN116756057A/zh
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Publication of WO2023165543A1 publication Critical patent/WO2023165543A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

Definitions

  • the present application relates to the field of computer technology, and in particular to a management method, device and storage medium of a shared cache.
  • Shared cache means that multiple entities in the cache architecture (such as multiple applications, multiple clients, or multiple processing cores (cores) of computing devices, etc.) share cache resources to meet different cache requirements. For example, for a central processing unit (central processing unit, CPU) including multiple cores in a computing device, the multiple cores share a third-level cache (last level cache, LLC) of the CPU. For another example, in a distributed cache system, the data of a single client is distributed and cached in different cache nodes. In contrast, in a scenario where there are multiple clients, multiple clients share the cache resources in a single cache node.
  • CPU central processing unit
  • LLC last level cache
  • the cache shared by multiple entities can be partitioned, so that different partitions are used to cache data to be cached by different entities.
  • the size of the partitions is usually specified artificially, or the size of the cache partitions is determined by a simple priority strategy.
  • the entire shared cache uses the same elimination algorithm, resulting in a performance loss of the shared cache. bad.
  • the present application provides a shared cache management method, device and storage medium for improving cache performance in the shared cache.
  • the present application provides a method for managing a shared cache, and the method is used for managing the shared cache.
  • the shared cache is used to cache the data requested by multiple IO requests, the multiple IO requests correspond to K categories, and the shared cache corresponds to N elimination algorithms.
  • the method includes: determining the access characteristics of the IO requests of each category in the K categories accessing the shared cache. According to the access characteristics of K categories of IO requests and the hit rate of the shared cache, determine the partition size and elimination algorithm of each category of IO requests in the shared cache.
  • the cache size of each category of IO requests in the shared cache is configured as the determined partition size of each category of IO requests in the shared cache, and the elimination algorithm of each category of IO requests in the shared cache is configured.
  • the access characteristic of the IO requests of each category in the K categories to access the shared cache is: the relationship between the hit rate of the IO requests of each category in the K categories under the N elimination algorithms and the size of the cache.
  • the management method of shared cache provided by the present application, by obtaining the access characteristics of each type of input/output (input/output, IO) request, determine the partition size and cache in the shared cache for each type of IO request.
  • the elimination algorithm is used to improve the cache performance of each type of IO request, thereby improving the cache performance in the entire shared cache.
  • the hit rate of the shared cache can be improved, thereby improving the efficiency of data reading; in the scenario of writing data, by increasing the hit rate of writing, the times of flushing the shared cache to the back-end storage unit are saved.
  • the above-mentioned determination of the access characteristics of the IO requests of each category in the K categories to access the shared cache includes: for the first elimination algorithm among the above-mentioned N elimination algorithms, simulating K in the shared cache
  • the IO request of each category in each category applies the hit rate of the first elimination algorithm in caches of different sizes to obtain the relationship between the hit rate and the cache size.
  • the first elimination algorithm is any one elimination algorithm among the N elimination algorithms.
  • the above-mentioned determination of the access characteristics of the IO requests of each category in the K categories to access the shared cache includes: for the first elimination algorithm among the above-mentioned N elimination algorithms, according to the first type of IO The reuse distance and different cache sizes of each IO request in the request determine the hit rate of the first type of IO request applied to the first elimination algorithm in caches of different sizes to obtain the relationship between the hit rate and the cache size.
  • the first elimination algorithm is any one of the N elimination algorithms
  • the first type of IO request is an IO request of any one of the K categories.
  • the above two possible designs provide two methods for determining the access characteristics of the IO requests of each of the K categories accessing the shared cache.
  • determining the partition size and elimination algorithm of each category of IO requests in the shared cache include: The X hit rates corresponding to the X cache sizes determined under each elimination algorithm for IO requests of each category determine the hit rate of IO requests of K categories in the shared cache for each combination.
  • the cache size corresponding to each category of IO requests when the hit rate of K categories of IO requests in the shared cache is the largest is determined as the partition size of each category of IO requests in the shared cache, and the K categories of IO requests
  • the elimination algorithm corresponding to each type of IO request when the hit rate of the request in the shared cache is the largest is determined as the elimination algorithm of each type of IO request in the shared cache.
  • X cache sizes and N elimination algorithms form X*N combinations, each combination includes a cache size and an elimination algorithm, and the X cache sizes are X cache sizes of cache presets corresponding to each category of IO requests.
  • the cache size and elimination algorithm of each category of IO requests in the K categories are configured in the shared cache, which can realize the optimization of the two factors affecting cache performance, the elimination algorithm and the cache size. Joint solution to optimize the cache size of IO requests of each category in the shared cache and the purpose of the elimination algorithm. Therefore, the optimized cache size and elimination algorithm of the IO requests of each category in the shared cache in the K categories can improve the overall cache performance of the shared cache.
  • the above method further includes: acquiring multiple IO requests.
  • the IO requests are divided into K categories according to features of addresses of data accessed by the multiple IO requests or according to category tags carried in the multiple IO requests.
  • the entity that initiates the IO request does not need to mark the category mark for the IO request for classification, so that the entity that initiates the IO request will not generate Additional resource overhead.
  • the method provided by this application does not invade the upper layer of the cache (that is, the entity that initiates the IO request)
  • the method provided by this application can be applied to a general cache system for diverse clients without ecological support.
  • the above-mentioned shared cache is an LLC of the CPU in the computing device, and the above-mentioned multiple IO requests are IO requests initiated by multiple processing cores in the CPU.
  • the shared cache is a cache in a cache node, and the multiple IO requests are IO requests initiated by multiple computing nodes accessing the cache node.
  • the shared cache is a cache pool formed by caches in multiple nodes, and the multiple IO requests are IO requests initiated by multiple computing nodes accessing the cache pool.
  • the above-mentioned access characteristics pass through the hit rate curve (hit rate curve, HRC) or missing rate curve (miss rate curve, MRC) characterization.
  • the above-mentioned determination of the access characteristics of the IO requests of each category in the K categories to access the shared cache includes: periodically determining the access characteristics of the IO requests of each category in the K categories to access the shared cache .
  • the above-mentioned access characteristics of the IO requests of the K categories and the hit rate of the shared cache determine that the IO requests of each category are in
  • the partition size and elimination algorithm in the shared cache includes: according to the access characteristics of the K categories of IO requests determined in the first cycle and the hit rate of the shared cache, determine the number of IO requests of each category in the shared cache in the first cycle Partition size and elimination algorithm.
  • the first period is any period for determining the access characteristics of the IO requests of each category in the K categories to access the shared cache.
  • the shared cache can periodically adjust the IO request of each category in the shared cache according to the cache size and elimination algorithm of each category of IO requests periodically determined by the computing device. Cache size and elimination algorithm, so as to improve the hit rate of IO requests in the shared cache in the time domain, thereby improving the overall cache performance of the shared cache in the time domain.
  • the present application provides a device for managing a shared cache.
  • the device for managing a shared cache is configured to execute any one of the methods provided in the first aspect above.
  • the present application may divide the shared cache management device into functional modules according to any one of the methods provided in the first aspect above.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the present application may divide the device for managing the shared cache into a determination unit, a configuration unit, and the like according to functions.
  • the present application provides a computing device, the computing device is used for managing a shared cache, and the computing device includes: a memory, one or more processors, and the one or more processors are configured to read the The program instructions in the method are used to execute any one of the methods provided in the first aspect and any possible design thereof.
  • the present application provides a computer-readable storage medium, the computer-readable storage medium includes program instructions, and when the program instructions are run on a computer or a processor, the computer or the processor executes any of the steps in the first aspect. Either method provided by a possible implementation.
  • the present application provides a computer program product, which, when running on a computing device, causes any one of the methods provided in any one of the possible implementations of the first aspect to be executed.
  • any device, computer storage medium or computer program product provided above can be applied to the corresponding method provided above, therefore, the beneficial effects that it can achieve can refer to the corresponding method. Beneficial effects are not repeated here.
  • the name of the management apparatus for the above-mentioned shared cache does not constitute a limitation on the device or functional module itself, and in actual implementation, these devices or functional modules may appear with other names. As long as the functions of each device or functional module are similar to those of the present application, they fall within the scope of the claims of the present application and their equivalent technologies.
  • FIG. 1 is a schematic diagram of a scenario of a shared cache
  • FIG. 2 is a schematic diagram of another scenario of a shared cache
  • FIG. 3 is a schematic diagram of another scenario of a shared cache
  • FIG. 4 is a schematic diagram of a hardware structure of a computing device provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a method for managing a shared cache provided by an embodiment of the present application
  • FIG. 6 is a schematic diagram of an entity-initiated IO request to access a shared cache provided in an embodiment of the present application
  • FIG. 7 is a schematic flowchart of a method for generating a classifier provided in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a classification of IO requests provided by the embodiment of the present application.
  • FIG. 9 is a schematic flowchart of another shared cache management method provided by an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of another shared cache management method provided by the embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of an apparatus 110 for managing a shared cache provided by an embodiment of the present application.
  • the computing unit When the computing speed of the computing unit does not match the speed at which the computing unit accesses the data stored in the storage unit, the computing unit will generate a large amount of idling in order to wait for data to be accessed in the storage unit. To solve this problem, caching technology came into being.
  • cache refers to a memory capable of high-speed data exchange.
  • a cache is located between a storage unit (such as an external memory, external memory for short) and a computing unit (such as a CPU).
  • the external memory may be, for example, a hard disk of the device, and the hard disk may be, for example, a solid state disk (solid state disk, SSD) or a mechanical hard disk (hard disk drive, HDD).
  • the computing unit by pre-loading high-value data from the storage unit to the cache, when the computing unit accesses these high-value data, it can directly read from the cache capable of high-speed data exchange. In this way, the data access efficiency of the computing unit can be improved, thereby reducing the idling time of the computing unit and increasing the execution speed of the application program.
  • the high-value data is, for example, the data recently accessed by the computing unit, or the data frequently accessed by the computing unit, or the working set data, etc., and the like is not limited thereto.
  • the working set can be understood as a data set composed of all the data required by an application.
  • the entity when the entity writes data to the storage unit, it can first write the data to be written into the cache, and then the cache periodically writes the cached data into the external storage (called flushing).
  • the entity is, for example, an application, a computing node, a client device, or a core of a CPU, etc., and is not limited thereto.
  • the input/output (input/output, IO) operation for writing data can be considered as completed when the data is written into the cache, which can improve the response speed of the entity.
  • the cache of the device may generally be implemented by the memory of the node and/or the SSD of the node.
  • memory also known as main memory, is a storage space that the CPU can directly address.
  • the memory may be a dynamic random access memory (dynamic random access memory, DRAM), etc., but is not limited thereto.
  • the cache resources shared among multiple entities in the cache architecture are called shared caches.
  • the multiple entities may be, for example, multiple applications, multiple computing nodes, multiple client devices, or multiple processing cores in the CPU of the computing device, etc., and is not limited thereto.
  • an application refers to an application program running on a computing device
  • a computing node is a computing node that needs to access a shared cache
  • a client device may be a client device of a storage system, a client device of an application program, etc. It can be any device including a CPU such as a general computer, a notebook computer, a tablet computer, a server, etc., and is not limited thereto.
  • the shared cache may be a L3 cache of a CPU including multiple processing cores in a computing device.
  • multiple entities that initiate IO requests to the shared cache are multiple processing cores in the CPU.
  • FIG. 1 shows a schematic diagram of a shared cache scenario.
  • the CPU 10 of the computing device includes four processing cores, which are processing core 1, processing core 2, processing core 3 and processing core 4.
  • each of the 4 processing cores of CPU 10 is equipped with an independent level 1 cache (level 1 cache) and level 2 cache (level 2 cache), and all 4 processing cores of CPU 10 can access CPU 10
  • the three-level cache, that is, the three-level cache of the CPU 10 is the shared cache of these four processing cores.
  • the shared cache may also be a cache in a cache node in the cache system. In this case, initiate an IO request to the shared cache
  • Multiple entities refer to multiple client devices accessing cache nodes, or multiple computing nodes accessing shared caches.
  • the specific form of the client device may also be any computing node with a computing processing function, which is not limited.
  • the cache system may be a distributed cache system. It can be understood that in a distributed cache system, data of one computing node may be cached in caches of multiple cache nodes in the distributed cache system. In contrast, the cache of one cache node in the distributed cache system can cache data of multiple computing nodes. Therefore, the cache of the cache nodes used to cache data of multiple computing nodes in the distributed cache system is the shared cache of the multiple computing nodes.
  • the above cache system may also be a centralized cache system.
  • a centralized cache system includes one cache node.
  • the data of multiple computing nodes are cached in the cache of the cache node. Therefore, the cache of the cache nodes in the centralized cache system is the shared cache of the multiple computing nodes.
  • the above cache nodes may be independent devices.
  • the independent device's cache is used as the cache node's cache.
  • the above functions implemented by the cache node are implemented by functional modules in an independent device, that is, the independent device can also implement other functions besides the function of the cache node.
  • part of the cache of the separate device is used as the cache of the cache node.
  • the functions implemented by the cache nodes in the distributed cache system are integrated into the computing devices serving as the storage nodes in the distributed storage system. That is to say, the computing device not only realizes the function of the storage node, but also realizes the function of the cache node.
  • part of the cache in the standalone device is used as the cache for the cache node.
  • FIG. 2 shows another schematic diagram of a shared cache scenario.
  • FIG. 2 shows j computing nodes accessing the caching system 20 of a distributed caching system 20, which are respectively computing node 1, computing node 2, computing node 3, ..., and computing node j, j is a positive integer.
  • the caching system 20 includes three caching nodes, namely caching node 1 , caching node 2 and caching node 3 .
  • the high-value data of any one of the j computing nodes is distributed and cached in the caches of multiple cache nodes in the cache system 20 .
  • the cache of a single cache node in the cache system 20 is the shared cache of the j computing nodes.
  • the shared cache can also be a cache pool formed by caches of multiple nodes.
  • the cache pool is a cache pool formed by caches of each node in the plurality of nodes.
  • multiple entities that initiate IO requests to the shared cache are multiple computing nodes accessing the cache pool. That is, the cache pool is used to cache the data of the multiple computing nodes,
  • the node providing cache for the cache pool may be a node in any network system, which is not limited.
  • the nodes that provide cache for the cache pool are storage nodes in the storage system, and the multiple computing nodes that access the cache pool are multiple client devices of the storage system.
  • the nodes providing cache for the cache pool are multiple servers in the server cluster, then the multiple computing nodes accessing the cache pool are multiple client devices of the server cluster, or, among the multiple computing nodes accessing the cache pool There is no limit to running multiple applications accessing the server cluster.
  • FIG. 3 shows another schematic diagram of a shared cache scenario.
  • node 1 , node 2 , and node 3 are storage nodes in the storage system
  • the cache of node 1 is cache 1
  • the cache of node 2 is cache 2
  • the cache of node 3 is cache 3 .
  • a part of cache 1 , a part of cache 2 , and a part of cache 3 may constitute a cache pool 30 .
  • the size of the cache is generally limited and much smaller than the size of the external memory, the data that can be stored in the cache is very limited.
  • the IO request for reading data initiated by the entity carries the logical address of the data to be read. That is, the logical address carried in the IO request for reading data is the logical address to be accessed by the IO request.
  • the IO request When there is data corresponding to the logical address carried by the IO request in the cache, the IO request is a read hit in the cache.
  • a cache miss can trigger a read IO request to the backend of the cache (such as an external memory) to read the requested data to be read, and cache the data to be read read from the backend in the cache.
  • the IO request for writing data initiated by the entity carries the data to be written and a logical address for storing the data to be written. That is, the logical address carried in the IO request for writing data is the logical address to be accessed by the IO request.
  • the cache can update the data written to the logical address in the cache based on the data to be written carried by this IO request, and then flush the updated data into the external storage.
  • the cache When there is no physical address corresponding to the logical address carried by the IO request in the cache, it means that the logical address has not been written into data before this IO request, or that the logical address has been written into data before this IO request, And the written data has been flushed from the cache to the external memory.
  • the IO request for writing data misses in the cache to the logical address storing the data to be written, which is referred to as the IO request misses in the cache.
  • the cache allocates a corresponding physical address for the logical address carried in the received IO request this time, and writes the current IO request carrying data to be written to the physical address, thereby realizing caching of the data to be written.
  • the IO request misses the data to be read in the cache, it is necessary to read the data from the backend of the cache (such as external storage) to the cache.
  • the backend of the cache such as external storage
  • the cache such as external storage
  • the L3 cache in the CPU when a cache miss occurs in the L3 cache in the CPU, it is necessary to read data from the memory of the computing device where the CPU is located to the L3 cache of the CPU.
  • memory when a cache miss occurs in the memory, it is necessary to read data from the external memory of the device where the memory is located to the memory.
  • the algorithm used to determine the data that needs to be eliminated among the existing data in the cache is the elimination algorithm.
  • the elimination algorithm is designed based on the access rules (such as the frequency of accessing data, etc.) when IO requests access to data, so that by applying the elimination algorithm in the cache, high-value data can be kept in the cache as long as possible, while Eliminate low-value data, which can improve the hit rate of IO requests for reading data in the cache, thereby improving cache performance.
  • the data cached in the cache will be periodically flushed into the external storage, or when the cached data in the cache exceeds a certain amount, the currently cached data will be flushed into the external storage.
  • some data whose subsequent update frequency may be relatively low may be flushed into the external memory, while data whose subsequent update frequency may be relatively high may be kept in the cache.
  • the hit rate of write hits in the cache for subsequent IO requests can be improved, thereby reducing the number of times the cache flushes data into the external storage.
  • the algorithm used to determine which data in the cache needs to be flushed into the external memory is the elimination algorithm.
  • Cache performance can generally be evaluated by hit rate or miss rate.
  • the hit rate of the read hit is: the number of times the IO request is read in the cache in a period of time and the total The ratio of the number of IO read requests.
  • Missing rate in the read data scenario the ratio of the number of cache misses in the cache for IO requests within a period of time to the number of all IO read requests during this period.
  • the hit ratio of write hits is the ratio of the number of write hits of IO requests in the cache within a period of time to the number of all IO write requests during this period.
  • Missing rate in the data writing scenario the ratio of the number of IO requests that miss write hits in the cache over a period of time to the number of all IO write requests during this period.
  • the hit rate is: the number of read hits in the cache for IO requests in a period of time and the number of write hits in the cache for IO requests in this period of time The sum, and the ratio of the total number of IO requests during this period.
  • Missing rate the ratio of the sum of the number of cache misses in the cache of IO requests in a period of time and the number of miss write hits in the cache of IO requests in the period of time, and the ratio of the number of all IO requests in the period of time.
  • cache performance is not only related to the elimination algorithm applied in the cache, but also related to the size of the cache itself. Therefore, in practice, cache performance is generally characterized by a cache miss rate curve (MRC) or a cache hit rate curve (HRC).
  • MRC is the corresponding relationship curve between the cache size and the miss rate, which is used to describe the miss rate of IO requests in the cache when the cache is of different sizes under an elimination algorithm.
  • HRC is the corresponding relationship curve between cache size and hit rate, which is used to describe the hit rate of IO requests in the cache when the cache is of different sizes under an elimination algorithm.
  • the reuse distance of the IO request is used to indicate the number of different logical addresses accessed by other IO requests during the interval between two consecutive accesses to the logical address carried by the IO request.
  • the reuse distance of an IO request can be represented by the number of different logical addresses. Specifically, for any one IO request (such as the first IO request) among the multiple IO requests initiated by the entity within a period of time, the reuse distance of the first IO request is: among the multiple IO requests initiated by the entity, The number of different logical addresses accessed by an IO request located between the first IO request and another IO request in time sequence. Wherein, the other IO request is an IO request for accessing the logical address carried in the first IO request in a previous timing sequence.
  • the IO requests initiated by the entity within a period of time include 10 IO requests, and the logical addresses accessed sequentially by these 10 IO requests in sequence are (a, b, c, d, a, d, a, c,b,a). Among them, each letter represents a logical address.
  • the logical address carried by the IO request is a. Because there is no IO request for accessing the logical address a before the first IO request in the above 10 IO requests. Therefore, the reuse distance of the first IO request is usually infinite by default (the symbol is ⁇ ). Similarly, for the 2nd IO request, the 3rd IO request and the 4th IO request in the above 10 IO requests, the reuse distances of the 2nd IO request, the 3rd IO request and the 4th IO request are all for infinity.
  • the logical address carried by the IO request is a. Since there is an IO request for accessing logical address a before the fifth IO request among the above 10 IO requests, and the previous IO request for accessing logical address a is the first IO request among the above 10 IO requests, and in timing The number of different logical addresses accessed by the IO request located between the fifth IO request and the first IO request is 3 (including the logical address b accessed by the second IO request, the logical address c accessed by the third IO request, And the logical address d) accessed by the fourth IO request. Therefore, the reuse distance of the 5th IO request is 3. Similarly, for the sixth IO request among the above 10 IO requests, the reuse distance of the sixth IO request is 1. And, for the seventh IO request in the above 10 IO requests, the seventh IO request The requested reuse distance is 1.
  • the logical address carried by the IO request is c. Since there is an IO request for accessing logical address c before the eighth IO request among the above 10 IO requests, and the previous IO request for accessing logical address c is the third IO request among the above 10 IO requests, and in terms of timing
  • the number of different logical addresses accessed by the IO request between the 8th IO request and the 3rd IO request is 2 (including the logical address d accessed by the 4th IO request and the 6th IO request, and the 5th IO request request and the logical address a) accessed by the 7th IO request. So the 8th IO request has a reuse distance of 2.
  • the reuse distance of the ninth IO request is 3.
  • the reuse distance accessed by the tenth IO request is 2.
  • the reuse time is used to indicate the time interval between two consecutive accesses to the same logical address. Therefore, the reuse time can be called the reuse time of the logical address.
  • the reuse time of a logical address can be represented by the number of IO requests.
  • the reuse time of the logical address carried by the first IO request is: In one IO request, the number of IO requests between the first IO request and another IO request in time sequence.
  • the other IO request is an IO request for accessing the logical address carried in the first IO request in a previous timing sequence.
  • the IO requests initiated by the entity within a period of time include 10 IO requests, and the logical addresses accessed sequentially by these 10 IO requests in sequence are (a, b, d, c, b, d, a, a , c, d).
  • each letter represents a logical address.
  • the logical address accessed by the IO request is a, and there is no IO request for accessing the logical address a before the first IO request among the above-mentioned 10 IO requests. Therefore, the reuse time of the logical address a accessed by the first IO request is usually infinite by default.
  • the logical address b accessed by the second IO request and the logical address d accessed by the third IO request , and the reuse time of the logical address c accessed by the fourth IO are infinite.
  • the logical address accessed by the IO request is b. Since there is an IO request for accessing logical address b in the fifth IO request among the above-mentioned 10 IO requests, and the previous IO request for accessing logical address b is the second IO request among the above-mentioned 10 IO requests, and in terms of timing There are 2 IO requests (including the 3rd IO request and the 4th IO request) between the 5th IO request and the 2nd IO request. Therefore, the reuse time of logical address b accessed by the fifth IO request is 2.
  • the reuse time of the logical address d accessed by the 6th IO request is 2.
  • the reuse time of the logical address a accessed by the seventh IO request is 5.
  • the reuse time of the logical address a accessed by the eighth IO request is 0.
  • the reuse time of the logical address c accessed by the ninth IO request is 4.
  • the reuse time of the logical address d accessed by the tenth IO request is 3.
  • first and second do not indicate a sequential relationship, but are used to distinguish different objects.
  • the first, second, etc. mentioned in the following documents are also used to distinguish different objects. text, etc., and should not be understood as indicating or implying relative importance or implying the number of technical features indicated.
  • the shared cache can usually be partitioned, so that the data requested by different types of IO requests is cached in different partitions of the cache.
  • different types of IO requests are, for example, IO requests initiated by different entities, which is not limited.
  • the access rules such as the frequency of accessing data, etc.
  • IO requests access to data within a period of time it is usually based on the access rules (such as the frequency of accessing data, etc.) when IO requests access to data within a period of time, artificially specifying the partition size, or using simple heuristics Policies (such as the priorities of different types of IO requests) determine the partition size of the cache, and the cache partitions divided in this way generally can only guarantee the cache performance for a period of time, but cannot guarantee the long-term cache performance.
  • the entire shared cache uses the same elimination algorithm, resulting in poor performance of the shared cache.
  • an embodiment of the present application provides a shared cache management method.
  • the method first determines the access characteristics of each category of IO requests to access the shared cache, and according to the determined The access characteristics of the IO request and the hit rate of the shared cache determine the partition size and elimination algorithm of each type of IO request in the shared cache. Furthermore, the determined partition size of each type of IO request in the shared cache and the elimination algorithm are applied to the shared cache.
  • the access characteristic of each category of IO requests is the relationship between the hit rate and cache size of each category of IO requests under multiple elimination algorithms respectively.
  • the above method when the above method is periodically executed, it is possible to timely adjust the IO requests of each category in the shared cache according to the periodically determined access characteristics of each category of I/O requests in the shared cache.
  • the size of the partition and the elimination algorithm can continuously guarantee the cache performance of the shared cache in the time dimension.
  • the embodiment of the present application also provides a shared cache management device, the management device is applied to a computing device, and the computing device can implement the management of the shared cache by executing the method provided in the embodiment of the present application.
  • the computing device may be any computing device such as a general computer, a notebook computer, a tablet computer, a mobile phone, or a vehicle terminal.
  • the foregoing computing device may be any computing device including a shared cache.
  • the computing device is a computing device having the CPU shown in FIG. 1 .
  • the computing device may be a server or a cache node (such as the cache node shown in FIG. 2 ) including a shared cache.
  • the computing device may be any node including a shared cache as shown in FIG. 3 , but is not limited thereto. It can be understood that when the computing device can be any node including a shared cache as shown in FIG. 3 , then the node can obtain and execute the information provided by the embodiment of the present application by interacting with other nodes including a shared cache in FIG. 3 . The data (such as IO request) required in the method, and execute the method described below in the embodiment of the present application based on the obtained data.
  • the data (such as IO request) required in the method, and execute the method described below in the embodiment of the present application based on the obtained data.
  • the above-mentioned computing device may also be a computing device connected and communicating with a node including a shared cache.
  • the node including the shared cache is the node that provides the cache for the cache pool as shown in FIG. limited.
  • the computing device can obtain the data (such as IO request) required for executing the method provided by the embodiment of the present application by interacting with the node providing the cache for the buffer pool, and execute the application based on the obtained data. Examples Methods described below.
  • FIG. 4 shows a schematic diagram of a hardware structure of a computing device provided by an embodiment of the present application.
  • the computing device 40 includes a processor 401 , a memory 402 , a communication interface 403 and a bus 404 .
  • the processor 401 , the memory 402 , and the communication interface 403 are connected through a bus 404 .
  • the processor 401 is the control center of the computing device 40, and may be a general-purpose CPU, and the processor 401 may also be other general-purpose processors, digital signal processing (digital signal processing, DSP), application-specific integrated circuit (application-specific integrated circuit, ASIC), field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, graphics Processor (graphics processing unit, GPU), neural network processing unit (neural processing unit, NPU), tensor processor (tensor processing unit, TPU) or artificial intelligence (artificial intelligent) chip, data processor (data processing unit, DPU), etc.
  • DSP digital signal processing
  • ASIC application-specific integrated circuit
  • FPGA field-programmable gate array
  • FPGA field-programmable gate array
  • processor 401 includes one or more CPUs, such as CPU 0 and CPU 1 shown in FIG. 4 .
  • the present application does not limit the number of processor cores in each processor.
  • the memory 402 is used to store program instructions or data to be accessed by an application process, and the processor 401 may execute the program instructions in the memory 402 to implement the shared cache management method provided by the embodiment of the present application.
  • Memory 402 includes volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory.
  • the volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable In addition to programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (RAM), which acts as external cache memory.
  • non-volatile memory may be storage class memory (storage class memory, SCM), solid state drive (solid state drive, SSD), mechanical hard disk (hard disk drive, HDD), etc.
  • storage-class memory may be, for example, non-volatile memory (non-volatile memory, NVM), phase-change memory (phase-change memory, PCM), persistent memory, and the like.
  • the memory 402 exists independently of the processor 401 .
  • the memory 402 is connected to the processor 401 through the bus 404 and is used for storing data, instructions or program codes.
  • the processor 401 invokes and executes the instructions or program codes stored in the memory 402, the shared cache management method provided by the embodiment of the present application can be realized.
  • the memory 402 and the processor 401 are integrated together.
  • the communication interface 403 is used to connect the computing device 40 to other devices (such as computing nodes shown in FIG. 2 or FIG. 3 ) through a communication network, and the communication network may be Ethernet, radio access network (radio access network, RAN) ), wireless local area networks (wireless local area networks, WLAN), etc.
  • the communication interface 403 includes a receiving unit for receiving data/messages, and a sending unit for sending data/messages.
  • the bus 404 can be an industry standard architecture (industry standard architecture, ISA) bus, a peripheral component interconnect (PCI) bus, a high-speed serial computer expansion bus (peripheral component interconnect express, PCIe), a computing fast link (compute express link, CXL) or extended industry standard architecture (extended industry standard architecture, EISA) bus, etc.
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 4 , but it does not mean that there is only one bus or one type of bus.
  • FIG. 4 does not constitute a limitation on the computing device 40.
  • the computing device 40 includes more or less components than those shown in FIG. 4, or Combining certain parts, or different arrangements of parts.
  • the shared cache is used to cache data of operations (such as reading or writing) requested by IO requests initiated by multiple entities.
  • the IO requests initiated by the multiple entities correspond to K categories
  • the shared cache corresponds to N elimination algorithms as an example for illustration. That is, the IO requests initiated by the multiple entities include K types of IO requests, and the shared cache is pre-configured with N elimination algorithms.
  • K and N are integers greater than 1, respectively.
  • each IO request carries a logical address, which is the logical address to be accessed by the IO request.
  • a logical address which is the logical address to be accessed by the IO request.
  • the method for managing the shared cache may be used to manage the read cache in the shared cache, or to manage the write cache in the shared cache.
  • the read-write cache separation of the shared cache means that the read cache and write cache in the shared cache are physically or software isolated.
  • the read cache is used to cache the data requested to be read by the IO request initiated by the entity.
  • the write cache is used to cache the data written by the IO request initiated by the entity.
  • FIG. 5 shows a schematic flowchart of a method for managing a shared cache provided by an embodiment of the present application.
  • the method may be applied to the CPU shown in FIG. 1 , or to the cache node shown in FIG. 2 , or to the node shown in FIG. 3 .
  • the method can be executed by a computing device having the hardware structure shown in FIG. 4 , and the method includes the following steps.
  • the computing device executes the process of the shared memory management method provided by the embodiment of the present application, the process of accessing the shared cache with the IO request initiated by the entity is performed in parallel. Therefore, during the process of accessing the shared cache by the IO requests initiated by multiple entities, the computing device obtains copies of the IO requests for accessing the shared cache initiated by the multiple entities. Therefore, the computing device acquires IO requests initiated by multiple entities, and these IO requests include K categories of IO requests.
  • FIG. 6 shows a schematic diagram of an entity-initiated IO request to access a shared cache.
  • cache node 2 includes a shared cache, and j computing nodes (including computing node 1 , computing node 2 , computing node 3 , . . . , and computing node j) can all access the shared cache of caching node 2 .
  • the shared cache in the cache node 2 also communicates with the backend storage of the cache node 2 (the backend storage may be located inside the cache node 2 or outside the cache node 2).
  • the shared cache can periodically flush the data written to the shared cache by j computing nodes through IO requests into the back-end storage.
  • the shared cache can pre-load the data stored in the backend into its own storage space, so that j computing nodes can subsequently read the data through IO requests.
  • the shared cache can load the data to be read from the backend storage, so that the j computing nodes can read the data to be read.
  • the computing device acquires a copy of the IO request for accessing the shared cache initiated by j computing nodes during the process of accessing the shared cache through the IO request of j computing nodes, so as to execute the embodiment of the present application provided method.
  • the IO request acquired by the computing device at S101 is an IO read request for reading data.
  • the IO request acquired by the computing device at S101 is an IO write request for writing data.
  • the computing device determines the category of each obtained IO request.
  • the IO request initiated by the entity carries a category flag identifying the category to which the IO request belongs.
  • the computing device determines the category of each IO request according to the category tag carried by each IO request in the acquired IO requests.
  • the category tag carried in the IO request may be a category tag added to the IO request when the entity initiates the IO request.
  • the category tag carried in the IO request may be used to indicate the entity that initiated the IO request. That is to say, the category of the IO request is divided according to the entity that initiates the IO request.
  • K categories of IO requests correspond to K entities, and IO requests initiated by the same entity have the same category flag, that is, IO requests initiated by the same entity belong to in the same category.
  • the entities may be different applications, different processing cores, or different computing nodes and client devices accessing the shared cache, which are not limited.
  • the computing device may determine the category of each obtained IO request through a classifier, and the classifier is used to classify the IO requests into K categories of IO requests, and specifically to classify IO requests with high similarity logical addresses are classified into one category.
  • the classifier is pre-generated based on the characteristics of a certain number of IO requests accessing logical addresses.
  • the computing device pre-generates a detailed description of the classifier based on the characteristics of a certain number of IO requests accessing logical addresses, refer to the description below, and will not repeat them here.
  • the computing device sequentially inputs the acquired logical address carried by each IO request into the classifier, and the classifier can output a class identifier indicating the class of each IO request.
  • the computing device determines the category of the IO request through the classifier, it adds a category identifier indicating its category to the IO request.
  • S102 Determine the access characteristics of the IO requests of each of the K categories to access the shared cache, the access characteristics being the relationship between the hit rate of the IO requests of each of the K categories under the N elimination algorithms and the size of the cache.
  • the N elimination algorithms are elimination algorithms pre-configured in the shared cache, that is, there are N elimination algorithms corresponding to the shared cache.
  • the computing device presets X cache sizes for each category of IO requests, and for a category of IO requests (such as the first category of IO requests), the X cache sizes correspond to the first category of IO requests X cache sizes for the cache preset.
  • the cache corresponding to the first type of IO request is the partition used to cache the read data requested by the first type of IO request in the shared cache
  • the cache size corresponding to the first type of IO request is the partition used in the shared cache.
  • the size of the partition used to cache the read data requested by the first type of IO request is smaller than the size of the shared cache.
  • the embodiment of the present application does not specifically limit the rule that the computing device presets X cache sizes for each type of IO request, and the size interval between the X cache sizes.
  • the computing device presets 3 cache sizes for the first type of IO requests. Assuming that the size of the shared cache is 4M, the computing device presets 3 cache sizes for the first type of IO requests as 1M, 2M and 3M.
  • the number of cache sizes preset by the above-mentioned computing device for each category of IO requests in the K categories can be X, that is, the preset cache size of the computing device for each category of IO requests in the K categories the same amount.
  • the number of cache sizes preset by the computing device for each category of IO requests in the K categories may also be different.
  • the number of preset cache sizes requested by the computing device for the first type of IO in the K categories is 3
  • the number of preset cache sizes requested by the computing device for the second type of IO in the K categories is 4, and so on .
  • the second type of IO request is an IO request of any type among the K types except the first type.
  • the relationship between the hit rate and the cache size of the IO requests of each of the K categories represented by the above access characteristics under the N elimination algorithms can be determined by the IO requests of each of the K categories in Characterized by the HRC of the shared cache under N elimination algorithms.
  • the relationship between the hit rate and the cache size of the IO requests of each of the K categories represented by the above access characteristics under the N elimination algorithms can be determined by comparing the IO requests of each of the K categories in N It is characterized by the MRC of the shared cache under the elimination algorithm, which is not limited in this embodiment of the present application.
  • the computing device determines the hit rate of the IO requests of each category in caches of different sizes under the N elimination algorithms, and then obtains the IO requests of each category in the K categories.
  • the computing device determines the access characteristics of the IO requests of each of the K categories to access the shared cache, which may be realized through the following possible implementation manners.
  • the computing device obtains the hit rate of each category of IO requests in caches of different sizes under N elimination algorithms by simulating in the shared cache, so as to obtain the IO requests of each category in N
  • the relationship between the hit rate and the cache size under the elimination algorithms for example, the HRC or MRC of each category of IO requests under the N elimination algorithms respectively.
  • the computing device can simulate the hit rate of sample IOs of each category in caches of different sizes under the N elimination algorithms in a shared cache, so as to obtain the sample IOs of each category in the N elimination algorithms
  • the relationship between the hit rate and the cache size for example, to obtain the HRC or MRC of each category of sample IO under N elimination algorithms.
  • the computing device determines the relationship between the hit rate and the cache size of the sample IO of each category under the N elimination algorithms respectively as the relationship between the hit rate and the cache size of the IO requests of each category under the N elimination algorithms respectively .
  • the computing device determines the HRC of the sample IOs of each category under the N elimination algorithms respectively as the HRC of the IO requests of each category under the N elimination algorithms respectively.
  • the computing device determines the MRC of the sample IOs of each category under the N elimination algorithms respectively as the MRC of the IO requests of each category under the N elimination algorithms respectively.
  • the sample IO of each category is the IO request obtained by the computing device based on the sampling of the IO requests of each category in the K categories obtained in S101.
  • the computing device scales down and simulates the hit rate of sample IOs of each category in caches of different sizes under N elimination algorithms in the shared cache, so as to obtain the hit rate of sample IOs of each category under N elimination algorithms
  • the computing device scales down and simulates the hit rate of sample IOs of each category in caches of different sizes under N elimination algorithms in the shared cache, so as to obtain the hit rate of sample IOs of each category under N elimination algorithms
  • the computing device determines that the IO requests of each category under the N elimination algorithms are stored in caches of different sizes according to the reuse distance of each IO request in each category of IO requests and different cache sizes.
  • the hit rate so as to obtain the relationship between the hit rate and the cache size of each category of IO requests under the N elimination algorithms.
  • the computing device can use the reuse distance and different cache sizes of each IO request in the first type of IO requests , determine the hit rate of the first type of IO request when applying the first elimination algorithm in caches of different sizes, so as to obtain the relationship between the hit rate of the first type of IO request under the first elimination algorithm and the size of the cache.
  • the first elimination algorithm is any one elimination algorithm among the N elimination algorithms.
  • the computing device can determine the sample IO of each category under the N elimination algorithms according to the reuse distance of each sample IO in each category of sample IO and different cache sizes The hit rate in caches of different sizes, so as to obtain the relationship between the hit rate of each category of sample IO under N elimination algorithms and the size of the cache. Furthermore, the computing device determines the relationship between the hit rate of each category of sample IO under the N elimination algorithms and the cache size as the relationship between the hit rate of each category of IO requests under the N elimination algorithms and the cache size .
  • the sample IOs of each category are the IO requests sampled by the computing device based on the IO requests of each of the K categories acquired in S101.
  • the computing device can determine that the first type of sample IO is used in caches of different sizes according to the reuse distance of each sample IO in the first type of sample IO and different cache sizes The hit rate during the first elimination algorithm, so as to obtain the relationship between the hit rate and the cache size of the first type of sample IO under the first elimination algorithm. Then, the computing device approximately determines the relationship between the hit rate of the first type of sample IO under the first elimination algorithm and the cache size as the relationship between the hit rate of the first type of IO request under the first elimination algorithm and the cache size.
  • the reuse distance of the sample IO refer to the detailed description of the reuse distance in the above terminology, which will not be repeated here.
  • the computing device determines according to the reuse distance of each sample IO in the first type of sample IO and different cache sizes
  • the hit rate of the first type of sample IO when the first elimination algorithm is applied in caches of different sizes so as to obtain a detailed description of the relationship between the hit rate of the first type of sample IO under the first elimination algorithm and the cache size, you can refer to the following description , which will not be repeated here.
  • the computing device can determine a set of relationships between different cache sizes and hit rates, that is, an HRC or MRC. Furthermore, for a category of IO requests, under N elimination algorithms, the computing device can determine the relationship between N sets of cache sizes and hit rates, that is, N HRCs or MRCs. Furthermore, for K categories of IO requests, under N elimination algorithms, the computing device can determine the relationship between N ⁇ K sets of cache sizes and hit rates, that is, N ⁇ K HRCs or MRCs.
  • the computing device determines that the sample IOs of each category are under the HRC or MRC under the N elimination algorithms, they can be obtained by using the first possible implementation above, or by using the second possible implementation.
  • the computing device can adopt the above-mentioned first possible implementation method to obtain the HRC or MRC of another part of the sample IOs under another part of the elimination algorithm , the computing device may use the foregoing second possible implementation manner to determine, which is not limited in this embodiment of the present application.
  • the computing device samples the obtained IO requests of each category among the K categories based on preset sampling conditions, so as to obtain sample IOs of each category.
  • the logical address carried by the sample IO satisfies the preset sampling condition.
  • the preset sampling condition is a sampling condition designed based on a preset sampling rate.
  • the preset sampling rate is preset by the computing device.
  • the preset sampling rate is 0.01, that is, one sample IO is sampled in 100 IO requests. It should be noted that when the computing device samples in each type of IO request under the preset sampling condition designed according to the preset sampling rate, the sampling rate for sampling in each type of IO request can be realized as the preset sampling rate.
  • the sample IO that satisfies the preset sampling condition satisfies: the remainder of the hash value of the logical address carried by the sample IO divided by the coefficient A is less than or equal to the preset sampling rate L and the coefficient A product.
  • the hash value of the logical address may be obtained by hashing the logical address based on any hash algorithm, which is not limited in this embodiment of the present application.
  • the coefficient A is a preset coefficient, and the value of A is not limited in the embodiment of the present application.
  • the preset sampling conditions can ensure that: when a computing device samples a sample IO that satisfies the preset sampling conditions in this category of IO requests, then this category of IO requests is related to The IO requests with the same logical address carried by the sample IO can be sampled by the computing device as the sample IO.
  • the preset sampling conditions can ensure that: when the computing device samples a sample IO that meets the preset sampling conditions in this type of IO request, the logical address accessed in this type of IO request is the same as the sample IO access All IO requests with the same logical address can be sampled as sample IO by the computing device. Therefore, any sampling condition that can guarantee the above-mentioned sampling purpose shall be within the scope of protection of the embodiments of the present application.
  • the computing device judges whether each IO request in the first-type IO request satisfies a preset sampling condition. If so, the computing device determines the IO request meeting the preset sampling condition as the sample IO. In this way, the computing device can sample a plurality of sample IOs at a preset sampling rate in the obtained first-type IO requests.
  • the computing device first determines the hash value of the logical address carried in the first IO request, and further determines the hash value Whether the remainder Y of dividing by the coefficient A is less than or equal to the product P of the preset sampling rate L and the coefficient A.
  • the computing device samples the first IO request, that is, the first IO request is determined as a sample IO of the first type of IO request.
  • the computing device can determine X hit rates corresponding to X cache sizes under each elimination algorithm for each type of IO request. In this way, the computing device can determine the hit ratios of K types of IO requests in the shared cache under different combinations according to the X hit rates corresponding to the X cache sizes of each category of IO requests under each elimination algorithm.
  • the detailed description of the X cache sizes can refer to the above, and will not be repeated here.
  • different combinations refer to combinations of different cache sizes and different elimination algorithms corresponding to each category of IO requests. For example, if the preset cache size of the computing device includes X, the elimination algorithm for shared cache provisioning includes N, so the combinations corresponding to one category of IO requests include X ⁇ N combinations.
  • the computing device can according to the hit rate of the first type of IO request in any combination (such as the first combination) and the first type of IO request in The ratio of the IO requests of the K categories determines the hit rate of the first type of IO requests in the shared cache under the first combination.
  • the computing device performs a product operation on the hit rate of the first type of IO requests under the first combination and the proportion of the first type of IO requests in the K types of IO requests, so as to obtain the first type of IO requests under the first combination The hit ratio of IO requests in the shared cache.
  • the hit rate of the first type of IO request under the first combination is Z1
  • the proportion of the first type of IO request in the K types of IO requests is R1
  • the proportion of the first type of IO requests in the K types of IO requests is determined by the computing device according to the number of IO requests in the first type of IO requests and the total number of K types of IO requests.
  • the computing device acquires the K categories of IO requests initiated by the entity and determines the category of each IO request, it can determine each category according to the total number of acquired IO requests and the number of IO requests of each category. The proportion of IO requests in K categories of IO requests.
  • the computing device can determine the hit rate of each category of IO requests in the shared cache in any combination. Further, the computing device sums the K hit rates of the K categories of IO requests in the shared cache respectively, to obtain the hit rates of the K categories of IO requests in the shared cache.
  • the K hit rates used for the summation are respectively the hit rates of the IO requests of the K categories in any combination in the shared cache. For example, taking the value of K as 2 as an example, assuming that under the first combination, the hit rate of the first type of IO request in the shared cache is K1, and under the second combination, the hit rate of the second type of IO request in the shared cache is K2. Then the hit rate of IO requests of K categories in the shared cache is: K1+K2.
  • the computing device sums the K hit rates of K categories of IO requests in the shared cache to obtain the hit rates of K categories of IO requests in the shared cache, the K categories of IO requests The sum of cache sizes is less than or equal to the size of the shared cache.
  • the computing device can obtain the (X ⁇ N) K hits.
  • the IO requests obtained by the device include Type 1 IO requests and Type 2 IO requests, and the proportion of Type 1 IO requests in the two types of IO requests is R1, and the proportion of Type 2 IO requests in the two types of IO requests The proportion in R2.
  • the elimination algorithms for shared cache provisioning include the first elimination algorithm and the second elimination algorithm.
  • the cache size preset by the computing device for each type of IO request includes cache size 1 and cache size 2 . In addition, there are 4 combinations corresponding to each type of IO request.
  • These 4 combinations include: combination 1 composed of the first elimination algorithm and cache size 1, combination 2 composed of the second elimination algorithm and cache size 1, and combination 2 composed of the first elimination algorithm and cache size 1.
  • 1 Combination of elimination algorithm and cache size 2 3 Combination of 2nd elimination algorithm and cache size 2 4.
  • the computing device is based on each type of IO request in X ⁇ N (that is, 2 ⁇
  • the hit rate 1 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 1 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 1) + The product of the hit rate of the second type of IO request under combination 1 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 1);
  • the hit rate 2 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 1 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 1) + The product of the hit rate of the second type of IO request under combination 2 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 2);
  • the hit rate 3 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 1 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 1) + The product of the hit rate of the second type of IO request under combination 3 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 3);
  • the hit rate 4 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 1 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 1) + The product of the hit rate of the second type of IO request under combination 4 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 4);
  • the hit rate 5 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 2 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 2) + The product of the hit rate of the second type of IO request under combination 1 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 1);
  • the hit rate 6 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 2 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 2) + The product of the hit rate of the second type of IO request under combination 2 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 2);
  • the hit rate 7 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 2 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 2) + The product of the hit rate of the second type of IO request under combination 3 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 3);
  • the hit rate 8 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 2 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 2) + The product of the hit rate of the second type of IO request under combination 4 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 4);
  • the hit rate 9 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 3 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 3) + The product of the hit rate of the second type of IO request under combination 1 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 1);
  • the hit rate 10 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 3 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 3) + The product of the hit rate of the second type of IO request under combination 2 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 2);
  • the hit rate 11 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 3 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 3) + Class 2 IO requests under combo 3
  • the product of the hit rate and R2 that is, the hit rate of the second type of IO request in the shared cache under combination 3;
  • the hit rate 12 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 3 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 3) + The product of the hit rate of the second type of IO request under combination 4 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 4);
  • the hit rate 13 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 4 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 4) + The product of the hit rate of the second type of IO request under combination 1 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 1);
  • the hit rate 14 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 4 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 4) + The product of the hit rate of the second type of IO request under combination 2 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 2);
  • the hit rate 15 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 4 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 4) + The product of the hit rate of the second type of IO request under combination 3 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 3);
  • the hit rate 16 of two types of IO requests in the shared cache is: the product of the hit rate of the first type of IO request under combination 4 and R1 (that is, the hit rate of the first type of IO request in the shared cache under combination 4) + The product of the hit rate of the second type of IO request under combination 4 and R2 (that is, the hit rate of the second type of IO request in the shared cache under combination 4).
  • the computing device determines the maximum hit rate of the IO requests of K categories in the shared cache, and determines the cache size indicated by the combination corresponding to each category when the maximum hit rate is obtained as the IO request of each category in the shared cache
  • the size of the partition in , and the elimination algorithm indicated by the combination corresponding to each category when the maximum hit rate is obtained, are determined as the elimination algorithm of the IO requests of each category in the shared cache.
  • the computing device will obtain the first category of IO requests with the maximum hit rate
  • the cache size 2 indicated by the corresponding combination 4 is determined as the partition size of the first type of IO request in the shared cache, and the second elimination algorithm indicated by the combination 4 corresponding to the first type of IO request when the maximum hit rate is obtained, Determined as the elimination algorithm for Type 1 IO requests in the shared cache.
  • the computing device determines the cache size 2 indicated by the combination 3 corresponding to the second type of IO request when the maximum hit rate is obtained, as the partition size of the second type IO request in the shared cache, and the second type of IO request when the maximum hit rate is obtained.
  • the first elimination algorithm indicated by the combination 3 corresponding to the type IO request is determined to be the elimination algorithm of the second type IO request in the shared cache.
  • the computing device can determine the X hit rates corresponding to the X cache sizes determined under each elimination algorithm based on each type of IO request, by constraining in the formula (1) Next, solve the following formula (2) to determine the maximum hit rate of IO requests of K categories in the shared cache under different combinations.
  • m represents the preset cache size
  • the number of m is X preset by the computing device
  • M represents the size of the shared cache, so the value of m satisfies m ⁇ [0,M].
  • K represents the number of categories of IO requests, or it can be understood that K represents the number of partitions in the shared cache. It should be understood that one category of IO requests corresponds to one partition of the shared cache, that is, one partition of the shared cache is used to cache data of one category of IO requests.
  • i represents the i-th partition among the K partitions, or it can be understood that i represents the i-th type of IO request among the K types of IO requests.
  • m i represents the cache corresponding to the i-th partition in the shared cache Save size.
  • p represents the elimination algorithm
  • P N ⁇ represents N elimination algorithms
  • p i represents the elimination algorithm configured in the i-th partition
  • p i is ⁇ P 1 , P 2 ,... , any of P N ⁇ .
  • Ri represents the proportion of IO requests of the i-th category in all IO requests.
  • the formula (1) indicates that the sum of K cache sizes of K types of IO requests in the shared cache is smaller than or equal to the size of the shared cache.
  • formula (2) Indicates the hit rate of the i-th category of IO requests when the cache size is m i under the elimination algorithm p i , where m i and p i are a combination of the above. Indicates the hit rate of the i-th category of IO requests in the shared cache under the combination of m i and p i . Furthermore, the formula (2) in Indicates the hit rate of IO requests of K categories in the shared cache under different combinations.
  • the argmax in the formula (2) means to take The maximum value of , that is, argmax represents the maximum hit rate of IO requests of K categories in the shared cache under different combinations.
  • the computing device can determine the maximum hit rate of K categories of IO requests in the shared cache under different combinations, and obtain the maximum hit rate of each category of IO
  • the cache size indicated by the combination corresponding to the request is determined as the partition size of each type of IO request in the shared cache, and the elimination algorithm indicated by the combination corresponding to each type of IO request when the maximum hit rate is obtained is determined as The elimination algorithm for each category of IO requests in the shared cache.
  • the computing device can solve X hit rates corresponding to X cache sizes determined under each elimination algorithm based on each type of IO request under the constraints of formula (1) by solving The above formula (3) is used to determine the maximum hit rate of IO requests of K categories in the shared cache under different combinations.
  • formula (3) Indicates the miss rate of the i-th category of IO requests when the cache size is m i under the elimination algorithm p i , where m i and p i are a combination of the above. Shows the miss rate of the i-th category of IO requests in the shared cache under the combination of m i and p i . Furthermore, the formula (3) in It can represent the miss rate of K categories of IO requests in the shared cache under different combinations. argmin in the formula (3) means to take The minimum value of , that is, argmin represents the minimum miss rate of K categories of IO requests in the shared cache under different combinations.
  • the computing device can determine the minimum miss rate of K types of IO requests in the shared cache under different combinations.
  • the computing device determines the maximum hit rate of IO requests of K categories in the shared cache under different combinations.
  • the computing device can determine the cache size indicated by the combination of IO requests of each category when the minimum miss rate is obtained as the partition size of the IO request of each category in the shared cache, and when the minimum miss rate is obtained
  • the elimination algorithm indicated by the combination corresponding to each type of IO request is determined as the elimination algorithm of each type of IO request in the shared cache.
  • S104 Configure the cache size of each category of IO requests in the shared cache as the partition size of each category of IO requests in the shared cache determined above, and eliminate each category of IO requests in the shared cache.
  • Algorithm configured as an elimination algorithm for each category of IO requests determined above in the shared cache.
  • the computing device configures the cache size of each category of IO requests in the shared cache as the above-identified IO cache size of each category.
  • the partition size of the request in the shared cache, and the elimination algorithm for each category of IO requests in the shared cache are configured as determined above The elimination algorithm for each category of IO requests in the shared cache.
  • the data cached in the shared cache for the first type of IO request is processed according to the elimination algorithm configured in the shared cache for the first type of IO request. disuse.
  • a possible implementation method is used when the first type of IO request accesses the shared cache under this configuration
  • the shared cache monitors that the cached data size of the first type of IO request in the shared cache exceeds the elimination threshold
  • the first type of IO request is stored in the shared cache according to the elimination algorithm configured in the shared cache for the first type of IO request
  • the data cached in is eliminated.
  • Another possible implementation manner is that the shared cache periodically eliminates the data cached in the shared cache by the first type of IO request according to the elimination algorithm.
  • the corresponding partition size and cache elimination algorithm can be determined in the shared cache for each type of IO request, so as to Improve the cache performance of each category of IO requests, thereby improving the cache performance in the entire shared cache.
  • the IO read request in the shared cache can be improved.
  • the read hit rate can improve the data read efficiency.
  • the IO write request in the shared cache can be improved.
  • the write hit rate can save the number of times the shared cache is flushed to the back-end storage unit, that is, the data transmission bandwidth between the shared cache and the back-end storage unit can be saved.
  • the methods described in S101-S104 above may be performed periodically.
  • the IO request obtained by the computing device at S101 is the IO request initiated by the entity obtained by the computing device within one cycle (for example, the current cycle).
  • the computing device executes S102-S103 based on the obtained IO requests in one cycle, so as to determine the partition size and elimination algorithm of each type of IO requests in the shared cache.
  • the computing device can determine the partition size of each type of IO request in the shared cache based on each cycle and configure the shared cache periodically with the elimination algorithm.
  • the computing device can determine the partition size of each type of IO request in the shared cache based on each cycle and the elimination algorithm to periodically adjust the size of each partition of the shared cache and its corresponding elimination algorithm.
  • the shared cache can be configured according to the partition size and elimination algorithm specified by the user, or the shared cache is a pooled cache, which is not discussed in this embodiment of the present application. limited.
  • the shared cache can periodically adjust each The cache size and elimination algorithm of the category IO requests in the shared cache, so as to realize the hit rate of IO requests in the shared cache guaranteed in the time domain, that is, the cache performance of the shared cache is guaranteed in the time domain.
  • the number of cache sizes preset by the computing device for the first type of IO request is 3 (that is, the value of X is 3), and they are 1M, 2M, and 3M respectively, and the computing device is in the first type of IO request.
  • the preset sampling rate L of sampling is 0.01, and when the computing device determines the hit rate of applying the first elimination algorithm in caches of different sizes for simulating the first type of sample IO, the corresponding cache size is 0.01M (that is, 1M ⁇ 0.01 ), 0.02M(2M ⁇ 0.01), and 0.03M(3M ⁇ 0.01).
  • the computing device applies for caches with sizes of 0.01M, 0.02M, and 0.03M in the shared cache (hereinafter referred to as simulation caches) for the first type of sample IO in the shared cache, respectively for simulating the first type of sample IO
  • the hit rate when applying the first elimination algorithm in these three cache spaces can be repaired to obtain the hit rate of the first type of sample IO applying the first elimination algorithm in the cache with a cache size of 0.01, and the hit rate with a cache size of 0.02M
  • the hit rate when the first elimination algorithm is applied in the cache, and the hit rate when the first elimination algorithm is applied in the cache with a cache size of 0.03M, and then the hit rate and the hit rate of the first type of sample IO under the first elimination algorithm can be obtained
  • the relationship between the cache size, that is, the HRC of the first type of sample IO is obtained under the first elimination algorithm.
  • the computing device can sequentially instruct each sample IO in the first type of sample IO to access the simulation cache 1, and count hits The number of sample IOs.
  • the computing device may first instruct the first sample IO of the first type of sample IO to access the simulation cache 1. Since the simulation cache 1 at this time is empty, the computing device will use the first sample IO Logical addresses are cached in analog cache 1. Next, the computing device instructs the second sample IO in the first type of sample IO to access the analog cache 1, and if the logical address of the second sample IO is the same as the logical address of the first sample IO, it means that the second sample IO is in Hit in simulated cache 1, if the logical address of the second sample IO is different from the logical address of the first sample IO, it means that the second sample IO misses in simulated cache 1.
  • the computing device will The logical address of the IO sample is cached in the analog cache 1.
  • the computing device instructs each sample IO in the first type of sample IO to access the analog cache 1 in turn, and counts the number of hit sample IOs.
  • the computing device also monitors the size of the logical address stored in the simulated cache 1 during the simulation process. When the size of the logical address stored in the simulated cache 1 exceeds a certain threshold, the first elimination algorithm is used to delete the logical address stored in the simulated cache 1. A part of the logical address is eliminated (for example, a part is deleted, or a part is made invalid).
  • the computing device calculates the hit ratio of the first type of sample IOs in the analog cache 1 based on the total number of IOs of the first type of sample IOs and the number of hit sample IOs. Similarly, the computing device simulates and counts the number of sample IOs hit by the first type of sample IO in the simulation cache 2 with a cache size of 0.02M, and based on the total number of IOs of the first type of sample IO and the number of hit sample IOs , the hit rate of the first type of sample IO in the simulation cache 2 is calculated.
  • the computing device simulates and counts the number of sample IOs hit by the first type of sample IO in the simulated cache 3 with a cache size of 0.03M, and based on the total number of IOs of the first type of sample IO and the number of hit sample IOs, The hit rate of the first type of sample IO in the simulation cache 3 is calculated.
  • the computing device can determine X hit rates corresponding to the X cache sizes when the first type of sample IO is applied with the first elimination algorithm.
  • the computing device obtains the relationship between the hit rate of the first type of sample IO under the first elimination algorithm and the cache size, that is, obtains the HRC of the first type of sample IO under the first elimination algorithm.
  • the computing device may first determine the number of missed sample IOs based on the total number of IOs of the first type of sample IOs and the number of hit sample IOs, and then based on the total number of IOs of the first type of sample IOs and the number of missed IOs The number of sample IOs is calculated to obtain the miss rate of the first type of sample IO in the simulation cache 1.
  • the computing device simulates and counts the number of sample IOs hit by the first type of sample IO in the simulation cache 2, and based on the total number of IOs of the first type of sample IO and the number of hit sample IOs, first determine the number of missed IOs The number of sample IOs, and then calculate the miss rate of the first type of sample IOs in the analog cache 2 according to the total number of IOs of the first type of sample IOs and the number of missed sample IOs.
  • the computing device simulates and Count the number of sample IOs hit by the first type of sample IO in the analog cache 3, and based on the total number of IOs of the first type of sample IO and the number of hit sample IOs, first determine the number of missed sample IOs, and then According to the total number of IOs of the first type of sample IOs and the number of missed sample IOs, the miss rate of the first type of sample IOs in the analog cache 3 is calculated.
  • the computing device can determine X miss rates corresponding to the X cache sizes when the first type of sample IO is applied with the first elimination algorithm.
  • the computing device obtains the relationship between the miss rate of the first type of sample IO under the first elimination algorithm and the cache size, that is, obtains the MRC of the first type of sample IO under the first elimination algorithm.
  • the computing device may appropriately increase the hit rate in the HRC curve after determining the HRC of the sample IOs of each category, or appropriately reduce the miss rate in the large MRC curve after determining the MRC of the sample IOs of each category, Used to compensate for cache misses caused by cache cold start.
  • what is actually intended to be simulated in the embodiment of the present application is the hit rate of the IO request when there is data in the cache, and the simulated hit rate when the cache is initially empty is usually lower than the hit rate when there is data in the cache Rate. Therefore, the embodiment of the present application compensates the hit rate in the simulated HRC or the miss rate in the MRC.
  • the specific compensation value of cold start compensation for the simulated hit rate in HRC or miss rate in MRC in this embodiment of the present application may be determined by the sample IO of each category used for simulating HRC or MRC.
  • the number of sample IOs that miss within the preset time period can be used as the hit rate compensation in the simulated HRC or in the MRC
  • the specific compensation value for the missing rate is not specifically limit the preset duration, nor does it limit the specific method for determining the compensation value.
  • a data prefetching mechanism may be used. That is, the entity will preload data that may be accessed in the future into the shared cache. Therefore, when the IO request initiated by the subsequent entity accesses the prefetched data, it will definitely hit. Therefore, the hit rate of the IO request under the prefetch mechanism is higher than that of the IO request without the prefetch mechanism.
  • the computing device may appropriately reduce the hit rate in the HRC curve after determining the HRC of the sample IOs of each category, or appropriately increase the miss rate in the MRC curve after determining the MRC of the sample IOs of each category, so as to Used to reduce the impact of the prefetch mechanism on the IO request hit rate.
  • reducing the specific value of the hit rate in the HRC simulated by the embodiment of the present application can be used to simulate each HRC or MRC
  • the computing device only needs to count the number of sample IOs that access the prefetched data in the sample IOs of each category, and can determine the specific value for reducing the hit rate in the simulated HRC (or increase The specific value of the deletion rate in the MRC).
  • the computing device can simulate the relationship between the hit rate of the first type of sample IO under the N elimination algorithms and the cache size, and simulate the hit rate and the size of the sample IO of each category under the N elimination algorithms Cache size relationship.
  • the computing device determines the relationship between the simulated hit rate and the cache size of each category of sample IO under N elimination algorithms respectively as the hit rate and Cache size relationship. For example, the computing device determines the HRC of the sample IOs of each category under the N elimination algorithms respectively as the HRC of the IO requests of each category under the N elimination algorithms respectively. Alternatively, the computing device determines the MRC of the sample IOs of each category under the N elimination algorithms respectively as the MRC of the IO requests of each category under the N elimination algorithms respectively.
  • the computing device determines the hit rate of the first type of sample IO when applying the first elimination algorithm in caches of different sizes according to the reuse distance of each sample IO in the first type of sample IO and different cache sizes, so as to get the first
  • the relationship between the hit rate of a class of sample IO under the first elimination algorithm and the cache size is described in detail.
  • the computing device may determine the reuse distance of each sample IO in the first type of sample IO based on the logical address accessed by each sample IO in the first type of sample IO. Next, in the first type of sample IOs, the computing device counts the number of identical reuse distances among the reuse distances of each sample IO, that is, counts the frequency of each reuse distance.
  • the first type of sample IO includes 10 sample IOs
  • the logical addresses accessed sequentially in these 10 sample IOs are (a, b, c, d, a, d, a, c, b, a )
  • the computing device statistics obtain that the reuse distance of each sample IO in the 10 sample IOs is ( ⁇ , ⁇ , ⁇ , ⁇ , 3, 1, 1, 2, 3, 2).
  • the computing device counts the number of the same reuse distance based on the reuse distance of each sample IO in the 10 sample IOs.
  • the number of reuse distance ⁇ (ie frequency) is 4, the number of reuse distance 1 (ie frequency) is 2, the number of reuse distance 2 (ie frequency) is 2, and the number of reuse records is 3
  • the number is (ie frequency) 2.
  • the computing device determines the hit rate of the first type of sample IO with different cache sizes based on the preset rules and the counted number of the same reuse distance in the first type of sample IO, so as to obtain the first type of sample IO in the first
  • the relationship between the hit rate and the cache size under the elimination algorithm is designed based on elimination algorithms, one elimination algorithm corresponds to one preset rule, and N elimination algorithms correspond to N preset rules.
  • the embodiment of the present application does not limit the specific design of the preset rule corresponding to the elimination algorithm.
  • the preset rule corresponding to LRU can be: determine the number of reuse distances that are smaller than the preset value is the number of hits of the first type of sample IO when the cache size is the data size requested by the preset number of sample IOs.
  • the computing device may predetermine the value of the preset value corresponding to each cache size based on the value of each cache size among the preset X cache sizes and the size of data accessed by a single sample IO.
  • the computing device can determine X hit times corresponding to X cache sizes when the first type of sample IO is applied with the first elimination algorithm.
  • the description of the size of the X caches refers to the above description, and will not be repeated here.
  • the size of data accessed by each sample IO is the same, for example, all are 4K, which is not limited.
  • the size of the access data requested by a single sample IO is preset in the computing device.
  • the computing device may also determine the average size of the access data requested by each sample IO according to the number of sample IOs included in the first type of sample IO and the total size of the access data requested by the first type of sample IO, and The average size is used as the size of the access data requested by a single sample IO, which is not limited in this embodiment of the present application.
  • the first type of sample IO includes 10 sample IOs, and based on the statistics of these 10 sample IOs, the number of reuse distances of ⁇ is 4, the number of reuse distances of 1 is 2, and the reuse distance is The number of 2 is 2, and the number of reuse distance 3 is 2.
  • the computing device determines that there is no reuse distance that will be less than 1, so the computing device determines that when the cache size is the size of the access data requested by 1 sample IO, the first type of sample IO The number of hits is 0.
  • the computing device can determine the number 2 of reuse distances less than 2 (that is, the number 2 of reuse distances of 1) as the requested access data when the cache size is 2 sample IOs When the size of , the number of hits of the first type of sample IO.
  • the computing device can calculate the number 4 of the reuse distance less than 3 (that is, the sum of the number 2 of the reuse distance of 1 and the number 2 of the reuse distance of 2 (ie 2+ 2)) is determined as the number of hits of the first type of sample IO when the cache size is the size of the access data requested by 3 sample IOs.
  • the computing device can calculate the number 6 of the reuse distances less than 4 (that is, the number 2 with a reuse distance of 1, the number 2 with a reuse distance of 2, and the number 2 with a reuse distance of 3
  • the sum of the number 2 (ie 2+2+2)) determine is the number of hits of the first type of sample IO when the cache size is the size of the access data requested by 4 sample IOs.
  • the computing device can determine the first-type samples under the LRU algorithm The number of IO hits at different cache sizes. Further, based on the determined number of hits and the number of first-type sample IOs, the computing device can calculate the hit rate of the first-type sample IOs under different cache sizes under the LRU algorithm. In this way, for the X cache sizes preset by the computing device for the first type of IO requests, the computing device determines X hit rates corresponding to the X cache sizes when the LRU algorithm is applied to the first type of sample IO. Thus, the computing device obtains the relationship between the hit rate of the first type of sample IO under the LRU algorithm and the cache size, that is, obtains the HRC of the first type of sample IO under the LRU algorithm.
  • the computing device may base on the total number of the first type of sample IOs and the number of hits of the first type of sample IO under the LRU algorithm at different cache sizes The number of hits determines the number of misses of the first type of sample IO in different cache sizes under the LRU algorithm. Furthermore, the computing device calculates the miss rate of the first type of sample IO under the LRU algorithm at different cache sizes according to the total number of the first type of sample IOs and the number of misses of the first type of sample IOs under the LRU algorithm at different cache sizes .
  • the computing device determines X hit rates corresponding to the X cache sizes when the LRU algorithm is applied to the first type of sample IO.
  • the computing device obtains the relationship between the miss rate of the first type of sample IO under the LRU algorithm and the cache size, that is, obtains the MRC of the first type of sample IO under the LRU algorithm.
  • the computing device can respectively determine N elimination The number of hits (or the number of misses) of the sample IO of each category under the algorithm at different cache sizes. Further, based on the determined number of hits (or misses) and the number of sample IOs of each category, the computing device can calculate the hit rate (or missing) of the sample IOs of each category under the N elimination algorithms at different cache sizes. Rate).
  • the computing device has obtained the relationship between the hit rate and the cache size (or the relationship between the miss rate and the cache size) of the sample IO of each category under the N elimination algorithms respectively, that is, the sample IO of each category HRC(MRC) under N knockout algorithms respectively.
  • the method provided in the embodiment of the present application also includes a method for generating a classifier as shown in FIG. 7 . As shown in FIG. 7, before S101, the method provided in the embodiment of the present application further includes S101a-S101d.
  • the computing device in S101a The acquired multiple IO requests are multiple IO requests acquired by the computing device within the first period of the first period.
  • the K types of IO requests obtained by the computing device at S101 are the K types of IO requests obtained by the computing device within the second period of the first cycle.
  • the first period of time is a period within the first cycle starting from the starting moment of the first cycle and having a duration of a preset duration.
  • the second time period is the remaining time period in the first cycle except the first time period.
  • the embodiment of the present application does not limit the duration of the first period and specific values of the preset duration.
  • the first period is 1 hour
  • the starting time of the first period is 10:00
  • the preset duration is 10 minutes
  • the first period is from 10:00 to 10:10
  • the second period It is from 10:11 to 11:00.
  • the multiple IO requests obtained by the computing device at S101a are the multiple IO requests obtained by the computing device within 10:00 ⁇ 10:10
  • the IO requests of K categories obtained by the computing device at S101 are the IO requests obtained by the computing device at 10:00.
  • the multiple IO requests obtained by the computing device in S101a are a preset number of IO requests in time sequence among all the IO requests obtained by the computing device in the first period.
  • the K types of IO requests obtained by the computing device in S101 are IO requests other than the preset number of IO requests among all the IO requests obtained by the computing device in the first cycle.
  • the embodiment of the present application does not limit the specific value of the preset number.
  • the multiple IO requests acquired by the computing device in S101a are among the 10,000 IO requests
  • the first 1,000 IO requests in timing that is, the first to the 1,000th IO request in timing among the 10,000 IO requests.
  • the K types of IO requests obtained by the computing device in S101 are 9000 IO requests except the first IO request to the 1000th IO request among the 10000 IO requests, that is, the timing of the 10000 IO requests.
  • the feature of the plurality of IO requests to access the logical address includes the access frequency of the plurality of IO requests to access the same logical address, and/or includes the reuse time of the logical addresses accessed by the plurality of IO requests.
  • the computing device counts the number of accessed logical addresses among the multiple IO requests.
  • the number of IO requests for a logical address (such as the first number).
  • the first quantity is the access frequency of the above-mentioned multiple IO requests to access the first logical address.
  • the computing device determines the determined first quantity as a frequency feature of each IO request accessing the first logical address among the plurality of IO requests.
  • the computing device may determine the frequency feature of each IO request in the above multiple IO requests.
  • the computing device may determine the reuse time of the logical address accessed by the IO request each time it obtains one IO request.
  • the computing device may also determine the reuse time of the logical address accessed by each IO request in the multiple IO requests after acquiring the multiple IO requests.
  • the detailed description of the reuse time can refer to the description in the terminology above, and will not be repeated here.
  • the computing device determines the first The reuse time of a logical address is different. That is to say, for one logical address, the computing device can determine multiple different reuse times.
  • the third IO request in these 10 requests accesses
  • the reuse time of logical address d is infinite
  • the reuse time of logical address d accessed by the 6th IO request is 2
  • the reuse time of logical address d accessed by the 10th IO request is 3.
  • the computing device can select a reuse time among different reuse times of the same logical address, and use the selected reuse time as the The reuse time characteristics of an IO request.
  • the computing device may arbitrarily select a reuse time among different reuse times of the same logical address, and use the selected reuse time as a reuse time characteristic of each IO request accessing the logical address.
  • the reuse time arbitrarily selected by the computing device is a non-infinite reuse time.
  • the computing device may calculate the mean value (or round up/down after calculating the mean value) of multiple different determined reuse times of the same logical address, and calculate the mean value (or round up/down after calculating the mean value) value) as the reuse time feature of each IO request accessing the logical address.
  • the multiple different reuse times used for calculating the mean value are multiple different reuse times except for the reuse time whose value is infinite.
  • the computing device calculates the average of the reuse time of the logical address d accessed by the sixth IO request is 2 and the reuse time of the logical address d accessed by the tenth IO request is 3 and rounds up (that is, [(2+3 )/2] rounded up), and the value 3 rounded up after calculating the average is used as the reuse time characteristic of each IO request accessing the logical address d.
  • the computing device divides the plurality of IO requests into K categories of IO requests according to the characteristics of the access logical addresses of the plurality of IO requests and at least one characteristic threshold.
  • the feature threshold includes a frequency threshold and/or a reuse time threshold.
  • the computing device and K-1 frequency thresholds divide the multiple IO requests into K categories of IO requests. It should be noted that logical addresses accessed by IO requests belonging to the same category have a high degree of similarity.
  • the K-1 frequency thresholds may be user-preset frequency thresholds.
  • the computing device divides the multiple frequencies determined by S101b into K frequency ranges according to the first preset algorithm, and the K-1 critical frequencies between the K frequency ranges are K -1 frequency threshold.
  • the first preset algorithm may be any classification algorithm, which is not limited in this embodiment of the present application. Among them, the logical addresses accessed by the IO requests whose frequency characteristics belong to a frequency range have a high degree of similarity.
  • the computing device will The time feature and K-1 reuse time thresholds divide the multiple IO requests into K categories of IO requests. It should be noted that logical addresses accessed by IO requests belonging to the same category have a high degree of similarity.
  • the K-1 reuse time thresholds may be user-preset reuse time thresholds.
  • the K-1 reuse time thresholds are calculated by the computing device according to the second preset algorithm, dividing the multiple reuse times determined in S101b into K reuse time ranges, and K-1 thresholds between the K reuse time ranges
  • the reuse time is K-1 reuse time thresholds.
  • the second preset algorithm may be any classification algorithm, which is not limited in this embodiment of the present application.
  • the reuse time feature belongs to the logical addresses accessed by the IO requests in a reuse time range, and has a high similarity.
  • the computing device calculates the plurality of IO requests according to frequency characteristics of each IO request in the plurality of IO requests, p frequency thresholds, reuse time characteristics of each IO request in the plurality of IO requests, and q reuse time thresholds.
  • IO requests divided into K categories. Wherein, both p and q are positive integers, and p+q ⁇ K-1. Wherein, the detailed description of the frequency threshold and the reuse time threshold can refer to the above description, and will not be repeated here.
  • the computing device may first divide the multiple IO requests according to the reuse time characteristics and q reuse time thresholds of each of the multiple IO requests For q+1 categories. Furthermore, for the IO requests of at least one category in the aforementioned q+1 categories, the computing device calculates the IO requests of each category in the at least one category according to the frequency characteristics and p frequency thresholds of each IO request in the at least one category Divide the IO requests into p+1 categories, so as to divide the multiple IO requests into K categories of IO requests. It should be noted that logical addresses accessed by IO requests belonging to the same category have a high degree of similarity.
  • the computing device may first The reuse time characteristics of each IO request and 1 A reuse time threshold (such as threshold 1), the multiple IO requests are divided into the first category of IO requests and the second category of IO requests.
  • the IO requests of the first category are IO requests whose reuse time characteristics are less than the threshold 1
  • the IO requests of the second category are IO requests whose reuse time characteristics are greater than the threshold 1.
  • the embodiment of the present application does not limit the situation that the reuse time characteristic is equal to the threshold value 1, for example, the IO request whose reuse time characteristic is equal to the threshold value 1 may be an IO request of the first category, or an IO request of the second category.
  • the computing device calculates according to the frequency characteristics of each IO request in the second category of IO requests and 1 frequency threshold (such as threshold 2), divide the IO requests of the second category into the IO requests of the third category and the IO requests of the fourth category.
  • 1 frequency threshold such as threshold 2
  • the IO request of the third category is an IO request whose frequency characteristic is less than the threshold value 2
  • the IO request of the fourth category is an IO request whose frequency characteristic is greater than the threshold value 2.
  • the embodiment of the present application does not limit the case where the frequency characteristic is equal to the threshold value 2, for example, the IO request whose frequency characteristic is equal to the threshold value 2 may be the IO request of the third category, or the IO request of the fourth category.
  • the multiple IO requests obtained by the computing device at S101a are divided into IO requests of the first category, IO requests of the third category, and IO requests of the fourth category.
  • the computing device may first divide the multiple IO requests into p +1 category. Furthermore, for the IO requests of at least one category in the aforementioned p+1 categories, the computing device calculates the IO requests of each category in the at least one category according to the reuse time characteristics and q reuse time thresholds of each IO request in the multiple IO requests. The IO requests are divided into q+1 categories, so as to divide the multiple IO requests into K categories of IO requests. It should be noted that logical addresses accessed by IO requests belonging to the same category have a high degree of similarity.
  • the computing device After the computing device divides the obtained multiple IO requests into K categories of IO requests, it marks each IO request with a category identifier, where the category identifier is used to indicate the category to which the IO request belongs.
  • the computing device divides the obtained multiple IO requests into two categories of IO requests (including category 1 IO requests and category 2 IO requests). In this way, the computing device indicates the ID 1 of the category 1 for each IO request tag in the category 1, and indicates the ID 2 of the category 2 for each IO request tag in the category 2.
  • the computing device generates a classifier according to the sample parameters of each of the multiple IO requests and the third preset algorithm.
  • the sample parameters of an IO request include the category identifier of the IO request and the logical address carried by the IO request.
  • the third preset algorithm may be any supervised learning classification algorithm, which is not limited in this embodiment of the present application.
  • the third preset algorithm may be a k-nearest-Neighbor (KNN) algorithm, or a KNN+prototype algorithm.
  • KNN k-nearest-Neighbor
  • the KNN+prototype algorithm is simpler than the KNN algorithm.
  • the computing device may input the sample parameters of each IO request in the above multiple IO requests into KNN (or KNN+prototype), so as to obtain a classifier.
  • the classifier receives the logical address of the IO request to be classified, it can first determine the sample parameter where the logical address with the highest similarity to the logical address is located, and output the class identifier in the sample parameter to indicate The category of the IO request to be classified.
  • the computing device may input the acquired logical address 1 of the IO request 1 into the above generated classifier.
  • the classifier determines that the logical address having the greatest similarity with logical address 1 is logical address 2 .
  • the classifier outputs the category identifier 1 of the sample parameter 1 where the logical address 2 is located, so as to indicate the category of the IO request 1 .
  • the computing device can generate a classifier for classifying IO requests.
  • the classifier generated by the computing device based on a part of the IO requests in the current cycle can be used to classify another part of the IO requests in the current cycle (for example, divided into K categories ),from According to the access characteristics of the classified K categories of IO requests accessing the shared cache, determine the partition size and elimination algorithm of each category of IO requests in the shared cache.
  • the classifier generated by the computing device in the current cycle may be used to classify the IO requests initiated by the entity in the next cycle of the current cycle, so that the classified IO requests access the corresponding cache. Therefore, based on the methods described in S101a-S101d, the entity initiating the IO request does not need to mark the IO request with a category mark for classification, so that the entity initiating the IO request does not generate additional resource overhead. Moreover, since the method provided by the embodiment of the present application does not invade the upper layer of the cache (that is, the entity that initiates the IO request), the method provided by the embodiment of the present application can be applied to a general cache system for diverse customers without ecological support .
  • the shared cache management method provided in the embodiment of the present application may also be applied to a scenario of fusion of read and write caches in the shared cache.
  • the read-write cache fusion of the shared cache means that the read cache and the write cache are not distinguished in the shared cache, and the IO request for reading data and the IO request for writing data share the shared cache.
  • FIG. 9 shows a schematic flowchart of another shared cache management method provided by an embodiment of the present application.
  • the method may be applied to the CPU shown in FIG. 1 , or to the cache node shown in FIG. 2 , or to the node shown in FIG. 3 .
  • the method can be executed by a computing device having the hardware structure shown in FIG. 4 , and the method includes the following steps.
  • IO requests initiated by multiple entities include K categories of IO requests, and each category of IO requests in the K categories includes IO read requests and IO write requests.
  • the IO request acquired by the computing device is one of an IO read request for reading data or an IO write request for writing data.
  • the IO requests acquired by the computing device include an IO read request for reading data and an IO write request for writing data.
  • the read access characteristic is the relationship between the read hit rate and the cache size of the IO read requests of each category in the K categories under N elimination algorithms
  • the write access characteristic is the IO write request of each category in the K categories respectively.
  • the relationship between write hit rate and cache size under N elimination algorithms refers to the hit rate of the read hit in the cache of the IO read request.
  • the write hit rate refers to the hit rate of IO write requests in the cache.
  • the computing device determines, according to the acquired IO read requests of each of the K categories, the read access characteristics of the IO read requests of each of the K categories accessing the shared cache. And, according to the acquired IO write requests of each category in the K categories, the computing device determines the write access characteristic of the IO write requests of each category in the K categories accessing the shared cache.
  • the computing device determines the detailed description of the read access characteristics of the IO read requests of each category in the K categories to access the shared cache, and according to the IO read requests of each category in the K categories The write request determines the IO request of each category in the K categories. For a detailed description of the write access characteristics of the shared cache for the write request to access the shared cache, you can refer to "the computing device determines the K The relevant descriptions of the access characteristics of the IO requests of each category to access the shared cache" will not be repeated here.
  • the computing device determines the IO of each category according to the read access characteristics of the IO read requests of each category in the K categories, the write access characteristics of the IO write requests of each category in the K categories, and the hit rate of the shared cache. Please refer to the description of S103 for a detailed description of the requested partition size in the shared cache and the elimination algorithm.
  • the computing device can obtain a hit rate of K categories of IO requests in the shared cache", in S203, the computing device According to the read hit rate of each category of IO read requests in any combination, the read hit weight coefficient, the write hit rate of each category of IO write requests in any combination, and the write hit weight coefficient, K can be obtained The comprehensive hit rate of IO requests of the category in the shared cache.
  • the read hit weight coefficient is used to characterize the influence degree of the read hit rate of each category of IO read requests in the shared cache on the comprehensive hit rate of the shared cache
  • the write hit weight coefficient is used to characterize the IO write request of each category in How much the write hit rate in the shared cache affects the combined hit rate of the shared cache.
  • the comprehensive hit rate of the shared cache is the hit rate of IO requests of K categories in the shared cache.
  • the embodiment of the present application does not limit specific values of the read hit weight coefficient and the write hit weight coefficient.
  • both the read hit weight coefficient and the write hit weight coefficient are preset weight coefficients.
  • the read hit weight coefficient and/or the write hit weight coefficient may be determined based on the entity's access rules to the shared cache in a recent period of time, or the read hit weight coefficient and/or the write hit weight coefficient may be determined based on the forecast for a period of time in the future.
  • the access rule of the estimated entity to the shared cache is determined.
  • the computing device can be in any combination (for example, the hit rate under the first combination) and the proportion of the first type of IO read request in the K types of IO requests determine the hit rate of the first type of IO read request in the shared cache under the first combination.
  • the computing device performs a product operation on the hit rate of the first type of IO read requests under the first combination and the proportion of the first type of IO read requests in the K types of IO requests, so as to obtain the first type under the first combination
  • the hit ratio of IO read requests in the shared cache For example, the hit rate under the first combination
  • the proportion of the first type of IO read request in the K types of IO requests determine the hit rate of the first type of IO read request in the shared cache under the first combination.
  • the computing device can according to the hit rate and The proportion of the first type of IO write request in the K types of IO requests determines the hit rate of the first type of IO write request in the shared cache under the first combination. For example, the computing device performs a product operation on the hit rate of the first type of IO write request under the first combination and the proportion of the first type of IO write request in the K types of IO requests, so as to obtain the first type under the first combination The hit ratio of IO write requests in the shared cache.
  • the computing device is based on the hit ratio (such as the first hit ratio) of the first type of IO read request in the shared cache under the first combination, the read hit weight coefficient, and the ratio of the first type of IO write request in the shared cache under the first combination.
  • the hit rate (such as the second hit rate) and the write hit weight coefficient determine the hit rate of the first type of IO request in the shared cache under the first combination.
  • the computing device sums the product of the first hit rate and the weight coefficient of the read hit, and the product of the second hit rate and the weight coefficient of the write hit, so as to obtain the first type of IO request in the shared cache under the first combination hit rate.
  • the hit ratio of the first type of IO request in the shared cache under the first combination is: first hit ratio ⁇ W1+second hit ratio ⁇ W2.
  • the computing device can determine the hit rate of each category of IO requests in the shared cache in any combination. Further, the computing device sums the K hit rates of the K categories of IO requests in the shared cache respectively, to obtain the hit rates of the K categories of IO requests in the shared cache. Further, for K categories of IO requests, the computing device can obtain (X ⁇ N hit rates of K categories of IO requests in the shared cache according to the X ⁇ N hit rates of each category of IO requests in X ⁇ N combinations. N) K hits.
  • the computing device determines the maximum hit rate of the K categories of IO requests in the shared cache, And the cache size indicated by the combination corresponding to each category when the maximum hit rate is obtained is determined as the partition size of the IO request of each category in the shared cache, and the combination indicated by each category when the maximum hit rate is obtained
  • the elimination algorithm determines the elimination algorithm for each category of IO requests in the shared cache. For specific description, reference may be made to the description in S103, and details are not repeated here.
  • the computing device sums the K hit rates of K categories of IO requests in the shared cache to obtain the hit rates of K categories of IO requests in the shared cache, the K categories of IO requests The sum of cache sizes is less than or equal to the size of the shared cache.
  • the methods described in S201-S104 above may be performed periodically, and related descriptions may refer to related descriptions in Embodiment 1, and details are not repeated here.
  • the shared cache can periodically adjust the cache size of each category of IO requests in the shared cache according to the cache size and elimination algorithm of each category of IO requests in the K categories periodically determined by the computing device and the elimination algorithm, so as to ensure the hit rate of IO requests in the shared cache in the time domain, that is, the cache performance of the shared cache is guaranteed in the time domain.
  • FIG. 10 shows a schematic flowchart of another method for managing a shared cache provided by an embodiment of the present application.
  • the method may be applied to the CPU shown in FIG. 1 , or to the cache node shown in FIG. 2 , or to the node shown in FIG. 3 .
  • the method can be executed by a computing device having the hardware structure shown in FIG. 4 .
  • the computing device first executes S201, and then the computing device executes S302.
  • the computing device first determines the read hit rate of the IO read requests of each category under the N elimination algorithms in caches of different sizes according to the obtained IO read requests of each category in the K categories, and the computing device According to the obtained IO write requests of each category in the K categories, determine the write hit rate of the IO write requests of each category in caches of different sizes under the N elimination algorithms. For example, taking the first type of IO request among the K types of IO requests as an example, the computing device can determine the buffer size of the first type of IO read request under N elimination algorithms according to the obtained first type of IO read request. The read hit rate in . And, according to the acquired first-type IO write requests, the computing device determines write hit ratios of the first-type IO write requests in caches of different sizes under the N elimination algorithms.
  • the computing device determines the detailed description of the read hit ratios of the IO read requests of each category in caches of different sizes under the N elimination algorithms, and the computing device According to the obtained IO write requests of each category in the K categories, the detailed description of determining the write hit rate of the IO write requests of each category in caches of different sizes under the N elimination algorithms can refer to the determination of N in S102. The relevant description of the hit rate of each category of IO requests in caches of different sizes under the elimination algorithm will not be repeated here.
  • the product of the read hit rate of the computing device to the first type of IO read request and the read hit weight coefficient, and the first type A class of IO write requests is summed to obtain the hit rate of the first type of IO request under the elimination algorithm and the cache size.
  • the computing device can determine the hit rate of each category of IO requests in caches of different sizes under the N elimination algorithms. In this way, the relationship between the hit rate and the cache size of the IO requests of each of the K categories under the N elimination algorithms is obtained, that is, the access characteristics of the IO requests of each of the K categories to access the shared cache are obtained .
  • the computing device executes S103-S104.
  • an appropriate cache size and elimination algorithm can be determined and configured for each type of IO request, thereby improving IO
  • the hit rate of requests in the shared cache improves the overall cache performance of the shared cache.
  • the above method described in FIG. 10 may be executed periodically, and related descriptions may refer to related descriptions in Embodiment 1, and details are not repeated here.
  • the shared cache can periodically adjust the IO requests of each category in the shared cache according to the cache size and elimination algorithm of the IO requests of each category in the K categories periodically determined by the computing device.
  • the cache size and elimination algorithm ensure the hit rate of IO requests in the shared cache in the time domain, that is, the cache performance of the shared cache is guaranteed in the time domain.
  • FIG. 11 shows a schematic structural diagram of a shared cache management device 110 provided by an embodiment of the present application.
  • the management device 110 is configured to execute the above-mentioned shared cache management method, for example, to execute the method shown in FIG. 5 , FIG. 7 , FIG. 9 or FIG. 10 .
  • the management device 110 may include a determination unit 111 and a configuration unit 112 .
  • the determination unit 111 is configured to determine the access characteristics of the IO requests of each category in the K categories to access the shared cache, and is used to determine the access characteristics of each category according to the access characteristics of the IO requests of the K categories and the hit rate of the shared cache.
  • the partition size and elimination algorithm of IO requests in the shared cache is the relationship between the hit rate and the cache size of the IO requests of each category in the K categories under the N elimination algorithms.
  • the configuration unit 112 is configured to configure the cache size of each category of IO requests in the shared cache as the determined partition size of each category of IO requests in the shared cache, and configure the cache size of each category of IO requests in the shared cache.
  • the elimination algorithm in the cache is configured to determine the elimination algorithm for each category of IO requests in the shared cache.
  • the determining unit 111 may be used to execute S102 and S103, and the configuring unit 112 may be used to execute S104.
  • the determination unit 111 may be used to execute S202 and S203, and the configuration unit 112 may be used to execute S104.
  • the determination unit 111 may be used to execute S302 and S103, and the configuration unit 112 may be used to execute S104.
  • the management device 110 further includes: a simulation unit 113, configured to, for the first elimination algorithm among the N elimination algorithms, simulate in the shared cache that the IO requests of each category in the K categories are applied in caches of different sizes
  • the hit rate of the first elimination algorithm is used to obtain the relationship between the hit rate and the cache size.
  • the first elimination algorithm is any one elimination algorithm among the N elimination algorithms.
  • the determining unit 111 is specifically configured to: for the first elimination algorithm among the N elimination algorithms, according to the reuse distance and different cache sizes of each IO request in the first type of IO request, determine the first type of IO request in Apply the hit rate of the first elimination algorithm to caches of different sizes to obtain the relationship between the hit rate and the size of the cache.
  • the first elimination algorithm is any one of the N elimination algorithms
  • the first type of IO request is an IO request of any one of the K categories.
  • the determining unit 111 is also specifically configured to: determine K categories of IO requests under each combination according to X hit rates corresponding to X cache sizes determined under each elimination algorithm based on each category of IO requests In the hit rate of the shared cache, and when the hit rate of the K categories of IO requests in the shared cache is the largest, the cache corresponding to the IO request of each category
  • the storage size is determined as the partition size of each category of IO requests in the shared cache
  • the elimination algorithm corresponding to each category of IO requests when the hit rate of K categories of IO requests in the shared cache is the largest is determined as each The elimination algorithm for category IO requests in the shared cache.
  • X cache sizes and N elimination algorithms constitute X*N combinations, each combination includes a cache size and an elimination algorithm; the X cache sizes are X cache sizes of cache presets corresponding to each category of IO requests.
  • the determining unit 111 may be used to execute S103.
  • the determining unit 111 may be configured to execute S203.
  • the management device 110 further includes: an obtaining unit 114, configured to obtain a plurality of IO requests before determining the access characteristics of each of the K categories of IO requests accessing the shared cache.
  • the classifying unit 115 is configured to classify the IO requests into K categories according to features of addresses of data accessed by the multiple IO requests or according to category marks carried in the multiple IO requests.
  • the acquiring unit 114 and the classifying unit 115 may be used to execute S101.
  • the above-mentioned shared cache is an LLC of the CPU in the computing device, and the above-mentioned multiple IO requests are IO requests initiated by multiple processing cores in the CPU.
  • the above-mentioned shared cache is a cache in a cache node
  • the above-mentioned multiple IO requests are IO requests initiated by multiple computing nodes accessing the cache node.
  • the shared cache is a cache pool formed by caches in multiple nodes, and the multiple IO requests are IO requests initiated by multiple computing nodes accessing the cache pool.
  • the above-mentioned access characteristics are characterized by HRC or MRC of the IO request.
  • the determining unit 111 is further configured to periodically determine the access characteristics of the IO requests of each category in the K categories accessing the shared cache. For the access characteristics of the IO requests of each category in the K categories determined in the first cycle to access the shared cache, the determining unit 111 is specifically configured to use the access characteristics of the K categories of IO requests determined in the first cycle and the characteristics of the shared cache. Hit rate, determine the partition size and elimination algorithm of the IO request of each category in the shared cache in the first cycle, wherein the first cycle is to determine the access characteristics of the IO requests of each category in the K categories to access the shared cache A cycle.
  • the functions implemented by the determination unit 111, the configuration unit 112, the simulation unit 113, and the classification unit 115 in the management device 110 can execute the program in the memory 402 in FIG. 4 through the processor 401 in FIG. 4 Code.
  • the functions implemented by the acquiring unit 114 can be implemented through the communication interface 403 in FIG. 4 .
  • FIG. 11 is schematic, and is only a logical function division, and there may be another division method in actual implementation. For example, two or more functions can also be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.
  • Embodiments of the present application also provide a computer program product and a computer-readable storage medium for storing the computer program product.
  • the computer program product may include one or more program instructions, and when the one or more program instructions are executed by one or more processors, the functions or parts described above with respect to FIG. 5 , FIG. 7 , FIG. 9 or FIG. 10 may be provided. Achievement able. Therefore, for example, one or more features referring to S101-S104 in FIG. 5 may be undertaken by one or more instructions in the computer program product.
  • a management device such as a shared cache for performing the method described in FIG. 5 , FIG. 7 , FIG. 9 or FIG. 10 may be configured to, in response to one or more program instructions stored in a computer-readable storage medium , providing various operations, functions, or actions.
  • the embodiment of the present application also provides a computing device, which can be used to execute the method described in FIG. 5 , FIG. 7 , FIG. 9 or FIG. 10 above, so as to realize the management of the shared cache.
  • the computing device may be the same device that includes the shared cache, or the computing device is a device that communicates with the device that includes the shared cache.
  • the computing device is a device that communicates with the device that includes the shared cache.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • a software program When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the processes or functions according to the embodiments of the present application are generated in whole or in part when the computer executes the instructions on the computer.
  • a computer can be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or may contain one or more data storage devices such as servers and data centers that can be integrated with the medium.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (solid state disk, SSD)), etc.

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Abstract

一种共享缓存的管理方法、装置及存储介质，涉及计算机技术领域。该方法包括：确定访问共享缓存的K个类别中每个类别的IO请求访问共享缓存的访问特性。根据确定的访问特性和共享缓存的命中率确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法。将每个类别的IO请求在共享缓存中的缓存大小配置为确定出的分区大小，以及将每个类别的IO请求在共享缓存中的淘汰算法配置为确定出淘汰算法。该方法能够提高共享缓存中的缓存性能。

Description

共享缓存的管理方法、装置及存储介质
本申请要求于2022年03月02日提交中国专利局、申请号为202210197738.6、发明名称为“一种共享缓存的管理方法及装置”的中国专利申请的优先权，以及于2022年07月29日提交的申请号为202210908210.5、发明名称为“共享缓存的管理方法、装置及存储介质”的中国专利申请的优先权，前述两件专利申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，尤其涉及一种共享缓存的管理方法、装置及存储介质。
背景技术
共享缓存是指为适应不同的缓存需求，缓存架构中的多个实体(例如多个应用、多个客户端、或计算设备的多个处理核(core)等)之间共享缓存资源。例如，对于计算设备中包括多个core的中央处理器(central processing unit，CPU)而言，多个core共享CPU的三级缓存(last level cache，LLC)。再例如，在分布式缓存系统中，单个客户端的数据分散缓存于不同的缓存节点，相对的，在存在多个客户端的场景下，多个客户端共享单个缓存节点中缓存资源。
在多个实体共享缓存时，为避免缓存竞争，可以对多个实体共享的缓存进行分区，从而使得不同的分区用于缓存不同实体的待缓存数据。
然而，当前在共享缓存中划分缓存分区时，通常是人为指定分区大小，或者是采用简单的优先级策略确定缓存分区的大小，另外，整个共享缓存使用同样的淘汰算法，从而导致共享缓存的性能不佳。
发明内容
本申请提供了一种共享缓存的管理方法、装置及存储介质，以用于提高共享缓存中的缓存性能。
为达上述目的，本申请提供如下技术方案：
第一方面，本申请提供一种共享缓存的管理方法，该方法用于对共享缓存进行管理。其中，共享缓存用于缓存多个IO请求所请求操作的数据，该多个IO请求对应K个类别，共享缓存对应N个淘汰算法。该方法包括：确定该K个类别中每个类别的IO请求访问共享缓存的访问特性。根据K个类别的IO请求的访问特性及共享缓存的命中率，确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法。将每个类别的IO请求在共享缓存中的缓存大小，配置为确定的每个类别的IO请求在共享缓存中的分区大小，以及将每个类别的IO请求在共享缓存中的淘汰算法，配置为确定的每个类别的IO请求在共享缓存中的淘汰算法。其中，K个类别中每个类别的IO请求访问共享缓存的访问特性为：该K个类别中每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系。
通过本申请提供的共享缓存的管理方法，通过获取每个类别的输入/输出(input/output，IO)请求的访问特性，为每个类别的IO请求在所述共享缓存中确定分区大小及缓存淘汰算法，以提高每类IO请求获得适当的缓存性能，从而提高整个共享缓存中的缓存性能。具体地，在读数据场景中，可以提高共享缓存的命中率，从而提高数据读取的效率，在写数据场景中，通过提高写命中率，节省了共享缓存向后端存储单元刷盘的次数。
在一种可能的设计方式中，上述确定该K个类别中的每个类别的IO请求访问共享缓存的访问特性包括：对于上述N个淘汰算法中的第一淘汰算法，在共享缓存中模拟K个类别中每个类别的IO请求在不同大小的缓存中应用第一淘汰算法的命中率，以得到命中率与缓存大小的关系。其中，第一淘汰算法是N个淘汰算法中的任意一个淘汰算法。
在另一种可能的设计方式中，上述确定该K个类别中的每个类别的IO请求访问共享缓存的访问特性包括：对于上述N个淘汰算法中的第一淘汰算法，根据第一类IO请求中每个IO请求的重用距离及不同的缓存大小，确定第一类IO请求在不同大小的缓存中应用第一淘汰算法的命中率，以得到命中率与缓存大小的关系。其中，第一淘汰算法是N个淘汰算法中的任意一种淘汰算法，第一类IO请求为K个类别中的任意一个类别的IO请求。
上述两种可能的设计，提供了两种确定K个类别中的每个类别的IO请求访问共享缓存的访问特性的方法。
在另一种可能的设计方式中，上述根据K个类别的IO请求的访问特性及共享缓存的命中率，确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法包括：根据基于每个类别的IO请求在每个淘汰算法下确定的X个缓存大小对应的X个命中率，确定每个组合下K个类别的IO请求在共享缓存的命中率。将K个类别的IO请求在共享缓存中的命中率最大时每个类别的IO请求对应的缓存大小，确定为每个类别的IO请求在共享缓存中的分区大小，以及将K个类别的IO请求在共享缓存中的命中率最大时每个类别的IO请求对应的淘汰算法，确定为每个类别的IO请求在共享缓存中的淘汰算法。其中，针对K个类别的IO请求中的任一个类别，X个缓存大小和N个淘汰算法构成X*N个组合，每个组合中包括一个缓存大小和一个淘汰算法，X个缓存大小是为与每个类别的IO请求对应的缓存预设的X个缓存大小。
通过该可能的设计，能够确定出K个类别的IO请求在共享缓存中的命中率最大时每个类别的IO请求对应的分区大小和淘汰算法。进而基于确定出的分区大小和淘汰算法配置K个类别中每个类别的IO请求在共享缓存中的缓存大小和淘汰算法，能够实现了通过对影响缓存性能的淘汰算法和缓存大小两个因子的联合求解来优化K个类别中每个类别的IO请求在共享缓存中的缓存大小和淘汰算法的目的。从而，优化后的K个类别中每个类别的IO请求在共享缓存中的缓存大小和淘汰算法能够提高共享缓存的整体缓存性能。
在另一种可能的设计方式中，在上述确定K个类别中每个类别的IO请求访问共享缓存的访问特性之前，上述方法还包括：获取多个IO请求。根据多个IO请求所访问数据的地址的特征或者根据多个IO请求中所携带的类别标记，将IO请求分成K个类别。
当根据多个IO请求所访问数据的地址的特征来将IO请求分成K个类别时，发起IO请求的实体无需为IO请求标记用于分类的类别标记，从而发起IO请求的实体的不会产生额外的资源开销。并且，由于本申请提供的方法不会侵入缓存的上层(即发起IO请求的实体)，因此本申请提供的方法能够适用于面向多样化客户的通用的缓存系统，而无需生态支持。
在另一种可能的设计方式中，上述共享缓存为计算设备中CPU的LLC，则上述多个IO请求为CPU中的多个处理核发起的IO请求。
在另一种可能的设计方式中，上述共享缓存为缓存节点中的缓存，则上述多个IO请求为访问缓存节点的多个计算节点发起的IO请求。
在另一种可能的设计方式中，上述共享缓存为多个节点中的缓存构成的缓存池，则上述多个IO请求为访问缓存池的多个计算节点发起的IO请求。
通过上述三种可能的设计，本申请提供的方法可以应用于多种场景。
在另一种可能的设计方式中，上述访问特性通过IO请求的命中率曲线(hit rate curve， HRC)或缺失率曲线(miss rate curve，MRC)表征。
在另一种可能的设计方式中，上述确定K个类别中每个类别的IO请求访问共享缓存的访问特性包括：周期性的确定K个类别中每个类别的IO请求访问共享缓存的访问特性。针对在第一周期确定的K个类别中每个类别的IO请求访问共享缓存的访问特性，上述根据K个类别的IO请求的访问特性及共享缓存的命中率，确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法包括：根据在第一周期确定的K个类别的IO请求的访问特性和共享缓存的命中率，在第一周期确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法。其中，第一周期是确定K个类别中每个类别的IO请求访问共享缓存的访问特性的任一个周期。
通过上述可能的设计，共享缓存可以根据计算设备周期性确定的K个类别中每个类别的IO请求的缓存大小和淘汰算法，从而能够周期性的调整每个类别的IO请求在共享缓存中的缓存大小和淘汰算法，从而实现了在时域上提高IO请求在共享缓存的命中率，从而在时域上提高了共享缓存的整体缓存性能。
第二方面，本申请提供了一种共享缓存的管理装置。该共享缓存的管理装置用于执行上述第一方面提供的任一种方法。本申请可以根据上述第一方面提供的任一种方法，对该共享缓存的管理装置进行功能模块的划分。例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。示例性的，本申请可以按照功能将该共享缓存的管理装置划分为确定单元和配置单元等。上述划分的各个功能模块执行的可能的技术方案和有益效果的描述均可以参考上述第一方面或其相应的可能的设计提供的技术方案，此处不再赘述。
第三方面，本申请提供一种计算设备，该计算设备用于管理共享缓存，该计算设备包括：存储器、一个或多个处理器，该一个或多个处理器被配置为读取存储在存储器中的程序指令，以执行如第一方面及其任一种可能的设计方式提供的任一种方法。
第四方面，本申请提供了一种计算机可读存储介质，该计算机可读存储介质包括程序指令，当程序指令在计算机或处理器上运行时，使得计算机或处理器执行第一方面中的任一种可能的实现方式提供的任一种方法。
第五方面，本申请提供了一种计算机程序产品，当其在计算设备上运行时，使得第一方面中的任一种可能的实现方式提供的任一种方法被执行。
可以理解的是，上述提供的任一种装置、计算机存储介质或计算机程序产品等均可以应用于上文所提供的对应的方法，因此，其所能达到的有益效果可参考对应的方法中的有益效果，此处不再赘述。
在本申请中，上述共享缓存的管理装置的名字对设备或功能模块本身不构成限定，在实际实现中，这些设备或功能模块可以以其他名称出现。只要各个设备或功能模块的功能和本申请类似，属于本申请权利要求及其等同技术的范围之内。
附图说明
图1为共享缓存的一种场景示意图；
图2为共享缓存的另一种场景示意图；
图3为共享缓存的又一种场景示意图；
图4为本申请实施例提供的一种计算设备的硬件结构示意图；
图5为本申请实施例提供的一种共享缓存的管理方法的流程示意图；
图6为本申请实施例提供的一种实体发起的IO请求访问共享缓存的示意图；
图7为本申请实施例提供的一种分类器的生成方法的流程示意图；
图8为本申请实施例提供的一种IO请求的分类示意图；
图9为本申请实施例提供的另一种共享缓存的管理方法的流程示意图；
图10为本申请实施例提供的又一种共享缓存的管理方法的流程示意图；
图11为本申请实施例提供的一种共享缓存的管理装置110的结构示意图。
具体实施方式
为了更清楚的理解本申请实施例，下面对本申请实施例中涉及的部分术语或技术进行说明：
1)、缓存(cache)
当计算单元的计算速度和计算单元访问存储单元所存储数据的访存速度不匹配时，计算单元为等待在存储单元中存取数据，会产生大量的空转。为解决该问题，缓存技术应运而生。
其中，缓存是指可以进行高速数据交换的存储器。一般的，缓存位于存储单元(如外部存储器，简称外存)和计算单元(如CPU)之间。其中，外存例如可以是设备的硬盘，硬盘例如可以是固态硬盘(solid state disk，SSD)、或者是机械硬盘(hard disk drive，HDD)等。
一方面，通过将高价值的数据预先从存储单元加载到缓存，进而计算单元在访问这些高价值的数据时，可以直接在能够进行高速数据交换的缓存中读取。这样，能够提高计算单元访存数据的效率，从而减少了计算单元空转的时间，提高了应用程序的执行速度。其中，高价值数据例如是计算单元最近访问过的数据，或者是计算单元访问频率比较高的数据，又或者是工作集数据，等等不限于此。这里，工作集可以理解为一个应用程序所需的全部数据构成的数据集。
另一方面，在实体向存储单元写入数据时，可以先将待写数据写入缓存，再由缓存定期的将缓存数据写入外存(称为刷盘)。其中，实体例如是应用、计算节点、客户端设备或CPU的核心等，不限于此。这样，对于实体而言，将数据写入缓存即可认为用于写入数据的输入/输出(input/output，IO)操作已完成，这样能够提高实体的响应速度。
可选的，设备的缓存一般可以由节点的内存和/或节点的SSD来实现。其中，内存又称主存，是CPU能直接寻址的存储空间。作为示例，内存可以是动态随机存取存储器(dynamic random access memory，DRAM)等，不限于此。
2)共享缓存
为适应不同的缓存需求，缓存架构中的多个实体之间共享的缓存资源称为共享缓存。其中，多个实体例如可以是多个应用、多个计算节点、多个客户端设备、或计算设备的CPU中的多个处理核等，不限于此。其中，应用是指运行于计算设备中的应用程序，计算节点为需要访问共享缓存的计算节点，客户端设备例如可以是存储系统的客户端设备、应用程序的客户端设备等等，计算设备例如可以是通用计算机、笔记本电脑、平板电脑、服务器等任意包括CPU的设备，对此不作限定。
共享缓存可以为计算设备中包括多个处理核的CPU的三级缓存。这种情况下，向共享缓存发起IO请求的多个实体即为CPU中的多个处理核。
作为示例，参考图1，图1示出了共享缓存的一种场景示意图。如图1所示，计算设备的CPU 10包括4个处理核，分别为处理核1、处理核2、处理核3以及处理核4。其中，CPU10的4个处理核中的每个处理核均配置有独立的一级缓存(level 1 cache)和二级缓存(level 2 cache)，且CPU 10的4个处理核均能够访问CPU 10的三级缓存，即CPU 10的三级缓存为这4个处理核的共享缓存。
共享缓存还可以为缓存系统中缓存节点中的缓存。这种情况下，向共享缓存发起IO请求 的多个实体即为访问缓存节点多个客户端设备、或者访问共享缓存的多个计算节点。其中，客户端设备的具体形式也可以是任意具有计算处理功能的计算节点，对此不作限定。
其中，缓存系统可以是分布式缓存系统。可以理解，在分布式缓存系统中，一个计算节点的数据可以缓存在分布式缓存系统中的多个缓存节点的缓存中。相对的，分布式缓存系统中的一个缓存节点的缓存中可以缓存有多个计算节点的数据。因此，分布式缓存系统中用于缓存多个计算节点数据的缓存节点的缓存，即为该多个计算节点的共享缓存。
上述缓存系统还可以是集中式缓存系统。一般的，集中式缓存系统包括一个缓存节点。这种情况下，多个计算节点的数据均缓存于该缓存节点的缓存中。因此，集中式缓存系统中缓存节点的缓存，即为该多个计算节点的共享缓存。
应理解，上述的缓存节点可以是独立设备。这种情况下，该独立设备的缓存均用作缓存节点的缓存。或者，上述缓存节点所实现的功能由独立设备中的功能模块实现，即该独立设备除用于实现缓存节点的功能，还可以实现其他功能用途。这种情况下，独立设备的部分缓存用作缓存节点的缓存。作为示例，分布式缓存系统中的缓存节点所实现的功能，集成于作为分布式存储系统中存储节点的计算设备中。也就是说，该计算设备除实现存储节点的功能，且该计算设备还实现缓存节点的功能。这种情况下，该独立设备中的部分缓存用作缓存节点的缓存。
作为示例，参考图2，图2示出了共享缓存的另一种场景示意图。如图2所示，图2示出了个分布式的缓存系统20的j个访问缓存系统20的计算节点，分别为计算节点1、计算节点2、计算节点3、…、以及计算节点j，j是正整数。且缓存系统20中包括3个缓存节点，分别为缓存节点1、缓存节点2以及缓存节点3。其中，j个计算节点中的任一个计算节点的高价值数据分散缓存于缓存系统20中的多个缓存节点的缓存。相对的，缓存系统20中的单个缓存节点的缓存即为该j个计算节点的共享缓存。
共享缓存还可以为多个节点的缓存所构成的缓存池。其中，缓存池为由该多个节点中每个节点的缓存所构成的缓存池。这种情况下，向共享缓存发起IO请求的多个实体即为访问缓存池的多个计算节点。也即，缓存池用于缓存该多个计算节点的数据，
其中，为缓存池提供缓存的节点可以是任意网络系统中的节点，对此不作限定。例如，为缓存池提供缓存的节点是存储系统中的存储节点，则访问缓存池的多个计算节点为该存储系统的多个客户端设备。再例如，为缓存池提供缓存的节点是服务器集群中的多个服务器，则访问缓存池的多个计算节点为该服务器集群的多个客户端设备，或者，访问缓存池的多个计算节点中运行有访问该服务器集群的多个应用，对此不作限定。
作为示例，参考图3，图3示出了共享缓存的又一种场景示意图。如图3所示，节点1、节点2、节点3为存储系统中的存储节点，节点1的缓存为缓存1，节点2的缓存为缓存2，节点3的缓存为缓存3。则缓存1的一部分缓存、缓存2的一部分缓存、以及缓存3的一部分缓存可以构成缓存池30。进而，存储系统的计算节点1、计算节点2、计算节点3、…、计算节点j的数据可以缓存于缓存池30中，缓存池30即为该j个计算节点的共享缓存。
3)、读命中、写命中
由于缓存的大小一般是有限的，且远远小于外存的大小，因此缓存中能够存储的数据十分有限。
在读数据的场景中，实体发起的用于读数据的IO请求中携带有待读数据的逻辑地址。也即，用于读数据的IO请求中携带的逻辑地址为该IO请求要访问的逻辑地址。
当缓存中存在与IO请求所携带逻辑地址对应数据时，则IO请求在缓存中读命中。
当缓存中不存在与IO请求所携带逻辑地址对应的数据时，则表示用于读数据的IO请求在缓存中未命中到待读数据，即缓存缺失(miss)发生。进而，缓存缺失可以触发向缓存的后端(如外存)读取IO请求所请求读取的待读数据，并将从后端读取到的待读数据缓存于缓存中。
可见，当IO请求在缓存中读命中时，则无需从后端读取待读数据，从而能够提高实体的响应速度。
在写数据的场景中，实体发起的用于写数据的IO请求中携带有待写数据和用于存储待写数据的逻辑地址。也即，用于写数据的IO请求中携带的逻辑地址为该IO请求要访问的逻辑地址。
当缓存中存在与IO请求所携带逻辑地址对应的物理地址，表示该逻辑地址在本次IO请求之前已经被写入数据，且缓存于缓存中，但还未从缓存刷入外存。这种情况下，称用于写数据的IO请求在缓存中命中到存储待写数据的逻辑地址，简称为IO请求在缓存中写命中。进而，缓存可以基于本次IO请求携带的待写数据更新缓存中已写入该逻辑地址的数据，并在后续将更新后的数据刷入外存。
当缓存中不存在与IO请求所携带逻辑地址对应的物理地址，表示该逻辑地址在本次IO请求之前还未被写入数据，或者该逻辑地址在本次IO请求之前已被写入数据，且写入的数据已由缓存刷入外存。这种情况下，称用于写数据的IO请求在缓存中未命中到存储待写数据的逻辑地址，简称为IO请求在缓存中未写命中。进而，缓存为本次接收到的IO请求中携带的逻辑地址分配对应的物理地址，并将本次IO请求携带待写数据写入该物理地址，从而实现对待写数据的缓存。
可见，当IO请求在缓存中写命中时，能够实现在缓存中对逻辑地址中已写入的数据进行更新，从而能够减少缓存向外存刷入数据的次数，进而能够节省缓存和外存之间的带宽。
4)、淘汰算法
在读数据场景中，当IO请求在缓存中未命中到待读数据，则需要从缓存的后端(如外存)读取数据到缓存。例如，对于CPU中的三级缓存，当CPU中的三级缓存发生缓存缺失，则需要从CPU所在计算设备的内存中读取数据到CPU的三级缓存。又例如，对于内存而言，当内存发生缓存缺失，则需要从内存所在设备的外存读取数据到内存。
如果缓存中的空闲空间不足以存储从后端读取到的数据，则需要对缓存内现存的数据进行淘汰(例如删除部分或全部数据，或将部分或全部数据标记为无效等)，从而为从后端新读取到的数据提供存储空间。其中，用于确定缓存内现存数据中需要被淘汰的数据的算法，即为淘汰算法。
一般的，淘汰算法基于IO请求访问数据时的访问规律(如访问数据的频率等)设计的，从而通过在缓存中应用淘汰算法，能够将高价值的数据尽可能久的保留在缓存中，而将低价值的数据淘汰出去，这样能够提高用于读数据的IO请求在缓存中读命中的命中率，从而提高缓存性能。
在写数据场景中，缓存中缓存的数据会定期的刷入外存中，或者在缓存中缓存的数据超过一定数量时，将当前缓存的数据刷入外存中。这种情况下，可以将后续更新频率可能较低的一些数据刷入外存，而将后续更新频率可能较高的数据保留在缓存中。这样，能够提高后续IO请求的在缓存中写命中的命中率，从而减少缓存向外存刷入数据的次数。这里，在缓存中确定哪些数据需要被刷入外存时用到的算法，即为淘汰算法。
5)、缓存性能
缓存性能一般可以通过命中率或缺失率来评价。
在读写缓存分离的场景(即读缓存和写缓存通过物理或软件方式互相隔离)中，读命中的命中率为：一段时间内IO请求在缓存中读命中的次数和这段时间内的全部IO读请求数量的比值。读数据场景下的缺失率：一段时间内IO请求在缓存中发生缓存缺失的次数和这段时间内的全部IO读请求数量的比值。写命中的命中率为：一段时间内IO请求在缓存中写命中的次数和这段时间内的全部IO写请求数量的比值。写数据场景下的缺失率为：一段时间内IO请求在缓存中未写命中的次数和这段时间内的全部IO写请求数量的比值。
在读写缓存融合的场景(即读数据和写数据公用缓存空间)中，命中率为：一段时间内IO请求在缓存中读命中的次数和这段时间内IO请求在缓存中写命中的次数之和，和这段时间内的全部IO请求数量的比值。缺失率为：一段时间内IO请求在缓存中发生缓存缺失的次数和这段时间内IO请求在缓存中未写命中的次数之和，和这段时间内的全部IO请求数量的比值。
可以理解，缓存性能除了与缓存中应用的淘汰算法相关，还与缓存本身的大小相关。因此在实际中，一般通过缓存的缺失率曲线(miss rate curve，MRC)或缓存的命中率曲线(hit rate curve，HRC)来表征缓存性能。其中，MRC为缓存大小和缺失率的对应关系曲线，用于描述在一种淘汰算法下，缓存在不同大小时，IO请求在缓存中的缺失率。HRC为缓存大小和命中率的对应关系曲线，用于描述在一种淘汰算法下，缓存在不同大小时，IO请求在缓存中的命中率。
6)、重用距离
对于实体发起的IO请求，IO请求的重用距离用于指示在连续两次访问该IO请求所携带逻辑地址的间隔期间，其他IO请求访问的不同逻辑地址的数量。
其中，IO请求的重用距离可以通过不同逻辑地址的数量来表征。具体而言，对于一段时间内实体发起的多个IO请求中的任意一个IO请求(例如第一IO请求)而言，第一IO请求的重用距离为：在实体发起的多个IO请求中，时序上位于第一IO请求与另一个IO请求之间的IO请求所访问的不同逻辑地址的数量。其中，该另一个IO请求为时序上前一个访问第一IO请求所携带逻辑地址的IO请求。
作为示例，假设实体在一段时间内发起的IO请求包括10个IO请求，且这10个IO请求在时序上依次访问的逻辑地址分别为(a，b，c，d，a，d，a，c，b，a)。其中，每个字母表示一个逻辑地址。
则对于上述10个IO请求中的第1个IO请求，该IO请求携带的逻辑地址为a。由于上述10个IO请求中在第1个IO请求之前没有访问逻辑地址a的IO请求。因此，第1个IO请求的重用距离通常默认为无穷大(符号为∞)。类似的，对于上述10个IO请求中的第2个IO请求、第3个IO请求以及第4个IO请求，第2个IO请求、第3个IO请求以及第4个IO请求的重用距离均为无穷大。
对于上述10个IO请求中的第5个IO请求，该IO请求携带的逻辑地址为a。由于上述10个IO请求中在第5个IO请求之前存在访问逻辑地址a的IO请求，且前一个访问逻辑地址a的IO请求为上述10个IO请求中的第1个IO请求，以及时序上位于第5个IO请求和第1个IO请求之间的IO请求访问的不同逻辑地址的数量为3(包括第2个IO请求访问的逻辑地址b，第3个IO请求访问的逻辑地址c，以及第4个IO请求访问的逻辑地址d)。因此，第5个IO请求的重用距离为3。类似的，对于上述10个IO请求中的第6个IO请求，第6个IO请求的重用距离为1。以及，对于上述10个IO请求中的第7个IO请求，第7个IO请 求的重用距离为1。
对于上述10个IO请求中的第8个IO请求，该IO请求携带的逻辑地址为c。由于上述10个IO请求中在第8个IO请求之前存在访问逻辑地址c的IO请求，且前一个访问逻辑地址c的IO请求为上述10个IO请求中的第3个IO请求，以及时序上位于第8个IO请求和第3个IO请求之间的IO请求访问的不同逻辑地址的数量为2(包括第4个IO请求和第6个IO请求访问的逻辑地址d，以及第5个IO请求和第7个IO请求访问的逻辑地址a)。因此，第8个IO请求的重用距离为2。类似的，对于上述10个IO请求中的第9个IO请求，第9个IO请求的重用距离为3。以及，对于上述10个IO请求中的第10个IO请求，第10个IO请求访问的重用距离为2。
7)、重用时间
重用时间用于指示相邻两次访问同一个逻辑地址的时间间隔。因此，重用时间可以称为逻辑地址的重用时间。
通常，逻辑地址的重用时间可以通过IO请求的个数来表征。具体而言，对于实体在一段时间内发起的多个IO请求中的任意一个IO请求(例如第一IO请求)而言，第一IO请求所携带逻辑地址的重用时间为：在实体发起的多个IO请求中，时序上位于第一IO请求和另一个IO请求之间的IO请求的数量。其中，该另一个IO请求为时序上前一个访问第一IO请求所携带逻辑地址的IO请求。
作为示例，假设实体在一段时间内发起的IO请求包括10个IO请求，且这10个IO请求在时序上依次访问的逻辑地址是(a、b、d、c、b、d、a、a、c、d)。其中，每个字母表示一个逻辑地址。
则对于上述10个IO请求中的第1个IO请求，该IO请求访问的逻辑地址为a，且上述10个IO请求中在第1个IO请求之前不存在访问逻辑地址a的IO请求。因此，第1个IO请求访问的逻辑地址a的重用时间通常默认为无穷大。类似的，对于上述10个IO请求中的第2个IO请求、第3个IO请求以及第4个IO请求，第2个IO请求访问的逻辑地址b、第3个IO请求访问的逻辑地址d、以及第4个IO访问的逻辑地址c的重用时间均为无穷大。
对于上述10个IO请求中的第5个IO请求，该IO请求访问的逻辑地址为b。由于上述10个IO请求中在第5个IO请求之存在访问逻辑地址b的IO请求，且前一个访问逻辑地址b的IO请求为上述10个IO请求中的第2个IO请求，以及时序上在第5个IO请求和第2个IO请求之间存在2个IO请求(包括第3个IO请求和第4个IO请求)。因此，第5个IO请求访问的逻辑地址b的重用时间为2。类似的，对于上述10个请求中的第6个IO请求，第6个IO请求访问的逻辑地址d的重用时间为2。对于上述10个请求中的第7个IO请求，第7个IO请求访问的逻辑地址a的重用时间为5。对于上述10个请求中的第8个IO请求，第8个IO请求访问的逻辑地址a的重用时间为0。对于上述10个请求中的第9个IO请求，第9个IO请求访问的逻辑地址c的重用时间为4。对于上述10个请求中的第10个IO请求，第10个IO请求访问的逻辑地址d的重用时间为3。
8)、其他术语
在本申请的实施例中，术语“第一”、“第二”并不是表示顺序关系，而是为了区别不同的对象，以下文件中提到的第一、第二等也是为了区别不同的报文等，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
还应理解，在本申请的各个实施例中，各个过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成 任何限定。
为避免缓存的竞争，通常可以对共享缓存进行分区，从而不同类别的IO请求所请求读取的数据缓存于缓存的不同分区中。其中，不同类别的IO请求例如是有不同实体发起的IO请求，对此不作限定。然而，当前在共享缓存中划分缓存的分区时，通常是基于一段时间内IO请求访存数据时的访存规律(如访问数据的频率等)人为的指定分区大小，或者是采用简单的启发式策略(例如不同类别的IO请求的优先级)确定缓存的分区大小，而这样划分的缓存的分区一般只能保证一段时间内的缓存性能，而不能保证长期的缓存性能。另外，整个共享缓存使用同样的淘汰算法，从而导致共享缓存的性能不佳。
基于此，本申请实施例提供一种共享缓存的管理方法，该方法先确定出多个类别中每个类别的IO请求访问共享缓存的访问特性，并根据确定出的多个类别中每个类别的IO请求的访问特性和共享缓存的命中率，确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法。进而，将确定出的每个类别的IO请求在共享缓存中的分区大小及淘汰算法应用于共享缓存。其中，每个类别的IO请求的访问特性为多个类别中每个类别的IO请求分别在多个淘汰算法下的命中率与缓存大小的关系。通过该方法，可以针对每个类别的IO请求的访问特性为每个类别的IO请求设置缓存大小及淘汰算法，从而提高了共享缓存的性能。
此外，当周期性的执行上述方法时，能够及时的根据周期性确定的多个类别中每个类别的I/O请求访问共享缓存的访问特性，定期调整每个类别的IO请求在共享缓存中的分区大小及淘汰算法，从而能够在时间维度上持续的保证共享缓存的缓存性能。
本申请实施例还提供一种共享缓存的管理装置，该管理装置应用于计算设备，该计算设备通过执行本申请实施例提供的方法，能够实现对共享缓存的管理。共享缓存的详细说明可以参考上文术语中的描述，不再赘述。作为示例，该计算设备可以是通用计算机、笔记本电脑、平板电脑、手机、车载终端等任意计算设备。
可选的，上述计算设备可以是任意包括共享缓存的计算设备。示例性的，该计算设备为具有图1所示CPU的计算设备。再示例性，该计算设备可以是包括共享缓存的服务器或缓存节点(例如图2所示的缓存节点)。又示例性的，该计算设备可以是如图3所示的包括共享缓存的任一个节点等，不限于此。可以理解，当计算设备可以是如图3所示的包括共享缓存的任一个节点，则该节点可以通过与图3中其他包括有共享缓存的节点的交互，来获取执行本申请实施例所提供方法中需要的数据(如IO请求)，并基于获取到的数据执行本申请实施例下文所述的方法。
可选的，上述计算设备也可以是与包括有共享缓存的节点连接通信的计算设备。作为示例，当包括有共享缓存的节点是图3所示的为缓存池提供缓存的节点，则该计算设备可以是独立于为缓存池提供缓存的节点的独立节点，如管理节点，对此不作限定。这种情况下，该计算设备可以通过与为缓存池提供缓存的节点的交互，来获取执行本申请实施例所提供方法中需要的数据(如IO请求)，并基于获取到的数据执行本申请实施例下文所述的方法。
参考图4，图4示出了本申请实施例提供的一种计算设备的硬件结构示意图。如图4所示，计算设备40包括处理器401、存储器402、通信接口403以及总线404。处理器401、存储器402、通信接口403之间通过总线404连接。
处理器401是计算设备40的控制中心，可以是一个通用CPU，处理器401还可能是其他通用处理器、数字信号处理器(digital signal processing，DSP)、专用集成电路(application-specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件、图形 处理器(graphics processing unit，GPU)、神经网络处理单元(neural processing unit，NPU)、张量处理器(tensor processing unit，TPU)或人工智能(artificial intelligent)芯片、数据处理器(data processing unit，DPU)等。
作为一个示例，处理器401包括一个或多个CPU，例如图4中所示的CPU 0和CPU 1。此外，本申请并不限定每个处理器中处理器核的个数。
存储器402用于存储程序指令或应用进程所要访问的数据，处理器401可以通过执行存储器402中的程序指令，以实现本申请实施例提供的共享缓存的管理方法。
存储器402包括易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、DRAM、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data date SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。非易失性存储器可以是储存级内存(storage class memory，SCM)、固态硬盘(solid state drive，SSD)、机械硬盘(hard disk drive，HDD)等。其中，储存级内存例如可以是非易失性内存(non-volatile memory，NVM)、相变化内存(phase-change memory，PCM)、持久化内存等。
在一种可能的实现方式中，存储器402独立于处理器401存在。存储器402通过总线404与处理器401相连接，用于存储数据、指令或者程序代码。处理器401调用并执行存储器402中存储的指令或程序代码时，能够实现本申请实施例提供的共享缓存的管理方法。
在另一种可能的实现方式中，存储器402和处理器401集成在一起。
通信接口403，用于计算设备40与其他设备(如图2或图3中所示计算节点等)通过通信网络连接，所述通信网络可以是以太网，无线接入网(radio access network，RAN)，无线局域网(wireless local area networks，WLAN)等。通信接口403包括用于接收数据/报文的接收单元，以及用于发送数据/报文的发送单元。
总线404，可以是工业标准体系结构(industry standard architecture，ISA)总线、外部设备互连(peripheral component interconnect，PCI)总线、高速串行计算机扩展总线(peripheral component interconnect express，PCIe)、计算快速链路(compute express link，CXL)或扩展工业标准体系结构(extended industry standard architecture，EISA)总线等。该总线可以分为地址总线、数据总线、控制总线等。为便于表示，图4中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
需要指出的是，图4中示出的结构并不构成对计算设备40的限定，除图4所示部件之外，该计算设备40包括比图4所示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
下面结合附图，对本申请实施例提供的共享缓存的管理方法进行详细描述。
在本申请实施例中，共享缓存用于缓存多个实体发起的IO请求所请求操作(例如读取或写入)的数据。在下文中，以该多个实体发起的IO请求对应K个类别，共享缓存对应N个淘汰算法为例进行说明。也即，该多个实体发起的IO请求包括K个类别的IO请求，且共享缓存预配有N个淘汰算法。其中，K和N分别是大于1的整数。
还应理解，每个IO请求中均携带有一个逻辑地址，该逻辑地址即为IO请求要访问的逻辑地址。例如，IO请求读取自身携带的逻辑地址中存储的待读数据，或者，IO请求向自身携带的逻辑地址中写入待写数据。因此，在本申请实施例下文中，IO请求携带的逻辑地址和IO请求访问的逻辑地址可以互换使用。
实施例一
在共享缓存的读写缓存分离的场景中，本申请实施例提供的共享缓存的管理方法可以用于管理共享缓存中的读缓存，或者用于管理共享缓存中的写缓存。其中，共享缓存的读写缓存分离是指共享缓存中的读缓存和写缓存通过物理或软件方式进行隔离。读缓存用于缓存实体发起的IO请求所请求读取的数据。写缓存用于缓存实体发起的IO请求写入的数据。
参考图5，图5示出了本申请实施例提供的一种共享缓存的管理方法的流程示意图。可选的，该方法可以应用于图1所示的CPU中，或者应用于图2所示的缓存节点中，或者应用于图3所示的节点中。该方法可以由具有图4所示硬件结构的计算设备执行，该方法包括以下步骤。
S101、获取由多个实体发起的IO请求，并确定每个IO请求的类别。其中，由多个实体发起的IO请求包括K个类别的IO请求。
其中，由于计算设备执行本申请实施例提供的共享内存的管理方法的流程，与实体发起的IO请求访问共享缓存的流程是并行进行的。因此，在多个实体发起的IO请求访问共享缓存的过程中，计算设备获取该多个实体发起的用于访问共享缓存IO请求的副本。从而计算设备获取到多个实体发起的IO请求，且这些IO请求为包括K个类别的IO请求。
作为示例，结合图2，参考图6，图6示出了一种实体发起的IO请求访问共享缓存的示意图。如图6所示，缓存节点2中包括共享缓存，且j个计算节点(包括计算节点1、计算节点2、计算节点3、…、以及计算节点j)均能访问缓存节点2的共享缓存。并且，缓存节点2中的共享缓存还与缓存节点2的后端存储(后端存储可以位于缓存节点2内部，也可以位于缓存节点2外部)通信。这样的话，在写数据的场景下，共享缓存可以定期将j个计算节点通过IO请求写入共享缓存的数据刷入后端存储中。在读数据的场景下，共享缓存可以预先将后端存储的数据加载到自身的存储空间中，以便j个计算节点后续通过IO请求读取这些数据。以及，当j个计算节点通过用于读数据的IO请求访问共享缓存时，共享缓存发生缓存缺失，则共享缓存可以从后端存储加载待读数据，以便j个计算节点读取待读数据。在本申请实施例中，计算设备在j个计算节点通过IO请求访问共享缓存的过程中，获取j个计算节点所发起的用于访问共享缓存IO请求的副本，以用于执行本申请实施例提供的方法。
需要说明，当本申请实施例提供的方法用于管理共享缓存中的读缓存时，计算设备在S101获取的IO请求为用于读数据的IO读请求。当本申请实施例提供的方法用于管理共享缓存中的写缓存时，计算设备在S101获取的IO请求为用于写数据的IO写请求。
进一步，计算设备确定获取到的每个IO请求的类别。
一种可能的实现方式中，实体发起的IO请求中携带有标识该IO请求所属类别的类别标记。这样，计算设备根据获取到的IO请求中每个IO请求所携带的类别标记，确定每个IO请求的类别。
可选的，IO请求中携带的类别标记可以是实体发起IO请求时在IO请求中添加的类别标记。这种情况下，IO请求中携带的类别标记可以用于指示发起该IO请求的实体。也就是说，IO请求的类别是按照发起IO请求的实体来划分的。这样的话，K个类别的IO请求对应K个实体，且由同一个实体发起的IO请求具有相同的类别标记，即由相同实体发起的IO请求属 于同一类别。其中，实体可以是不同的应用，不同的处理核、或者访问共享缓存的不同计算节点、客户端设备等，对此不作限定。
另一种可能的实现方式中，计算设备可以通过分类器确定获取到的每个IO请求的类别，该分类器用于将IO请求分为K个类别的IO请求，并具体用于将携带有较高相似度的逻辑地址的IO请求分为一个类别。其中，分类器是预先基于一定数量的IO请求访问逻辑地址的特征生成的。计算设备预先基于一定数量的IO请求访问逻辑地址的特征生成分类器的详细说明，参考下文描述，这里不再赘述。
具体的，计算设备依次将获取到的每个IO请求所携带的逻辑地址输入分类器中，分类器即可输出指示每个IO请求类别的类别标识。
可选的，计算设备在通过分类器确定IO请求的类别后，为IO请求添加指示其类别的类别标识。
S102、确定K个类别中每个类别的IO请求访问共享缓存的访问特性，该访问特性为K个类别中每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系。
其中，N个淘汰算法是共享缓存预配的淘汰算法，也即，共享缓存对应有N个淘汰算法。
其中，计算设备为每个类别的IO请求预设有X个缓存大小，对于一个类别的IO请求(如第一类IO请求)而言，该X个缓存大小是为与第一类IO请求对应的缓存预设的X个缓存大小。与第一类IO请求对应的缓存，即为共享缓存中用于缓存第一类IO请求所请求读取数据的分区，与第一类IO请求对应的缓存的缓存大小，即为共享缓存中用于缓存第一类IO请求所请求读取数据的分区大小。可以理解，计算设备为每个类别的IO请求预设的缓存大小，小于共享缓存的大小。
应理解，本申请实施例对计算设备为每个类别的IO请求预设X个缓存大小的规律，以及X个缓存大小之间的大小间隔不作具体限定。
作为示例，计算设备为第一类IO请求预设3个缓存大小，假设共享缓存的大小为4M，则计算设备为第一类IO请求预设的3个缓存大小可以为1M、2M以及3M。
可选的，上述计算设备为K个类别中每个类别的IO请求预设的缓存大小的数量可以均为X个，即计算设备为K个类别中每个类别的IO请求预设的缓存大小的数量相同。当然，计算设备为K个类别中每个类别的IO请求预设的缓存大小的数量也可以不同。例如，计算设备为K个类别中的第一类IO请求预设的缓存大小的数量为3，计算设备为K个类别中的第二类IO请求预设的缓存大小的数量为4，等等。其中，第二类IO请求为K个类别中除第一类别外的任意一个类别的IO请求。
为简单描述，本申请实施例在下文中，以计算设备为K个类别中每个类别的IO请求预设的缓存大小的数量均为X个为例进行说明。
可选的，上述访问特性所表征的K个类别中每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系，可以通过K个类别中每个类别的IO请求分别在N个淘汰算法下在共享缓存的HRC来表征。或者，上述访问特性所表征的K个类别中每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系，可以通过K个类别中每个类别的IO请求分别在N个淘汰算法下在共享缓存的MRC来表征，本申请实施例对此不作限定。
具体的，计算设备基于获取到的K个类别中每个类别的IO请求，确定N个淘汰算法下每个类别的IO请求在不同大小的缓存中的命中率后，即得到K个类别中每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系，也即得到K个类别中每个类别的IO请求访问共享缓存的访问特性。
其中，计算设备基于获取到的K个类别中每个类别的IO请求，确定K个类别中每个类别的IO请求访问共享缓存的访问特性的过程，可以通过下述可能的实现方式实现。
第一种可能的实现方式中，计算设备通过在共享缓存中模拟得到N个淘汰算法下每个类别的IO请求在不同大小的缓存中的命中率，从而得到每个类别的IO请求分别在N个淘汰算法下的命中率和缓存大小的关系，例如，得到每个类别的IO请求分别在N个淘汰算法下的HRC或MRC。
具体的，计算设备可以通过在共享缓存中缩比例的模拟N个淘汰算法下每个类别的样本IO在不同大小的缓存中的命中率，从而得到每个类别的样本IO分别在N个淘汰算法下的命中率和缓存大小的关系，例如，得到每个类别的样本IO分别在N个淘汰算法下的HRC或MRC。进而，计算设备将每个类别的样本IO分别在N个淘汰算法下的命中率和缓存大小的关系，确定为每个类别的IO请求分别在N个淘汰算法下的命中率和缓存大小的关系。例如，计算设备将每个类别的样本IO分别在N个淘汰算法下的HRC，确定为每个类别的IO请求分别在N个淘汰算法下的HRC。或者，计算设备将每个类别的样本IO分别在N个淘汰算法下的MRC，确定为每个类别的IO请求分别在N个淘汰算法下的MRC。
其中，每个类别的样本IO为计算设备基于在S101中获取到的K个类别中每个类别的IO请求中采样得到的IO请求，具体采样过程参考下文描述，这里不作赘述。
其中，计算设备在共享缓存中缩比例的模拟N个淘汰算法下每个类别的样本IO在不同大小的缓存中的命中率，从而得到每个类别的样本IO分别在N个淘汰算法下的命中率和缓存大小的关系的过程的详细说明，可以参考下文描述，这里不再赘述。
第二种可能的实现方式中，计算设备根据每个类别的IO请求中每个IO请求的重用距离及不同的缓存大小，确定N个淘汰算法下每个类别的IO请求在不同大小的缓存中的命中率，从而得到每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系。
例如，对于K个类别的IO请求中的第一类IO请求和N个淘汰算法中的第一淘汰算法，计算设备可以根据第一类IO请求中每个IO请求的重用距离及不同的缓存大小，确定第一类IO请求在不同大小的缓存中应用第一淘汰算法时的命中率，从而得到第一类IO请求在第一淘汰算法下的命中率与缓存大小的关系。其中，第一淘汰算法是N个淘汰算法中的任意一个淘汰算法。
可选的，为节省计算设备的计算资源和效率，计算设备可以根据每个类别的样本IO中每个样本IO的重用距离及不同的缓存大小，确定N个淘汰算法下每个类别的样本IO在不同大小的缓存中的命中率，从而得到每个类别的样本IO分别在N个淘汰算法下的命中率与缓存大小的关系。进而，计算设备将每个类别的样本IO分别在N个淘汰算法下的命中率与缓存大小的关系，确定为每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系。其中，每个类别的样本IO即为计算设备基于在S101中获取到的K个类别中每个类别的IO请求中采样得到的IO请求。
例如，对于第一类样本IO和第一淘汰算法，计算设备可以根据第一类样本IO中每个样本IO的重用距离及不同的缓存大小，确定第一类样本IO在不同大小的缓存中应用第一淘汰算法时的命中率，从而得到第一类样本IO在第一淘汰算法下的命中率与缓存大小的关系。然后，计算设备将第一类样本IO在第一淘汰算法下的命中率与缓存大小的关系，近似的确定为第一类IO请求在第一淘汰算法下的命中率与缓存大小的关系。其中，样本IO的重用距离的详细说明，可以参考上文术语中重用距离的详细描述，这里不再赘述。
其中，计算设备根据第一类样本IO中每个样本IO的重用距离及不同的缓存大小，确定 第一类样本IO在不同大小的缓存中应用第一淘汰算法时的命中率，从而得到第一类样本IO在第一淘汰算法下的命中率与缓存大小的关系的详细说明，可以参考下文描述，这里不再赘述。
可以看出，对于一个类别的IO请求而言，在一个淘汰算法下，计算设备可以确定出一组不同缓存大小和命中率的关系，即一条HRC或MRC。进而，对于一个类别的IO请求而言，在N个淘汰算法下，计算设备可以确定出N组缓存大小和命中率的关系，即N条HRC或MRC。进而，对于K个类别的IO请求，在N个淘汰算法下，计算设备可以确定出N×K组缓存大小和命中率的关系，即N×K条HRC或MRC。
需要说明，计算设备确定每个类别的样本IO分别在N个淘汰算法下的HRC或MRC时，可以均采用上述第一种可能的实现方式得到，或者均采用第二种可能的实现方式得到。当然，对于一部分类别的样本IO在一部分淘汰算法下的HRC或MRC，计算设备可以采用上述第一种可能的实现方式得到，而对于另一部分类别的样本IO在另一部分淘汰算法下的HRC或MRC，计算设备可以采用上述第二种可能的实现方式来确定，本申请实施例对此不作限定。
下面，对计算设备在S101获取的K个类别中每个类别的IO请求中采样得到每个类别的样本IO的的过程进行简单说明。
具体的，计算设备基于预设采样条件，在获取到的K个类别中每个类别的IO请求中进行采样，以得到每个类别的样本IO。其中，样本IO携带的逻辑地址满足预设采样条件。
其中，预设采样条件是基于预设采样率设计的采样条件。预设采样率是计算设备预设的，例如，预设采样率为0.01，即100个IO请求中采样一个样本IO。需要说明，当计算设备以根据预设采样率设计的预设采样条件在每个类别的IO请求中采样时，可以实现在每个类别的IO请求中采样的采样率为预设采样率。
作为示例，若预设采样率为L，满足预设采样条件的样本IO满足：样本IO携带的逻辑地址的哈希值除以系数A的余数，小于或等于预设采样率L和系数A的乘积。其中，逻辑地址的哈希值可以基于任意一种哈希算法对逻辑地址进行哈希后得到，本申请实施例对此不作限定。系数A为预设的系数，本申请实施例对A的取值不作限定。
需要说明，在一个类别的IO请求中，预设采样条件能够保证：当计算设备在这一类别的IO请求中采样到一个满足预设采样条件的样本IO，则这一类别的IO请求中与该样本IO所携带逻辑地址相同的IO请求，均可以被计算设备采样为样本IO。换句话说，预设采样条件能够保证：当计算设备在这一类别的IO请求中采样到一个满足预设采样条件的样本IO，则这一类别的IO请求中访问逻辑地址与该样本IO访问的逻辑地址相同的IO请求，均可以被计算设备采样为样本IO。因此，任意能够保证上述采样目的的采样条件，均应在本申请实施例的保护范围内。
具体的，对于K个类别中的任意一个类别的IO请求(如第一类IO请求)而言，计算设备判断第一类IO请求中的每个IO请求是否满足预设采样条件。若满足，则计算设备将满足预设采样条件的IO请求确定为样本IO。这样，计算设备可以在获取到的第一类IO请求中以预设采样率采样到多个样本IO。
作为示例，对于第一类IO请求中的任意一个IO请求(如第一IO请求)而言，计算设备先确定第一IO请求中携带的逻辑地址的哈希值，并进一步确定该哈希值除以系数A的余数Y，是否小于或等于预设采样率L和系数A的乘积P。当Y小于或等于P，则计算设备对第一IO请求进行采样，即将第一IO请求被确定为第一类IO请求的一个样本IO。
可以理解，在实际中，由于实体发起的IO请求访问共享缓存是实时进行的，因此计算设 备在这一过程中，每获取并确定一个IO请求的类别后，即判断该IO请求是否满足预设采样条件，以确定是否对其进行采样。
S103、根据K个类别中每个类别的IO请求的访问特性及共享缓存的命中率，确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法。
具体的，基于计算设备在S102确定的K个类别中每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系(即K个类别中每个类别的IO请求的访问特性)，计算设备可以确定每个类别的IO请求在每个淘汰算法下的X个缓存大小对应的X个命中率。这样，计算设备根据每个类别的IO请求在每个淘汰算法下的X个缓存大小对应的X个命中率，可以确定不同组合下K个类别的IO请求在共享缓存的命中率。这里，X个缓存大小的详细说明可以参考上文，这里不再赘述。
其中，不同组合是指每个类别的IO请求对应的不同缓存大小和不同淘汰算法的组合。例如，若计算设备预设的缓存大小包括X个，共享缓存预配的淘汰算法包括N个，因此一个类别的IO请求对应的组合包括X×N个组合。
应理解，基于计算设备在S102确定的K个类别中每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系(即K个类别中每个类别的IO请求的访问特性)可知，一个类别的IO请求在一个组合下，对应有该类别的IO请求在这个组合下的一个命中率。因此，计算设备根据每个类别的IO请求在任意一个组合下的命中率，可以得到K个类别的IO请求在共享缓存中的一个命中率。
具体的，对于K个类别的IO请求中的第一类IO请求而言，计算设备可以根据第一类IO请求在任意一个组合(如第一组合)下的命中率和第一类IO请求在K个类别的IO请求中的占比，确定第一组合下第一类IO请求在共享缓存中的命中率。示例性的，计算设备对第一类IO请求在第一组合下的命中率和第一类IO请求在K个类别的IO请求中的占比作乘积运算，从而得到第一组合下第一类IO请求在共享缓存中的命中率。例如，假设第一类IO请求在第一组合下的命中率为Z1，且第一类IO请求在K个类别的IO请求中的占比为R1，则第一组合下第一类IO请求在共享缓存中的命中率K1＝Z1×R1。
其中，第一类IO请求在K个类别的IO请求中的占比为计算设备根据第一类IO请求中IO请求的数量和K个类别的IO请求的总数确定的。可选的，计算设备可以在获取实体发起的K个类别的IO请求并确定每个IO请求的类别后，根据获取到的IO请求的总数和每个类别的IO请求的数量，确定每个类别的IO请求在K个类别的IO请求中的占比。
类似的，计算设备可以确定任意组合下每个类别的IO请求在共享缓存中的命中率。进而，计算设备对K个类别的IO请求分别在共享缓存中的K个命中率求和，即可得到K个类别的IO请求在共享缓存中的命中率。其中，用于求和的K个命中率分别为K个类别的IO请求分别在任意一个组合下在共享缓存中的命中率。例如，以K的取值为2为例，假设第一组合下第一类IO请求在共享缓存中的命中率为K1，第二组合下第二类IO请求在共享缓存的命中率为K2，则K个类别的IO请求在共享缓存中的命中率为：K1+K2。
需要说明，在计算设备对K个类别的IO请求分别在共享缓存中的K个命中率求和，以得到K个类别的IO请求在共享缓存中的命中率时，K个类别的IO请求的缓存大小之和，小于或等于共享缓存的大小。
进而，对于K个类别的IO请求，计算设备根据每个类别的IO请求分别在X×N个组合下的X×N个命中率，可以得到K个类别的IO请求在共享缓存中的(X×N)K个命中率。
作为示例，以K的取值为2，N的取值为2，X的取值为2为例，这种情况下，计算设 备获取的IO请求包括第1类IO请求和第2类IO请求，且第1类IO请求在2个类别的IO请求中的占比为R1，第2类IO请求在2个类别的IO请求中的占比为R2。共享缓存预配的淘汰算法包括第1淘汰算法和第2淘汰算法。计算设备为每个类别的IO请求预设的缓存大小包括缓存大小1和缓存大小2。并且，每个类别的IO请求对应有4个组合，这4个组合包括：由第1淘汰算法和缓存大小1构成的组合1、由第2淘汰算法和缓存大小1构成的组合2、由第1淘汰算法和缓存大小2构成的组合3、由第2淘汰算法和缓存大小2构成的组合4。这样的话，在第1类IO请求的缓存大小和第2类IO请求的缓存大小之和，小于或等于共享缓存的前提下，计算设备根据每个类别的IO请求在X×N(即2×2＝4)个组合下的命中率，可以计算得到2个类别的IO请求在共享缓存中的(X×N)K(即42＝16)个命中率，分别为：
2个类别的IO请求在共享缓存中的命中率1为：第1类IO请求在组合1下的命中率与R1的乘积(即组合1下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合1下的命中率与R2的乘积(即组合1下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率2为：第1类IO请求在组合1下的命中率与R1的乘积(即组合1下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合2下的命中率与R2的乘积(即组合2下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率3为：第1类IO请求在组合1下的命中率与R1的乘积(即组合1下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合3下的命中率与R2的乘积(即组合3下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率4为：第1类IO请求在组合1下的命中率与R1的乘积(即组合1下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合4下的命中率与R2的乘积(即组合4下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率5为：第1类IO请求在组合2下的命中率与R1的乘积(即组合2下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合1下的命中率与R2的乘积(即组合1下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率6为：第1类IO请求在组合2下的命中率与R1的乘积(即组合2下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合2下的命中率与R2的乘积(即组合2下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率7为：第1类IO请求在组合2下的命中率与R1的乘积(即组合2下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合3下的命中率与R2的乘积(即组合3下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率8为：第1类IO请求在组合2下的命中率与R1的乘积(即组合2下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合4下的命中率与R2的乘积(即组合4下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率9为：第1类IO请求在组合3下的命中率与R1的乘积(即组合3下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合1下的命中率与R2的乘积(即组合1下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率10为：第1类IO请求在组合3下的命中率与R1的乘积(即组合3下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合2下的命中率与R2的乘积(即组合2下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率11为：第1类IO请求在组合3下的命中率与R1的乘积(即组合3下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合3下 的命中率与R2的乘积(即组合3下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率12为：第1类IO请求在组合3下的命中率与R1的乘积(即组合3下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合4下的命中率与R2的乘积(即组合4下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率13为：第1类IO请求在组合4下的命中率与R1的乘积(即组合4下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合1下的命中率与R2的乘积(即组合1下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率14为：第1类IO请求在组合4下的命中率与R1的乘积(即组合4下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合2下的命中率与R2的乘积(即组合2下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率15为：第1类IO请求在组合4下的命中率与R1的乘积(即组合4下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合3下的命中率与R2的乘积(即组合3下第2类IO请求在共享缓存中的命中率)；
2个类别的IO请求在共享缓存中的命中率16为：第1类IO请求在组合4下的命中率与R1的乘积(即组合4下第1类IO请求在共享缓存中的命中率)+第2类IO请求在组合4下的命中率与R2的乘积(即组合4下第2类IO请求在共享缓存中的命中率)。
进一步，计算设备确定K个类别的IO请求在共享缓存中的最大命中率，并将获得最大命中率时每个类别对应的组合所指示的缓存大小，确定为每个类别的IO请求在共享缓存中的分区大小，以及将获得最大命中率时每个类别对应的组合所指示的淘汰算法，确定为每个类别的IO请求在共享缓存中的淘汰算法。
例如，假设上述的2个类别的IO请求在共享缓存中的命中率15为上述2个类别的IO请求在共享缓存中的最大命中率，则计算设备将获得最大命中率时第1类IO请求对应的组合4所指示的缓存大小2，确定为第1类IO请求在共享缓存中的分区大小，以及将获得最大命中率时第1类IO请求对应的组合4所指示的第2淘汰算法，确定为第1类IO请求在共享缓存中的淘汰算法。并且，计算设备将获得最大命中率时第2类IO请求对应的组合3所指示的缓存大小2，确定为第2类IO请求在共享缓存中的分区大小，以及将获得最大命中率时第2类IO请求对应的组合3所指示的第1淘汰算法，确定为第2类IO请求在共享缓存中的淘汰算法。
可选的，在一种可能的实现方式中，计算设备可以根据基于每个类别的IO请求在每个淘汰算法下确定的X个缓存大小对应的X个命中率，通过在公式(1)约束下求解下述公式(2)来确定出不同组合下K个类别的IO请求在共享缓存的最大命中率。

其中，m表示预设的缓存大小，m个数量为计算设备预设的X个，M表示共享缓存的大小，因此m的取值满足mε[0,M]。K表示IO请求的类别数量，或者理解为，K表示共享缓存中分区的数量。应理解，一个类别的IO请求对应共享缓存的一个分区，即共享缓存的一个分区用于缓存一个类别的IO请求的数据。i表示K个分区中的第i个分区，或者理解为，i表示K个类别的IO请求中的第i个类别的IO请求。mi表示共享缓存中第i个分区对应的缓 存大小。p表示淘汰算法，{P1，P2，...，PN}表示N个淘汰算法，pi表示第i个分区配置的淘汰算法，pi取{P1，P2，...，PN}中的任一个。Ri表示第i个类别的IO请求在全部IO请求中的占比。
进而，公式(1)表示K个类别的IO请求在共享缓存中的K个缓存大小的和，小于或等于共享缓存的大小。
公式(2)中的表示在淘汰算法pi下，第i个类别的IO请求在缓存大小为mi时的命中率，其中，mi和pi即为上述的一个组合。表示在mi和pi构成的组合下第i个类别的IO请求在共享缓存中的命中率。进而，公式(2)中的表示不同组合下K个类别的IO请求在共享缓存中的命中率。公式(2)中的argmax表示取的最大值，也即，argmax表示取不同组合下K个类别的IO请求在共享缓存中的最大命中率。
从而，通过在公式(1)约束下求解公式(2)，计算设备可以确定不同组合下K个类别的IO请求在共享缓存中的最大命中率，并将获得最大命中率时每个类别的IO请求对应的组合所指示的缓存大小，确定为每个类别的IO请求在共享缓存中的分区大小，以及将获得最大命中率时每个类别的IO请求对应的组合所指示的淘汰算法，确定为每个类别的IO请求在共享缓存中的淘汰算法。
在另一种可能的实现方式中，计算设备可以根据基于每个类别的IO请求在每个淘汰算法下确定的X个缓存大小对应的X个命中率，通过在公式(1)约束下求解下述公式(3)来确定出不同组合下K个类别的IO请求在共享缓存的最大命中率。
其中，m、M、K、i、mi、p、{P1，P2，...，PN}、pi、以及Ri的详细说明，可以参考上一种可能实现方式中的描述，这里不再赘述。
公式(3)中的表示在淘汰算法pi下，第i个类别的IO请求在缓存大小为mi时的缺失率，其中，mi和pi即为上述的一个组合。示在mi和pi构成的组合下第i个类别的IO请求在共享缓存中的缺失率。进而，公式(3)中的可表示不同组合下K个类别的IO请求在共享缓存中的缺失率。公式(3)中的argmin表示取的最小值，也即，argmin表示取不同组合下K个类别的IO请求在共享缓存中的最小缺失率。
从而，通过在公式(1)约束下求解公式(3)，计算设备可以确定不同组合下K个类别的IO请求在共享缓存中的最小缺失率。相应的，计算设备确定了不同组合下K个类别的IO请求在共享缓存中的最大命中率。这样，计算设备即可将获得最小缺失率时每个类别的IO请求对应的组合所指示的缓存大小，确定为每个类别的IO请求在共享缓存中的分区大小，以及将获得最小缺失率时每个类别的IO请求对应的组合所指示的淘汰算法，确定为每个类别的IO请求在共享缓存中的淘汰算法。
S104、将每个类别的IO请求在共享缓存中的缓存大小，配置为上述确定的每个类别的IO请求在共享缓存中的分区大小，以及将每个类别的IO请求在共享缓存中的淘汰算法，配置为上述确定的每个类别的IO请求在共享缓存中的淘汰算法。
具体的，计算设备在确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法后，将每个类别的IO请求在共享缓存中的缓存大小，配置为上述确定的每个类别的IO请求在共享缓存中的分区大小，以及将每个类别的IO请求在共享缓存中的淘汰算法，配置为上述确定的 每个类别的IO请求在共享缓存中的淘汰算法。
进而，在配置每个类别的IO请求在共享缓存中的缓存大小和淘汰算法后，实体发起的不同类别的IO请求即可在该配置下访问共享缓存。
具体的，在读数据场景下，对于实体发起的任一个类别的IO请求(如第一类IO请求)而言，在第一类IO请求在该配置下访问共享缓存的过程中，当共享缓存监控到第一类IO请求在共享缓存中所缓存的数据大小超过淘汰阈值，则根据为第一类IO请求在共享缓存中配置的淘汰算法对第一类IO请求在共享缓存中所缓存的数据进行淘汰。
在写数据场景下，对于实体发起的任一个类别的IO请求(如第一类IO请求)而言，在第一类IO请求在该配置下访问共享缓存的过程中，一种可能的实现方式为，当共享缓存监控到第一类IO请求在共享缓存中所缓存的数据大小超过淘汰阈值，则根据为第一类IO请求在共享缓存中配置的淘汰算法对第一类IO请求在共享缓存中所缓存的数据进行淘汰。另一种可能的实现方式为，共享缓存定期的根据淘汰算法对第一类IO请求在共享缓存中所缓存的数据进行淘汰。
综上，通过S101-S104所述的共享缓存的管理方法，能够根据每个类别的IO请求的访问特性，为每个类别的IO请求在共享缓存中确定对应的分区大小及缓存淘汰算法，以提高每个类别的IO请求的缓存性能，进而提高整个共享缓存中的缓存性能。
当S101-S104所述方法用于管理共享缓存中的读缓存时，基于本申请实施例所提供方法为每个类别的IO请求确定的分区大小和淘汰算法，能够提高IO读请求在共享缓存中的读命中率，从而能够提高数据读取效率。当S101-S104所述方法用于管理共享缓存中的写缓存时，基于本申请实施例所提供方法为每个类别的IO请求确定的分区大小和淘汰算法，能够提高IO写请求在共享缓存中的写命中率，进而能够节省共享缓存向后端存储单元刷盘的次数，也即节省了共享缓存和后端存储单元之间的数据传输带宽。
在一些实施例中，上述S101-S104所述的方法可以周期性的执行。这种情况下，计算设备在S101获取的IO请求，即为计算设备在一个周期(例如当前周期)内获取的由实体发起的IO请求。进而，计算设备基于获取的一个周期内的IO请求执行S102-S103，从而确定出每个类别的IO请求在共享缓存中的分区大小及淘汰算法。那么在S104，计算设备即可基于每个周期确定出每个类别的IO请求在共享缓存中的分区大小及淘汰算法周期性的配置共享缓存。换句话说，计算设备可以基于每个周期确定出每个类别的IO请求在共享缓存中的分区大小及淘汰算法周期性的调整共享缓存的每个分区大小及其对应的淘汰算法。
需要说明，在S101-S104所述的方法被第一次执行时，共享缓存中可以按照用户指定分区大小和淘汰算法进行配置，或者，共享缓存为池化式缓存，本申请实施例对此不作限定。
可见，当S101-S104所述的方法周期性执行时，根据计算设备周期性确定的K个类别中每个类别的IO请求在共享缓存中的缓存大小和淘汰算法，共享缓存可以定期调整每个类别的IO请求在共享缓存中的缓存大小和淘汰算法，从而实现了在时域上保证的IO请求在共享缓存的命中率，即在时域上保证了共享缓存的缓存性能。
下面，针对在第一类IO请求中采样得到的第一类样本IO，且以N个淘汰算法中的第一淘汰算法为例，通过示例对S102中“计算设备在共享缓存中缩比例的模拟N个淘汰算法下每个类别的样本IO在不同大小的缓存中的命中率，从而得到每个类别的样本IO分别在N个淘汰算法下的命中率和缓存大小的关系”的过程进行说明。
其中，第一类IO请求、第一类样本IO、以及第一淘汰算法的说明可以参考上文中的相关描述，这里不作赘述。
作为示例，假设计算设备为第一类IO请求预设的缓存大小的数量为3(即X取值为3)，且分别为1M、2M、以及3M，以及计算设备在第一类IO请求中采样的预设采样率L为0.01，则计算设备确定用于模拟第一类样本IO在不同大小的缓存中应用第一淘汰算法的命中率时，对应的缓存大小为0.01M(即1M×0.01)，0.02M(2M×0.01)、以及0.03M(3M×0.01)。这样，计算设备则在共享缓存中为第一类样本IO在共享缓存中申请大小为0.01M、0.02M以及0.03M的缓存(下文称为模拟缓存)，以分别用于模拟第一类样本IO在这三个缓存空间中应用第一淘汰算法时的命中率，从而能修得到第一类样本IO在缓存大小为0.01的缓存中应用第一淘汰算法的命中率、在缓存大小为0.02M的缓存中应用第一淘汰算法时的命中率、以及在缓存大小为0.03M的缓存中应用第一淘汰算法时的命中率，进而能够得到第一类样本IO在第一淘汰算法下的命中率和缓存大小的关系，即得到了第一类样本IO在第一淘汰算法下HRC。
以计算设备为第一类样本IO在共享缓存中申请缓存大小为0.01M的模拟缓存1为例，计算设备可以依次指示第一类样本IO中的每个样本IO访问模拟缓存1，并统计命中的样本IO的个数。
具体的，当模拟开始后，计算设备可以首先指示第一类样本IO中的第一个样本IO访问模拟缓存1，由于此时的模拟缓存1为空，因此计算设备将第一个样本IO的逻辑地址缓存于模拟缓存1中。接着，计算设备指示第一类样本IO中的第二个样本IO访问模拟缓存1，若第二个样本IO的逻辑地址和第一个样本IO的逻辑地址相同，则表示第二个样本IO在模拟缓存1中命中，若第二个样本IO的逻辑地址和第一个样本IO的逻辑地址不同，则表示第二个样本IO在模拟缓存1中未命中，这时，计算设备将第二个IO样本的逻辑地址缓存于模拟缓存1中。依此类推，计算设备指示第一类样本IO中的每个样本IO依次访问模拟缓存1，并统计命中的样本IO的个数。需要说明，计算设备还在模拟过程中监控为模拟缓存1中所存储逻辑地址的大小，当模拟缓存1中所存储逻辑地址的大小超过一定阈值，则通过第一淘汰算法将模拟缓存1中的逻辑地址淘汰一部分(例如删除一部分，或将一部分置为无效)。
进而，计算设备基于第一类样本IO的IO总数和命中的样本IO的个数，计算得到第一类样本IO在模拟缓存1中的命中率。类似的，计算设备模拟并统计第一类样本IO在缓存大小为0.02M的模拟缓存2中命中的样本IO的个数，并基于第一类样本IO的IO总数和命中的样本IO的个数，计算得到第一类样本IO在模拟缓存2中的命中率。以及，计算设备模拟并统计第一类样本IO在缓存大小为0.03M的模拟缓存3中命中的样本IO的个数，并基于第一类样本IO的IO总数和命中的样本IO的个数，计算得到第一类样本IO在模拟缓存3中的命中率。
这样，若计算设备为第一类IO请求预设有X个缓存大小，则计算设备可以确定第一类样本IO在应用第一淘汰算法时X个缓存大小对应的X个命中率。从而，计算设备得到第一类样本IO在第一淘汰算法下的命中率与缓存大小的关系，也即得到了第一类别的样本IO在第一淘汰算法下HRC。
可选的，计算设备也可以基于第一类样本IO的IO总数和命中的样本IO的个数，先确定未命中的样本IO的个数，进而根据第一类样本IO的IO总数和未命中的样本IO的个数，计算得到第一类样本IO在模拟缓存1中的缺失率。类似的，计算设备模拟并统计第一类样本IO在模拟缓存2中命中的样本IO的个数，并基于第一类样本IO的IO总数和命中的样本IO的个数，先确定未命中的样本IO的个数，进而根据第一类样本IO的IO总数和未命中的样本IO的个数，计算得到第一类样本IO在模拟缓存2中的缺失率。以及，计算设备模拟并统 计第一类样本IO在模拟缓存3中命中的样本IO的个数，并基于第一类样本IO的IO总数和命中的样本IO的个数，先确定未命中的样本IO的个数，进而根据第一类样本IO的IO总数和未命中的样本IO的个数，计算得到第一类样本IO在模拟缓存3中的缺失率。
这样，若计算设备为第一类IO请求预设有X个缓存大小，则计算设备可以确定第一类样本IO在应用第一淘汰算法时X个缓存大小对应的X个缺失率。从而，计算设备得到第一类样本IO在第一淘汰算法下的缺失率和缓存大小的关系，也即得到了第一类样本IO在第一淘汰算法下MRC。
需要说明，由于每次模拟开始时，计算设备为样本IO申请的模拟缓存为空，相当于缓存断电后重新启动(即缓存冷启动)后的状态。因此，计算设备在确定每个类别的样本IO的HRC后可以适当增大HRC曲线中的命中率，或者，在确定每个类别的样本IO的MRC后适当减小大MRC曲线中的缺失率，以用于补偿缓存冷启动带来的缓存缺失。应理解，本申请实施例中实际想要模拟的是缓存中缓存有数据时IO请求的命中率，而缓存一开始为空时模拟出的命中率，通常低于缓存中缓存有数据时的命中率。因此，本申请实施例对模拟出的HRC中的命中率或MRC中的缺失率予以补偿。
其中，本申请实施例对模拟出的HRC中的命中率或MRC中的缺失率作冷启动补偿的具体补偿值，可以由用于模拟HRC或MRC的每个类别的样本IO来确定。例如，本申请实施例可以将第一类样本IO开始在申请的模拟缓存中模拟时，预设时长内未命中的样本IO的个数，作为对模拟出的HRC中的命中率补偿或MRC中的缺失率的具体补偿值。这里，本申请实施例对该预设时长不作具体限定，以及对确定补偿值的具体方法也不作限定。
还需说明，实体发起的IO请求访问共享缓存时，可以采用数据预取机制。即实体会将未来一段时间可能访问的数据预先加载到共享缓存中。因此，当后续实体发起的IO请求访问预取的数据时，是必定会命中的。因此，预取机制下的IO请求的命中率高于未采用预取机制时IO请求的命中率。因此，计算设备在确定每个类别的样本IO的HRC后可以适当减小HRC曲线中的命中率，或者，在确定每个类别的样本IO的MRC后适当增大MRC曲线中的缺失率，以用于降低预取机制对IO请求命中率的影响。
其中，减小本申请实施例模拟出的HRC中的命中率的具体数值(或增大本申请实施例模拟出的MRC中的缺失率的具体数值)，可以为用于模拟HRC或MRC的每个类别的样本IO中访问预取数据的样本IO的个数。应理解，实体发起的IO请求访问预取的数据时，实体会在IO请求中标记预取标识，以指示该IO请求所访问的数据是预取的。因此，计算设备只需统计每个类别的样本IO中访问预取数据的样本IO的个数，即可确定降低模拟出的HRC中的命中率的具体数值(或增大本申请实施例模拟出的MRC中的缺失率的具体数值)。
类似的，计算设备可以模拟出第一类样本IO分别在N个淘汰算法下的命中率和缓存大小的关系，以及，模拟出每个类别的样本IO分别在N个淘汰算法下的命中率和缓存大小的关系。
进一步的，计算设备将模拟出的每个类别的样本IO分别在N个淘汰算法下的命中率和缓存大小的关系，确定为每个类别的IO请求分别在N个淘汰算法下的命中率和缓存大小的关系。例如，计算设备将每个类别的样本IO分别在N个淘汰算法下的HRC，确定为每个类别的IO请求分别在N个淘汰算法下的HRC。或者，计算设备将每个类别的样本IO分别在N个淘汰算法下的MRC，确定为每个类别的IO请求分别在N个淘汰算法下的MRC。
下面，对S102中“计算设备根据第一类样本IO中每个样本IO的重用距离及不同的缓存大小，确定第一类样本IO在不同大小的缓存中应用第一淘汰算法时的命中率，从而得到第 一类样本IO在第一淘汰算法下的命中率与缓存大小的关系”的详细过程予以说明。
具体的，计算设备可以基于第一类样本IO中每个样本IO所访问的逻辑地址，确定第一类样本IO中每个样本IO的重用距离。接着，在第一类样本IO中，计算设备统计每个样本IO的重用距离中相同重用距离的个数，也即统计每个重用距离的频率。
作为示例，假设第一类样本IO中包括10个样本IO，且这10个样本IO中依次访问的逻辑地址分别为(a，b，c，d，a，d，a，c，b，a)，且计算设备统计得到这10个样本IO中每个样本IO的重用距离分别为(∞，∞，∞，∞，3，1，1，2，3，2)。然后，计算设备基于这10个样本IO中每个样本IO的重用距离，统计相同重用距离的个数。其中，重用距离为∞的个数(即频率)为4，重用距离为1的个数(即频率)为2，重用距离为2的个数(即频率)为2，重用记录为3的个数为(即频率)2。
进一步，计算设备基于预设规则和统计到的第一类样本IO中相同重用距离的个数，确定不同缓存大小时第一类样本IO的命中率，从而得到第一类样本IO分别在第一淘汰算法下的命中率与缓存大小的关系。其中，预设规则是基于淘汰算法设计的，一种淘汰算法对应一种预设规则，N个淘汰算法对应N个预设规则。本申请实施例对与淘汰算法对应的预设规则的具体设计不作限定。
以第一淘汰算法是最近最少使用算法(least recently used，LRU)为例，对于第一类样本IO，与LRU对应的预设规则可以为：将小于预设数值的重用距离的个数，确定为在缓存大小为预设数值个样本IO所请求访问的数据大小时第一类样本IO的命中次数。这里，计算设备可以预先基于预设的X个缓存大小中每个缓存大小的取值和单个样本IO所访问数据的大小，确定出每个缓存大小对应的预设数值的取值。例如，X个缓存大小中的一个缓存大小为1M，且单个样本IO的大小为4K，则预设数值的取值＝1M/4K＝256。这样，计算设备可以确定第一类样本IO在应用第一淘汰算法时X个缓存大小对应的X个命中次数。其中，X个缓存大小的说明以参考上文描述，这里不再赘述。
其中，可选的，本申请实施例可以默认每个样本IO所访问的数据大小相同，例如均为4K，对此不作限定。这种情况下，计算设备中预设有单个样本IO所请求访问数据的大小。可选的，计算设备也可以根据第一类样本IO中所包括样本IO的数量和第一类样本IO所请求访问数据的总大小，确定出每个样本IO所请求访问数据的平均大小，并将该平均大小作为单个样本IO所请求访问数据的大小，本申请实施例对此不作限定。
作为示例，假设第一类样本IO中包括10个样本IO，且基于这10个样本IO中统计到的重用距离为∞的个数为4，重用距离为1的个数为2，重用距离为2的个数为2，重用距离为3的个数为2。
则如果预设数值的取值为1，则计算设备确定不存在将小于1的重用距离，因此计算设备确定在缓存大小为1个样本IO所请求访问数据的大小时，第一类样本IO的命中次数为0。
如果预设数值的取值为2，则计算设备可以将小于2的重用距离的个数2(即重用距离为1的个数2)，确定为在缓存大小为2个样本IO所请求访问数据的大小时，第一类样本IO的命中次数。
如果预设数值的取值为3，则计算设备可以将小于3的重用距离的个数4(即重用距离为1的个数2和重用距离为2的个数2的加和(即2+2))，确定为在缓存大小为3个样本IO所请求访问数据的大小时，第一类样本IO的命中次数。
如果预设数值的取值为4，则计算设备可以将小于4的重用距离的个数6(即重用距离为1的个数2、重用距离为2的个数2、以及重用距离为3的个数2的加和(即2+2+2))，确定 为在缓存大小为4个样本IO所请求访问数据的大小时，第一类样本IO的命中次数。
进而，基于不同的预设数值的取值、与LRU算法对应的预设规则、以及统计到的第一类样本IO中相同重用距离的个数，计算设备可以确定出LRU算法下第一类样本IO在不同缓存大小时的命中次数。进一步，计算设备基于确定的命中次数和第一类样本IO的数量，可以计算得到LRU算法下第一类样本IO在不同缓存大小时的命中率。这样，对于计算设备为第一类IO请求预设的X个缓存大小，计算设备确定出了第一类样本IO在应用LRU算法时X个缓存大小对应的X个命中率。从而，计算设备得到了第一类样本IO在LRU算法下的命中率与缓存大小的关系，也即得到了第一类样本IO在LRU算法下的HRC。
可选的，计算设备在确定出LRU算法下第一类样本IO在不同缓存大小时的命中次数后，可以基于第一类样本IO的总数和LRU算法下第一类样本IO在不同缓存大小时的命中次数，确定出LRU算法下第一类样本IO在不同缓存大小时的未命中的次数。进而，计算设备根据第一类样本IO的总数和LRU算法下第一类样本IO在不同缓存大小时的未命中的次数，计算得到LRU算法下第一类样本IO在不同缓存大小时的缺失率。这样，对于计算设备为第一类IO请求预设的X个缓存大小，计算设备确定出了第一类样本IO在应用LRU算法时X个缓存大小对应的X个命中率。从而，计算设备得到第一类样本IO在LRU算法下的缺失率与缓存大小的关系，也即得到了第一类样本IO在LRU算法下的MRC。
类似的，基于不同的预设数值的取值、与N个淘汰算法对应的N个预设规则、以及每个类别的样本IO中相同重用距离的个数，计算设备可以分别确定出N个淘汰算法下每个类别的样本IO在不同缓存大小时的命中次数(或未命中次数)。进一步，计算设备基于确定的命中次数(或未命中次数)和每个类别的样本IO的数量，可以计算得到N个淘汰算法下每个类别的样本IO在不同缓存大小时的命中率(或缺失率)。这样，计算设备即得到了每个类别的样本IO在分别在N个淘汰算法下的命中率与缓存大小的关系(或缺失率与缓存大小的关系)，也即得到了每个类别的样本IO分别在N个淘汰算法下的HRC(MRC)。
下面，对S101中“计算设备预先基于一定数量的IO请求访问逻辑地址的特征生成分类器”的过程予以说明。
具体的，在S101之前，本申请实施例提供的方法还包括图7所示的一种分类器的生成方法。如图7所示，在S101之前，本申请实施例提供的方法还包括S101a-S101d。
S101a、获取由多个实体发起的多个IO请求。
其中，计算设备获取该多个IO请求的说明可以参考S101中获取实体发起的IO请求的相关描述，不再赘述。
可选的，当上述S101-S104所述的方法是周期性执行的，以执行S101-S104所述方法的周期是第一周期为例，则在一种可能的实现方式中，计算设备在S101a获取的多个IO请求为计算设备在第一周期的第一时段内获取的多个IO请求。这种情况下，计算设备在S101获取的K个类别的IO请求为计算设备在第一周期的第二时段内获取的K个类别的IO请求。其中，第一时段是第一周期内从第一周期的起始时刻开始、且时长为预设时长的时段。第二时段为第一周期内除第一时段外的剩余时段。这里，本申请实施例对第一周期的时长以及预设时长的具体取值不作限定。
作为示例，假设第一周期为1小时，第一周期的起始时刻为10:00，且预设时长为10分钟，则第一时段为从10:00～10:10的时段，第二时段为10:11～11:00的时段。这样的话，计算设备在S101a获取的多个IO请求为计算设备在10:00～10:10内获取的多个IO请求，计算设备在S101获取的K个类别的IO请求为计算设备在10:11～11:00内获取的K个类别的IO请求。
在另一种可能的实现方式中，计算设备在S101a获取的多个IO请求为计算设备在第一周期内获取的全部IO请求中时序上的前预设数量个IO请求。这种情况下，计算设备在S101获取的K个类别的IO请求为计算设备在第一周期内获取的全部IO请求中除该预设数量个IO请求之外的IO请求。其中，本申请实施例对预设数量的具体取值不作限定。
作为示例，假设预设数量的取值为1000，且计算设备在第一周期内获取的全部IO请求包括10000个IO请求，则计算设备在S101a获取的多个IO请求为该10000个IO请求中时序上的前1000个IO请求，也即该10000个IO请求中时序上的第1个IO请求～第1000个IO请求。这样的话，计算设备在S101获取的K个类别的IO请求为该10000个IO请求中除第1个IO请求～第1000个IO请求外的9000个IO请求，也即该10000个IO请求中时序上的第1001个IO请求～第10000个IO请求。
S101b、提取上述多个IO请求访问逻辑地址的特征。
其中，该多个IO请求访问逻辑地址的特征包括该多个IO请求访问相同逻辑地址的访问频率，和/或，包括该多个IO请求所访问逻辑地址的重用时间。
可选的，在获取上述多个IO请求后，对于该多个IO请求中的任意一个IO请求所访问的逻辑地址(如第一逻辑地址)，计算设备在该多个IO请求中统计访问第一逻辑地址的IO请求的数量(如第一数量)。可以理解，第一数量即为上述多个IO请求访问第一逻辑地址的访问频率。进而，计算设备将确定的第一数量确定为上述多个IO请求中访问第一逻辑地址的每个IO请求的频率特征。
类似的，计算设备可以确定出上述多个IO请求中每个IO请求的频率特征。
可选的，计算设备在获取上述多个IO请求的过程中，可以每获取一个IO请求，即确定该IO请求所访问逻辑地址的重用时间。或者，计算设备也可以在获取上述多个IO请求后，确定该多个IO请求中每个IO请求所访问逻辑地址的重用时间。其中，重用时间的详细说明可以参考上文术语中的描述，不再赘述。
可以理解，对于上述多个IO请求，该多个IO请求中可能存在访问相同逻辑地址(如第一逻辑地址)的至少两个IO请求，且对于该至少两个IO请求，计算设备确定的第一逻辑地址的重用时间不同。也就是说，针对一个逻辑地址，计算设备可以确定出多个不同的重用时间。示例性的，对于时序上依次访问逻辑地址(a、b、d、c、b、d、a、a、c、d)的10个IO请求，这10个请求中的第3个IO请求访问的逻辑地址d的重用时间为无穷大，第6个IO请求访问的逻辑地址d的重用时间为2，第10个IO请求访问的逻辑地址d的重用时间为3。
这种情况下，计算设备可以在确定每个IO请求所访问逻辑地址的重用时间后，在相同逻辑地址的不同重用时间中选择一个重用时间，并将选择的重用时间作为访问该逻辑地址的每个IO请求的重用时间特征。
可选的，计算设备可以在相同逻辑地址的不同重用时间中任意选择一个重用时间，并将选择的重用时间作为访问该逻辑地址的每个IO请求的重用时间特征。其中，计算设备任意选择的重用时间为非无穷大的重用时间。或者，计算设备可以对确定出的相同逻辑地址的多个不同的重用时间求取均值(或求取均值后向上/向下取整)，并将求取的均值(或求取均值后取整的值)作为访问该逻辑地址的每个IO请求的重用时间特征。本申请对此不作限定。其中，用于求取均值的多个不同的重用时间为除取值为无穷大的重用时间之外的多个不同重用时间。
作为示例，对于时序上依次访问逻辑地址(a、b、d、c、b、d、a、a、c、d)的10个IO请求，由于这10个请求中的第3个IO请求访问的逻辑地址d的重用时间为无穷大，第6个 IO请求访问的逻辑地址d的重用时间为2，第10个IO请求访问的逻辑地址d的重用时间为3。则计算设备可以将2或3作为访问逻辑地址d的每个IO请求的重用时间特征。或者，计算设备对第6个IO请求访问的逻辑地址d的重用时间为2和第10个IO请求访问的逻辑地址d的重用时间为3求取平均并向上取整(即[(2+3)/2]向上取整)，并将求取平均后取整的值3作为访问逻辑地址d的每个IO请求的重用时间特征。
S101c、根据上述多个IO请求访问逻辑地址的特征，将该多个IO请求划分为K个类别的IO请求。
具体的，计算设备根据上述多个IO请求访问逻辑地址的特征和至少一个特征阈值，将该多个IO请求划分为K个类别的IO请求。其中，特征阈值包括频率阈值和/或重用时间阈值。
在一种可能的情况中，当上述多个IO请求访问逻辑地址的特征包括该多个IO请求访问相同逻辑地址的访问频率，则计算设备根据该多个IO请求中每个IO请求的频率特征和K-1个频率阈值，将该多个IO请求划分为K个类别的IO请求。需要说明，属于同一类别的IO请求所访问的逻辑地址之间具有较高的相似度。
可选的，该K-1个频率阈值可以是用户预设的频率阈值。或者，该K-1个频率阈值是计算设备根据第一预设算法，将S101b确定的多个频率划分为K个频率范围，该K个频率范围之间的K-1个临界频率即为K-1个频率阈值。其中，第一预设算法可以是任意的分类算法，本申请实施例对比不作限定。其中，频率特征属于一个频率范围的IO请求所访问的逻辑地址，具有较高的相似度。
在另一种可能的情况中，当上述多个IO请求访问逻辑地址的特征包括该多个IO请求所访问逻辑地址的重用时间，则计算设备根据该多个IO请求中每个IO请求的重用时间特征和K-1个重用时间阈值，将该多个IO请求划分为K个类别的IO请求。需要说明，属于同一类别的IO请求所访问的逻辑地址之间具有较高的相似度。
可选的，该K-1个重用时间阈值可以是用户预设的重用时间阈值。或者，该K-1个重用时间阈值是计算设备根据第二预设算法，将S101b确定的多个重用时间划分为K个重用时间范围，该K个重用时间范围之间的K-1个临界重用时间即为K-1个重用时间阈值。其中，第二预设算法可以是任意的分类算法，本申请实施例对比不作限定。其中，重用时间特征属于一个重用时间范围的IO请求所访问的逻辑地址，具有较高的相似度。
在又一种可能的情况中，当上述多个IO请求访问逻辑地址的特征包括该多个IO请求访问相同逻辑地址的访问频率，以及包括该多个IO请求所访问逻辑地址的重用时间，则计算设备根据该多个IO请求中每个IO请求的频率特征、p个频率阈值、该多个IO请求中每个IO请求的重用时间特征、以及q个重用时间阈值，将该多个IO请求划分为K个类别的IO请求。其中，p和q均为正整数，且p+q≤K-1。其中，频率阈值和重用时间阈值的详细说明可以参考上文描述，不再赘述。
可选的，对于计算设备在S101a获取的多个IO请求，计算设备可以先根据该多个IO请求中每个IO请求的重用时间特征和q个重用时间阈值，先将该多个IO请求划分为q+1个类别。进而，对于前述q+1个类别中至少一个类别的IO请求，计算设备根据该至少一个类别中每个IO请求的频率特征和p个频率阈值，将该至少一个类别中每个类别的IO请求划分为p+1个类别的IO请求，从而实现将该多个IO请求划分为K个类别的IO请求。需要说明，属于同一类别的IO请求所访问的逻辑地址之间具有较高的相似度。
作为示例，以p和q的取值均为1、K的取值为3为例，参考图8，对于计算设备在S101a获取的多个IO请求，计算设备可以先根据该多个IO请求中每个IO请求的重用时间特征和1 个重用时间阈值(如阈值1)，将该多个IO请求划分为第一类别的IO请求和第二类别的IO请求。其中，第一类别的IO请求为重用时间特征小于阈值1的IO请求，第二类别的IO请求为重用时间特征大于阈值1的IO请求。其中，本申请实施例对重用时间特征等于阈值1的情况不作限定，例如重用时间特征等于阈值1的IO请求可以为第一类别的IO请求，或者为第二类别的IO请求。
进而，对于第一类别的IO请求或第二类别的IO请求中的任一个类别的IO请求，如第二类别的IO请求，计算设备根据第二类别的IO请求中每个IO请求的频率特征和1个频率阈值(如阈值2)，将第二类别的IO请求划分为第三类别的IO请求和第四类别的IO请求。其中，第三类别的IO请求为频率特征小于阈值2的IO请求，第四类别的IO请求为频率特征大于阈值2的IO请求。其中，本申请实施例对频率特征等于阈值2的情况不作限定，例如频率特征等于阈值2的IO请求可以为第三类别的IO请求，或者为第四类别的IO请求。
这样，计算设备在S101a获取的多个IO请求即被划分为第一类别的IO请求、第三类别的IO请求以及第四类别的IO请求。
可选的，对于计算设备在S101a获取的多个IO请求，计算设备可以先根据该多个IO请求中每个IO请求的频率特征和p个频率阈值，先将该多个IO请求划分为p+1个类别。进而，对于前述p+1个类别中至少一个类别的IO请求，计算设备根据该多个IO请求中每个IO请求的重用时间特征和q个重用时间阈值，将该至少一个类别中每个类别的IO请求划分为q+1个类别，从而实现将该多个IO请求划分为K个类别的IO请求。需要说明，属于同一类别的IO请求所访问的逻辑地址之间具有较高的相似度。
S101d、根据划分为K个类别的多个IO请求生成分类器。
计算设备在将上述获取到的多个IO请求划分为K个类别的IO请求后，为每个IO请求标记类别标识，该类别标识用于指示IO请求所属的类别。
例如，计算设备将上述获取到的多个IO请求划分为2个类别的IO请求(包括类别1的IO请求和类别2的IO请求)。这样，计算设备为类别1中的每个IO请求标记指示类别1的标识1，并为类别2中的每个IO请求标记指示类别2的标识2。
进而，计算设备根据上述多个IO请求中每个IO请求的样本参数和第三预设算法，生成分类器。其中，一个IO请求的样本参数包括该IO请求的类别标识和该IO请求所携带的逻辑地址。其中，第三预设算法可以是任一种有监督学习的分类算法，本申请实施例对此不作限定。
可选的，第三预设算法可以是k临近算法(k-Nearest-Neighbor，KNN)，或者是KNN+prototype算法。其中，KNN+prototype算法相较于KNN算法更为简单。进而，计算设备可以将上述多个IO请求中每个IO请求的样本参数输入KNN(或KNN+prototype)，从而得到分类器。这样，当分类器接收到待分类的IO请求的逻辑地址时，可以先确定与该逻辑地址相似度最大的逻辑地址所在的样本参数，并将该样本参数中的类别标识输出，以用于指示待分类的IO请求的类别。
例如，在S101中，计算设备可以将获取到的IO请求1的逻辑地址1输入上述生成的分类器。这样，分类器确定与逻辑地址1具有最大相似度的逻辑地址为逻辑地址2。进而，分类器将逻辑地址2所在的样本参数1的类别标识1输出，以用于指示IO请求1的类别。
这样，基于S101a～S101d所述的方法，计算设备可以生成用于对IO请求进行分类的分类器。当S101-S104所述的方法是周期性执行时，计算设备基于当前周期内的一部分IO请求生成的分类器，可以用于对当前周期内的另一部分IO请求进行分类(例如分为K个类别)，从 而根据分类后的K个类别的IO请求访问共享缓存的访问特性，确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法。
此外，计算设备在当前周期内生成的分类器，可以用于对实体在当前周期的下一周期内发起的IO请求进行分类，从而使得分类后的IO请求访问与其对应的缓存。因此，基于S101a～S101d所述的方法，发起IO请求的实体无需为IO请求标记用于分类的类别标记，从而发起IO请求的实体的不会产生额外的资源开销。并且，由于本申请实施例提供的方法不会侵入缓存的上层(即发起IO请求的实体)，因此本申请实施例提供的方法能够适用于面向多样化客户的通用的缓存系统，而无需生态支持。
实施例二
本申请实施例提供的共享缓存的管理方法还可以应用于共享缓存中的读写缓存融合的场景。其中，共享缓存的读写缓存融合是指共享缓存中不区分读缓存和写缓存，用于读数据的IO请求和用于写数据的IO请求共用共享缓存。
在共享缓存中的读写缓存融合的场景下，参考图9，图9示出了本申请实施例提供的另一种共享缓存的管理方法的流程示意图。可选的，该方法可以应用于图1所示的CPU中，或者应用于图2所示的缓存节点中，或者应用于图3所示的节点中。该方法可以由具有图4所示硬件结构的计算设备执行，该方法包括以下步骤。
S201、获取由多个实体发起的IO请求，并确定每个IO请求的类别。其中，多个实体发起的IO请求包括K个类别的IO请求，K个类别中每个类别的IO请求包括IO读请求和IO写请求。
计算设备获取由多个实体发起的IO请求，并确定每个IO请求的类别的详细说明可以参考S101的描述，不再赘述。
需要说明，在S101中，计算设备获取的IO请求为用于读数据的IO读请求或用于写数据的IO写请求中的一种。而在S201中，计算设备获取的IO请求包括用于读数据的IO读请求和用于写数据的IO写请求。
S202、确定K个类别中每个类别的IO读请求访问共享缓存的读访问特性，以及确定K个类别中每个类别的IO写请求访问共享缓存的写访问特性。
其中，读访问特性为K个类别中每个类别的IO读请求分别在N个淘汰算法下的读命中率与缓存大小的关系，写访问特性为K个类别中每个类别的IO写请求分别在N个淘汰算法下的写命中率与缓存大小的关系。这里，读命中率是指IO读请求在缓存中读命中的命中率。写命中率是指IO写请求在缓存中写命中的命中率。
具体的，计算设备根据获取到的K个类别中每个类别的IO读请求，确定K个类别中每个类别的IO读请求访问共享缓存的读访问特性。以及，计算设备根据获取到的K个类别中每个类别的IO写请求，确定K个类别中每个类别的IO写请求访问共享缓存的写访问特性。
其中，计算设备根据K个类别中每个类别的IO读请求确定K个类别中每个类别的IO读请求访问共享缓存的读访问特性的详细说明，以及根据K个类别中每个类别的IO写请求确定K个类别中每个类别的IO写请求访问共享缓存的写访问特性的详细说明，均可以参考S102中“计算设备基于获取到的K个类别中每个类别的IO请求，确定K个类别中每个类别的IO请求访问共享缓存的访问特性”的相关描述，不再赘述。
S203、根据K个类别中每个类别的IO读请求的读访问特性、K个类别中每个类别的IO写请求的写访问特性及共享缓存的命中率，确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法。
具体的，计算设备根据K个类别中每个类别的IO读请求的读访问特性、K个类别中每个类别的IO写请求的写访问特性及共享缓存的命中率，确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法的详细说明，可以参考S103的描述。
需要说明的是，对于S103中“计算设备根据每个类别的IO请求在任意一个组合下的命中率，可以得到K个类别的IO请求在共享缓存中的一个命中率”，在S203，计算设备可以根据每个类别的IO读请求在任意一个组合下的读命中率、读命中权重系数、每个类别的IO写请求在任意一个组合下的写命中率、以及写命中权重系数，得到K个类别的IO请求在共享缓存中的综合命中率。
其中，读命中权重系数用于表征每个类别的IO读请求在共享缓存中的读命中率对共享缓存的综合命中率的影响程度，写命中权重系数用于表征每个类别的IO写请求在共享缓存中的写命中率对共享缓存的综合命中率的影响程度。其中，共享缓存的综合命中率为K个类别的IO请求在共享缓存中的命中率。其中，本申请实施例对读命中权重系数和写命中权重系数的具体取值不作限定。例如，读命中权重系数和写命中权重系数均为预设的权重系数。又例如，读命中权重系数和/或写命中权重系数可以基于近一段时间内实体对共享缓存的访问规律确定，或者，读命中权重系数和/或写命中权重系数可以基于对未来一段时间内预估的实体对共享缓存的访问规律确定。
具体的，对于K个类别中任意一个类别的IO请求(如第一类IO请求)，计算设备可以根据第一类IO请求中的IO读请求(第一类IO读请求)在任意一个组合(如第一组合)下的命中率和第一类IO读请求在K个类别的IO请求中的占比，确定第一组合下第一类IO读请求在共享缓存中的命中率。例如，计算设备对第一类IO读请求在第一组合下的命中率和第一类IO读请求在K个类别的IO请求中的占比作乘积运算，从而得到第一组合下第一类IO读请求在共享缓存中的命中率。
类似的，对于第一类IO请求中的IO写请求(以下简称第一类IO写请求)，计算设备可以根据第一类IO写请求在任意一个组合(如第一组合)下的命中率和第一类IO写请求在K个类别的IO请求中的占比，确定第一组合下第一类IO写请求在共享缓存中的命中率。例如，计算设备对第一类IO写请求在第一组合下的命中率和第一类IO写请求在K个类别的IO请求中的占比作乘积运算，从而得到第一组合下第一类IO写请求在共享缓存中的命中率。
其中，第一类IO读请求在K个类别的IO请求中的占比、第一类IO写请求在K个类别的IO请求中的占比的详细说明，可以参考S103中的相关描述，不再赘述。
进而，计算设备根据第一组合下第一类IO读请求在共享缓存中的命中率(如第一命中率)、读命中权重系数、第一组合下第一类IO写请求在共享缓存中的命中率(如第二命中率)、以及写命中权重系数，确定第一组合下第一类IO请求在共享缓存中的命中率。例如，计算设备对第一命中率和读命中权重系数的乘积、以及第二命中率和写命中权重系数的乘积作求和运算，从而得到第一组合下第一类IO请求在共享缓存中的命中率。作为示例，假设读命中权重系数为W1，写命中权重系数为W2，则第一组合下第一类IO请求在共享缓存中的命中率为：第一命中率×W1+第二命中率×W2。
类似的，计算设备可以确定任意组合下每个类别的IO请求在共享缓存中的命中率。进而，计算设备对K个类别的IO请求分别在共享缓存中的K个命中率求和，即可得到K个类别的IO请求在共享缓存中的命中率。进一步，对于K个类别的IO请求，计算设备根据每个类别的IO请求在X×N个组合下的X×N个命中率，可以得到K个类别的IO请求在共享缓存中的(X×N)K个命中率。进一步，计算设备确定K个类别的IO请求在共享缓存中的最大命中率， 并将获得最大命中率时每个类别对应的组合所指示的缓存大小，确定为每个类别的IO请求在共享缓存中的分区大小，以及将获得最大命中率时每个类别对应的组合所指示的淘汰算法，确定为每个类别的IO请求在共享缓存中的淘汰算法。具体说明可以参考S103中的描述，不再赘述。
需要说明，在计算设备对K个类别的IO请求分别在共享缓存中的K个命中率求和，以得到K个类别的IO请求在共享缓存中的命中率时，K个类别的IO请求的缓存大小之和，小于或等于共享缓存的大小。
然后，计算设备执行S104。
这样，通过S201-S104所述的共享缓存的管理方法，能够在共享缓存中的读写缓存融合的场景下，为每个类别的IO请求确定并配置合适的缓存大小和淘汰算法，从而能够提高IO请求在共享缓存的命中率，进而提高了共享缓存的整体缓存性能。
在一些实施例中，上述S201-S104所述的方法可以周期性的执行，相关说明可以参考实施例一中的相关描述，不再赘述。通过周期性执行S201-S104，共享缓存可以根据计算设备周期性确定的K个类别中每个类别的IO请求的缓存大小和淘汰算法，定期调整每个类别的IO请求在共享缓存中的缓存大小和淘汰算法，从而实现了在时域上保证IO请求在共享缓存的命中率，即在时域上保证了共享缓存的缓存性能。
实施例三
在共享缓存中的读写缓存融合的场景下，参考图10，图10示出了本申请实施例提供的又一种共享缓存的管理方法的流程示意图。可选的，该方法可以应用于图1所示的CPU中，或者应用于图2所示的缓存节点中，或者应用于图3所示的节点中。并可以由具有图4所示硬件结构的计算设备执行。计算设备先执行S201，然后，计算设备执行S302。
S302、根据K个类别中每个类别的IO读请求、读命中权重系数、K个类别中每个类别的IO写请求、以及写命中权重系数，确定K个类别中每个类别的IO请求访问共享缓存的访问特性。
其中，读命中权重系数和写命中权重系数的详细说明可以参考上文，不再赘述。
具体的，计算设备先根据获取到的K个类别中每个类别的IO读请求，确定N个淘汰算法下每个类别的IO读请求在不同大小的缓存中的读命中率，以及，计算设备根据获取到的K个类别中每个类别的IO写请求，确定N个淘汰算法下每个类别的IO写请求在不同大小的缓存中的写命中率。例如，以K个类别的IO请求中的第一类IO请求为例，计算设备可以根据获取到的第一类IO读请求，确定N个淘汰算法下第一类IO读请求在不同大小的缓存中的读命中率。以及，计算设备根据获取到的第一类IO写请求，确定N个淘汰算法下第一类IO写请求在不同大小的缓存中的写命中率。
其中，IO读请求、读命中率、IO写请求、写命中率、第一类IO读请求、以及第一类IO写请求的说明，均可以参考上文相关描述，不再赘述。
其中，计算设备根据获取到的K个类别中每个类别的IO读请求，确定N个淘汰算法下每个类别的IO读请求在不同大小的缓存中的读命中率的详细说明，以及计算设备根据获取到的K个类别中每个类别的IO写请求，确定N个淘汰算法下每个类别的IO写请求在不同大小的缓存中的写命中率的详细说明，均可以参考S102中确定N个淘汰算法下每个类别的IO请求在不同大小的缓存中的命中率的相关描述，不再赘述。
进而，对于K个类别的IO请求中的第一类IO请求，在相同淘汰算法和相同缓存大小下，计算设备对第一类IO读请求的读命中率和读命中权重系数的乘积、以及第一类IO写请求的 写命中率和写命中权重系数的乘积作加和运算，从而得到该淘汰算法和缓存大小下第一类IO请求的命中率。
类似的，计算设备即可确定出N个淘汰算法下每个类别的IO请求在不同大小的缓存中的命中率。这样，即得到了K个类别中每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系，也即得到K个类别中每个类别的IO请求访问共享缓存的访问特性。
然后，计算设备执行S103-S104。
这样，通过图10所述的共享缓存的管理方法，能够在共享缓存中的读写缓存融合的场景下，为每个类别的IO请求确定并配置合适的缓存大小和淘汰算法，从而能够提高IO请求在共享缓存的命中率，进而提高了共享缓存的整体缓存性能。
在一些实施例中，上述图10所述的方法可以周期性的执行，相关说明可以参考实施例一中的相关描述，不再赘述。通过周期性执行图10所述的方法，共享缓存可以根据计算设备周期性确定的K个类别中每个类别的IO请求的缓存大小和淘汰算法，定期调整每个类别的IO请求在共享缓存中的缓存大小和淘汰算法，从而实现了在时域上保证IO请求在共享缓存的命中率，即在时域上保证了共享缓存的缓存性能。
上述主要从方法的角度对本申请实施例提供的方案进行了介绍。
为了实现上述功能，如图11所示，图11示出了本申请实施例提供的一种共享缓存的管理装置110的结构示意图。管理装置110用于执行上述的共享缓存的管理方法，例如用于执行图5、图7、图9或图10所示的方法。其中，管理装置110可以包括确定单元111和配置单元112。
确定单元111，用于确定K个类别中每个类别的IO请求访问共享缓存的访问特性，以及，用于根据K个类别的IO请求的访问特性及共享缓存的命中率，确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法。其中，访问特性为K个类别中每个类别的IO请求分别在N个淘汰算法下的命中率与缓存大小的关系。配置单元112，用于将每个类别的IO请求在共享缓存中的缓存大小，配置为确定的每个类别的IO请求在共享缓存中的分区大小，以及，将每个类别的IO请求在共享缓存中的淘汰算法，配置为确定的每个类别的IO请求在共享缓存中的淘汰算法。
作为示例，结合图5，确定单元111可以用于执行S102和S103，配置单元112可以用于执行S104。结合图9，确定单元111可以用于执行S202和S203，配置单元112可以用于执行S104。结合图10，确定单元111可以用于执行S302和S103，配置单元112可以用于执行S104。
可选的，管理装置110还包括：模拟单元113，用于对于N个淘汰算法中的第一淘汰算法，在共享缓存中模拟K个类别中每个类别的IO请求在不同大小的缓存中应用第一淘汰算法的命中率，以得到命中率与缓存大小的关系。其中，第一淘汰算法是N个淘汰算法中的任意一个淘汰算法。
可选的，确定单元111具体用于：对于N个淘汰算法中的第一淘汰算法，根据第一类IO请求中每个IO请求的重用距离及不同的缓存大小，确定第一类IO请求在不同大小的缓存中应用第一淘汰算法的命中率，以得到命中率与缓存大小的关系。其中，第一淘汰算法是N个淘汰算法中的任意一种淘汰算法，第一类IO请求为K个类别中的任意一个类别的IO请求。
可选的，确定单元111还具体用于：根据基于每个类别的IO请求在每个淘汰算法下确定的X个缓存大小对应的X个命中率，确定每个组合下K个类别的IO请求在共享缓存的命中率，以及，将K个类别的IO请求在共享缓存中的命中率最大时每个类别的IO请求对应的缓 存大小，确定为每个类别的IO请求在共享缓存中的分区大小，将K个类别的IO请求在共享缓存中的命中率最大时每个类别的IO请求对应的淘汰算法，确定为每个类别的IO请求在共享缓存中的淘汰算法。其中，针对K个类别的IO请求中的任一个类别，X个缓存大小和N个淘汰算法构成X*N个组合，每个组合中包括一个缓存大小和一个淘汰算法；X个缓存大小是为与每个类别的IO请求对应的缓存预设的X个缓存大小。
作为示例，结合图5，确定单元111可以用于执行S103。结合图9，确定单元111可以用于执行S203。
可选的，管理装置110还包括：获取单元114，用于在确定K个类别中每个类别的IO请求访问共享缓存的访问特性之前，获取多个IO请求。分类单元115，用于根据多个IO请求所访问数据的地址的特征或者根据多个IO请求中所携带的类别标记，将IO请求分成K个类别。
作为示例，结合图5，获取单元114和分类单元115可以用于执行S101。
可选的，上述共享缓存为计算设备中CPU的LLC，则上述多个IO请求为CPU中的多个处理核发起的IO请求。
可选的，上述共享缓存为缓存节点中的缓存，则上述多个IO请求为访问缓存节点的多个计算节点发起的IO请求。
可选的，上述共享缓存为多个节点中的缓存构成的缓存池，则上述多个IO请求为访问缓存池的多个计算节点发起的IO请求。
可选的，上述的访问特性通过IO请求的HRC或MRC表征。
可选的，确定单元111还用于周期性的确定K个类别中每个类别的IO请求访问共享缓存的访问特性。针对在第一周期确定的K个类别中每个类别的IO请求访问共享缓存的访问特性，确定单元111具体用于根据在第一周期确定的K个类别的IO请求的访问特性和共享缓存的命中率，在第一周期确定每个类别的IO请求在共享缓存中的分区大小及淘汰算法，其中，第一周期是确定K个类别中每个类别的IO请求访问共享缓存的访问特性的任一个周期。
关于上述可选方式的具体描述可以参见前述的方法实施例，此处不再赘述。此外，上述提供的任一种管理装置110的解释以及有益效果的描述均可参考上述对应的方法实施例，不再赘述。
作为示例，结合图4，管理装置110中的确定单元111、配置单元112、模拟单元113以及分类单元115所实现的功能可以通过图4中的处理器401执行图4中的存储器402中的程序代码实现。获取单元114所实现的功能可以通过图4中的通信接口403实现。
本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
需要说明的是，图11中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如，还可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
本申请实施例还提供一种计算机程序产品，以及用于存储该计算机程序产品的计算机可读存储介质。该计算机程序产品可以包括一个或多个程序指令，当该一个或多个程序指令被一个或多个处理器运行时可以提供以上针对图5、图7、图9或图10描述的功能或者部分功 能。因此，例如，参考图5中S101～S104的一个或多个特征可以由该计算机程序产品中的一个或多个指令来承担。
在一些示例中，诸如针对执行图5、图7、图9或图10所述方法的共享缓存的管理装置可以被配置为，响应于通过计算机可读存储介质中存储的一个或多个程序指令，提供各种操作、功能、或者动作。
本申请实施例还提供给一种计算设备，该计算设备可以用于执行上文图5、图7、图9或图10所述的方法，从实现对共享缓存的管理。
可选的，该计算设备可以是包括共享缓存的设备是同一个设备，或者，该计算设备是与包括共享缓存的设备连接通信的设备，详细说明可以参考图4中对计算设备的相关描述，不再赘述。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机指令。在计算机上和执行计算机执行指令时，全部或部分地产生按照本申请实施例的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，计算机指令可以从一个网站站点、计算机、服务器或者数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可以用介质集成的服务器、数据中心等数据存储设备。可用介质可以是磁性介质(例如，软盘、硬盘、磁带)，光介质(例如，DVD)、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种共享缓存的管理方法，其特征在于，所述共享缓存用于缓存多个输入输出IO请求所请求操作的数据，所述多个IO请求对应K个类别，所述共享缓存对应N个淘汰算法；所述方法包括：
    确定所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性，所述访问特性为所述K个类别中每个类别的IO请求分别在所述N个淘汰算法下的命中率与缓存大小的关系；
    根据所述K个类别的IO请求的访问特性及所述共享缓存的命中率，确定每个类别的IO请求在所述共享缓存中的分区大小及淘汰算法；
    将每个类别的IO请求在所述共享缓存中的缓存大小，配置为所述确定的每个类别的IO请求在所述共享缓存中的分区大小，以及，将每个类别的IO请求在所述共享缓存中的淘汰算法，配置为所述确定的每个类别的IO请求在所述共享缓存中的淘汰算法。
  2. 根据权利要求1所述的方法，其特征在于，所述确定所述K个类别中的每个类别的IO请求访问所述共享缓存的访问特性包括：
    对于所述N个淘汰算法中的第一淘汰算法，在所述共享缓存中模拟所述K个类别中每个类别的IO请求在不同大小的缓存中应用第一淘汰算法的命中率，以得到所述命中率与缓存大小的关系；其中，所述第一淘汰算法是所述N个淘汰算法中的任意一个淘汰算法。
  3. 根据权利要求1所述的方法，其特征在于，所述确定所述K个类别中的每个类别的IO请求访问所述共享缓存的访问特性包括：
    对于所述N个淘汰算法中的第一淘汰算法，根据第一类IO请求中每个IO请求的重用距离及不同的缓存大小，确定所述第一类IO请求在不同大小的缓存中应用所述第一淘汰算法的命中率，以得到所述命中率与缓存大小的关系；其中，所述第一淘汰算法是所述N个淘汰算法中的任意一种淘汰算法，所述第一类IO请求为所述K个类别中的任意一个类别的IO请求。
  4. 根据权利要求1-3中任一项所述的方法，其特征在于，所述根据所述K个类别的IO请求的访问特性及所述共享缓存的命中率，确定每个类别的IO请求在所述共享缓存中的分区大小及淘汰算法包括：
    根据基于每个类别的IO请求在每个淘汰算法下确定的X个缓存大小对应的X个命中率，确定每个组合下所述K个类别的IO请求在所述共享缓存的命中率；其中，针对所述K个类别的IO请求中的任一个类别，所述X个缓存大小和所述N个淘汰算法构成X*N个组合，每个组合中包括一个缓存大小和一个淘汰算法；所述X个缓存大小是为与每个类别的IO请求对应的缓存预设的X个缓存大小；
    将所述K个类别的IO请求在所述共享缓存中的命中率最大时每个类别的IO请求对应的缓存大小，确定为每个类别的IO请求在所述共享缓存中的分区大小，以及将所述K个类别的IO请求在所述共享缓存中的命中率最大时每个类别的IO请求对应的淘汰算法，确定为每个类别的IO请求在所述共享缓存中的淘汰算法。
  5. 根据权利要求1-4中任一项所述的方法，其特征在于，在确定所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性之前，所述方法还包括：
    获取所述多个IO请求；
    根据所述多个IO请求所访问数据的地址的特征或者根据所述多个IO请求中所携带的类别标记，将所述IO请求分成所述K个类别。
  6. 根据权利要求1-5中任一项所述的方法，其特征在于，所述共享缓存为计算设备中的中央处理单元CPU的三级缓存LLC，所述多个IO请求为所述CPU中的多个处理核发起的IO请求。
  7. 根据权利要求1-5中任一项所述的方法，其特征在于，所述共享缓存为缓存节点中的缓存，所述多个IO请求为访问所述缓存节点的多个计算节点发起的IO请求。
  8. 根据权利要求1-5中任一项所述的方法，其特征在于，所述共享缓存为多个节点中的缓存构成的缓存池，所述多个IO请求为访问所述缓存池的多个计算节点发起的IO请求。
  9. 根据权利要求1-8中任一项所述的方法，其特征在于，所述访问特性通过IO请求的命中率曲线HRC或缺失率曲线MRC表征。
  10. 根据权利要求1-9中任一项所述的方法，其特征在于，所述确定所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性包括：
    周期性的确定所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性；
    针对在第一周期确定的所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性，所述根据所述K个类别的IO请求的访问特性及所述共享缓存的命中率，确定每个类别的IO请求在所述共享缓存中的分区大小及淘汰算法包括：
    根据在所述第一周期确定的所述K个类别的IO请求的访问特性和所述共享缓存的命中率，在所述第一周期确定每个类别的IO请求在所述共享缓存中的分区大小及淘汰算法；所述第一周期是确定所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性的任一个周期。
  11. 一种共享缓存的管理装置，其特征在于，所述共享缓存用于缓存多个输入输出IO请求所请求操作的数据，所述多个IO请求对应K个类别，所述共享缓存对应N个淘汰算法；所述装置包括：
    确定单元，用于确定所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性，所述访问特性为所述K个类别中每个类别的IO请求分别在所述N个淘汰算法下的命中率与缓存大小的关系；以及，用于根据所述K个类别的IO请求的访问特性及所述共享缓存的命中率，确定每个类别的IO请求在所述共享缓存中的分区大小及淘汰算法；
    配置单元，用于将每个类别的IO请求在所述共享缓存中的缓存大小，配置为所述确定的每个类别的IO请求在所述共享缓存中的分区大小，以及，将每个类别的IO请求在所述共享缓存中的淘汰算法，配置为所述确定的每个类别的IO请求在所述共享缓存中的淘汰算法。
  12. 根据权利要求11所述的装置，其特征在于，所述装置还包括：
    模拟单元，用于对于所述N个淘汰算法中的第一淘汰算法，在所述共享缓存中模拟所述K个类别中每个类别的IO请求在不同大小的缓存中应用第一淘汰算法的命中率，以得到所述命中率与缓存大小的关系；其中，所述第一淘汰算法是所述N个淘汰算法中的任意一个淘汰算法。
  13. 根据权利要求11所述的装置，其特征在于，所述确定单元具体用于：
    对于所述N个淘汰算法中的第一淘汰算法，根据第一类IO请求中每个IO请求的重用距离及不同的缓存大小，确定所述第一类IO请求在不同大小的缓存中应用所述第一淘汰算法的命中率，以得到所述命中率与缓存大小的关系；其中，所述第一淘汰算法是所述N个淘汰算法中的任意一种淘汰算法，所述第一类IO请求为所述K个类别中的任意一个类别的IO请求。
  14. 根据权利要求11-13中任一项所述的装置，其特征在于，所述确定单元还具体用于：
    根据基于每个类别的IO请求在每个淘汰算法下确定的X个缓存大小对应的X个命中率，确定每个组合下所述K个类别的IO请求在所述共享缓存的命中率；其中，针对所述K个类别的IO请求中的任一个类别，所述X个缓存大小和所述N个淘汰算法构成X*N个组合，每个组合中包括一个缓存大小和一个淘汰算法；所述X个缓存大小是为与每个类别的IO请求对应的缓存预设的X个缓存大小；
    将所述K个类别的IO请求在所述共享缓存中的命中率最大时每个类别的IO请求对应的缓存大小，确定为每个类别的IO请求在所述共享缓存中的分区大小，以及将所述K个类别的IO请求在所述共享缓存中的命中率最大时每个类别的IO请求对应的淘汰算法，确定为每个类别的IO请求在所述共享缓存中的淘汰算法。
  15. 根据权利要求11-14中任一项所述的装置，其特征在于，所述装置还包括：
    获取单元，用于在确定所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性之前，获取所述多个IO请求；
    分类单元，用于根据所述多个IO请求所访问数据的地址的特征或者根据所述多个IO请求中所携带的类别标记，将所述IO请求分成所述K个类别。
  16. 根据权利要求11-15中任一项所述的装置，其特征在于，所述共享缓存为计算设备中的中央处理单元CPU的三级缓存LLC，所述多个IO请求为所述CPU中的多个处理核发起的IO请求。
  17. 根据权利要求11-15中任一项所述的装置，其特征在于，所述共享缓存为缓存节点中的缓存，所述多个IO请求为访问所述缓存节点的多个计算节点发起的IO请求。
  18. 根据权利要求11-15中任一项所述的装置，其特征在于，所述共享缓存为多个节点中的缓存构成的缓存池，所述多个IO请求为访问所述缓存池的多个计算节点发起的IO请求。
  19. 根据权利要求11-18中任一项所述的装置，其特征在于，所述访问特性通过IO请求的命中率曲线HRC或缺失率曲线MRC表征。
  20. 根据权利要求11-19中任一项所述的装置，其特征在于，
    所述确定单元还用于周期性的确定所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性；
    针对在第一周期确定的所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性，所述确定单元具体用于根据在所述第一周期确定的所述K个类别的IO请求的访问特性和所述共享缓存的命中率，在所述第一周期确定每个类别的IO请求在所述共享缓存中的分区大小及淘汰算法；所述第一周期是确定所述K个类别中每个类别的IO请求访问所述共享缓存的访问特性的任一个周期。
  21. 一种计算设备，其特征在于，所述计算设备用于管理共享缓存，所述计算设备包括：存储器、一个或多个处理器，所述一个或多个处理器被配置为读取存储在所述存储器中的程序指令，以执行如权利要求1-10中任一项所述的方法。
  22. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质包括程序指令，当所述程序指令在计算机或处理器上运行时，使得所述计算机或所述处理器执行权利要求1-10中任一项所述的方法。
PCT/CN2023/079164 2022-03-02 2023-03-02 共享缓存的管理方法、装置及存储介质 WO2023165543A1 (zh)

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