WO2023164813A1

WO2023164813A1 - Source/drain confined epitaxy method, device preparation method, device, and apparatus

Info

Publication number: WO2023164813A1
Application number: PCT/CN2022/078676
Authority: WO
Inventors: 刘桃; 徐敏; 张卫; 汪大伟; 孙新; 陈鲲; 杨静雯; 吴春蕾; 王晨; 徐赛生; 尹睿
Original assignee: 复旦大学; 上海集成电路制造创新中心有限公司
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2023-09-07

Abstract

A source/drain confined epitaxy method for a gate-all-around device, the method comprising: forming on a substrate (105) several fin structures which are arranged in a first direction, and forming on the several fin structures several dummy gate structures (104) which are arranged in a second direction, wherein each dummy gate structure (104) crosses each of the several fin structures; etching the fin structures to form several source/drain cavities; forming between adjacent fin structures first isolation layers (106) which are arranged in the first direction, so as to isolate the source/drain cavities between the adjacent fin structures; performing epitaxy on a source/drain layer (107) in the source/drain cavities; and removing the first isolation layers (106). The thickness of the source/drain layer (107) may be limited within a critical thickness of stress release, so as to mitigate a stress relaxation phenomenon caused by mismatch dislocation. By means of limiting the thickness of the source/drain layer (107), the area of a contact face between the source/drain layer (107) and a gate electrode can be limited, thereby limiting parasitic capacitance. Further disclosed are a method for preparing a semiconductor device comprising a gate-all-around device, and a semiconductor device and an electronic apparatus.

Description

Source-drain limited epitaxy method, device preparation method, device, and equipment

technical field

The invention relates to the field of GAAFET device manufacturing technology, in particular to a source-drain limited epitaxy method, device preparation method, device and equipment.

Background technique

The height of gate-all-around devices at advanced nodes is relatively high, which already provides the largest effective area. Stressing the channel using SiGe S/D epitaxy has become integral to device performance.

The diamond-structured SiGe source and drain exert uneven stress on the channel stress of nanowires or nanosheets at different stacking levels, and it is difficult to control uniformity.

In the gate-all-around device, the device current is increased by increasing the number of stacked nanowires or nanoflakes, and the height of the fin structure (Fin) increases with the increase of the number of stacked nanowires or nanoflakes.

As the height of Fin increases and the volume of epitaxial SiGe increases, the SiGe source and drain between single Fins may still overlap, and dislocations are likely to occur at the overlapping position, resulting in stress relaxation of the SiGe source and drain, especially the failure to realize the source and drain Wrap Around Contact (WAC), the contact resistance is difficult to meet the requirements.

In addition, due to the substantial increase in the height of Fin, the epitaxial thickness of the SiGe source and drain also increases significantly. If the SiGe source and drain of this thickness are kept within the epitaxial critical thickness for stress relief, the Ge composition of the epitaxial SiGe needs to be reduced. It cannot meet the stress required to provide the channel; if the Ge composition is increased under this SiGe thickness, it may cause misfit dislocations between the SiGe source and drain, Si nanowires or sheets, and the Si substrate, resulting in stress relaxation. . The corresponding parasitic capacitance increases.

Therefore, how to control the thickness of the source and drain within the critical thickness of stress release, thereby reducing the mismatch dislocation caused by excessive source and drain thickness, so as to reduce the stress relaxation phenomenon caused by mismatch dislocation and eliminate the excessive source and drain thickness, Therefore, the increase of the parasitic capacitance caused by the excessive contact area between the source drain and the gate; by controlling the thickness of the source drain, it can further solve the source-drain overlapping stacking fault phenomenon with the increase of the source drain thickness, so as to reduce the resulting The phenomenon of stress relaxation, and the realization of wrap-around contact; these technical problems have become technical problems that the industry needs to solve urgently.

Contents of the invention

The invention provides a source-drain limited epitaxy method, a device preparation method, and corresponding devices and equipment to solve the problem that the thickness of the source/drain layer between adjacent Fins of the GAA device is not limited.

According to the first aspect of the present invention, a method for source-drain controllable confinement epitaxy on a gate-all-around device is provided, including:

providing a substrate;

forming several fin structures arranged along a first direction on the substrate, and shallow trench isolation structures between adjacent fin structures;

forming a plurality of dummy gate structures arranged along the second direction on the plurality of fin structures, and each dummy gate structure straddles each fin structure in the plurality of fin structures;

etching the fin structure to form a plurality of source/drain cavities;

forming a first isolation layer arranged along the first direction between adjacent fin structures to isolate source/drain cavities between adjacent fin structures;

epitaxial source/drain layer in the source/drain cavity;

removing the first isolation layer;

Wherein, the first direction and the second direction are perpendicular to each other.

Optionally, the thickness of the first isolation layer is adapted to the thickness of the source/drain layer.

Optionally, the height of the first isolation layer is not lower than the fin structure.

Optionally, the material of the first isolation layer is SiO2.

Optionally, the forming the first isolation layer arranged along the first direction between adjacent fin structures specifically includes:

depositing an isolation layer in the plurality of source/drain cavities;

Carrying out CMP treatment to the isolation layer;

Photolithography and etching are performed on the isolation layer after the CMP treatment, and only the isolation layer between adjacent fin structures is left to form the first isolation layer.

Optionally, the material of the source/drain layer is SiGe.

Optionally, after etching away the first isolation layer, further comprising:

An interlayer dielectric layer is formed on the source/drain layer and the shallow trench isolation structure.

According to a second aspect of the present invention, a method for preparing a semiconductor device is provided, comprising:

The method for source-drain controllable confinement epitaxy on a gate-all-around device according to any one of the first aspect of the present invention.

According to a third aspect of the present invention, there is provided a semiconductor device prepared by using the method for manufacturing a semiconductor device described in the second aspect of the present invention.

According to a fourth aspect of the present invention, there is provided an electronic device including the semiconductor device described in the third aspect of the present invention.

The present invention provides a method for source-drain controllable confinement epitaxy on a gate-all-around device. Before the source/drain layer is epitaxial in the source/drain cavity, an arrangement along the first direction is formed between adjacent fin structures. The first isolation layer is used to isolate the source/drain cavity between adjacent fin structures; thus, under the limitation of the first isolation layer, the thickness of the source/drain layer is controllable, so that the thickness of the source/drain layer can be It is limited within the critical thickness of the stress release, thereby reducing the mismatch dislocation caused by the excessive thickness of the source/drain layer, so as to reduce the stress relaxation phenomenon caused by the mismatch dislocation; of course, by adjusting the thickness of the source/drain layer The restriction can limit the area of the contact surface between the source/drain layer and the gate, thereby limiting the parasitic capacitance.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

Fig. 1 is a schematic flow chart of a method for source-drain controllable confinement epitaxy on a gate-all-around device in an embodiment of the present invention;

Fig. 2 (a) - Fig. 2 (c) are the first structure schematic diagram of the gate-all-around device in different stages of etching in an embodiment of the present invention;

FIG. 3(a)-FIG. 3(c) are schematic diagrams of gate-all-around device structures at different stages of etching in an embodiment of the present invention;

Figure 4(a)-Figure 4(c) is a schematic diagram of the gate-all-around device structure at different stages of etching in an embodiment of the present invention;

FIG. 5(a)-FIG. 5(c) are four schematic diagrams of the gate-all-around device structure at different stages of etching in an embodiment of the present invention;

Fig. 6(a)-Fig. 6(c) are schematic diagrams of gate-all-around device structures at different stages of etching in an embodiment of the present invention;

Explanation of reference signs:

101 - sacrificial layer

102-channel layer

103-Pseudo gate spacer

104-false gate structure;

105 - substrate;

106-the first isolation layer;

107-source/drain layer;

108 —Device contact structure.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and not necessarily Used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device comprising a sequence of steps or elements is not necessarily limited to the expressly listed instead, may include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.

Gate-all-around devices at advanced nodes are taller to provide maximum effective area. Compared with FinFET, which uses multi-Fin structure to increase the device current, it is more likely to use a single Fin structure in GAAFET devices to increase the device current by increasing the number or width of stacked nanowires or nanosheets, so it can be used without reducing performance. To relax the limitation of fin structure pitch (Fin pitch), and in GAAFET devices, using SiGe S/D epitaxy technology to apply stress to the channel has become indispensable for device performance.

However, in the process of producing SiGe source/drain by SiGe S/D epitaxy in the source/drain region, there are the following technical problems:

In a gate-all-around device, the height of Fin increases with the number of stacked nanowires or nanoflakes, and in a single Fin structure, the requirement for the spacing between Fin and Fin is relatively loose. As the height of Fin increases significantly, the thickness of SiGe source/drain produced by SiGeS/D epitaxy also increases significantly. The greater the thickness of SiGe source/drain, the greater the stress, which will cause stress relaxation, so SiGe source/drain should be kept Within the epitaxial critical thickness for stress release; the thickness of the SiGe source and drain epitaxial: refers to the thickness along the dummy gate jump direction;

At the same time, the thicker the SiGe source/drain, the larger the overlapping area between the gate and the SiGe source/drain, and the corresponding increase in parasitic capacitance;

In the prior art, during the SiGe S/D epitaxy process, the thickness of the SiGe source/drain can be controlled by adjusting the Ge composition of the SiGe source/drain, but the control of the Ge composition content in the SiGe S/D epitaxy is not easy to grasp. If the SiGe source/drain of this thickness is kept within the epitaxial critical thickness for stress release to ensure the thickness of stress release, it is necessary to reduce the Ge composition of epitaxial SiGe. If the Ge composition of epitaxial SiGe is too low and the stress is insufficient, it may not be possible. To meet the stress required to provide the channel; at this time, increase the Ge composition, the thickness is too thick or cause misfit dislocations between the SiGe source/drain and the Si nanowire or sheet and the Si substrate, resulting in stress relaxation; mismatch Misalignment means:

The normal SiGe lattice is larger than the Si lattice, and the SiGe film will change its lattice size to adapt to the lattice constant of the Si substrate during the epitaxy process, thereby generating compressive strain. But when SiGe exceeds the critical thickness, misfit dislocations will be generated in the film, which will cause stress relaxation. .

In addition, as the height of Fin increases and the volume of epitaxial SiGe increases, the SiGe source and drain between single Fins may still overlap together, and overlapping stacking faults are likely to occur at the overlapping position, resulting in stress relaxation of the SiGe source and drain. Moreover, Ideally, patterning photolithography is performed on the etch barrier layer, opening windows in the areas where contacts need to be made, and filling metal materials to form contacts. At this time, not only contacts can be formed on the top of the SiGe source/drain , its side and bottom can also be wrapped by metal to form a wrap-around contact to reduce contact resistance; however, when the SiGe source/drain between single Fins may still overlap, the source-drain wrap-around contact (WAC ), the contact resistance is difficult to meet the requirements.

Therefore, the existing technical means cannot well control the thickness of the SiGe source/drain, and thus cannot solve the above-mentioned overlapping stacking fault problem.

Secondly, the width of the SiGe source/drain of the diamond structure is not uniform in the vertical direction. Therefore, the SiGe source/drain exerts uneven stress on the channel stress of nanowires or nanosheets at different stacking levels, and it is difficult to control uniformity. Prior art means also fail to solve the technical problem.

Aiming at the above-mentioned technical problems, the present invention creatively proposes the following solutions: in the source-drain cavities formed after source-drain etching, Confinement (confinement) isolation structures arranged at intervals are arranged, and the SiGe source/drain is arranged to be aligned along its thickness direction. isolation.

Due to the limitation of the Confinement isolation structure, the width distribution of the SiGe source/drain in the vertical direction is uniform, so that the stress applied to different stacked channels is uniform; and at this time, it is easier to control the distribution of Ge components in the SiGe source and drain. Stress application effect of different stacked channels.

In addition, by controlling the width Wconfinement of SiO2Confinement, the volume of SiGe source/drain can be effectively controlled, avoiding invalid stress or even stress relaxation caused by exceeding the critical thickness, while effectively controlling the increase of parasitic capacitance and resistance, and also solving the problem of overlapping stacking faults. The problem.

Due to the limitation of the Confinement isolation structure, the width distribution of the SiGe source and drain in the vertical direction is uniform, and the stress applied to different stacked channels is more uniform.

Therefore, the technical solution proposed by the present invention can effectively solve problems that cannot be solved by using existing means.

The technical solution of the present invention will be described in detail below with specific embodiments. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

Please refer to Fig. 1-Fig. 6(c), wherein, Fig. 2-Fig. Figure (b) is a schematic cross-sectional view of the current device along the dotted line ② in Figure (a), and Figure (c) is the current device along the dotted line ① in Figure (a). Schematic diagram of the formed cross section.

Take Fig. 2 as an example to describe the above content in detail, wherein Fig. 2(a) is a top view of the current device formed after step S14 (wherein only the top view of the fin structure and gate structure is shown), and Fig. (2b) is the top view of the current device A schematic cross-sectional view of the device formed along the dotted line ② in Figure (a), and Figure 2(c) is a schematic cross-sectional view of the current device formed along the dotted line ① in Figure 1(a).

According to an embodiment of the present invention, a method for source-drain controllable confinement epitaxy on a gate-all-around device is provided, including:

S11: providing a substrate 105;

S12: forming several fin structures arranged along a first direction on the substrate, and shallow trench isolation structures between adjacent fin structures, the first direction is shown in the direction indicated by the arrow in FIG. 2(a) ;

The forming process of the plurality of fin structures is as follows: growing sacrificial layers 101 and channel layers 102 arranged at intervals on the substrate, etching the substrate and the sacrificial layers and channel layers on the substrate to form a plurality of fin structures, Cavities are formed between the plurality of fin structures after etching;

The specific formation process of the shallow trench isolation structure is: filling the cavity between the above-mentioned several fin structures with an isolation material to form an isolation layer;

S13: Forming a plurality of dummy gate structures 104 arranged along a second direction on the plurality of fin structures, and each dummy gate structure spans each fin structure in the plurality of fin structures, the second direction is as shown in FIG. 2 The direction of the arrow shown in (a) is perpendicular to the plane of the substrate;

Thus, the dummy gate structure covers a pair of sidewalls and part of the top of each fin structure, and the sidewalls are a pair of sidewalls in the first direction;

The formation process of the dummy gate structure is as follows: after step S12 is performed, the dummy gate material is deposited on the surface of the device, the top of the dummy gate material is CMP polished so that the dummy gate material reaches a specified height, and the dummy gate material is etched. forming the dummy gate structure;

Executing step S13: after forming several dummy gate structures arranged along the second direction on the several fin structures, it further includes: covering the dummy gate spacers 103 on both sides of each dummy gate structure, so that the dummy gate structures are homologous Drain region isolation, the two sides of the aforementioned dummy gate structure refer to the two side walls of the dummy gate structure along the second direction;

S14: Etching the fin structure to form several source/drain cavities, as shown in FIG. 2 ,

Etching the fin structure extending from the dummy gate structure and the spacer layers on both sides of the dummy gate structure along the second direction to form a source-drain cavity; the aforementioned source-drain cavity refers to: after step S14 is completed, cavities formed by gaps between the dummy gate structures;

After etching the fin structure to form several source/drain cavities, it also includes:

An inner spacer is formed between the channel layers; specifically, an isolation material is filled on the sidewall of the channel layer to form an inner spacer, since the inner spacer is formed between the sidewall of the channel layer and the dummy gate structure, thereby isolating the channel layer and the dummy gate structure;

S15: Form a first isolation layer 106 arranged along the first direction between adjacent fin structures to isolate the source/drain cavities between adjacent fin structures, as shown in FIG. 3, FIG. 3(a ) The thickness indicated by the double arrow is the thickness of the first isolation layer;

Wherein, the first isolation layer is formed in the source-drain cavity;

S16: Epitaxial source/drain layer 107 in the source/drain cavity, as shown in FIG. 4 ;

Due to the limitation of the first isolation layer, the thickness of the source/drain layer is limited, so that the thickness of the source/drain layer can be limited within the critical thickness for stress relief, thereby reducing the excessive thickness of the source/drain layer The mismatch dislocation caused by the mismatch dislocation, so as to reduce the stress relaxation phenomenon caused by the mismatch dislocation; of course, by limiting the thickness of the source/drain layer, the contact surface between the source/drain layer and the gate can be limited. The size of the area, thereby controlling the parasitic capacitance.

S17: removing the first isolation layer; thereby releasing the isolation between the epitaxial source/drain layers, as shown in Figure 5;

In one embodiment, the thickness of the first isolation layer is adapted to the thickness of the source/drain layer.

The adaptation refers to: since the volume of the epitaxial source/drain layer is controlled by the width Wconfinement of the first isolation layer, the volume of the epitaxial source/drain layer is controlled by adjusting the width of the first isolation layer, so that The thickness of the epitaxial source/drain layer along the first direction is controlled within the epitaxial critical thickness for stress relief to avoid ineffective stress and stress relaxation. In addition, by controlling the thickness of the source/drain layer, further The source/drain layer overlapping stacking fault phenomenon generated with the increase of the thickness of the source/drain layer is solved, so as to reduce the phenomenon of stress relaxation caused thereby.

In one embodiment, the height of the first isolation layer is not lower than the height of the fin structure;

The height of the first isolation layer is not limited to be the same as the height of the fin structure, as long as it can effectively isolate the epitaxial source/drain layer and achieve corresponding technical effects.

In one embodiment, the material of the first isolation layer is SiO2;

In other implementation manners, the material forming the first isolation layer may be other isolation materials that can achieve a similar isolation effect.

In one embodiment, the forming the first isolation layer arranged along the first direction between adjacent fin structures specifically includes:

depositing an isolation layer in the plurality of source/drain cavities;

Performing CMP treatment on the isolation layer; the CMP treatment is a polishing process, so that the isolation layers in the plurality of source/drain cavities meet a specified height;

performing photolithography and etching on the isolation layer after the CMP treatment, and only retaining the isolation layer between adjacent fin structures to form the first isolation layer;

The specific steps of photolithography and etching the isolation layer after the CMP treatment are: covering the surface of the device after the CMP treatment with photoresist, patterning the photoresist so that the photoresist covers the target isolation layer, The target isolation layer is the first isolation layer, and the isolation layer is etched using the patterned photoresist as a mask to obtain the first isolation layer.

In another embodiment, the isolation layer can be photolithographically and etched first, only the isolation layer between adjacent fin structures is retained, and then the isolation layer is subjected to CMP treatment to form the first isolation layer;

In one embodiment, the material of the source/drain layer is SiGe.

Since the first isolation layer is added before the epitaxy of the source/drain layer, the longitudinal thickness of the source/drain layer is uniform, so that the source/drain layer exerts uniform stress on the channel layer, and when passing Regulating the content of Ge in SiGe to adjust the thickness of the source/drain layer is easier to achieve than the source/drain layer of diamond structure.

In one embodiment, after etching away the first isolation layer, the following steps are further included:

1) Forming an interlayer dielectric layer on the source/drain layer and the shallow trench isolation structure.

The interlayer dielectric layer is formed in several source/drain cavities, and since step S15 is added before generating the epitaxial source/drain layer, the interlayer dielectric layer covers each of the source/drain Layer top and side walls;

Before depositing an interlayer dielectric layer on the source/drain layer and the shallow trench isolation structure, it also includes: depositing a dielectric material on the source/drain layer and the shallow trench isolation structure, and depositing the The dielectric material is etched to a specific height, and the dielectric material is etched to form the interlayer dielectric layer.

2) Remove the dummy gate structure.

In one embodiment, the dummy gate structure is made of polysilicon material.

3) Selectively etching the sacrificial layer, thereby releasing the Si channel layer.

A dummy gate cavity is formed after the dummy gate structure is removed and the sacrificial layer is released.

In one embodiment, the material forming the sacrificial layer is SiGe;

In one embodiment, the selective etching method is dry etching;

In other implementation manners, other methods may also be used to selectively etch the sacrificial layer.

4) Filling the dummy gate cavity with a metal gate material.

Before filling the metal gate material in the dummy gate cavity, it also includes: filling the dummy gate cavity with a high dielectric constant material; the metal gate material covering the high dielectric constant material; the high dielectric Constant material and metal gate (Metal gate, MG) complete the full wrapping of the channel layer;

In one implementation manner, the high dielectric constant material (High-k, HK) is a high-K material; the metal gate material is a material widely used in the prior art.

CMP is performed on the metal gate material and the high dielectric constant material to remove the metal gate material and the high dielectric constant material on top of the interlayer dielectric layer.

Precipitating an etching barrier layer (Nitride) on the outer surface of the structure formed in the above steps, using the etching barrier layer as a mask, etching the interlayer dielectric layer at the top and sidewall of the source/drain layer to form a contact hole, A device contact structure 108 is formed by depositing a metal material in the contact hole, as shown in FIG. 6 .

Later, patterned photolithography can be done on it, opening windows in the area where contact needs to be formed, and filling metal materials, such as W, TiN, etc. to form a contact structure. At this time, not only contact can be formed on the top of the source and drain, but also The side and bottom surfaces can also be wrapped with metal materials, and the contact structure completely wraps the source/drain layer to form a wraparound contact and reduce the contact resistance.

By limiting the thickness of the source/drain layer, the overlapping stacking fault phenomenon of the source/drain layer generated with the increase of the thickness of the source/drain layer is further solved, and then the wrap-around contact is realized.

According to an embodiment of the present invention, a method for manufacturing a semiconductor device is also provided, including:

The method for source-drain controllable confinement epitaxy on a gate-all-around device according to any one of the foregoing embodiments of the present invention.

According to an embodiment of the present invention, a semiconductor device is also provided, which is manufactured by using the method for manufacturing a semiconductor device of the present invention.

According to an embodiment of the present invention, an electronic device including a semiconductor device of the present invention is also provided.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims

A method for source-drain controllable confinement epitaxy on a gate-around device, characterized in that it includes:

providing a substrate;

forming several fin structures arranged along a first direction on the substrate, and shallow trench isolation structures between adjacent fin structures;

forming a plurality of dummy gate structures arranged along the second direction on the plurality of fin structures, and each dummy gate structure straddles each fin structure in the plurality of fin structures;

etching the fin structure to form a plurality of source/drain cavities;

forming a first isolation layer arranged along the first direction between adjacent fin structures to isolate source/drain cavities between adjacent fin structures;

epitaxial source/drain layer in the source/drain cavity;

removing the first isolation layer;

Wherein, the first direction and the second direction are perpendicular to each other.
The method for source-drain controllable confinement epitaxy on a gate-all-around device according to claim 1, wherein the thickness of the first isolation layer is adapted to the thickness of the source/drain layer.
The method for source-drain controllable confinement epitaxy on a gate-all-around device according to claim 1, wherein the height of the first isolation layer is not lower than that of the fin structure.
The method for source-drain controllable confinement epitaxy on a gate-all-around device according to claim 3, characterized in that the material of the first isolation layer is SiO 2 .
The method for source-drain controllable confinement epitaxy on a gate-all-around device according to any one of claims 1-3, wherein the first isolation arranged along the first direction is formed between adjacent fin structures Layers specifically include:

depositing an isolation layer in the plurality of source/drain cavities;

Carrying out CMP treatment to the isolation layer;

Photolithography and etching are performed on the isolation layer after the CMP treatment, and only the isolation layer between adjacent fin structures is left to form the first isolation layer.
The method for source-drain controllable confinement epitaxy on a gate-all-around device according to claim 3, characterized in that the material of the source/drain layer is SiGe.
The method for source-drain controllable confinement epitaxy on a gate-all-around device according to claim 1, further comprising: after etching away the first isolation layer:

An interlayer dielectric layer is formed on the source/drain layer and the shallow trench isolation structure.
A method for manufacturing a semiconductor device, comprising:

The method for source-drain controllable confinement epitaxy on a gate-all-around device according to any one of claims 1 to 7.
A semiconductor device, characterized in that it is manufactured by using the method for manufacturing a semiconductor device according to claim 8.
An electronic device comprising the semiconductor device according to claim 9.