WO2023162537A1

WO2023162537A1 - Pulse reception circuit, signal transmission device, electronic device, and vehicle

Info

Publication number: WO2023162537A1
Application number: PCT/JP2023/001905
Authority: WO
Inventors: 洋介山中; 雄二嶋田; 弘治齊藤
Original assignee: ローム株式会社
Priority date: 2022-02-28
Filing date: 2023-01-23
Publication date: 2023-08-31

Abstract

A pulse reception circuit 227 comprises: a first constant current source CC1r that generates a first reference current I1r; a second constant current source CC1f that generates a second reference current I1f; a first receiver RXr that adds together a first reception current Ir induced by a secondary-side coil 231s of a first transformer 231 and the first reference current I1r to generate a first current signal I3r; a second receiver RXf that adds together a second reception current If induced by a secondary-side coil 232s of a second transformer 232 and the second reference current I2f to generate a second current signal I3f; a first signal conversion unit R2r that converts the first current signal I3r to a first voltage signal Vr; a second signal conversion unit R2f that converts the second current signal I3f to a second voltage signal Vf; and a comparator HC that compares the first voltage signal Vr with the second voltage signal Vf and generates an output pulse signal OUT.

Description

Pulse receiver circuit, signal transmission device, electronic equipment, vehicle

The inventions disclosed in this specification relate to pulse receiving circuits, signal transmission devices, electronic devices, and vehicles.

Conventionally, signal transmission devices that transmit pulse signals while insulating input and output have been used in various applications (power supply devices, motor drive devices, etc.).

Patent Document 1 can be cited as an example of conventional technology related to the above.

JP 2017-188903 A

However, the pulse receiving circuit used in the conventional signal transmission device has room for further investigation regarding common-mode noise immunity.

The invention disclosed in the present specification provides a pulse receiver circuit, a signal transmission device, an electronic device, and a vehicle that are excellent in common-mode noise immunity in view of the above-described problems found by the inventors of the present application. With the goal.

For example, the pulse receiver circuit disclosed herein includes a first constant current source configured to generate a first reference current and a second constant current source configured to generate a second reference current. a first receiver configured to sum a first received current induced in a secondary coil of the first transformer and the first reference current to produce a first current signal; and a second transformer. a second receiver configured to sum a second received current induced in the secondary coil of the second receiver and the second reference current to generate a second current signal; a first signal converter configured to convert the second current signal into a signal; a second signal converter configured to convert the second current signal into a second voltage signal; the first voltage signal and the second voltage signal; a comparator configured to compare the voltage signal to generate an output pulse signal.

Also, for example, the pulse receiving circuit disclosed in this specification reduces the low frequency component of the first received current induced in the secondary coil of the first transformer to generate the first filter output signal. and a second high-pass filter configured to reduce low-frequency components of the second received current induced in the secondary coil of the second transformer to generate a second filter output signal. a highpass filter; a first subtractor configured to subtract the second filter output signal from the first filter output signal to produce a first difference signal; and the first filter output from the second filter output signal. a second subtractor configured to subtract a signal to produce a second difference signal; and a positive component of said first difference signal interposed between said first subtractor and a first input of said comparator. a first positive component extraction unit configured to generate a first extraction signal by extracting only the second difference, provided between the second subtractor and a second input terminal of the comparator; a second positive component extractor configured to generate a second extracted signal by extracting only the positive component of the signal.

In addition, other features, elements, steps, advantages, and characteristics will become clearer with the following detailed description and accompanying drawings.

According to the invention disclosed in this specification, it is possible to provide a pulse receiving circuit, a signal transmission device, an electronic device, and a vehicle with excellent common-mode noise immunity.

FIG. 1 is a diagram showing the basic configuration of a signal transmission device. FIG. 2 is a diagram showing the basic structure of a transformer chip. FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. 4 is a plan view of the semiconductor device shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. 3. FIG. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. FIG. 8 is an enlarged view (separation structure) of region XIII shown in FIG. FIG. 9 is a diagram schematically showing a layout example of a transformer chip. FIG. 10 is a diagram illustrating a configuration example of an electronic device. FIG. 11 is a diagram showing a comparative example of the signal transmission device. FIG. 12 is a diagram showing a first embodiment of the signal transmission device. FIG. 13 is a diagram illustrating an example of pulse reception operation. FIG. 14 is a diagram showing how undershoot occurs. FIG. 15 is a diagram showing a second embodiment of the signal transmission device. FIG. 16 is a diagram showing how undershoot is improved. FIG. 17 is a diagram showing a third embodiment of the signal transmission device. FIG. 18 is a diagram showing how an erroneous output of the output pulse signal occurs. FIG. 19 is a diagram showing a fourth embodiment of the signal transmission device. FIG. 20 is a diagram showing how the erroneous output of the output pulse signal is improved. FIG. 21 is a diagram showing how in-phase noise is superimposed at the reception timing of regular pulses. FIG. 22 is a diagram showing a fifth embodiment of the signal transmission device. FIG. 23 is a diagram showing a configuration example of a vehicle.

<Signal transmission device (basic configuration)>
FIG. 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example provides insulation between the primary circuit system 200p (VCC1-GND1 system) and the secondary circuit system 200s (VCC2-GND2 system), and the secondary circuit system 200s from the primary circuit system 200p A semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal to the secondary circuit system 200s and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

The controller chip 210 is a semiconductor chip that operates by being supplied with a power supply voltage VCC1 (for example, a maximum of 7 V based on GND1). For example, a pulse transmission circuit 211 and

buffers

212 and 213 are integrated in the controller chip 210 .

The pulse transmission circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 according to the input pulse signal IN. More specifically, when the pulse transmission circuit 211 notifies that the input pulse signal IN is at a high level, the transmission pulse signal S11 is pulse-driven (single-shot or multiple-shot transmission pulse output) and the input pulse signal S11 is output. When notifying that the signal IN is at low level, the transmission pulse signal S21 is pulse-driven. That is, the pulse transmission circuit 211 pulse-drives one of the transmission pulse signals S11 and S21 according to the logic level of the input pulse signal IN.

The buffer 212 receives the input of the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

The buffer 213 receives the input of the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

The driver chip 220 is a semiconductor chip that operates by being supplied with a power supply voltage VCC2 (for example, 30 V maximum based on GND2).

Buffers

221 and 222, a pulse receiving circuit 223, and a driver 224 are integrated in the driver chip 220, for example.

The buffer 221 waveform-shapes the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231 ) and outputs it to the pulse receiving circuit 223 .

The buffer 222 waveform-shapes the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs it to the pulse receiving circuit 223.

The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 according to the received pulse signals S12 and S22 input via the

buffers

221 and 222. More specifically, the pulse receiving circuit 223 raises the output pulse signal OUT to a high level in response to the pulse drive of the reception pulse signal S12, and raises the output pulse signal OUT in response to the pulse drive of the reception pulse signal S22. Driver 224 is driven to fall to low level. That is, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. As the pulse receiving circuit 223, for example, an RS flip-flop can be preferably used.

The driver 224 generates the output pulse signal OUT based on the driving control of the pulse receiving circuit 223.

The transformer chip 230 uses

transformers

231 and 232 to provide DC isolation between the controller chip 210 and the driver chip 220, while transforming the transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 into the reception pulse signal S12. and output to the pulse receiving circuit 223 as S22. In this specification, the phrase "directly insulate" means that objects to be insulated are not connected by a conductor.

More specifically, the transformer 231 outputs the reception pulse signal S12 from the secondary coil 231s in response to the transmission pulse signal S11 input to the primary coil 231p. On the other hand, the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s according to the transmission pulse signal S21 input to the primary coil 232p.

Thus, due to the characteristics of the spiral coil used for inter-insulation communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (=rise signal and fall signal), and then sent to two transformers. 231 and 232 from the primary circuit system 200p to the secondary circuit system 200s.

The signal transmission device 200 of this configuration example independently has a transformer chip 230 on which only the

transformers

231 and 232 are mounted separately from the controller chip 210 and the driver chip 220, and these three chips are integrated into a single chip. It is sealed in a package.

With such a configuration, both the controller chip 210 and the driver chip 220 can be formed by a general low-to-medium-voltage process (withstand voltage of several V to several tens of V). It is no longer necessary to use a high withstand voltage process (several kV withstand voltage), making it possible to reduce manufacturing costs.

It should be noted that the signal transmission device 200 can be suitably used, for example, as a power supply device or a motor drive device for in-vehicle equipment mounted in a vehicle. In addition to engine vehicles, the above vehicles include electric vehicles (BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV (plug-in hybrid electric vehicle / plug-in hybrid vehicle), or FCEV / FCV (xEV such as fuel cell electric vehicle/fuel cell vehicle) is also included.

<Transformer chip (basic structure)>
Next, the basic structure of the transformer chip 230 will be described. FIG. 2 is a diagram showing the basic structure of the transformer chip 230. As shown in FIG. In the transformer chip 230 of this figure, the transformer 231 includes a primary side coil 231p and a secondary side coil 231s facing each other in the vertical direction. The transformer 232 includes a primary side coil 232p and a secondary side coil 232s facing each other in the vertical direction.

Both the primary side coils 231p and 232p are formed on the first wiring layer (lower layer) 230a of the transformer chip 230 . The

secondary coils

231 s and 232 s are both formed on the second wiring layer (upper layer in this figure) 230 b of the transformer chip 230 . The secondary coil 231s is arranged directly above the primary coil 231p and faces the primary coil 231p. In addition, the secondary coil 232s is arranged directly above the primary coil 232p and faces the primary coil 232p.

The primary coil 231p is spirally laid so as to surround the internal terminal X21 in a clockwise direction, starting from the first end connected to the internal terminal X21, and the second end corresponding to the end point is the internal terminal X21. It is connected to the terminal X22. On the other hand, the primary coil 232p is spirally laid so as to surround the internal terminal X23 in a counterclockwise direction, starting from the first end connected to the internal terminal X23, and the second coil 232p corresponds to the end point. The end is connected to the internal terminal X22. The internal terminals X21, X22 and X23 are linearly arranged in the order shown.

The internal terminal X21 is connected to the external terminal T21 of the second layer 230b via the conductive wiring Y21 and via Z21. The internal terminal X22 is connected to the external terminal T22 of the second layer 230b through a conductive wiring Y22 and via Z22. The internal terminal X23 is connected to the external terminal T23 of the second layer 230b through the conductive wiring Y23 and via Z23. The external terminals T21 to T23 are linearly arranged and used for wire bonding with the controller chip 210. FIG.

The secondary coil 231s is spirally laid so as to surround the external terminal T24 in a counterclockwise direction, with a first end connected to the external terminal T24 as a starting point, and a second end corresponding to the end point. is connected to the external terminal T25. On the other hand, the secondary coil 232s is spirally laid so as to surround the periphery of the external terminal T26 clockwise, starting from the first end connected to the external terminal T26. The end is connected to the external terminal T25. The external terminals T24, T25 and T26 are linearly arranged in the order shown in the figure and used for wire bonding with the driver chip 220. FIG.

The

secondary coils

231s and 232s are AC-connected to the

primary coils

231p and 232p by magnetic coupling, respectively, and are DC-insulated from the

primary coils

231p and 232p. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230 and DC-insulated from the controller chip 210 by the transformer chip 230 .

<Transformer chip (2-channel type)>
FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. FIG. 5 is a plan view showing a layer in which the low-potential coil 22 (corresponding to the primary side coil of the transformer) is formed in the semiconductor device 5 shown in FIG. FIG. 6 is a plan view showing a layer in which the high potential coil 23 (=corresponding to the secondary side coil of the transformer) is formed in the semiconductor device 5 shown in FIG. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG.

3 to 7, the semiconductor device 5 includes a semiconductor chip 41 having a rectangular parallelepiped shape. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

A wide bandgap semiconductor consists of a semiconductor that exceeds the bandgap of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or more. The wide bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride) and GaAs (gallium arsenide).

The semiconductor chip 41 includes a semiconductor substrate made of silicon in this form. The semiconductor chip 41 may be an epitaxial substrate having a laminated structure including a semiconductor substrate made of silicon and an epitaxial layer made of silicon. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip side walls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular shape in this embodiment) in plan view (hereinafter simply referred to as "plan view") as seen from their normal direction Z. .

The chip sidewalls 44A-44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C and a fourth chip sidewall 44D. The first chip side wall 44A and the second chip side wall 44B form long sides of the semiconductor chip 41 . The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. As shown in FIG. The third chip side wall 44C and the fourth chip side wall 44D form short sides of the semiconductor chip 41 . The third chip side wall 44C and the fourth chip side wall 44D extend in the second direction Y and face the first direction X. As shown in FIG. Chip side walls 44A-44D are ground surfaces.

The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41 . The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A-53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular shape in this embodiment) matching the first main surface 42 in plan view. The insulating main surface 52 extends parallel to the first main surface 42 .

The insulating sidewalls 53A-53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C and a fourth insulating sidewall 53D. The insulating side walls 53A to 53D extend from the peripheral edge of the insulating main surface 52 toward the semiconductor chip 41 and connect to the chip side walls 44A to 44D. Specifically, the insulating sidewalls 53A-53D are formed flush with the chip sidewalls 44A-44D. The insulating sidewalls 53A-53D form ground surfaces flush with the chip sidewalls 44A-44D.

The insulating layer 51 has a multi-layer insulating laminate structure including a bottom insulating layer 55 , a top insulating layer 56 and a plurality of (eleven layers in this embodiment) interlayer insulating layers 57 . The bottom insulating layer 55 is an insulating layer that directly covers the first major surface 42 . The top insulating layer 56 is an insulating layer that forms the insulating main surface 52 . A plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56 . The bottom insulating layer 55 has a single layer structure containing silicon oxide in this embodiment. The top insulating layer 56 has a single layer structure containing silicon oxide in this form. The thickness of the bottom insulating layer 55 and the thickness of the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

The plurality of interlayer insulating layers 57 each have a laminated structure including a first insulating layer 58 on the bottom insulating layer 55 side and a second insulating layer 59 on the top insulating layer 56 side. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59 . The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

A second insulating layer 59 is formed on the first insulating layer 58 . It contains an insulating material different from the first insulating layer 58 . The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). The thickness of the second insulating layer 59 preferably exceeds the thickness of the first insulating layer 58 .

The total thickness DT of the insulating layer 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of layers of the interlayer insulating layers 57 are arbitrary, and are adjusted according to the dielectric breakdown voltage (dielectric breakdown tolerance) to be achieved. Insulating materials for the lowermost insulating layer 55, the uppermost insulating layer 56, and the interlayer insulating layer 57 are arbitrary, and are not limited to specific insulating materials.

The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this form, more than one) transformers 21 (corresponding to the previously mentioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21 . A plurality of transformers 21 are formed in the inner portion of the insulating layer 51 spaced apart from the insulating sidewalls 53A-53D. A plurality of transformers 21 are formed at intervals in the first direction X. As shown in FIG.

Specifically, the plurality of transformers 21 are, in plan view, a first transformer 21A, a second transformer 21B, a third transformer 21C, and a first transformer 21A, a second transformer 21B, and a A fourth transformer 21D is included. A plurality of transformers 21A-21D each have a similar structure. The structure of the first transformer 21A will be described below as an example. Descriptions of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D are omitted because the description of the structure of the first transformer 21A applies mutatis mutandis.

With reference to FIGS. 5-7, the first transformer 21A includes a low potential coil 22 and a high potential coil 23. FIG. The low potential coil 22 is formed within the insulating layer 51 . The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. As shown in FIG. The low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between the bottom insulating layer 55 and the top insulating layer 56 (that is, the plurality of interlayer insulating layers 57) in this embodiment.

The low potential coil 22 is formed on the lowermost insulating layer 55 (semiconductor chip 41 ) side within the insulating layer 51 , and the high potential coil 23 is formed on the uppermost insulating layer 56 with respect to the low potential coil 22 within the insulating layer 51 . It is formed on the (insulating main surface 52) side. That is, the high potential coil 23 faces the semiconductor chip 41 with the low potential coil 22 interposed therebetween. The low-potential coil 22 and the high-potential coil 23 can be arranged at any position. Also, the high-potential coil 23 may face the low-potential coil 22 with one or more interlayer insulating layers 57 interposed therebetween.

The distance between the low-potential coil 22 and the high-potential coil 23 (that is, the number of layers of the interlayer insulation layers 57) is appropriately adjusted according to the withstand voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counted from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counted from the uppermost insulating layer 56 side.

The low-potential coil 22 is embedded through the first insulating layer 58 and the second insulating layer 59 in the interlayer insulating layer 57 . The low potential coil 22 includes a first inner end 24 , a first outer end 25 and a first helix 26 helically routed between the first inner end 24 and the first outer end 25 . The first spiral portion 26 is wound in a spiral shape extending in an elliptical shape (oval shape) in plan view. A portion forming the innermost peripheral edge of the first spiral portion 26 defines an elliptical first inner region 66 in plan view.

The number of turns of the first spiral portion 26 may be 5 or more and 30 or less. The width of the first spiral portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first spiral portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first spiral portion 26 is defined by the width in the direction orthogonal to the spiral direction. The first winding pitch of the first spiral portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction orthogonal to the helical direction.

The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary, and are not limited to the shapes shown in FIG. 5 and the like. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape, a square shape, or a circular shape in a plan view. The first inner region 66 may be divided into a polygonal shape such as a triangular shape, a quadrangular shape, or a circular shape in plan view according to the winding shape of the first spiral portion 26 .

The low potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum and tungsten. The low potential coil 22 may have a laminated structure including barrier layers and body layers. The barrier layer defines a recess space within the interlayer insulating layer 57 . A body layer is embedded in the recessed space defined by the barrier layer. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum and tungsten.

The high-potential coil 23 is embedded through the first insulating layer 58 and the second insulating layer 59 in the interlayer insulating layer 57 . The high potential coil 23 includes a second inner end 27 , a second outer end 28 and a second helix 29 helically routed between the second inner end 27 and the second outer end 28 . The second spiral portion 29 is wound in a spiral shape extending in an elliptical shape (oval shape) in plan view. In this embodiment, the portion forming the innermost peripheral edge of the second spiral portion 29 defines an elliptical second inner region 67 in plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z. As shown in FIG.

The number of turns of the second spiral portion 29 may be 5 or more and 30 or less. The number of turns of the second spiral portion 29 relative to the number of turns of the first spiral portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second spiral portion 29 preferably exceeds the number of turns of the first spiral portion 26 . Of course, the number of turns of the second spiral portion 29 may be less than the number of turns of the first spiral portion 26 or may be equal to the number of turns of the first spiral portion 26 .

The width of the second spiral portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second spiral portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second spiral portion 29 is defined by the width in the direction orthogonal to the spiral direction. The width of the second spiral portion 29 is preferably equal to the width of the first spiral portion 26 .

The second winding pitch of the second spiral portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction orthogonal to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helix 26 .

The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary, and are not limited to the shapes shown in FIG. 6 and the like. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape, a square shape, or a circular shape in a plan view. The second inner region 67 may be divided into a polygonal shape such as a triangular shape, a square shape, or a circular shape in plan view according to the winding shape of the second spiral portion 29 .

The high-potential coil 23 is preferably made of the same conductive material as the low-potential coil 22. That is, the high-potential coil 23 preferably includes barrier layers and body layers, similar to the low-potential coil 22 .

Referring to FIG. 4, semiconductor device 5 includes a plurality of (12 in this drawing) low potential terminals 11 and a plurality of (12 in this drawing) high potential terminals 12 . A plurality of low potential terminals 11 are electrically connected to low potential coils 22 of corresponding transformers 21A to 21D, respectively. A plurality of high potential terminals 12 are electrically connected to high potential coils 23 of corresponding transformers 21A to 21D, respectively.

A plurality of low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51 . Specifically, the plurality of low-potential terminals 11 are formed in a region on the side of the insulating sidewall 53B at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X. It is

The plurality of low potential terminals 11 includes a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E and a sixth low potential terminal 11F. include. Each of the plurality of low potential terminals 11A to 11F is formed two by two in this embodiment. The number of the plurality of low potential terminals 11A-11F is arbitrary.

The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

The fifth low potential terminal 11E is electrically connected to the first outer terminal 25 of the first transformer 21A (low potential coil 22) and the first outer terminal 25 of the second transformer 21B (low potential coil 22). there is The sixth low potential terminal 11F is electrically connected to the first outer terminal 25 of the third transformer 21C (low potential coil 22) and the first outer terminal 25 of the fourth transformer 21D (low potential coil 22). there is

The plurality of high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low-potential terminals 11 . Specifically, the plurality of high-potential terminals 12 are formed in a region on the side of the insulating sidewall 53A spaced apart from the plurality of low-potential terminals 11 in the second direction Y, and are arranged in the first direction X at intervals. ing.

A plurality of high-potential terminals 12 are formed in regions adjacent to the corresponding transformers 21A to 21D in plan view. The high potential terminal 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12. means.

Specifically, the plurality of high-potential terminals 12 are formed at intervals along the first direction X so as to face the plurality of transformers 21A to 21D along the first direction X in plan view. . More specifically, the plurality of high potential terminals 12 are arranged along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and the region between the adjacent high potential coils 23 in plan view. formed with a gap. As a result, the plurality of high-potential terminals 12 are arranged in line with the plurality of transformers 21A to 21D in the first direction X in plan view.

The plurality of high potential terminals 12 includes a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E and a sixth high potential terminal 12F. include. Each of the plurality of high-potential terminals 12A to 12F is formed two by two in this embodiment. The number of high potential terminals 12A to 12F is arbitrary.

The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in plan view. The fifth high potential terminal 12E is formed in a region between the first transformer 21A and the second transformer 21B in plan view. The sixth high potential terminal 12F is formed in a region between the third transformer 21C and the fourth transformer 21D in plan view.

The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). there is The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23). there is

5 to 7, semiconductor device 5 includes first low-potential wiring 31, second low-potential wiring 32, first high-potential wiring 33 and second high-potential wiring formed in insulating layer 51, respectively. 34. In this form, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33 and a plurality of second high potential wirings 34 are formed.

The first low potential wiring 31 and the second low potential wiring 32 fix the low potential coil 22 of the first transformer 21A and the low potential coil 22 of the second transformer 21B to the same potential. The first low potential wiring 31 and the second low potential wiring 32 fix the low potential coil 22 of the third transformer 21C and the low potential coil 22 of the fourth transformer 21D to the same potential. In this form, the first low potential wiring 31 and the second low potential wiring 32 fix all the low potential coils 22 of the transformers 21A to 21D to the same potential.

The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Also, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D at the same potential in this form.

The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The multiple first low-potential wirings 31 have the same structure. The structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described below as an example. The description of the structure of the other first low potential wiring 31 is omitted because the description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis.

The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, and one or more (in this embodiment, more than one) pad plug electrodes. 76 , and one or more (in this form, more than one) substrate plug electrodes 77 .

The through wiring 71, the low potential connection wiring 72, the lead wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are made of the same conductive material as the low potential coil 22 and the like. It is preferable that they are formed respectively. That is, the through wiring 71, the low potential connection wiring 72, the lead wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are similar to the low potential coil 22 and the like. It preferably includes a barrier layer and a body layer, respectively.

The through wiring 71 penetrates the plurality of interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape extending along the normal direction Z. As shown in FIG. Through wire 71 is formed in a region between lowermost insulating layer 55 and uppermost insulating layer 56 in insulating layer 51 in this embodiment. The through wire 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wire 71 is formed in the same interlayer insulating layer 57 as the high potential coil 23 and covered with the uppermost insulating layer 56 . The lower end of the through wire 71 is formed on the same interlayer insulating layer 57 as the low potential coil 22 .

The through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80 in this embodiment. In the through wire 71, the first electrode layer 78, the second electrode layer 79, and the wire plug electrode 80 are made of the same conductive material as the low potential coil 22 and the like. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 each include a barrier layer and a body layer, like the low-potential coil 22 and the like.

The first electrode layer 78 forms the upper end of the through wire 71 . The second electrode layer 79 forms the lower end of the through wire 71 . The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. As shown in FIG. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z. As shown in FIG.

A plurality of wiring plug electrodes 80 are embedded in a plurality of interlayer insulating layers 57 positioned between the first electrode layer 78 and the second electrode layer 79, respectively. A plurality of wiring plug electrodes 80 are laminated from the bottom insulating layer 55 toward the top insulating layer 56 so as to be electrically connected to each other, and electrically connect the first electrode layer 78 and the second electrode layer 79 to each other. Connected. The plurality of wiring plug electrodes 80 each have a planar area less than the planar area of the first electrode layer 78 and the planar area of the second electrode layer 79 .

Note that the number of lamination of the plurality of wiring plug electrodes 80 matches the number of lamination of the plurality of interlayer insulating layers 57 . Although six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57 in this embodiment, the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the plurality of interlayer insulating layers 57 .

The low-potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connection wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. As shown in FIG. The low-potential connection wiring 72 preferably has a plane area larger than that of the wiring plug electrode 80 . A low potential connection wire 72 is electrically connected to the first inner end 24 of the low potential coil 22 .

The lead wiring 73 is formed in a region between the semiconductor chip 41 and the through wiring 71 within the interlayer insulating layer 57 . The lead-out wiring 73 is formed in the first interlayer insulating layer 57 counted from the lowermost insulating layer 55 in this embodiment. Lead wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. A first end of lead-out wiring 73 is located in a region between semiconductor chip 41 and the lower end of through-wiring 71 . A second end of the lead wire 73 is located in a region between the semiconductor chip 41 and the low potential connection wire 72 . The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in a region between the first end portion and the second end portion.

The first connection plug electrode 74 is formed in a region between the through wire 71 and the lead wire 73 within the interlayer insulating layer 57 and is electrically connected to first ends of the through wire 71 and the lead wire 73 . The second connection plug electrode 75 is formed in a region between the low-potential connection wiring 72 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second ends of the low-potential connection wiring 72 and the lead-out wiring 73 . It is

A plurality of pad plug electrodes 76 are formed in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wire 71 in the uppermost insulating layer 56, and are formed at the upper ends of the low potential terminal 11 and the through wire 71. They are electrically connected to each other. A plurality of substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the lead wiring 73 within the lowermost insulating layer 55 . In this embodiment, the substrate plug electrode 77 is formed in a region between the semiconductor chip 41 and the first ends of the lead wires 73, and is electrically connected to the semiconductor chip 41 and the first ends of the lead wires 73, respectively. there is

6 and 7, a plurality of first high potential wires 33 are connected to corresponding high potential terminals 12A-12D and second inner ends 27 of corresponding transformers 21A-21D (high potential coils 23), respectively. electrically connected. The multiple first high-potential wirings 33 each have a similar structure. The structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described below as an example. The description of the structure of the other first high-potential wiring 33 is omitted because the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis.

The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, more than one) pad plug electrodes 82 . The high potential connection wiring 81 and the pad plug electrode 82 are preferably made of the same conductive material as the low potential coil 22 and the like. That is, the high potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a body layer like the low potential coil 22 and the like.

The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 in the same interlayer insulating layer 57 as the high-potential coil 23 . The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. As shown in FIG. A high potential connecting wire 81 is electrically connected to the second inner end 27 of the high potential coil 23 . The high-potential connection wiring 81 is spaced from the low-potential connection wiring 72 in plan view, and does not face the low-potential connection wiring 72 in the normal direction Z. As shown in FIG. As a result, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the withstand voltage of the insulation layer 51 is increased.

A plurality of pad plug electrodes 82 are formed in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connection wiring 81 in the uppermost insulating layer 56, are electrically connected to each other. Each of the plurality of pad plug electrodes 82 has a plane area smaller than the plane area of the high-potential connection wiring 81 in plan view.

Referring to FIG. 7, the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2<D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT<D1). A ratio D2/D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary, and are appropriately adjusted according to the dielectric breakdown voltage to be achieved.

6 and 7, semiconductor device 5 includes dummy patterns 85 embedded in insulating layer 51 so as to be positioned around transformers 21A to 21D in plan view.

The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from that of the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A-21D. In other words, the dummy pattern 85 does not function as the transformers 21A-21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A-21D and suppresses electric field concentration on the high-potential coil 23. FIG. In this form, the dummy pattern 85 is routed with a line density equal to the line density of the high-potential coil 23 per unit area. The fact that the line density of the dummy patterns 85 is equal to the line density of the high-potential coil 23 means that the line density of the dummy patterns 85 is within ±20% of the line density of the high-potential coil 23 .

The depth position of the dummy pattern 85 inside the insulating layer 51 is arbitrary, and is adjusted according to the electric field strength to be alleviated. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 with respect to the normal direction Z. As shown in FIG. The dummy pattern 85 being close to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is equal to the distance between the dummy pattern 85 and the low-potential coil 22 in the normal direction Z. means less than the distance of

In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. With respect to the normal direction Z, the smaller the distance between the dummy pattern 85 and the high-potential coil 23, the more the electric field concentration on the high-potential coil 23 can be suppressed. Dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as high-potential coil 23 . In this case, electric field concentration on the high-potential coil 23 can be suppressed more appropriately. Dummy pattern 85 includes a plurality of dummy patterns having different electrical states. The dummy pattern 85 may include a high potential dummy pattern.

The depth position of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary, and is adjusted according to the electric field strength to be alleviated. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 with respect to the normal direction Z. As shown in FIG. The high-potential dummy pattern 86 being close to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is equal to the high-potential dummy pattern 86 and the low-potential coil 23 . It means less than the distance between the coils 22 .

The dummy pattern 85 includes floating dummy patterns formed in an electrically floating state within the insulating layer 51 so as to be positioned around the transformers 21A to 21D.

In this form, the floating dummy pattern is drawn in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in plan view. The floating dummy pattern may be formed in a shape with an end, or may be formed in a shape without an end.

The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary, and is adjusted according to the electric field intensity to be relaxed.

The number of floating lines is arbitrary and adjusted according to the electric field to be relaxed. A floating dummy pattern may be composed of a plurality of floating patterns.

Referring to FIG. 7, semiconductor device 5 includes second functional device 60 formed on first main surface 42 of semiconductor chip 41 in device region 62 . The second functional device 60 is formed using the surface layer portion of the first main surface 42 of the semiconductor chip 41 and/or the region above the first main surface 42 of the semiconductor chip 41, and includes the insulating layer 51 (lowermost It is covered by an insulating layer 55). In FIG. 7, the second functional device 60 is simply indicated by the dashed line indicated on the surface layer of the first main surface 42. As shown in FIG.

The second functional device 60 is electrically connected to the low potential terminal 11 via the low potential wiring and electrically connected to the high potential terminal 12 via the high potential wiring. The low potential wiring has the same structure as the first low potential wiring 31 (second low potential wiring 32) except that it is routed in the insulating layer 51 so as to be connected to the second functional device 60. have. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34) except that it is routed in the insulating layer 51 so as to be connected to the second functional device 60. have. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 is omitted.

The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device and a semiconductor switching device. The passive device, the second functional device 60, may include a network in which any two or more of passive devices, semiconductor rectifying devices and semiconductor switching devices are selectively combined. The circuitry may form part or all of an integrated circuit.

Passive devices may include semiconductor passive devices. Passive devices may include either or both resistors and capacitors. The semiconductor rectifier device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode and a fast recovery diode. The semiconductor switching device may include at least one of BJT [Bipolar Junction Transistor], MISFET [Metal Insulator Field Effect Transistor], IGBT [Insulated Gate Bipolar Junction Transistor] and JFET [Junction Field Effect Transistor].

5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded within the insulating layer 51. As shown in FIG. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape with a gap from the insulating side walls 53A to 53D in plan view, and partitions the insulating layer 51 into a device region 62 and an outer region 63 . The seal conductor 61 suppresses entry of moisture and cracks from the outer region 63 into the device region 62 .

The device region 62 includes a first functional device 45 (plurality of transformers 21), a second functional device 60, a plurality of low potential terminals 11, a plurality of high potential terminals 12, a first low potential wiring 31, and a second low potential wiring. 32 , first high potential wiring 33 , second high potential wiring 34 and dummy pattern 85 . The outer area 63 is an area outside the device area 62 .

The seal conductor 61 is electrically separated from the device region 62 . Specifically, the seal conductor 61 includes the first functional device 45 (the plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, It is electrically separated from the second low potential wiring 32 , the first high potential wiring 33 , the second high potential wiring 34 and the dummy pattern 85 . More specifically, the seal conductor 61 is fixed in an electrically floating state. Seal conductor 61 does not form a current path leading to device region 62 .

The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this form, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. Thereby, the seal conductor 61 defines a quadrangular (specifically rectangular) device region 62 in plan view. In addition, the seal conductor 61 defines an outer region 63 of a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view.

Specifically, the seal conductor 61 has an upper end portion on the insulating main surface 52 side, a lower end portion on the semiconductor chip 41 side, and a wall portion extending like a wall between the upper end portion and the lower end portion. In this embodiment, the upper end of the seal conductor 61 is spaced from the insulating main surface 52 toward the semiconductor chip 41 and positioned within the insulating layer 51 . The upper end of the seal conductor 61 is covered with the top insulating layer 56 in this embodiment. The upper ends of the seal conductors 61 may be covered by one or more interlayer insulation layers 57 . The top end of the seal conductor 61 may be exposed from the top insulating layer 56 . The bottom end of the seal conductor 61 is spaced from the semiconductor chip 41 toward the top end.

Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12 . In addition, the seal conductor 61 includes the first functional device 45 (the plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, and the second high-potential wiring within the insulating layer 51. It faces the wiring 34 and the dummy pattern 85 in a direction parallel to the insulating main surface 52 . The seal conductor 61 may face a portion of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating main surface 52 .

The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, more than one) seal via conductors 65 . The number of seal via conductors 65 is arbitrary. An uppermost seal plug conductor 64 of the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61 . A plurality of seal via conductors 65 form the lower ends of the seal conductors 61 respectively. Seal plug conductor 64 and seal via conductor 65 are preferably made of the same conductive material as low potential coil 22 . That is, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a body layer like the low potential coil 22 and the like.

The plurality of seal plug conductors 64 are respectively embedded in the plurality of interlayer insulating layers 57 and formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. A plurality of seal plug conductors 64 are stacked from the bottom insulating layer 55 toward the top insulating layer 56 so as to be connected to each other. The number of laminated seal plug conductors 64 matches the number of laminated interlayer insulating layers 57 . Of course, one or more seal plug conductors 64 may be formed to penetrate the multiple interlayer insulating layers 57 .

If an assembly of a plurality of seal plug conductors 64 forms one ring-shaped seal conductor 61, not all of the plurality of seal plug conductors 64 need to be ring-shaped. For example, at least one of the plurality of seal plug conductors 64 may be formed with ends. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of band-like portions with ends. However, considering the risk of moisture and cracks entering the device region 62, it is preferable that the plurality of seal plug conductors 64 be endless (annular).

A plurality of seal via conductors 65 are formed in regions between the semiconductor chip 41 and the seal plug conductors 64 in the bottom insulating layer 55 . A plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductors 64 . The plurality of seal via conductors 65 have plane areas less than the plane area of the seal plug conductors 64 . When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of the seal plug conductor 64 .

The width of the seal conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the seal conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the seal conductor 61 is defined by the width in the direction orthogonal to the extending direction of the seal conductor 61 .

7 and 8, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 to electrically isolate the seal conductor 61 from the semiconductor chip 41. FIG. Isolation structure 130 preferably includes an insulator. The isolation structure 130 consists of the field insulating film 131 formed in the 1st main surface 42 of the semiconductor chip 41 in this form.

The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41 . The thickness of the field insulating film 131 is arbitrary as long as the semiconductor chip 41 and the seal conductor 61 can be insulated. Field insulating film 131 may have a thickness of 0.1 μm or more and 5 μm or less.

The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the separation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The separation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion in which the lower end portion (seal via conductor 65 ) of the seal conductor 61 bites toward the semiconductor chip 41 side. Of course, the connecting portion 132 may be formed flush with the main surface of the isolation structure 130 .

The isolation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a body portion 130C between the inner end portion 130A and the outer end portion 130B. The inner end portion 130A defines a region in which the second functional device 60 is formed (that is, the device region 62) in plan view. The inner end portion 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41 .

The outer end portion 130B is exposed from the chip side walls 44A to 44D of the semiconductor chip 41 and continues to the chip side walls 44A to 44D of the semiconductor chip 41. As shown in FIG. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. As shown in FIG. The outer end portion 130B forms a flush ground surface between the chip side walls 44A to 44D of the semiconductor chip 41 and the insulating side walls 53A to 53D of the insulating layer 51. As shown in FIG. Of course, in another form, the outer end 130B may be formed in the first major surface 42 spaced apart from the chip sidewalls 44A-44D.

The main body portion 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41 . The body portion 130C has a connecting portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connecting portion 132 is formed at a portion of the body portion 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms other than the field insulating film 131 .

Referring to FIG. 7, semiconductor device 5 further includes an inorganic insulating layer 140 formed on insulating main surface 52 of insulating layer 51 so as to cover seal conductor 61 . Inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52 .

The inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142 in this embodiment. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide with no impurity added. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the withstand voltage on the high-potential coil 23 can be increased.

When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V/cm) of USG exceeds the breakdown voltage (V/cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142 .

The first inorganic insulating layer 141 may contain at least one of BPSG (boron doped phosphor silicate glass) and PSG (phosphorus silicate glass) as an example of silicon oxide. However, in this case, since silicon oxide contains impurities (boron or phosphorus), it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the withstand voltage on the high-potential coil 23 . . Of course, the inorganic insulating layer 140 may have a single layer structure consisting of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142 .

The inorganic insulating layer 140 covers the entire area of the seal conductor 61 and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed outside the seal conductor 61 . A plurality of low potential pad openings 143 expose a plurality of low potential terminals 11 respectively. A plurality of high potential pad openings 144 respectively expose a plurality of high potential terminals 12 . The inorganic insulating layer 140 may have an overlapping portion that runs over the peripheral portion of the low potential terminal 11 . The inorganic insulating layer 140 may have an overlapping portion overlying the peripheral portion of the high potential terminal 12 .

The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140 . The organic insulating layer 145 may contain a photosensitive resin. Organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. Organic insulating layer 145 comprises polyimide in this form. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140 . Furthermore, the total thickness of inorganic insulating layer 140 and organic insulating layer 145 is preferably equal to or greater than distance D2 between low potential coil 22 and high potential coil 23 . In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Also, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. According to these structures, it is possible to suppress the thickening of the inorganic insulating layer 140 and the organic insulating layer 145, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 appropriately increases the withstand voltage of the high-potential coil 23. be able to.

The organic insulating layer 145 includes a first portion 146 covering the low potential side region and a second portion 147 covering the high potential side region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 interposed therebetween. The first portion 146 has a plurality of low potential terminal openings 148 exposing the plurality of low potential terminals 11 (low potential pad openings 143 ) respectively in a region outside the seal conductor 61 . The first portion 146 may have an overlap portion that runs over the periphery (overlap portion) of the low potential pad opening 143 .

The second portion 147 is spaced apart from the first portion 146 and exposes the inorganic insulating layer 140 between the first portion 146 and the second portion 147 . The second portion 147 has a plurality of high potential terminal openings 149 that respectively expose a plurality of high potential terminals 12 (high potential pad openings 144). The second portion 147 may have an overlap portion that runs over the periphery (overlap portion) of the high potential pad opening 144 .

The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121. are doing.

Embodiments of the present invention can be implemented in other forms. In the above embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form having only the second functional device 60 without having the first functional device 45 may be employed. In this case, dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

That is, when voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, unwanted conduction between the high potential terminal 12 and the seal conductor 61 can be suppressed. Also, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, unwanted conduction between the low potential terminal 11 and the seal conductor 61 can be suppressed.

Also, in the above embodiment, an example in which the second functional device 60 is formed has been described. However, the second functional device 60 is not necessarily required and may be removed.

Also, in the above embodiment, an example in which the dummy pattern 85 is formed has been described. However, the dummy pattern 85 is not necessarily required and may be removed.

Also, in the above-described embodiment, an example in which the first functional device 45 is of a multi-channel type including a plurality of transformers 21 has been described. However, a single-channel first functional device 45 including a single transformer 21 may be employed.

<Trans sequence>
FIG. 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the semiconductor device 5 described above). The transformer chip 300 in this figure includes a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, and pads a1 to a8. , pads b1 to b8, pads c1 to c4, and pads d1 to d4.

In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary coil L1s forming the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. ing. Pads a2 and b2 are connected to one end of the secondary coil L2s forming the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

Pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

The primary side coil forming the first transformer 301, the primary side coil forming the second transformer 302, the primary side coil forming the third transformer 303, and the primary side coil forming the fourth transformer 304 are are also not shown in this figure. However, the primary side coils basically have the same configuration as the secondary side coils L1s to L4s, respectively, and face the secondary side coils L1s to L4s, respectively. located directly below each.

That is, one end of the primary coil forming the first transformer 301 is connected to pads a5 and b5, and the other end of the primary coil is connected to pads c3 and d3. Pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

Pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are drawn from the inside of the transformer chip 300 to the surface via vias (not shown).

Of the plurality of pads, pads a1 to a8 respectively correspond to first current supply pads, and pads b1 to b8 respectively correspond to first voltage measurement pads. Pads c1 to c4 respectively correspond to second current supply pads, and pads d1 to d4 respectively correspond to second voltage measurement pads.

Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, in addition to rejecting defective products in which each coil is disconnected, it is also necessary to appropriately reject defective products in which the resistance value of each coil is abnormal (for example, a short circuit between coils). is possible, and by extension, it becomes possible to prevent the outflow of defective products to the market.

For the transformer chip 300 that has passed the defective product inspection, the plurality of pads may be used as connection means with the primary side chip and the secondary side chip (for example, the controller chip 210 and the driver chip 220 described above). .

Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input end or signal output end of the secondary chip, respectively. Pads c1 and d1 and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input end or signal output end of the primary chip, respectively. Pads c3 and d3 and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

Here, as shown in FIG. 9, the first to fourth transformers 301 to 304 are coupled and arranged for each signal transmission direction. Referring to this drawing, for example, a first transformer 301 and a second transformer 302 that transmit signals from the primary chip to the secondary chip are formed into a first pair by a first guard ring 305 . Also, for example, a third transformer 303 and a fourth transformer 304 that transmit signals from the secondary chip to the primary chip are formed into a second pair by a second guard ring 306 .

The reason for such coupling is that when the primary side coils and secondary side coils forming the first to fourth transformers 301 to 304 are laminated in the vertical direction of the substrate of the transformer chip 300, This is to ensure a withstand voltage between the primary coil and the secondary coil. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

It should be noted that the first guard ring 305 and the second guard ring 306 may be connected to low-impedance wiring such as ground terminals via pads e1 and e2, respectively.

Also, in the transformer chip 300, the pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Moreover, the pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Moreover, the pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Also, the pads c4 and d4 are shared with the corresponding primary coils. With such a configuration, the number of pads can be reduced, and the size of the transformer chip 300 can be reduced.

Further, as shown in FIG. 9, the primary coils and secondary coils forming the first to fourth transformers 301 to 304 are rectangular (or tracks with rounded corners) in plan view of the transformer chip 300 . shape). With such a configuration, the area of the portion where the primary side coil and the secondary side coil overlap becomes large, and it is possible to improve the transmission efficiency of the transformer.

Of course, the transformer arrangement in this figure is only an example, and the number, shape, and arrangement of coils and arrangement of pads are arbitrary. Also, the chip structure and transformer arrangement described so far can be applied to general semiconductor devices in which coils are integrated on a semiconductor chip.

<Electronic equipment>
FIG. 10 is a diagram showing a configuration example of an electronic device in which the signal transmission device 200 is installed. The electronic device A of this configuration example includes an upper gate driver IC 1H (u/v/w), a lower gate driver IC 1L (u/v/w), an upper power transistor 2H (u/v/w), and a lower gate driver IC 1L (u/v/w). It has a side power transistor 2L (u/v/w), an ECU 3, and a motor 4.

The upper gate driver IC1H (u/v/w) provides insulation between the ECU 3 and the upper power transistor 2H (u/v/w), and operates the upper gate according to an upper gate control signal input from the ECU 3. By generating a drive signal, the upper power transistor 2H (u/v/w) is driven.

The lower gate driver IC1L (u/v/w) provides insulation between the ECU 3 and the lower power transistor 2L (u/v/w), and responds to the lower gate control signal input from the ECU 3. to drive the lower power transistor 2L (u/v/w) by generating a lower gate drive signal.

As the upper gate driver IC1H (u/v/w) and the lower gate driver IC1L (u/v/w), the aforementioned signal transmission device 200 can be suitably used. In that case, the above upper gate control signal (or lower gate control signal) corresponds to the aforementioned input pulse signal IN, and the aforementioned upper gate drive signal (or lower gate drive signal) corresponds to the aforementioned gate signal VG. corresponds to

The upper power transistors 2H (u/v/w) serve as upper switches forming a three-phase (U-phase/V-phase/W-phase) half-bridge output stage, respectively. application end) and each phase input end of the motor 4 .

The lower power transistor 2L (u/v/w) is used as a lower switch forming a three-phase (U-phase/V-phase/W-phase) half-bridge output stage, and is connected to each phase input terminal of the motor 4. It is connected between the system ground terminal.

In this figure, IGBTs [insulated gate bipolar transistors] are used as the upper power transistor 2H (u/v/w) and the lower power transistor 2L (u/v/w). It is also possible to use a MOSFET [metal oxide semiconductor field effect transistor].

The ECU 3 generates the aforementioned input pulse signal IN and outputs it to the upper power transistor 2H (u/v /w) and the lower power transistor 2L (u/v/w) to control the rotation of the motor 4 .

The motor 4 is a three-phase motor that is rotationally driven according to three-phase drive voltages U/V/W respectively input from three-phase (U-phase/V-phase/W-phase) half bridge output stages.

<Signal transmission device (comparative example)>
FIG. 11 is a diagram showing a comparative example of the signal transmission device 200 (=general configuration for comparison with the embodiment described later). In this figure, buffers 212 and 213 (in this figure, inverters) and a buffer 221 and 222 (inverters in this figure), latches 225 and 226, and

transformers

231 and 232 are depicted.

The transformer 231 includes a primary side coil 231p and a secondary side coil 231s. The transformer 232 includes a primary side coil 232p and a secondary side coil 232s.

Focusing on the inside of the transformer chip 230, the first node of the primary coil 231p is connected to the external terminal T21. Both the second node of the primary coil 231p and the first node of the primary coil 232p are connected to the external terminal T22. A second node of the primary coil 232p is connected to the external terminal T23. A first node of the secondary coil 231s is connected to the external terminal T24. A second node of the secondary coil 231s and a first node of the secondary coil 232s are both connected to the external terminal T25. A second node of the secondary coil 232s is connected to the external terminal T26.

Looking at the outside of the transformer chip 230, the external terminal T21 is connected to the output terminal of the buffer 212. The external terminal T22 is connected to the ground terminal GND1. The external terminal T23 is connected to the output terminal of the buffer 213 . The external terminal T24 is connected to the input terminal of the buffer 221 . The external terminal T25 is connected to the ground terminal GND2. The external terminal T26 is connected to the input terminal of the buffer 222 .

The buffer 212 pulse-drives the primary coil 231p with the rising edge (=rising edge from low level to high level) of the input pulse signal IN as a trigger. On the other hand, the buffer 213 pulse-drives the primary coil 232p using the fall edge (=falling edge from high level to low level) of the input pulse signal IN as a trigger.

The

buffers

221 and 222 receive inputs of induced voltages generated in the

secondary coils

231s and 232s by pulse-driving the

primary coils

231p and 232p, respectively.

Latches

225 and 226 latch the logic levels of the received pulse signals output from

buffers

221 and 222, respectively.

Thus, the signal transmission device 200 of this comparative example transmits the rising edge and the falling edge of the input pulse signal IN with the two

transformers

231 and 232 . Such signal transmission operation is as described in detail so far.

<Discussion 1>
By the way, the signal transmission device 200 of this comparative example uses a so-called CMOS buffer circuit as pulse drive means for the

primary coils

231p and 232p. Therefore, there is room for further study on common-mode noise immunity.

In the following, in view of the above considerations, a novel embodiment that can improve the common-mode noise immunity of the signal transmission device 200 will be proposed.

<Signal transmission device (first embodiment)>
FIG. 12 is a diagram showing a first embodiment of the signal transmission device 200. As shown in FIG. The signal transmission device 200 of this embodiment includes a pulse receiving circuit 227 as means for receiving induced pulse signals generated in the

secondary coils

231s and 232s. It should be noted that the same reference numerals as in FIGS. 1, 2 and 11 are assigned to the components that have already been described to omit redundant description.

The pulse receiving circuit 227 includes constant current sources CC1r and CC1f, receivers RXr and RXf, a hysteresis comparator HC, resistors R2r and R2f, and capacitors Cr and Cf.

A first end of the capacitor Cr is connected to the external terminal T24 of the transformer chip 230. The second end of the capacitor Cr is connected to the application end of the node voltage VAr (=the input end of the receiver RXr). Capacitor Cf is connected to external terminal T26 of transformer chip 230 . The second end of the capacitor Cf is connected to the application end of the node voltage VAf (=input end of the receiver RXf). An external terminal T2 of the transformer chip 230 is connected to the ground terminal GND2. A resistor may be provided between the external terminal T24 and the capacitor Cr and between the external terminal T26 and the capacitor Cf.

The constant current source CC1r is connected between the application end of the power supply voltage VCC2 and the application end of the node voltage VAr, and generates a reference current I1r independent of the power supply voltage VCC2. The constant current source CC1f is connected between the application terminal of the power supply voltage VCC2 and the application terminal of the node voltage VAf, and generates a reference current I1f independent of the power supply voltage VCC2.

Receiver RXr receives input of added current I2r obtained by adding reception current Ir induced in secondary coil 231s of transformer 231 and reference current I1r generated by constant current source CC1r, and generates current signal I3r. . More specifically, receiver RXr includes transistors N1r and N2r (for example, N-channel MISFET) and transistors P1r and P2r (for example, P-channel MISFET).

The gate of the transistor N1r and the gate and drain of the transistor N2r are all connected to the node voltage VAr application end. The sources of the transistors N1r and N2r are both connected to the ground terminal GND2. The drain of transistor N1r is connected to the drain of transistor P1r.

The sources of the transistors P1r and P2r are both connected to the application terminal of the power supply voltage VCC2. The gates of the transistors P1r and P2r are both connected to the drain of the transistor P1r. The drain of the transistor P2r is connected to the application terminal of the voltage signal Vr. The transistors P1r and P2r connected in this manner function as a current mirror that generates a current signal I3r proportional to the drain current of the transistor P1r and outputs it from the drain of the transistor P2r.

Receiver RXf receives input of added current I2f obtained by adding reception current If induced in secondary coil 232s of transformer 232 and reference current I1f generated by constant current source CC1f, and generates current signal I3f. . Specifically, the receiver RXf includes transistors N1f and N2f (for example, N-channel MISFET) and transistors P1f and P2f (for example, P-channel MISFET).

The gate of the transistor N1f and the gate and drain of the transistor N2f are both connected to the node voltage VAf application end. The sources of the transistors N1f and N2f are both connected to the ground terminal GND2. The drain of transistor N1f is connected to the drain of transistor P1f.

The sources of the transistors P1f and P2f are both connected to the application terminal of the power supply voltage VCC2. The gates of the transistors P1f and P2f are both connected to the drain of the transistor P1f. The drain of the transistor P2f is connected to the application terminal of the voltage signal Vf. The transistors P1f and P2f connected in this way function as a current mirror that generates a current signal I3f proportional to the drain current of the transistor P1f and outputs it from the drain of the transistor P2f.

The resistor R2r (=corresponding to the first signal converter) is connected between the drain of the transistor P2r and the ground terminal GND2, and converts the current signal I3r into the voltage signal Vr (=I3r×R2r).

A resistor R2f (=corresponding to a second signal converter) is connected between the drain of the transistor P2f and the ground terminal GND2, and converts the current signal I3f into a voltage signal Vf (=I3f×R2f).

The hysteresis comparator HC includes a comparator CMP, resistors R3r and R3f, and transistors N3r and N3f (eg N-channel MISFET).

The non-inverting input terminal of the comparator CMP is connected to the application terminal of the voltage signal Vr. The inverting input terminal of the comparator CMP is connected to the application terminal of the voltage signal Vf. A non-inverting output terminal of the comparator CMP is connected to an application terminal of the output pulse signal OUT. The inverted output terminal of the comparator CMP is connected to the application terminal of the inverted output pulse signal OUTB.

A first end of the resistor R3r is connected to the non-inverting input end of the comparator CMP. A second end of the resistor R3r is connected to the drain of the transistor N3r. The source of the transistor N3r is connected to the ground terminal GND2. The gate of the transistor N3r is connected to the application end of the inverted output pulse signal OUTB.

A first end of the resistor R3f is connected to the inverting input end of the comparator CMP. A second end of the resistor R3f is connected to the drain of the transistor N3f. The source of the transistor N3f is connected to the ground terminal GND2. The gate of the transistor N3f is connected to the application end of the output pulse signal OUT.

The hysteresis comparator HC configured as described above compares the voltage signal Vr input to the non-inverting input terminal and the voltage signal Vf input to the inverting input terminal to obtain the output pulse signal OUT and the inverted output pulse signal OUTB (= A logic inversion signal of the output pulse signal OUT) is generated.

In line with this diagram, the hysteresis comparator HC sets the output pulse signal OUT to high level and the inverted output pulse signal OUTB to low level when the voltage signal Vr is higher than the voltage signal Vf. On the other hand, the hysteresis comparator HC sets the output pulse signal OUT to low level and the inverted output pulse signal OUTB to high level when the voltage signal Vr is lower than the voltage signal Vf.

Here, when the output pulse signal OUT is at low level and the inverted output pulse signal OUTB is at high level, the transistor N3r is turned on and the transistor N3f is turned off. As a result, Vr=I3r*(R2r//R3r) and Vf=I3f*R2f. Therefore, in order for the output pulse signal OUT to rise from the low level to the high level, it is necessary to satisfy I3r.times.(R2r//R3r)>I3f.times.R2f.

On the other hand, when the output pulse signal OUT is at high level and the inverted output pulse signal OUTB is at low level, the transistor N3r is turned off and the transistor N3f is turned on. As a result, Vr=I3r*R2r and Vf=I3f*(R2f//R3f). Therefore, in order for the output pulse signal OUT to fall from high level to low level, it is necessary to satisfy I3r×R2r>I3f×(R2f//R3f).

That is, the hysteresis comparator HC has hysteresis such that the threshold voltage is switched according to the output pulse signal OUT. With a configuration that generates the output pulse signal OUT and the inverted output pulse signal OUTB using such a hysteresis comparator HC, the

latches

225 and 226 of the comparative example can be omitted.

FIG. 13 is a diagram showing an example of the pulse reception operation in the pulse reception circuit 217 of the first embodiment. From top to bottom, input pulse signal IN, received current Ir, received current If, voltage signals Vr (solid line) and Vf. (broken line) and the output pulse signal OUT are depicted.

When the input pulse signal IN rises from low level to high level, the reception current Ir flows in a pulse shape. At this time, the added current I2r, which is the sum of the received current Ir and the reference current I1r, increases and the node voltage VAr rises. Therefore, the transistor N1r becomes more conductive and the current signal I3r increases. As a result, the voltage signal Vr (=I3r×(R2r//R3r)) becomes higher than the voltage signal Vf (=I3f×R2f), and the output pulse signal OUT rises from low level to high level. When the output pulse signal OUT rises to high level, the transistor N3r turns off and the transistor N3f turns on. Therefore, in the hysteresis comparator HC, the state in which the voltage signal Vr is lowered is released, and the state is switched to the state in which the voltage signal Vf is lowered.

On the other hand, when the input pulse signal IN falls from high level to low level, the reception current If flows in a pulse shape. At this time, the added current I2f obtained by adding the received current If and the reference current I1f increases, and the node voltage VAf rises. Therefore, the conductivity of the transistor N1f increases and the current signal I3f increases. As a result, the voltage signal Vr (=I3r×R2r) becomes higher than the voltage signal Vf (=I3f×(R2f//R3f)), and the output pulse signal OUT rises from high level to low level. When the output pulse signal OUT falls to low level, the transistor N3r turns on and the transistor N3f turns off. Therefore, in the hysteresis comparator HC, the state in which the voltage signal Vf is lowered is released, and the state is switched to the state in which the voltage signal Vr is lowered.

In this manner, the pulse receiving circuit 227 of this embodiment generates the voltage signals Vr and Vf according to the sum of the received currents Ir and If and the reference currents I1r and I1f, compares them, and outputs the pulse signal OUT. to generate

By adopting this configuration, common-mode noise can be removed through differential input to the hysteresis comparator HC, so it is possible to improve common-mode noise immunity. Further, unlike the comparative example (FIG. 11) described above, it is not necessary to use a CMOS buffer, so the responsiveness of the output pulse signal OUT to the input pulse signal IN can be improved.

<Discussion 2>
FIG. 14 is a diagram showing how undershoot occurs in the node voltages VAr and VAf. From top to bottom, the output pulse signal OUT, the ground voltage GND1, the node voltage VAr (solid line), and the node voltage VAf (broken line). Depicted.

By the way, in the pulse receiving circuit 227 of the first embodiment, undershoot may occur in the node voltages VAr and VAf when receiving a regular pulse based on the pulse edge of the input pulse signal IN (see dashed frame α). In addition, when common-mode noise (for example, common-mode noise associated with fluctuations in ground voltage GND1) is applied, node voltages VAr and VAf may undershoot (see dashed frame β).

In the following, in view of the above considerations, a novel embodiment is proposed in which the node voltages VAr and VAf are less likely to undershoot.

<Signal Transmission Device (Second Embodiment)>
FIG. 15 is a diagram showing a second embodiment of the signal transmission device 200. As shown in FIG. The signal transmission device 200 of this embodiment is based on the above-described first embodiment (FIG. 12), and further includes high-pass filters HPFr and HPFf and a subtractor SUB as components of the pulse receiving circuit 227 . In addition, description is abbreviate|omitted by attaching|subjecting the code|symbol same as FIG. 12 about an already-appearing component.

The high-pass filter HPFr is provided between the gates of the transistors P1r and P2r, and reduces the low frequency components of the received current Ir.

The high-pass filter HPFf is provided between the gates of the transistors P1f and P2f to reduce the low frequency components of the received current If.

The subtractor SUB subtracts the current signal I3f from the current signal I3f to generate a differential current signal (I3f-I3r) and differentially output it.

The resistor R2r converts the absolute value of the negative component of the differential current signal (I3f-I3r) into the voltage signal Vr. On the other hand, the resistor R2f converts the positive component of the differential current signal (I3f-I3r) into the voltage signal Vf.

FIG. 16 is a diagram showing how the undershoot of the node voltages VAr and VAf is improved. Similar to FIG. A voltage VAf (dashed line) is depicted.

Both the undershoots of the node voltages VAr and VAf are low frequency components compared to the regular pulse based on the pulse edge of the input pulse signal IN. Therefore, the undershoot of the node voltages VAr and VAf can be suppressed by providing the high-pass filters HPFr and HPFf having appropriate cutoff frequencies fc.

<Discussion 3>
By the way, the aforementioned receivers RXr and RXf receive inputs of the node voltages VAr and VAf at the respective gates of the N-channel type transistors N1r and N1f. However, when the level of common-mode noise superimposed on the node voltages VAr and VAf is high, the node voltages VAr and VAf swing to a negative potential lower than the ground voltage GND2, which interferes with the receiving operations of the receivers RXr and RXf. (see dashed box γ).

In the following, in view of the above considerations, a novel embodiment is proposed in which the receiving operations of the receivers RXr and RXf are less likely to be hindered even when the node voltages VAr and VAf swing to negative potentials.

<Signal transmission device (third embodiment)>
FIG. 17 is a diagram showing a third embodiment of the signal transmission device 200. As shown in FIG. The signal transmission device 200 of this embodiment is based on the above-described first embodiment (FIG. 12), but the receivers RXr and RXf are modified. In addition, description is abbreviate|omitted by attaching|subjecting the code|symbol same as FIG. 12 about an already-appearing component.

Referring to this figure, receiver RXr includes transistors N4r and N5r (for example, N-channel MISFET), transistors P3r to P6r (for example, P channel type MISFET). A capacitor Cr2 and a constant current source CC1r2 are added to the front stage of the receiver RXr.

A first end of the capacitor Cr2 is connected to the external terminal T24 of the transformer chip 230. The second end of the capacitor Cr2 and the first end of the constant current source CC1r2 are both connected to the gate of the transistor P5r and the gate and drain of the transistor P6r. A second end of the constant current source CC1r2 is connected to the ground terminal GND2. The sources of the transistors P5r and P6r are both connected to the application terminal of the power supply voltage VCC2. The drain of transistor P5r is connected to the drain of transistor N4r.

The sources of the transistors N4r and N5r are both connected to the application terminal of the ground terminal GND2. The gates of the transistors N4r and N5r are both connected to the drain of the transistor N4r. The drain of transistor N5r is connected to the drain of transistor P3r. The sources of the transistors P3r and P4r are both connected to the application terminal of the power supply voltage VCC2. The gates of the transistors P3r and P4r are both connected to the drain of the transistor P3r. The drain of the transistor P4r is connected to the application terminal of the voltage signal Vr.

On the other hand, the receiver RXf includes transistors N4f and N5f (for example, N-channel MISFET) and transistors P3f to P6f (for example, P-channel MISFET) in addition to the transistors N1f and N2f and the transistors P1f and P2f. include. Also, a capacitor Cf2 and a constant current source CC1f2 are added to the front stage of the receiver RXf.

A first end of the capacitor Cf2 is connected to the external terminal T26 of the transformer chip 230. The second end of the capacitor Cf2 and the first end of the constant current source CC1f2 are both connected to the gate of the transistor P5f and the gate and drain of the transistor P6f. A second end of the constant current source CC1f2 is connected to the ground terminal GND2. The sources of the transistors P5f and P6f are both connected to the application terminal of the power supply voltage VCC2. The drain of transistor P5f is connected to the drain of transistor N4f.

The sources of the transistors N4f and N5f are both connected to the application terminal of the ground terminal GND2. The gates of the transistors N4f and N5f are both connected to the drain of the transistor N4f. The drain of transistor N5f is connected to the drain of transistor P3f. The sources of the transistors P3f and P4f are both connected to the application terminal of the power supply voltage VCC2. The gates of the transistors P3f and P4f are both connected to the drain of the transistor P3f. The drain of the transistor P4f is connected to the application terminal of the voltage signal Vf.

As described above, in the signal transmission device 200 of the present embodiment, the receiver RXr receives the received pressure signal induced at the external terminal T24 at the gates of both the parallel-connected N-channel transistor N1r and P-channel transistor P5r. accept. Similarly, the receiver RXf receives the reception signal induced at the external terminal T26 at the gates of both the parallel-connected N-channel transistor N1f and P-channel transistor P5f.

With such a configuration, even if the node voltages VAr and VAf swing to negative potentials, the receiving operations of the receivers RXr and RXf are unlikely to be disturbed.

Although this diagram is based on the first embodiment (FIG. 12), it goes without saying that the high-pass filters HPFr and HPFf may be provided based on the second embodiment (FIG. 15).

<Discussion 4>
FIG. 18 is a diagram showing how an erroneous output of the output pulse signal OUT occurs. From the top, the input pulse signal IN, the received current If, the node voltage VAf, the voltage signal Vr (solid line), and the voltage signal Vf (broken line). , as well as the output pulse signal OUT.

As already mentioned above, when a regular pulse based on the pulse edge of the input pulse signal IN is received, the node voltages VAr and VAf may undershoot due to the capacitors Cr and Cf provided for input coupling. When such an undershoot occurs, the vertical relationship between the voltage signals Vr and Vf is unintentionally inverted, which may cause an abnormality in the logic level of the output pulse signal OUT.

For example, comparing the solid line (=error output) and the broken line (=normal output) of the output pulse signal OUT, after the output pulse signal OUT falls to low level, the voltage signal Vf is reduced due to the undershoot of the node voltage VAf. It can be seen that as a result of falling below the voltage signal Vr, the output pulse signal OUT returns to high level earlier than it should.

In the following, in view of the above considerations, a new embodiment is proposed in which erroneous output of the output pulse signal OUT is less likely to occur.

<Signal transmission device (fourth embodiment)>
FIG. 19 is a diagram showing a fourth embodiment of the signal transmission device 200. As shown in FIG. The signal transmission device 200 of this embodiment is based on the above-described first embodiment (FIG. 12), and further includes undershoot suppressors USSr and USSf as components of the pulse receiving circuit 227 . In addition, description is abbreviate|omitted by attaching|subjecting the code|symbol same as FIG. 12 about an already-appearing component.

The undershoot suppression unit USSr includes a constant current source CC2r, a delay unit DLYr, transistors N6r and N7r (N-channel MISFETs in this figure), and an AND gate ANDr.

A first end of the constant current source CC2r is connected to the application end of the power supply voltage VCC2. A second end of the constant current source CC2r is connected to the drain of the transistor N6r and the gate and drain of the transistor N7r. The source of the transistor N6r is connected to the application terminal of the node voltage VAr. The source of the transistor N7r is connected to the ground terminal GND2. The gate of the transistor N6r is connected to the application terminal of the node voltage VBr. Note that the constant current source CC2r may be replaced with a resistor, for example.

The delay unit DLYr generates a delayed inverted output pulse signal OUTBd by delaying the inverted output pulse signal OUTB by the delay time tdr. That is, the delayed inverted output pulse signal OUTBd rises to a high level when the delay time tdr has passed since the inverted output pulse signal OUTB rises to a high level, and the delayed inverted output pulse signal OUTBd rises to a high level after the inverted output pulse signal OUTB has fallen to a low level. Falls to a low level when tdr has elapsed.

The AND gate ANDr generates the node voltage VBr by performing a logical AND operation of the delayed inverted output pulse signal OUTBd and the inverted input inverted output pulse signal OUTB (=corresponding to the output pulse signal OUT). That is, the node voltage VBr becomes low level when at least one of the delayed inverted output pulse signal OUTBd and the output pulse signal OUT is at low level, and both the delayed inverted output pulse signal OUTBd and the output pulse signal OUT are at high level. sometimes high level.

When the node voltage VBr is at low level, the transistor N6r is turned off, so that the constant current source CC2r is disconnected from the node voltage VAr application terminal. On the other hand, when the node voltage VBr is at a high level, the transistor N6r is turned on, so that the constant current source CC2r is electrically connected to the application end of the node voltage VAr.

The undershoot suppression unit USSr of this configuration example keeps the input node (=node voltage VAr application end) in the receiver RXr for a predetermined period (=delay time tdr) after the output pulse signal OUT rises from low level to high level. ) impedance.

The undershoot suppression unit USSf includes a constant current source CC2f, a delay unit DLYf, transistors N6f and N7f (N-channel MISFETs in this figure), and a logical AND gate ANDf.

A first end of the constant current source CC2f is connected to the application end of the power supply voltage VCC2. A second end of the constant current source CC2f is connected to the drain of the transistor N6f and the gate and drain of the transistor N7f. The source of the transistor N6f is connected to the application terminal of the node voltage VAf. The source of the transistor N7f is connected to the ground terminal GND2. The gate of the transistor N6f is connected to the application end of the node voltage VBf. Note that the constant current source CC2f may be replaced with a resistor, for example.

The delay unit DLYf generates a delayed output pulse signal OUTd by delaying the output pulse signal OUT by the delay time tdf. That is, the delayed output pulse signal OUTd rises to high level when the delay time tdf elapses after the output pulse signal OUT rises to high level, and the delay time tdf elapses after the output pulse signal OUT falls to low level. Falls to low level when

The logical AND gate ANDf generates the node voltage VBf by logical AND operation of the delayed output pulse signal OUTd and the inverted input output pulse signal OUT (=corresponding to the inverted output pulse signal OUTB). That is, the node voltage VBf becomes low level when at least one of the delayed output pulse signal OUTd and the inverted output pulse signal OUTB is at low level, and both the delayed output pulse signal OUTd and the inverted output pulse signal OUTB are at high level. sometimes high level.

When the node voltage VBf is at low level, the transistor N6f is turned off, so that the constant current source CC2f is cut off from the node voltage VAf application end. On the other hand, when the node voltage VBf is at a high level, the transistor N6f is turned on, so that the constant current source CC2f is electrically connected to the application end of the node voltage VAf.

The undershoot suppression unit USSf of this configuration example applies the input node (=node voltage VAf) in the receiver RXf for a predetermined period (=delay time tdf) after the output pulse signal OUT falls from high level to low level. end) to lower the impedance.

In this figure, the first embodiment (FIG. 12) is used as the basis, but the second embodiment (FIG. 15) or the third embodiment (FIG. 17) may be used as the basis.

FIG. 20 is a diagram showing how the erroneous output of the output pulse signal OUT is improved. From the top, the input pulse signal IN, the received current If, the node voltage VAf, the voltage signal Vr (solid line), and the voltage signal Vf (broken line). , the output pulse signal OUT, and the node voltage VBf are depicted.

Regarding the node voltage VAf and the output pulse signal OUT, the solid line indicates the behavior when the undershoot suppression unit USSf is provided, and the dashed line indicates the behavior when the undershoot suppression unit USSf is not provided.

As shown in the figure, when the input pulse signal IN falls from high level to low level, the node voltage VBf rises to high level over a predetermined period (=delay time tdf). At this time, the transistor N6f is turned on, so that the constant current source CC2f is electrically connected to the application end of the node voltage VAf.

Therefore, the impedance of the input node (=the end to which the node voltage VAf is applied) in the receiver RXf is lowered, so that the undershoot of the node voltage VAf can be suppressed, and the voltage value can be stabilized quickly (the node voltage VAf and the solid line see dashed line).

In addition, by suppressing the undershoot of the node voltage VAf, unintended inversion of the voltage signals Vr and Vf is less likely to occur, so it is possible to prevent the output pulse signal OUT (see the solid line and broken line of the output pulse signal OUT). ).

In addition, in this figure, the description has been given focusing only on the suppression of the undershoot of the node voltage VAf, but the same applies to the undershoot of the node voltage VAr.

<Discussion 5>
FIG. 21 is a diagram showing how in-phase noise is superimposed at the reception timing of regular pulses, and depicts reception currents Ir and If. Note that the solid line in the figure indicates the common-mode noise, and the broken line indicates the normal pulse.

As shown in this figure, when in-phase noise is superimposed at the reception timing of regular pulses, the + and - components of the reception currents Ir and If become the same, resulting in a total of 0. Therefore, there is a possibility that the receiving operation will be hindered.

In the following, in view of the above considerations, a new embodiment is proposed in which reception operation is less likely to be hindered even when in-phase noise is superimposed at the reception timing of regular pulses.

<Signal transmission device (fifth embodiment)>
FIG. 22 is a diagram showing a fifth embodiment of the signal transmission device 200. As shown in FIG. The signal transmission device 200 of the present embodiment includes a pulse receiving circuit 228 as means for receiving inputs of received currents Ir and If and generating an output pulse signal OUT.

The pulse receiving circuit 228 includes high-pass filters HPFr and HPFf, subtractors SUBr and SUBf, positive component extractors PEXr and PEXf, and a hysteresis comparator HC.

The high-pass filter HPFr reduces the low-frequency component of the received current Ir induced in the secondary coil 231s of the transformer 231 to generate the first filter output signal IrF (=corresponding to the current signal I3r in FIG. 17).

The high-pass filter HPFf reduces the low-frequency component of the received current If induced in the secondary coil 232s of the transformer 232 to generate the second filter output signal IfF (=corresponding to the current signal I3f in FIG. 17).

A subtractor SUBr subtracts the second filter output signal IfF from the first filter output signal IrF to generate a first difference signal IrF-IfF.

A subtractor SUBf subtracts the first filter output signal IrF from the second filter output signal IfF to generate a second difference signal IfF-IrF.

The positive component extraction unit PEXr is provided between the subtractor SUBr and the inverting input terminal (-) of the hysteresis comparator HC, and extracts only the positive component of the first difference signal IrF−IfF to obtain the voltage signal Vr (=th 1 extraction signal).

The positive component extraction unit PEXf is provided between the subtractor SUBf and the non-inverting input terminal (+) of the hysteresis comparator HC, and extracts only the positive component of the second difference signal IfF-IrF to obtain the voltage signal Vf (= corresponding to the second extraction signal).

It should be noted that the subtractors SUBr and SUBf and the positive component extractors PEXr and PEXf may be collectively understood as the subtractor SUB in FIG.

The hysteresis comparator HC compares the voltage signal Vr input to the non-inverting input terminal (+) and the voltage signal Vf input to the inverting input terminal (-) to generate the output pulse signal OUT.

In this way, after obtaining the first difference signal IrF-IfF and the second difference signal IfF-IrF by calculating the difference between the reception currents Ir and If, only the positive components of each are extracted, thereby determining the reception timing of the regular pulse. Even when in-phase noise is superimposed at , a desired regular pulse component can be extracted. Therefore, it is possible to generate a correct output pulse signal OUT without interfering with the receiving operation.

<Application to vehicles>
FIG. 23 is an external view showing one configuration example of the vehicle X10. A vehicle X10 of this configuration example is equipped with a battery (not shown in the figure) and various electronic devices X11 to X18 that operate with power supplied from the battery.

In addition to the engine vehicle, the vehicle X10 includes an electric vehicle (BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV/PHV (plug-in hybrid electric vehicle/plug-in hybrid vehicle), or FCEV/FCV (xEV such as fuel cell electric vehicle/fuel cell vehicle]) is also included.

Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 performs engine-related control (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.) or motor-related control (torque control, power regeneration control, etc.). It is an electronic control unit that performs

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamp] and DRL [daytime running lamp].

The electronic device X13 is a transmission control unit that performs controls related to the transmission.

The electronic device X14 is a braking unit that performs control related to the movement of the vehicle X10 (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that controls the driving of door locks and security alarms.

The electronic equipment X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, etc., which are built into the vehicle X10 at the factory shipment stage as standard equipment or manufacturer options. is.

The electronic device X17 is an electronic device arbitrarily attached to the vehicle X10 as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device equipped with a high withstand voltage motor, such as an in-vehicle blower, oil pump, water pump, and battery cooling fan.

Note that the electronic devices X11 to X18 can be understood as specific examples of the electronic device A described above. That is, the signal transmission device 200 described above can be incorporated in any of the electronic devices X11 to X18.

<Summary>
The following provides a general description of the various embodiments described above.

For example, the pulse receiver circuit disclosed herein includes a first constant current source configured to generate a first reference current and a second constant current source configured to generate a second reference current. a first receiver configured to sum a first received current induced in a secondary coil of the first transformer and the first reference current to produce a first current signal; and a second transformer. a second receiver configured to sum a second received current induced in the secondary coil of the second receiver and the second reference current to generate a second current signal; a first signal converter configured to convert the second current signal into a signal; a second signal converter configured to convert the second current signal into a second voltage signal; the first voltage signal and the second voltage signal; A configuration (first configuration) is provided with a comparator configured to compare voltage signals and generate an output pulse signal.

In the pulse receiving circuit having the first configuration, the comparator may have a configuration (second configuration) having hysteresis so that the threshold is switched according to the output pulse signal.

Further, the pulse receiving circuit having the first or second configuration includes a first high-pass filter configured to reduce low-frequency components of the first received current, and a low-frequency component of the second received current. A configuration (third configuration) further including a second high-pass filter configured to

Further, in the pulse receiving circuit having any one of the first to third configurations, the first receiver and the second receiver are gates of both N-channel transistors and P-channel transistors connected in parallel, respectively, from the previous stage. may be configured (fourth configuration) to receive the signal of .

Further, in the pulse receiving circuit having any one of the first to fourth configurations, the input node in the first receiver is maintained for a predetermined period after the output pulse signal is switched from the first logic level to the second logic level. a first undershoot suppressor configured to reduce impedance; and an input node in the second receiver for a predetermined period after the output pulse signal switches from the second logic level to the first logic level. A configuration (fifth configuration) that further includes a second undershoot suppressing section that is configured to lower the impedance may be employed.

Also, for example, the pulse receiving circuit disclosed in this specification reduces the low frequency component of the first received current induced in the secondary coil of the first transformer to generate the first filter output signal. and a second high-pass filter configured to reduce low-frequency components of the second received current induced in the secondary coil of the second transformer to generate a second filter output signal. a highpass filter; a first subtractor configured to subtract the second filter output signal from the first filter output signal to produce a first difference signal; and the first filter output from the second filter output signal. a second subtractor configured to subtract a signal to produce a second difference signal; and a first subtractor configured to extract only the positive component of the first difference signal to produce a first extracted signal. a positive component extraction unit; a second positive component extraction unit configured to generate a second extraction signal by extracting only a positive component of the second difference signal; the first extraction signal and the second extraction; and a comparator configured to generate an output pulse signal by comparing with the signal (sixth configuration).

Further, for example, the signal transmission device disclosed in this specification includes a pulse transmission circuit configured to receive an input pulse signal and generate a transmission pulse signal; a pulse receiving circuit according to any one of the first to sixth configurations configured to generate an output pulse signal; and the receiving of the transmission pulse signal while insulating between the pulse transmitting circuit and the pulse receiving circuit. and a transformer configured to transmit as a pulse signal (seventh configuration).

The signal transmission device according to the seventh configuration includes a first chip integrated with the pulse transmission circuit, a second chip integrated with the pulse reception circuit, a third chip integrated with the transformer, may be sealed in a single package (eighth configuration).

Further, for example, an electronic device disclosed in this specification includes a switch element configured to be driven by the output pulse signal, and a signal transmission device according to the seventh or eighth configuration. configuration (ninth configuration).

Further, for example, the vehicle disclosed in this specification is configured to include the electronic device according to the ninth configuration (tenth configuration).

<Other Modifications>
In addition to the above embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. For example, the mutual replacement of bipolar transistors with MOS field effect transistors and the logic level inversion of various signals are optional. That is, the above embodiments should be considered as examples in all respects and not restrictive, and the technical scope of the present invention is defined by the scope of the claims, It should be understood that all changes that come within the meaning and range of equivalency of the claims are included.

1H (u/v/w) Upper gate driver IC
1L (u/v/w) lower gate driver IC
2H (u/v/w) Upper power transistor 2L (u/v/w) Lower power transistor 3 ECU
4 motor 5 semiconductor device 11, 11A to 11F low potential terminal 12, 12A to 12F high potential terminal 21, 21A to 21D transformer (transformer)
22 Low potential coil (primary coil)
23 High potential coil (secondary coil)
24 first inner end 25 first outer end 26 first helix 27 second inner end 28 second outer end 29 second helix 31 first low potential wire 32 second low potential wire 33 first high potential wire 34 second 2 high-potential wiring 41 semiconductor chip 42 first main surface 43 second main surface 44A to 44D chip sidewall 45 first functional device 51 insulating layer 52 insulating main surface 53A to 53D insulating sidewall 55 bottom insulating layer 56 top insulating layer 57 interlayer Insulating layer 58 First insulating layer 59 Second insulating layer 60 Second functional device 61 Seal conductor 62 Device region 63 Outer region 64 Seal plug conductor 65 Seal via conductor 66 First inner region 67 Second inner region 71 Penetration wire 72 Low potential connection Wiring 73 Lead Wiring 74 First Connection Plug Electrode 75 Second Connection Plug Electrode 76 Pad Plug Electrode 77 Substrate Plug Electrode 78 First Electrode Layer 79 Second Electrode Layer 80 Wiring Plug Electrode 81 High Potential Connection Wiring 82 Pad Plug Electrode 85 Dummy Pattern 86 high-potential dummy pattern 87 first high-potential dummy pattern 88 second high-potential dummy pattern 89 first region 90 second region 91 third region 92 first connecting portion 93 first pattern 94 second pattern 95 third pattern 96 second 1 outer peripheral line 97 second outer peripheral line 98 first intermediate line 99 first connection line 100 slit 130 separation structure 140 inorganic insulating layer 141 first inorganic insulating layer 142 second inorganic insulating layer 143 low potential pad opening 144 high potential pad opening 145 Organic insulating layer 146 First part 147 Second part 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p Primary circuit system 200s Secondary circuit system 210 Controller chip (first chip)
211 pulse transmission circuit (pulse generator)
212, 213 buffer 220 driver chip (second chip)
221, 222 buffer 223 pulse receiving circuit (RS flip-flop)
224

driver

225, 226 latch 227 pulse receiving circuit 230 transformer chip (third chip)
230a First wiring layer (lower layer)
230b Second wiring layer (upper layer)
231, 232

transformers

231p, 232p

primary coils

231s, 232s secondary coils 300 transformer chip 301 first transformer 302 second transformer 303 third transformer 304 fourth transformer 305 first guard ring 306 second guard ring a1 to a8 pads (Equivalent to the first current supply pad)
b1 to b8 pads (corresponding to the first voltage measurement pads)
c1 to c4 pads (equivalent to second current supply pads)
d1 to d4 pads (equivalent to second voltage measurement pads)
e1, e2 Pad A Electronic device ANDr, ANDf AND gate Cr, Cr2, Cf, Cf2 Capacitor CC1r, CC1r2, CC2r, CC1f, CC1f2, CC2f Constant current source CMP Comparator DLYr, DLYf Delay block HC Hysteresis comparator HPFr, HPFf High pass Filter L1p, L2p Primary side coil L1s, L2s, L3s, L4s Secondary side coil N1r~N7r, N1f~N7f Transistor (N channel type MISFET)
P1r-P6r, P1f-P6f Transistors (P-channel MISFET)
PEXr, PEXf Positive component extractor R2r, R2f Resistor (equivalent to signal converter)
R3r, R3f Resistance RXr, Rxf Receiver SUB, SUBr, SUBf Subtractor T21, T22, T23, T24, T25, T26 External terminal USSr, USSf Undershoot suppressor X First direction X10 Vehicle X11 to X18 Electronic device X21, X22, X23 Internal terminal Y Second direction Y21, Y22, Y23 Wiring Z Normal direction Z21, Z22, Z23 Via

Claims

a first constant current source configured to generate a first reference current;
a second constant current source configured to generate a second reference current;
a first receiver configured to sum a first received current induced in a secondary coil of a first transformer and the first reference current to generate a first current signal;
a second receiver configured to sum a second received current induced in a secondary coil of a second transformer and the second reference current to generate a second current signal;
a first signal converter configured to convert the first current signal to a first voltage signal;
a second signal converter configured to convert the second current signal to a second voltage signal;
a comparator configured to compare the first voltage signal and the second voltage signal to generate an output pulse signal;
A pulse receiver circuit.
2. The pulse receiving circuit according to claim 1, wherein said comparator has hysteresis such that a threshold is switched according to said output pulse signal.
a first high pass filter configured to reduce low frequency components of the first receive current;
a second high pass filter configured to reduce low frequency components of the second receive current;
3. The pulse receiver circuit of claim 1 or 2, further comprising:
4. The first receiver and the second receiver according to any one of claims 1 to 3, wherein the gates of both the N-channel type transistor and the P-channel type transistor connected in parallel receive the signal from the preceding stage, respectively. Pulse receiver circuit.
a first undershoot suppression unit configured to reduce impedance of an input node in the first receiver for a predetermined period after the output pulse signal switches from the first logic level to the second logic level;
a second undershoot suppression unit configured to reduce impedance of an input node in the second receiver for a predetermined period after the output pulse signal switches from the second logic level to the first logic level;
The pulse receiving circuit according to any one of claims 1 to 4, further comprising:
a first high-pass filter configured to reduce low-frequency components of the first received current induced in the secondary coil of the first transformer to generate a first filter output signal;
a second high pass filter configured to reduce low frequency components of the second receive current induced in the secondary coil of the second transformer to produce a second filter output signal;
a first subtractor configured to subtract the second filtered output signal from the first filtered output signal to produce a first difference signal;
a second subtractor configured to subtract the first filtered output signal from the second filtered output signal to produce a second difference signal;
a first positive component extractor configured to generate a first extracted signal by extracting only a positive component of the first difference signal;
a second positive component extractor configured to generate a second extracted signal by extracting only the positive component of the second difference signal;
a comparator configured to compare the first extracted signal and the second extracted signal to generate an output pulse signal;
A pulse receiver circuit.
a pulse transmission circuit configured to receive an input pulse signal and generate a transmission pulse signal;
a pulse receiving circuit according to any one of claims 1 to 6, configured to receive an input of a received pulse signal and generate an output pulse signal;
a transformer configured to transmit the transmission pulse signal as the reception pulse signal while insulating between the pulse transmission circuit and the pulse reception circuit;
A signaling device comprising:
a first chip integrated with the pulse transmission circuit;
a second chip integrated with the pulse receiving circuit;
a third chip integrated with the transformer;
8. The signal transmission device according to claim 7, wherein the are sealed in a single package.
a switch element configured to be driven by the output pulse signal;
A signal transmission device according to claim 7 or 8;
An electronic device.
A vehicle comprising the electronic device according to claim 9.