WO2023160047A1

WO2023160047A1 - Register, central processing unit and electronic device

Info

Publication number: WO2023160047A1
Application number: PCT/CN2022/133307
Authority: WO
Inventors: 钟建福; 李梅; 廖家兴
Original assignee: 华为技术有限公司
Priority date: 2022-02-28
Filing date: 2022-11-21
Publication date: 2023-08-31
Also published as: CN116707513A

Abstract

Provided in the present application are a register, a central processing unit and an electronic device. The register comprises a first latch, a second latch and a logic gate, wherein an input end of the first latch is connected to a clock signal input end, a data input end, and an output end of the logic gate; an output end of the first latch is connected to an input end of the second latch; and an output end of the second latch is connected to a data output end. An input end of the logic gate is connected to the data input end and the data output end, and the output end of the logic gate is connected to the first latch. When the potential of the data input end is the same as the potential of the data output end, the logic gate can control the output potential of the first latch to be the same as the potential of the data output end, such that signal flipping of the clock signal input end does not cause flipping of a node inside the register, and accordingly the power consumption of the flipping of a clock signal inside the register can be reduced.

Description

A kind of register, central processing unit and electronic equipment

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 202210188236.7 and the application title "a register, a central processing unit and an electronic device" filed with the China Patent Office on February 28, 2022, the entire contents of which are incorporated herein by reference In this application.

technical field

The present application relates to the field of electronic technology, in particular to a register, a central processing unit and electronic equipment.

Background technique

Registers are some small storage areas inside the central processing unit (Central Processing Unit, CPU) used to store data, and are used to temporarily store the data and results involved in the calculation. Registers are also a functional unit that consumes a large proportion of power consumption in the central processing unit, usually accounting for 20% to 30% of the power consumption of digital modules.

However, the current register mostly adopts the master-slave latch (master-slave latch) structure as shown in Figure 1. The two latches latch data at the rising and falling edges of the clock signal CP0 respectively. This structure It has the advantage of small area, but it needs to use the clock buffer to generate two-phase clock signals to drive the master latch and the slave latch respectively. Regardless of whether the input data D0 is refreshed, the clock signal CP0 is driving the master latch or the slave latch. The memory is used to sample data, which often does useless work, resulting in consumption of power consumption. Some data show that in terms of dynamic power consumption, the power consumed by the clock signal flipping CP0 inside the register accounts for 80% of the dynamic power consumption of the register. Therefore, reducing the power consumption of the clock signal CP0 flipping inside the register can effectively reduce the power consumption of the register. power consumption.

Contents of the invention

The application provides a register, a central processing unit and electronic equipment, which are used to reduce the power consumption of the register.

In a first aspect, an embodiment of the present application provides a register, and the register may include a first latch, a second latch, a logic gate, a clock signal input terminal, a data input terminal, and a data output terminal. The input end of the first latch is respectively connected with the output end of clock signal input end, data input end and logic gate, the output end of the first latch is connected with the input end of the second latch, and the second latch The output terminal is connected to the data output terminal. Wherein, the first latch is used to realize data latching or punch-through under the control of the clock signal input terminal, and the second latch is used to realize data punch-through or latching, thereby realizing the basic function of the register. The input terminals of the logic gate are respectively connected to the data input terminal and the data output terminal, and the output terminals of the logic gate are connected to the first latch; the logic gate can be used to control the first latch when the potentials of the data input terminal and the data output terminal are the same The potential of the register output is the same as the potential of the data output terminal. In this way, when the potentials of the data input terminal and the data output terminal are the same, since the logic gate controls the potential output of the first latch to be the same as the potential of the data output terminal, the signal inversion of the clock signal input terminal will not cause the inversion of the internal nodes of the register, and then it can be Reduce the power consumption of register internal clock signal toggling.

It should be noted that the connection between two terminals mentioned in this application includes, but is not limited to, direct electrical connection, or coupling through other electrical devices.

The present application will be described in detail below in combination with specific embodiments. It should be noted that, this embodiment is for better explaining the present application, but not limiting the present application.

Exemplarily, the logic gate is specifically used to output a signal of a second potential when the potentials of the data input terminal and the data output terminal are both the first potential, so as to control the potential of the output terminal of the first latch to be the first potential, and the first potential and The second potential is a different potential.

In one of the embodiments, the logic gate can be specifically used to output a high potential signal from the output terminal of the logic gate to control the output terminal of the first latch when the potentials of the data input terminal and the data output terminal are both low potential. Potential is low potential.

Exemplarily, the logic gate may include a first NOR gate, and the first latch may include a second NOR gate; the input ends of the first NOR gate are respectively connected to the data input end and the data output end, and the second OR The input terminals of the NOT gate are respectively connected with the data input terminal and the output terminal of the first NOR gate, and the output terminals of the second NOR gate are connected with the output terminal of the first latch. In this way, when both the data input terminal and the data output terminal are at low potential, the output terminal of the first NOR gate is at high potential. When the output terminal of the first NOR gate is at high potential, no matter whether the potential at the data input terminal is high potential or low potential, the output terminal of the second NOR gate will output low potential, so that the potential at the output terminal of the first latch for low potential. In this way, when the signal at the input end of the clock signal is reversed, the signal output from the first latch to the second latch is always kept at a low potential, and the internal nodes of the second latch will not be reversed, thereby reducing the internal clock signal of the register. Flip power consumption.

In a feasible implementation manner, the register may further include a first transistor, and the first latch may further include a first logic control circuit and an AND gate. The first logic control circuit may include a second transistor, a third transistor, a fourth transistor and a fifth transistor. Wherein, the first transistor, the second transistor and the third transistor are all P-type transistors, and the fourth transistor and the fifth transistor are N-type transistors.

The gate of the first transistor is connected to the clock signal input end, the first electrode of the first transistor is connected to the first reference voltage end, the second electrode of the first transistor is connected to the first node of the register; the first electrode of the second transistor connected to the first node, the gate of the second transistor is connected to the second node of the register, the second electrode of the second transistor is connected to the fifth node of the register; the first electrode of the third transistor is connected to the first reference voltage terminal, The gate of the third transistor is connected to the third node of the register, the second electrode of the third transistor is connected to the fifth node; the first electrode of the fourth transistor is connected to the fifth node, and the gate of the fourth transistor is connected to the third node The second electrode of the fourth transistor is connected to the first electrode of the fifth transistor; the gate of the fifth transistor is connected to the second node, and the second electrode of the fifth transistor is connected to the second reference voltage terminal. The input end of the AND gate is connected with the fifth node and the clock signal input end respectively, and the output end of the AND gate is connected with the input end of the second NOR gate; the second node is connected with the data input end, and the third node is connected with the first latch connected to the output of the device. Wherein, the second reference voltage terminal is grounded, and the potential of the first reference voltage terminal is greater than the potential of the second reference voltage terminal.

Further, the second latch can control the circuit and the first inverter with a second logic. The second logic control circuit may include a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor. Wherein, both the sixth transistor and the seventh transistor are P-type transistors, and the eighth transistor and the ninth transistor are both N-type transistors. The first electrode of the sixth transistor is connected to the first node, the gate of the sixth transistor is connected to the third node, the second electrode of the sixth transistor is connected to the sixth node of the register; the first electrode of the seventh transistor is connected to the first The reference voltage terminal is connected, the gate of the seventh transistor is connected to the fourth node of the register, the second electrode of the seventh transistor is connected to the sixth node of the register; the first electrode of the eighth transistor is connected to the sixth node, and the eighth transistor The gate of the eighth transistor is connected to the fourth node, the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor; the gate of the ninth transistor is connected to the third node, and the second electrode of the ninth transistor is connected to the second reference voltage The input end of the first inverter is connected to the sixth node, the output end of the first inverter is connected to the fourth node, and the fourth node is connected to the data output end.

Exemplarily, in order to improve the stability of the register, in the register, the first latch may further include a tenth transistor, an eleventh transistor and a second inverter. Wherein, both the tenth transistor and the eleventh transistor are N-type transistors. The input end of the second inverter is connected to the fifth node, and the output end of the second inverter is connected to the gate of the tenth transistor; the first electrode of the tenth transistor is respectively connected to the second electrode of the fourth transistor and the fifth node. The first electrode of the transistor is connected, the second electrode of the tenth transistor is connected with the first electrode of the eleventh transistor; the gate of the eleventh transistor is connected with the clock signal input end, the second electrode of the eleventh transistor is connected with the sixth node connection.

In a feasible embodiment, in order to realize that when the clock signal input terminal is at a high potential, the first latch latches data, and the second latch transmits data, and when the clock signal input terminal is at a low potential, the first latch One latch latches data, the second latch transmits data, and the register also includes a third inverter and a fourth inverter; the input end of the third inverter is connected to the data input end, and the third inverter The output end of the fourth inverter is connected to the second node, the input end of the fourth inverter is connected to the fourth node, and the output end of the fourth inverter is connected to the data output end. In this register, only a single-phase clock signal is required, that is, no clock buffer is required inside the register, and the pass-through and latching of the first latch and the second latch are directly controlled by the high and low potentials of the clock signal input terminal. . And the clock signal input terminal controls a total of 4 transistors, and the number of transistors controlled by the clock signal input terminal is small, which can reduce the input capacitance of the clock signal input terminal, thereby reducing the impact on the clock tree at the back end, thereby reducing the physical implementation subsequent clock tree power consumption.

It should be noted that, in this application, when the gate of an N-type transistor is at a high potential, the transistor is in an on state, and when the gate is at a low potential, the transistor is in an off state. When the gate of the P-type transistor is at a low potential, the transistor is in an on state, and when the gate is at a high potential, the transistor is in an off state. In addition, in the present application, the first electrode of the transistor may be the source or the drain, and the second electrode may be the drain or the source, which is not limited herein.

In another embodiment, the logic gate can be specifically used to output a signal with a low potential at the output terminal of the logic gate to control the potential at the output terminal of the first latch to be high potential.

Exemplarily, the logic gate may include a first NAND gate, and the first latch may include a second NAND gate; the input terminals of the first NAND gate are respectively connected to the data input terminal and the data output terminal, and the second The input end of the NAND gate is respectively connected with the data input end and the output end of the first NAND gate, and the output end of the second NAND gate is connected with the output end of the first latch. In this way, when both the data input terminal and the data output terminal are at high potential, the output terminal of the first NOR gate is at low potential. When the output terminal of the first NOR gate is low potential, no matter whether the potential of the data input terminal is high potential or low potential, the output terminal of the second NOR gate will output high potential, so that the potential of the output terminal of the first latch for high potential. In this way, when the signal at the input end of the clock signal is reversed, the signal output from the first latch to the second latch is always kept at a high potential, and the internal nodes of the second latch will not be reversed, thereby reducing the internal clock signal of the register. Flip power consumption.

In a feasible implementation manner, the register may further include a first transistor, and the first latch may further include a first logic control circuit and an OR gate. The first logic control circuit may include a second transistor, a third transistor, a fourth transistor and a fifth transistor. Wherein, the first transistor, the second transistor and the third transistor are all N-type transistors, and the fourth transistor and the fifth transistor are P-type transistors. The gate of the first transistor is connected to the clock signal input end, the first electrode of the first transistor is connected to the first reference voltage end, the second electrode of the first transistor is connected to the first node of the register; the first electrode of the second transistor connected to the first node, the gate of the second transistor is connected to the second node of the register, the second electrode of the second transistor is connected to the fifth node of the register; the first electrode of the third transistor is connected to the first reference voltage terminal, The gate of the third transistor is connected to the third node of the register, the second electrode of the third transistor is connected to the fifth node; the first electrode of the fourth transistor is connected to the fifth node, and the gate of the fourth transistor is connected to the third node The second electrode of the fourth transistor is connected to the first electrode of the fifth transistor; the gate of the fifth transistor is connected to the second node, and the second electrode of the fifth transistor is connected to the second reference voltage terminal. The input end of the OR gate is connected with the fifth node and the clock signal input end respectively, and the output end of the OR gate is connected with the input end of the second NOR gate; the second node is connected with the data input end, and the third node is connected with the first latch connected to the output of the device. Wherein, the first reference voltage terminal is grounded, and the potential of the second reference voltage terminal is greater than that of the first reference voltage terminal.

Further, the second latch can control the circuit and the first inverter with a second logic. The second logic control circuit may include a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. Wherein, both the sixth transistor and the seventh transistor are N-type transistors, and the eighth transistor and the ninth transistor are both P-type transistors. The first electrode of the sixth transistor is connected to the first node, the gate of the sixth transistor is connected to the third node, the second electrode of the sixth transistor is connected to the sixth node of the register; the first electrode of the seventh transistor is connected to the first The reference voltage terminal is connected, the gate of the seventh transistor is connected to the fourth node of the register, the second electrode of the seventh transistor is connected to the sixth node of the register; the first electrode of the eighth transistor is connected to the sixth node, and the eighth transistor The gate of the eighth transistor is connected to the fourth node, the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor; the gate of the ninth transistor is connected to the third node, and the second electrode of the ninth transistor is connected to the second reference voltage The input end of the first inverter is connected to the sixth node, the output end of the first inverter is connected to the fourth node, and the fourth node is connected to the data output end.

Exemplarily, in order to improve the stability of the register, in the register, the first latch may further include a tenth transistor, an eleventh transistor and a second inverter. Wherein, both the tenth transistor and the eleventh transistor are P-type transistors. The input end of the second inverter is connected to the fifth node, and the output end of the second inverter is connected to the gate of the tenth transistor; the first electrode of the tenth transistor is respectively connected to the second electrode of the fourth transistor and the fifth node. The first electrode of the transistor is connected, the second electrode of the tenth transistor is connected with the first electrode of the eleventh transistor; the gate of the eleventh transistor is connected with the clock signal input end, the second electrode of the eleventh transistor is connected with the sixth node connection.

In a feasible embodiment, in order to realize that when the clock signal input terminal is at a high potential, the first latch latches data, and the second latch transmits data, and when the clock signal input terminal is at a low potential, the first latch One latch latches data, the second latch transmits data, and the register also includes a third inverter, a fourth inverter, and a fifth inverter; the input terminal of the third inverter is connected to the data input terminal , the output terminal of the third inverter is connected to the second node, the input terminal of the fourth inverter is connected to the fourth node, the output terminal of the fourth inverter is connected to the data output terminal, and the input terminal of the fifth inverter terminal is connected to the clock signal input terminal, and the output terminal of the fifth inverter is respectively connected to the gate of the first transistor, the gate of the eleventh transistor and the input terminal of the OR gate. In this register, only a single-phase clock signal is required, that is, no clock buffer is required inside the register, and the pass-through and latching of the first latch and the second latch are directly controlled by the high and low potentials of the clock signal input terminal. . And the clock signal input end is connected with the fifth inverter, that is, the clock signal input end is connected with two transistors, the clock signal input end is connected with the eleventh transistor, the first transistor and the OR gate through the fifth inverter, and the OR gate In general, there are two transistors connected to the input terminal of the inverted clock signal. Therefore, in this embodiment, a total of 6 transistors need to be connected to the clock signal and the inverted clock signal, and the number of connected transistors is still small, so the input capacitance of the clock signal can still be reduced, thereby reducing the number of clocks to the back end. The impact caused by the clock tree can reduce the power consumption of the clock tree after physical implementation.

It should be noted that, in the present application, the first latch and the second latch may be provided in the embodiment of the present application, or may be existing registered latches, which are not limited herein.

In the second aspect, the embodiment of the present application further provides a central processing unit, and the electronic device may include a circuit board and a register electrically connected to the circuit board as provided in any one of the above-mentioned implementation manners of the first aspect.

In a third aspect, an embodiment of the present application further provides an electronic device, which may include a housing and a central processing unit as provided in the second aspect above arranged in the housing.

The technical effects that can be achieved by the second aspect and the third aspect can be described with reference to the technical effects that can be achieved by any possible design in the first aspect, and will not be repeated here.

Description of drawings

FIG. 1 is a schematic structural diagram of a traditional register;

FIG. 2 is a schematic structural diagram of a register provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of another register provided by the embodiment of the present application;

FIG. 4 is a schematic structural diagram of another register provided by the embodiment of the present application;

FIG. 5 is a schematic structural diagram of a first logic control circuit provided in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a second logic control circuit provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another register provided by the embodiment of the present application;

FIG. 8 is a schematic structural diagram of the first logic control circuit in the register shown in FIG. 7;

FIG. 9a to FIG. 9h are schematic diagrams of states corresponding to the working process of the register shown in FIG. 7;

FIG. 10 is a schematic structural diagram of another register provided by the embodiment of the present application;

FIG. 11 is a schematic structural diagram of another register provided by the embodiment of the present application;

FIG. 12 is a schematic structural diagram of a first logic control circuit provided by an embodiment of the present application;

FIG. 13 is a schematic structural diagram of a second logic control circuit provided in an embodiment of the present application;

FIG. 14 is a schematic structural diagram of another register provided by the embodiment of the present application;

FIG. 15 is a schematic structural diagram of the first logic control circuit in the register shown in FIG. 14;

16a to 16h are schematic diagrams of states corresponding to the working process of the register shown in FIG. 14 ;

FIG. 17 is a schematic structural diagram corresponding to a central processing unit provided by the embodiment of the present application.

Explanation of reference signs:

100-central processing unit; 20-circuit board; 10-register; 11-first latch; 12-second latch; 13-logic gate; 111-first logic control circuit; 121-second logic control Circuit; N1-first inverter; N2-second inverter; N3-third inverter; N4-fourth inverter; N5-fifth inverter; M1-first transistor; M2- M3-third transistor; M4-fourth transistor; M5-fifth transistor; M6-sixth transistor; M7-seventh transistor; M8-eighth transistor; M9-ninth transistor; M10-tenth Transistor; M11-the eleventh transistor; A1-the first NOR gate; A2-the second NOR gate; B-AND gate; C1-the first NAND gate; C2-the second NAND gate; D1-OR gate ;CP-clock signal input terminal; D-data input terminal; Q-data output terminal; V1-first reference voltage terminal; V2-second reference voltage terminal;①-first node;②-second node;③- The third node; ④-the fourth node; ⑤-the fifth node; ⑥-the sixth node.

Detailed ways

In order to make the purpose, technical solution and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar structures in the drawings, and thus their repeated descriptions will be omitted. The words expressing position and direction described in this application are all described by taking the accompanying drawings as an example, but changes can also be made according to needs, and all changes are included in the protection scope of this application. The drawings in this application are only used to illustrate the relative positional relationship and do not represent the true scale.

It should be noted that specific details are set forth in the following description to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described here, and those skilled in the art can make similar promotions without departing from the connotation of the present application. The present application is therefore not limited by the specific embodiments disclosed below. The subsequent description of the specification is a preferred implementation mode for implementing the application, but the description is for the purpose of illustrating the general principles of the application, and is not intended to limit the scope of the application. The scope of protection of the present application should be defined by the appended claims.

In order to facilitate understanding of the technical solutions provided by the embodiments of the present application, the application scenarios thereof are firstly introduced below. Registers are some small storage areas used to store data inside the central processing unit, and are used to temporarily store the data involved in the calculation and the results of the calculation. The central processing unit can be applied to electronic devices such as terminal devices or cloud server devices, and of course, can also be applied to other electronic devices, which is not limited here.

In order to make the purpose, technical solution and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 2 , FIG. 2 is a schematic structural diagram of a register provided by an embodiment of the present application. As shown in FIG. 2 , the register 10 may include a first latch 11 , a second latch 12 , a logic gate 13 , a clock signal input terminal CP, a data input terminal D and a data output terminal Q. The input end of the first latch 11 is connected with the output end of clock signal input end CP, data input end D and logic gate 13 respectively, and the output end of the first latch 11 is connected with the input end of the second latch 12 , the output end of the second latch is connected to the data output end Q. Wherein, the first latch 11 is used to realize data latching or pass-through under the control of the clock signal input terminal CP, and the second latch is used to realize data pass-through or latching, so as to realize the basic function of the register.

Continue to refer to Fig. 2, the input terminal of logic gate 13 is connected with data input terminal D and data output terminal Q respectively, and the output terminal of logic gate 13 is connected with first latch 11; This logic gate 13 can be used in data input terminal D When the potential is the same as the potential of the data output terminal Q, the potential output by the first latch 11 is controlled to be the same as the potential of the data output terminal Q. In this way, when the potentials of the data input terminal D and the data output terminal Q are the same, since the logic gate 13 controls the potential output of the first latch 11 to be the same as the potential of the data output terminal Q, the signal reversal of the clock signal input terminal CP will not occur. This causes the inversion of the internal nodes of the register, thereby reducing the power consumption of the internal clock signal inversion of the register.

The present application will be described in detail below in combination with specific embodiments. It should be noted that this embodiment is for better explaining the present application, but not limiting the present application.

The first implementation of the logic gate in this application will be described below.

In this embodiment, the logic gate 13 can be specifically used to output a high potential signal to control the potential of the output terminal of the first latch 11 to be low when the potentials of the data input terminal D and the data output terminal Q are both low potentials. potential.

For example, refer to FIG. 3 . FIG. 3 is a schematic structural diagram of another register provided by an embodiment of the present application. The logic gate 13 may include a first NOR gate A1, and the first latch 11 may include a second NOR gate A2; the input terminals of the first NOR gate A1 are respectively connected to the data input terminal D and the data output terminal Q, The input terminal of the second NOR gate A2 is respectively connected with the data input terminal D and the output terminal of the first NOR gate A1 , and the output terminal of the second NOR gate A2 is connected with the output terminal of the first latch 11 . In this way, when the data input terminal D and the data output terminal Q are both at low potential, the output terminal of the first NOR gate A1 is at high potential. When the output terminal of the first NOR gate A1 is at a high potential, regardless of whether the potential at the data input terminal D is high or low, the output terminal of the second NOR gate A2 will output a low potential, so that the first latch The potential of the output terminal of 11 is a low potential. In this way, when the signal at the clock signal input terminal CP is reversed, the signal output from the first latch 11 to the second latch 12 is always kept at a low potential, and the internal nodes of the second latch 12 will not be reversed, thereby reducing The power consumption of the internal clock signal flipping of the small register.

In a feasible implementation manner, as shown in FIG. 4 , the register 10 may further include a first transistor M1, and the first latch 11 may further include a first logic control circuit 111 and an AND gate B. Referring to FIG. 5 , the first logic control circuit 111 may include a second transistor M2 , a third transistor M3 , a fourth transistor M4 and a fifth transistor M5 . Wherein, the first transistor M1 , the second transistor M2 and the third transistor M3 are all P-type transistors, and the fourth transistor M4 and the fifth transistor M5 are N-type transistors. The gate of the first transistor M1 is connected to the clock signal input terminal CP, the first electrode of the first transistor M1 is connected to the first reference voltage terminal V1, and the second electrode of the first transistor M1 is connected to the first node ① of the register 10; The first electrode of the second transistor M2 is connected to the first node ①, the gate of the second transistor M2 is connected to the second node ② of the register 10, and the second electrode of the second transistor M2 is connected to the fifth node ⑤ of the register 10; The first electrode of the third transistor M3 is connected to the first reference voltage terminal V1, the gate of the third transistor M3 is connected to the third node ③ of the register 10, and the second electrode of the third transistor M3 is connected to the fifth node ⑤; The first electrode of the four transistor M4 is connected to the fifth node ⑤, the gate of the fourth transistor M4 is connected to the third node ③, the second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5; the fifth transistor The gate of M5 is connected to the second node ②, and the second electrode of the fifth transistor M5 is connected to the second reference voltage terminal V2. The input terminal of the AND gate B is connected with the fifth node ⑤ and the clock signal input terminal CP respectively, and the output terminal of the AND gate B is connected with the input terminal of the second NOR gate A2; the second node ② is connected with the data input terminal D, and the second node ② is connected with the data input terminal D. The three nodes ③ are connected to the output terminal of the first latch 11 . Wherein, the second reference voltage terminal V2 is grounded, and the potential of the first reference voltage terminal V1 is greater than the potential of the second reference voltage terminal V2.

Further, continuing to refer to FIG. 4 , the second latch 12 may control the circuit 121 and the first inverter N1 with a second logic. Referring to FIG. 6 , the second logic control circuit 121 may include a sixth transistor M6 , a seventh transistor M7 , an eighth transistor M8 and a ninth transistor M9 . Wherein, both the sixth transistor M6 and the seventh transistor M7 are P-type transistors, and the eighth transistor M8 and the ninth transistor M9 are both N-type transistors. The first electrode of the sixth transistor M6 is connected to the first node ①, the gate of the sixth transistor M6 is connected to the third node ③, the second electrode of the sixth transistor M6 is connected to the sixth node ⑥ of the register 10; the seventh transistor The first electrode of M7 is connected to the first reference voltage terminal V1, the gate of the seventh transistor M7 is connected to the fourth node ④ of the register 10, and the second electrode of the seventh transistor M7 is connected to the sixth node ⑥ of the register 10; The first electrode of the eighth transistor M8 is connected to the sixth node ⑥, the gate of the eighth transistor M8 is connected to the fourth node ④, the second electrode of the eighth transistor M8 is connected to the first electrode of the ninth transistor M9; the ninth transistor M8 The gate of M9 is connected to the third node ③, the second electrode of the ninth transistor M9 is connected to the second reference voltage terminal V2; the input terminal of the first inverter N1 is connected to the sixth node ⑥, and the first inverter N1 The output terminal of the output terminal is connected to the fourth node ④, and the fourth node ④ is connected to the data output terminal Q.

Exemplarily, in order to improve the stability of the register, refer to FIG. 7 , which is a schematic structural diagram of another register provided by an embodiment of the present application. In the register 10, the first latch 11 may further include a tenth transistor M10, an eleventh transistor M11 and a second inverter N2. Wherein, both the tenth transistor M10 and the eleventh transistor M11 are N-type transistors. The input end of the second inverter N2 is connected to the fifth node ⑤, and the output end of the second inverter N2 is connected to the gate of the tenth transistor M10; with reference to FIG. 8, the first electrode of the tenth transistor M10 is respectively connected to the gate of the tenth transistor M10 The second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5, the second electrode of the tenth transistor M10 is connected to the first electrode of the eleventh transistor M11; the gate of the eleventh transistor M11 is connected to the clock signal input The terminal CP is connected, and the second electrode of the eleventh transistor M11 is connected to the sixth node ⑥.

In a feasible embodiment, in order to realize that when the clock signal input terminal CP is high potential, the first latch 11 latches data, and the second latch 12 transmits data, while the clock signal input terminal CP is low potential potential, the first latch 11 latches data, and the second latch 12 transmits data. Continue referring to FIG. 7, the register 10 also includes a third inverter N3 and a fourth inverter N4; the third inverter The input terminal of N3 is connected to the data input terminal, the output terminal of the third inverter N3 is connected to the second node ②, the input terminal of the fourth inverter N4 is connected to the fourth node ④, and the output of the fourth inverter N4 The terminal is connected with the data output terminal Q.

In the register provided by this application, only a single-phase clock signal is required, that is, no clock buffer is required inside the register, and the first latch 11 and the second latch are directly controlled by the high and low potentials of the clock signal input terminal CP. The punch-through and latch of device 12. And in the register provided by the embodiment of FIG. 7 , the clock signal input terminal CP controls a total of 4 transistors, and the number of transistors controlled by the clock signal input terminal CP is small, which can reduce the input capacitance of the clock signal input terminal CP, thereby reducing the impact on the rear The impact caused by the end-to-end clock tree can reduce the power consumption of the clock tree after physical implementation.

The working process of the register shown in FIG. 7 is described in detail below by taking the register shown in FIG. 7 as an example. In the following description, "1" represents a high potential signal, and "0" represents a low potential signal. The working process of the register has the following two situations:

the first case,

State 1: CP=0, D=0; Q may be 0 or 1.

As shown in Figure 9a, when CP=0, D=0, Q=1, the fourth transistor M4, the fifth transistor M5, the tenth transistor M10, the seventh transistor M7, the ninth transistor M9 and the first transistor M1 are all is turned on, and the second transistor M2, the third transistor M3, the eleventh transistor M11, the sixth transistor M6 and the eighth transistor M8 are all turned off.

The first node ①=1, the second node ②=1, the fifth node ⑤=0, the third node ③=1, the sixth node ⑥=1, the fourth node ④=0, Q=1.

As shown in FIG. 9b, when CP=0, D=0, and Q=0, the fourth transistor M4, the fifth transistor M5, the tenth transistor M10, the eighth transistor M8, the ninth transistor M9 and the first transistor M1 all is turned on, and the second transistor M2, the third transistor M3, the eleventh transistor M11, the sixth transistor M6 and the seventh transistor M7 are all turned off.

The first node ①=1, the second node ②=1, the fifth node ⑤=0, the third node ③=1, the sixth node ⑥=0, the fourth node ④=1, Q=0.

State 2: CP=1 (jumps from 0 to 1), D=0; Q=0.

As shown in FIG. 9c, when CP=1 and D=0, the fourth transistor M4, the fifth transistor M5, the tenth transistor M10, the eleventh transistor M11, the eighth transistor M8 and the ninth transistor M9 are all turned on, The second transistor M2, the third transistor M3, the sixth transistor M6, the seventh transistor M7 and the first transistor M1 are all turned off. In this state, both the tenth transistor M10 and the eleventh transistor M11 are turned on, and the second reference voltage terminal V2 pulls down the potential of the sixth node ⑥ through the fifth transistor M5, the tenth transistor M10 and the eleventh transistor M11.

State 3: CP=1, D=1 (jumps from 0 to 1); Q=0.

As shown in FIG. 9d, when CP=1 and D=1, the second transistor M2, the fourth transistor M4, the tenth transistor M10, the eleventh transistor M11, the eighth transistor M8 and the ninth transistor M9 are all turned on, The third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the first transistor M1 are all turned off. In this state, both the tenth transistor M10 and the eleventh transistor M11 are turned on, and the sixth node ⑥ pulls down the first node ① through the tenth transistor M10, the eleventh transistor M11, the second transistor M2 and the fourth transistor M4 potential.

The first node ①=0, the second node ②=0, the fifth node ⑤=0, the third node ③=1, the sixth node ⑥=0, the fourth node ④=1, Q=0.

the second case,

State 1: CP=0, D=1; Q may be 0 or 1.

As shown in Figure 9e, when CP=0, D=1, Q=0, the second transistor M2, the fourth transistor M4, the eighth transistor M8, the ninth transistor M9 and the first transistor M1 are all turned on, and the third The transistor M3, the fifth transistor M5, the tenth transistor M10, the eleventh transistor M11, the sixth transistor M6 and the seventh transistor M7 are all turned off.

The first node ①=1, the second node ②=0, the fifth node ⑤=1, the third node ③=1, the sixth node ⑥=0, the fourth node ④=1, Q=0.

As shown in Figure 9f, when CP=0, D=1, Q=1, the second transistor M2, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7 and the first transistor M1 are all turned on, and the third The transistor M3, the fifth transistor M5, the tenth transistor M10, the eleventh transistor M11, the eighth transistor M8 and the ninth transistor M9 are all turned off.

The first node ①=1, the second node ②=0, the fifth node ⑤=1, the third node ③=0, the sixth node ⑥=1, the fourth node ④=0, Q=1.

State 2: CP=1 (jumps from 0 to 1), D=1; Q=1.

As shown in Figure 9g, when CP=1 and D=1, the second transistor M2, the third transistor M3, the eleventh transistor M11, the sixth transistor M6 and the seventh transistor M7 are all turned on, and the fourth transistor M4, The fifth transistor M5, the tenth transistor M10, the eighth transistor M8, the ninth transistor M9 and the first transistor M1 are all turned off.

State 3: CP=1, D=0 (jump from 1 to 0); Q=1.

As shown in Figure 9h, when CP=1 and D=0, the third transistor M3, the fifth transistor M5, the eleventh transistor M11, the sixth transistor M6 and the seventh transistor M7 are all turned on, and the second transistor M2, The fourth transistor M4, the tenth transistor M10, the eighth transistor M8, the ninth transistor M9 and the first transistor M1 are all turned off.

The first node ①=1, the second node ②=1, the fifth node ⑤=1, the third node ③=0, the sixth node ⑥=1, the fourth node ④=0, Q=1.

To sum up, in this application, the working principle of the register 10 is shown in Table 1 below:

Table 1

It can be seen from the above table 1 that when the clock signal input terminal CP=0, the first latch 11 passes through, the potential of the fifth node ⑤ changes with the potential change of the second node ②, and the second latch 12 latches the data , the data latched by the second latch 12 does not change with the change of the data input terminal D, and the output of the data output terminal Q remains unchanged; when the clock signal input terminal CP changes from 0 to 1 (that is, the rising edge of the clock signal) , trigger the first latch 11 to latch the data, the potential of the third node ③ remains the same as the potential of the second node ②, the second latch 12 passes through, and the data output terminal Q outputs the value latched by the first latch 11 Data; when CP=1, the data latched by the first latch 11 does not change with the change of D, the potential of the third node ③ remains unchanged, the second latch 12 passes through, and the output of the data output terminal Q remains constant.

Another implementation of the logic gate in this application will be described below.

In another embodiment, the logic gate 13 can be specifically used to output a low potential signal to control the potential of the output terminal of the first latch 11 to be high when the potentials of the data input terminal D and the data output terminal Q are both high potentials potential.

For example, refer to FIG. 10 , which is a schematic structural diagram of another register provided by an embodiment of the present application. The logic gate 13 may include a first NAND gate C1, and the first latch 11 may include a second NAND gate C2; the input terminals of the first NAND gate C1 are respectively connected to the data input terminal D and the data output terminal Q , the input terminal of the second NAND gate C2 is respectively connected with the data input terminal D and the output terminal of the first NAND gate C1, and the output terminal of the second NAND gate C2 is connected with the output terminal of the first latch. In this way, when the data input terminal D and the data output terminal Q are both at high potential, the output terminal of the first NOR gate A1 is at low potential. When the output terminal of the first NOR gate A1 is low potential, regardless of whether the potential of the data input terminal D is high potential or low potential, the output terminal of the second NOR gate A2 will output a high potential, so that the first latch The potential of the output terminal of 11 is a high potential. In this way, when the signal at the clock signal input terminal CP is reversed, the signal output from the first latch 11 to the second latch 12 is always kept at a high potential, and the internal nodes of the second latch 12 will not be reversed, thereby reducing The power consumption of the internal clock signal flipping of the small register.

In a feasible implementation manner, as shown in FIG. 11 , the register 10 may further include a first transistor M1, and the first latch 11 may further include a first logic control circuit 111 and an OR gate D1. Referring to FIG. 12 , the first logic control circuit 111 may include a second transistor M2 , a third transistor M3 , a fourth transistor M4 and a fifth transistor M5 . Wherein, the first transistor M1 , the second transistor M2 and the third transistor M3 are all N-type transistors, and the fourth transistor M4 and the fifth transistor M5 are P-type transistors. The gate of the first transistor M1 is connected to the clock signal input terminal CP, the first electrode of the first transistor M1 is connected to the first reference voltage terminal V1, and the second electrode of the first transistor M1 is connected to the first node ① of the register 10; The first electrode of the second transistor M2 is connected to the first node ①, the gate of the second transistor M2 is connected to the second node ② of the register 10, and the second electrode of the second transistor M2 is connected to the fifth node ⑤ of the register 10; The first electrode of the third transistor M3 is connected to the first reference voltage terminal V1, the gate of the third transistor M3 is connected to the third node ③ of the register 10, and the second electrode of the third transistor M3 is connected to the fifth node ⑤; The first electrode of the four transistor M4 is connected to the fifth node ⑤, the gate of the fourth transistor M4 is connected to the third node ③, the second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5; the fifth transistor The gate of M5 is connected to the second node ②, and the second electrode of the fifth transistor M5 is connected to the second reference voltage terminal V2. The input end of the OR gate D1 is respectively connected with the fifth node ⑤ and the clock signal input end CP, the output end of the OR gate D1 is connected with the input end of the second NOR gate A2; the second node ② is connected with the data input end D, and the second node ② is connected with the data input end D. The three nodes ③ are connected to the output terminal of the first latch 11 . Wherein, the first reference voltage terminal V1 is grounded, and the potential of the second reference voltage terminal V2 is higher than the potential of the first reference voltage terminal V1.

Further, continuing to refer to FIG. 11 , the second latch 12 may control the circuit 121 and the first inverter N1 with a second logic. Referring to FIG. 13 , the second logic control circuit 121 may include a sixth transistor M6 , a seventh transistor M7 , an eighth transistor M8 and a ninth transistor M9 . Wherein, both the sixth transistor M6 and the seventh transistor M7 are N-type transistors, and the eighth transistor M8 and the ninth transistor M9 are both P-type transistors. The first electrode of the sixth transistor M6 is connected to the first node ①, the gate of the sixth transistor M6 is connected to the third node ③, the second electrode of the sixth transistor M6 is connected to the sixth node ⑥ of the register 10; the seventh transistor The first electrode of M7 is connected to the first reference voltage terminal V1, the gate of the seventh transistor M7 is connected to the fourth node ④ of the register 10, and the second electrode of the seventh transistor M7 is connected to the sixth node ⑥ of the register 10; The first electrode of the eighth transistor M8 is connected to the sixth node ⑥, the gate of the eighth transistor M8 is connected to the fourth node ④, the second electrode of the eighth transistor M8 is connected to the first electrode of the ninth transistor M9; the ninth transistor M8 The gate of M9 is connected to the third node ③, the second electrode of the ninth transistor M9 is connected to the second reference voltage terminal V2; the input terminal of the first inverter N1 is connected to the sixth node ⑥, and the first inverter N1 The output terminal of the output terminal is connected to the fourth node ④, and the fourth node ④ is connected to the data output terminal Q.

Exemplarily, in order to improve the stability of the register, refer to FIG. 14 , which is a schematic structural diagram of another register provided by an embodiment of the present application. In the register 10, the first latch 11 may further include a tenth transistor M10, an eleventh transistor M11 and a second inverter N2. Wherein, both the tenth transistor M10 and the eleventh transistor M11 are P-type transistors. The input terminal of the second inverter N2 is connected to the fifth node ⑤, and the output terminal of the second inverter N2 is connected to the gate of the tenth transistor M10; with reference to FIG. 15, the first electrode of the tenth transistor M10 is respectively connected to the gate of the tenth transistor M10 The second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5, the second electrode of the tenth transistor M10 is connected to the first electrode of the eleventh transistor M11; the gate of the eleventh transistor M11 is connected to the clock signal input The terminal CP is connected, and the second electrode of the eleventh transistor M11 is connected to the sixth node ⑥.

In a feasible embodiment, in order to realize that when the clock signal input terminal CP is high potential, the first latch 11 latches data, and the second latch 12 transmits data, while the clock signal input terminal CP is low potential potential, the first latch 11 latches data, and the second latch 12 transmits data. Continue referring to FIG. 14 , the register 10 also includes a third inverter N3, a fourth inverter N4, and a fifth inverter N5; the input terminal of the third inverter N3 is connected to the data input terminal, the output terminal of the third inverter N3 is connected to the second node ②, the input terminal of the fourth inverter N4 is connected to the fourth node ④, and the output terminal of the third inverter N3 is connected to the fourth node ④. The output terminals of the four inverters N4 are connected to the data output terminal Q, the input terminals of the fifth inverter N5 are connected to the clock signal input terminal CP, and the output terminals of the fifth inverter N5 are respectively connected to the gate of the first transistor M1 , the gate of the eleventh transistor M11 and the input terminal of the OR gate D1 are connected.

In the register provided by this application, only a single-phase clock signal is required, that is, no clock buffer is required inside the register, and the first latch 11 and the second latch are directly controlled by the high and low potentials of the clock signal input terminal CP. The punch-through and latch of device 12. And in the register provided in the embodiment of FIG. 14, the clock signal input terminal CP is connected to the fifth inverter N5, that is, the clock signal input terminal CP is connected to two transistors, and the clock signal input terminal CP is connected to the fifth inverter N5 through the fifth inverter N5. The eleventh transistor M11 and the first transistor M1 are connected to the OR gate C, and generally two transistors in the OR gate C are connected to the inverted clock signal input terminal CP. Therefore, in this application, a total of 6 transistors need to be connected to the clock signal and the inverted clock signal. Although the number of connected transistors is two more than the register 10 in FIG. 7 , it is still less, so the clock signal can still be reduced. Input capacitance, so as to reduce the impact on the back-end clock tree, and then reduce the power consumption of the clock tree after physical implementation.

Taking the register shown in FIG. 14 as an example below, its working process will be described in detail. In the following description, "1" represents a high potential signal, and "0" represents a low potential signal. The working process of the register has the following two situations:

the first case,

State 1: CP=0, D=0; Q may be 0 or 1.

As shown in Fig. 16a, when CP=0, CP'=1, D=0, Q=1, the second transistor M2, the fourth transistor M4, the eighth transistor M8, the ninth transistor M9 and the first transistor M1 all conduct is turned on, and the third transistor M3, the fifth transistor M5, the tenth transistor M10, the eleventh transistor M11, the sixth transistor M6 and the seventh transistor M7 are all turned off.

The first node ①=0, the second node ②=1, the fifth node ⑤=0, the third node ③=0, the sixth node ⑥=1, the fourth node ④=0, Q=1.

As shown in Figure 16b, when CP=0, CP'=1, D=0, Q=0, the second transistor M2, the third transistor M3, the sixth transistor M6, the seventh transistor M7 and the first transistor M1 are all is turned on, and the fourth transistor M4, the fifth transistor M5, the tenth transistor M10, the eleventh transistor M11, the eighth transistor M8 and the ninth transistor M9 are all turned off.

The first node ①=0, the second node ②=1, the fifth node ⑤=0, the third node ③=1, the sixth node ⑥=0, the fourth node ④=1, Q=0.

State 2: CP=1 (jumps from 0 to 1), D=0; Q=0.

As shown in Figure 16c, when CP=1, CP'=0, D=0, the second transistor M2, the third transistor M3, the eleventh transistor M11, the sixth transistor M6 and the seventh transistor M7 are all turned on, The fourth transistor M4, the fifth transistor M5, the tenth transistor M10, the eighth transistor M8, the ninth transistor M9 and the first transistor M1 are all turned off.

State 3: CP=1, D=1 (jumps from 0 to 1); Q=0.

As shown in Figure 16d, when CP=1, CP'=0, D=1, the third transistor M3, the fifth transistor M5, the eleventh transistor M11, the sixth transistor M6 and the seventh transistor M7 are all turned on, The second transistor M2, the fourth transistor M4, the tenth transistor M10, the eighth transistor M8, the ninth transistor M9 and the first transistor M1 are all turned off.

The first node ①=1, the second node ②=0, the fifth node ⑤=0, the third node ③=1, the sixth node ⑥=0, the fourth node ④=1, Q=0.

the second case,

State 1: CP=0, D=1; Q may be 0 or 1.

As shown in Figure 16e, when CP=0, CP'=1, D=1, Q=0, the fourth transistor M4, the fifth transistor M5, the tenth transistor M10, the seventh transistor M7, the ninth transistor M9 and The first transistor M1 is all turned on, and the second transistor M2 , the third transistor M3 , the eleventh transistor M11 , the sixth transistor M6 and the eighth transistor M8 are all off.

The first node ①=1, the second node ②=0, the fifth node ⑤=1, the third node ③=0, the sixth node ⑥=0, the fourth node ④=1, Q=0.

As shown in Figure 16f, when CP=0, CP'=1, D=1, Q=1, the fourth transistor M4, the fifth transistor M5, the tenth transistor M10, the eighth transistor M8, the ninth transistor M9 and The first transistor M1 is all turned on, and the second transistor M2 , the third transistor M3 , the eleventh transistor M11 , the sixth transistor M6 and the seventh transistor M7 are all off.

The first node ①=0, the second node ②=0, the fifth node ⑤=1, the third node ③=0, the sixth node ⑥=1, the fourth node ④=0, Q=1.

State 2: CP=1 (jumps from 0 to 1), D=1; Q=1.

As shown in Figure 16g, when CP=1, CP'=0, D=1, the fourth transistor M4, the fifth transistor M5, the tenth transistor M10, the eleventh transistor M11, the eighth transistor M8 and the ninth transistor M9 are all turned on, and the second transistor M2, the third transistor M3, the sixth transistor M6, the seventh transistor M7 and the first transistor M1 are all turned off. In this state, both the tenth transistor M10 and the eleventh transistor M11 are turned on, and the second reference voltage terminal V2 pulls up the potential of the sixth node ⑥ through the fifth transistor M5, the tenth transistor M10 and the eleventh transistor M11.

State 3: CP=1, D=0 (jump from 1 to 0); Q=1.

As shown in Figure 16h, when CP=1, CP'=0, D=0, the second transistor M2, the fourth transistor M4, the tenth transistor M10, the eleventh transistor M11, the eighth transistor M8 and the ninth transistor M9 are all turned on, and the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the first transistor M1 are all turned off. In this state, both the tenth transistor M10 and the eleventh transistor M11 are turned on, and the sixth node ⑥ pulls up the first node ① through the tenth transistor M10, the eleventh transistor M11, the second transistor M2 and the fourth transistor M4 potential.

To sum up, in this application, the working principle of register 10 is shown in Table 2 below:

Table 2

It can be seen from the above table 2 that when the clock signal input terminal CP=0, the first latch 11 passes through, the potential of the fifth node ⑤ changes with the potential change of the second node ②, and the second latch 12 latches the data , the data latched by the second latch 12 does not change with the change of the data input terminal D, and the output of the data output terminal Q remains unchanged; when the clock signal input terminal CP changes from 0 to 1 (that is, the rising edge of the clock signal) , trigger the first latch 11 to latch the data, the potential of the third node ③ remains the same as the potential of the second node ②, the second latch 12 passes through, and the data output terminal Q outputs the value latched by the first latch 11 Data; when CP=1, the data latched by the first latch 11 does not change with the change of D, the potential of the third node ③ remains unchanged, the second latch 12 passes through, and the output of the data output terminal Q remains constant.

Correspondingly, referring to FIG. 17 , FIG. 17 is a schematic structural diagram of a central processing unit provided in the embodiment of the present application, in which the central processing unit 100 includes a circuit board 20 and any of the above-mentioned registers 10 provided in the embodiment of the present application . Since the problem-solving principle of the central processing unit 100 is similar to that of the aforementioned register 10 , the implementation of the central processing unit 100 can refer to the implementation of the aforementioned register 10 , and repeated descriptions will not be repeated here.

Correspondingly, the present application also provides an electronic device, which may include a housing such as a central processing unit disposed in the housing. The electronic device may be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, and any other product or component with a data processing function. The other essential components of the electronic device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present application.

Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A register, characterized by comprising: a logic gate, a first latch, a second latch, a clock signal input terminal, a data input terminal and a data output terminal, wherein:

The input end of the first latch is respectively connected with the clock signal input end, the data input end and the output end of the logic gate, and the output end of the first latch is connected with the second latch The input terminal of the latch is connected, and the output terminal of the second latch is connected with the data output terminal;

The input terminals of the logic gate are respectively connected with the data input terminal and the data output terminal, and the output terminals of the logic gate are connected with the first latch; When the potential of the terminal and the data output terminal are the same, the potential output of the first latch is controlled to be the same as the potential of the data output terminal.
The register according to claim 1, wherein the logic gate is specifically configured to output a signal of a second potential to control the The potential at the output terminal of the first latch is a first potential, and the first potential and the second potential are different potentials.
The register according to claim 1 or 2, wherein the logic gate comprises a first NOR gate, and the first latch comprises a second NOR gate;

The input end of the first NOR gate is respectively connected with the data input end and the data output end, and the input end of the second NOR gate is respectively connected with the data input end and the first NOR gate The output terminal of the second NOR gate is connected with the output terminal of the first latch.
The register according to claim 3, wherein the register further comprises a first transistor, and the first latch further comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor and an AND gate;

The gate of the first transistor is connected to the clock signal input terminal, the first electrode of the first transistor is connected to the first reference voltage terminal, and the second electrode of the first transistor is connected to the first node connection;

The first electrode of the second transistor is connected to the first node, the gate of the second transistor is connected to the second node of the register, and the second electrode of the second transistor is connected to the first node of the register. Five-node connection;

The first electrode of the third transistor is connected to the first reference voltage terminal, the gate of the third transistor is connected to the third node of the register, the second electrode of the third transistor is connected to the first Five-node connection;

The first electrode of the fourth transistor is connected to the fifth node, the gate of the fourth transistor is connected to the third node, the second electrode of the fourth transistor is connected to the fifth node of the fifth transistor an electrode connection;

The gate of the fifth transistor is connected to the second node, and the second electrode of the fifth transistor is connected to the second reference voltage terminal;

The input end of the AND gate is respectively connected to the fifth node and the clock signal input end, and the output end of the AND gate is connected to the input end of the second NOR gate;

The second node is connected to the data input end, and the third node is connected to the output end of the first latch;

The first transistor, the second transistor and the third transistor are all P-type transistors, the fourth transistor and the fifth transistor are N-type transistors, the second reference voltage terminal is grounded, and the first The potential of the reference voltage terminal is greater than the potential of the second reference voltage terminal.
The register according to claim 4, wherein the second latch comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a first inverter; wherein:

The first electrode of the sixth transistor is connected to the first node, the gate of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the sixth node of the register connect;

The first electrode of the seventh transistor is connected to the first reference voltage terminal, the gate of the seventh transistor is connected to the fourth node of the register, the second electrode of the seventh transistor is connected to the first Six-node connection;

The first electrode of the eighth transistor is connected to the sixth node, the gate of the eighth transistor is connected to the fourth node, the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor an electrode connection;

The gate of the ninth transistor is connected to the third node, and the second electrode of the ninth transistor is connected to the second reference voltage terminal;

The input end of the first inverter is connected to the sixth node, the output end of the first inverter is connected to the fourth node, and the fourth node is connected to the data output end;

Both the sixth transistor and the seventh transistor are P-type transistors, and the eighth transistor and the ninth transistor are both N-type transistors.
The register according to claim 5, wherein the first latch further comprises a tenth transistor, an eleventh transistor and a second inverter; wherein:

The input end of the second inverter is connected to the fifth node, and the output end of the second inverter is connected to the gate of the tenth transistor;

The first electrode of the tenth transistor is respectively connected to the second electrode of the fourth transistor and the first electrode of the fifth transistor, and the second electrode of the tenth transistor is connected to the first electrode of the eleventh transistor. an electrode connection;

The gate of the eleventh transistor is connected to the clock signal input terminal, and the second electrode of the eleventh transistor is connected to the sixth node;

Both the tenth transistor and the eleventh transistor are N-type transistors.
The register according to claim 6, wherein the register further comprises a third inverter and a fourth inverter;

The input end of the third inverter is connected to the data input end and the second node, the input end of the fourth inverter is connected to the fourth node, and the input end of the fourth inverter The output terminal is connected with the data output terminal.
The register according to claim 1 or 2, wherein the logic gate comprises a first NAND gate, and the first latch comprises a second NAND gate;

The input end of the first NAND gate is connected with the data input end and the data output end respectively, and the input end of the second NAND gate is respectively connected with the data input end and the first NAND gate The output terminal of the second NAND gate is connected with the output terminal of the first latch.
The register according to claim 8, wherein the register further comprises a first transistor, and the first latch further comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor and an OR gate;

The gate of the first transistor is connected to the clock signal input terminal, the first electrode of the first transistor is connected to the first reference voltage terminal, and the second electrode of the first transistor is connected to the first node connection;

The first electrode of the second transistor is connected to the first node, the gate of the second transistor is connected to the second node of the register, and the second electrode of the second transistor is connected to the first node of the register. Five-node connection;

The first electrode of the third transistor is connected to the first reference voltage terminal, the gate of the third transistor is connected to the third node of the register, the second electrode of the third transistor is connected to the first Five-node connection;

The first electrode of the fourth transistor is connected to the fifth node, the gate of the fourth transistor is connected to the third node, the second electrode of the fourth transistor is connected to the fifth node of the fifth transistor an electrode connection;

The gate of the fifth transistor is connected to the second node, and the second electrode of the fifth transistor is connected to the second reference voltage terminal;

The input end of the OR gate is respectively connected to the fifth node and the clock signal input end, and the output end of the OR gate is connected to the input end of the second NAND gate;

The second node is connected to the data input end, and the third node is connected to the output end of the first latch;

The first transistor, the second transistor and the third transistor are all N-type transistors, the fourth transistor and the fifth transistor are P-type transistors, the first reference voltage terminal is grounded, and the second The potential of the reference voltage terminal is greater than the potential of the first reference voltage terminal.
The register according to claim 9, wherein the second latch comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a first inverter; wherein:

The first electrode of the sixth transistor is connected to the first node, the gate of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the sixth node of the register connect;

The first electrode of the seventh transistor is connected to the first reference voltage terminal, the gate of the seventh transistor is connected to the fourth node of the register, the second electrode of the seventh transistor is connected to the first Six-node connection;

The first electrode of the eighth transistor is connected to the sixth node, the gate of the eighth transistor is connected to the fourth node, the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor an electrode connection;

The gate of the ninth transistor is connected to the third node, and the second electrode of the ninth transistor is connected to the second reference voltage terminal;

The input end of the first inverter is connected to the sixth node, the output end of the first inverter is connected to the fourth node, and the fourth node is connected to the data output end;

Both the sixth transistor and the seventh transistor are N-type transistors, and the eighth transistor and the ninth transistor are both P-type transistors.
The register according to claim 10, wherein the first latch further comprises a tenth transistor, an eleventh transistor and a second inverter; wherein:

The input end of the second inverter is connected to the fifth node, and the output end of the second inverter is connected to the gate of the tenth transistor;

The first electrode of the tenth transistor is respectively connected to the second electrode of the fourth transistor and the first electrode of the fifth transistor, and the second electrode of the tenth transistor is connected to the first electrode of the eleventh transistor. an electrode connection;

The gate of the eleventh transistor is connected to the clock signal input terminal, and the second electrode of the eleventh transistor is connected to the sixth node;

Both the tenth transistor and the eleventh transistor are P-type transistors.
The register according to claim 11, wherein the register further comprises a third inverter, a fourth inverter and a fifth inverter;

The input end of the third inverter is connected to the data input end and the second node, the input end of the fourth inverter is connected to the fourth node, and the input end of the fourth inverter The output end is connected to the data output end, the input end of the fifth inverter is connected to the clock signal input end, the output end of the fifth inverter is connected to the gate of the first transistor, the The gate of the eleventh transistor is connected to the input terminal of the AND gate.
A central processing unit, characterized by comprising a circuit board and the register according to any one of claims 1-12, the register being electrically connected to the circuit board.
An electronic device, characterized by comprising a casing such as the central processing unit according to claim 13 disposed in the casing.