WO2023155695A1

WO2023155695A1 - Processor, control method, device, and medium

Info

Publication number: WO2023155695A1
Application number: PCT/CN2023/074407
Authority: WO
Inventors: 罗犇
Original assignee: 阿里巴巴（中国）有限公司
Priority date: 2022-02-21
Filing date: 2023-02-03
Publication date: 2023-08-24
Also published as: CN114691592A

Abstract

Disclosed in the embodiments of the present disclosure are a processor, a control method, a device, and a medium. The processor comprises at least one processor core and at least one upper limit register, wherein the upper limit register is used for storing an upper limit rate, and when a first rate, at which a target processor core corresponding to a target upper limit register generates a split lock, is greater than or equal to a target upper limit rate in the target upper limit register, the highest frequency of the target processor core is reduced, and/or the target processor core triggers an alignment check exception, the target upper limit register belongs to the at least one upper limit register, and the target processor core belongs to the at least one processor core. By means of the solution, when the normal execution of an application program of a user is not affected to the greatest possible extent, the performance of a processor core not being reduced too much due to the generation of a split lock can be ensured, thereby improving the user experience.

Description

Processor, control method, device and medium

This application claims the priority of the Chinese patent application with the application number 202210156946.1 and the application title "processor, control method, device and medium" filed with the China Patent Office on February 21, 2022, the entire contents of which are incorporated herein by reference Applying.

technical field

The present disclosure relates to the field of network technology, and specifically relates to a processor, a control method, equipment and media.

Background technique

Unaligned memory access may occur when the processor is used for computing operations. For example, a processor supporting Symmetrical Multi-Processing (SMP) may include multiple processor cores (cores), multiple processor cores A data read across two cache data lines (cache lines) may occur in a processor core. When this situation occurs, in order to ensure the atomicity of data reading, the entire bus of the processor needs to be locked. This situation can be understood as that the processor core has generated a split lock (splitlock). Although the above scheme can guarantee the atomicity of data reading, because the bus of the processor is locked, other processor cores may not be able to access the memory concurrently when the bus is locked, resulting in a decrease in the performance of the processor.

In related technologies, the application program running on the processor and the compiler of the application program can avoid allocating variable addresses across cachelines as much as possible, so as to reduce the number of splitlock generation and reduce the probability of bus locking.

Although the above solution can reduce the probability of bus locking, in scenarios where applications cannot be controlled, such as cloud computing scenarios, cloud computing service providers cannot control applications running on processors, so how to When an application that may generate a splitlock is running on the CPU, on the premise that the performance of the processor will not be too much affected by the splitlock, it is relevant to protect other applications running on the processor so that other applications can run normally technical problems to be solved.

Contents of the invention

In order to solve problems in related technologies, embodiments of the present disclosure provide a processor, a control method, a device, and a medium.

In a first aspect, an embodiment of the present disclosure provides a processor, wherein the processor includes at least one processor core and at least one upper limit register;

The upper limit register is used to store the upper limit rate. When the first rate of the target processor core corresponding to the target upper limit register produces a split lock (splitlock) greater than or equal to the target upper limit rate in the target upper limit register, the highest frequency of the target processor core is lower, and/or the target processor core triggers an alignment check exception, the target upper limit register belongs to at least one upper limit register, and the target processor core belongs to at least one processor core.

With reference to the first aspect, in the first implementation manner of the first aspect of the present disclosure,

The processor also includes a frequency control logic circuit, at least one processor core and at least one upper limit register are connected to the frequency control logic circuit;

The frequency control logic circuit is used to obtain the rate at which at least one processor core generates splitlock, read the upper limit rate from at least one upper limit register, and reduce the maximum frequency of the target processor core in response to the first rate being greater than or equal to the target upper limit rate.

With reference to the first implementation of the first aspect, in the second implementation of the first aspect of the present disclosure,

Reduce the maximum frequency of the target processor core, including:

Obtain the highest frequency after the reduction of the target processor core, and adjust the highest frequency of the target processor core to the highest frequency after the reduction, until the second rate at which the target processor core generates splitlock is less than the target upper limit rate;

Among them, the highest frequency after reduction is obtained according to Ft ₁ =Fc ₁ *R/C ₁ , Ft ₁ is the highest frequency after reduction, Fc ₁ is the frequency before reduction of the target processor core, R is the target upper limit rate, and C ₁ is the first a rate.

In combination with any one of the first to second implementations of the first aspect, the present disclosure is in a third implementation of the first aspect, wherein the frequency control logic circuit is also used for:

Obtain the third rate at which the current target processor core generates a splitlock;

In response to the third rate being less than the target upper limit rate, increasing the maximum frequency of the target processor core.

With reference to the third implementation of the first aspect, in the fourth implementation of the first aspect of the present disclosure, the frequency control logic circuit is further used for:

Obtain the current frequency adjustment count value and the pre-increase frequency of the current target processor core. The frequency adjustment count value starts from the moment when the frequency of the target processor core is lowered, and the frequency adjustment count threshold is continuously decremented according to the count decrement speed. ;

Increase the maximum frequency of the target processor core, including:

Obtain the highest frequency after the increase according to the frequency before the increase, the third rate and the frequency adjustment count value, and set the maximum frequency of the target processor core as the highest frequency after the increase. The third rate and the frequency adjustment count value are the same as the increase After the highest frequency negative correlation.

With reference to the fourth implementation of the first aspect, the present disclosure is in the fifth implementation of the first aspect, wherein the highest frequency after the increase is obtained according to the frequency before the increase, the third rate, and the frequency adjustment count value, including:

According to Ft ₂ =Fc ₂ +Fc ₂ *(R/C ₂ -1)*((T-Tc)/T), obtain the highest frequency Ft ₂ after the increase, where Fc ₂ is the frequency before the increase, and R is the target upper limit rate, C ₂ is the third rate, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.

With reference to the fourth implementation manner of the first aspect, the present disclosure is in a sixth implementation manner of the first aspect, wherein,

The processor also includes a frequency adjustment count threshold register for storing the frequency adjustment count threshold and a frequency adjustment count value register for storing the frequency adjustment count value, the frequency adjustment count threshold register and the frequency adjustment count value register are connected to the frequency control logic circuit ;

The frequency control logic circuit is used to store the frequency adjustment count threshold read from the frequency adjustment count threshold register in the frequency adjustment count value register at the moment when the frequency of the control target processor core is reduced, and to adjust the frequency according to the count decrement speed The frequency adjustment counting threshold in the counting value register is continuously decremented;

Get the current frequency adjustment count value, including:

Read the current frequency adjustment count value from the frequency adjustment count value register.

With reference to the fourth implementation manner of the first aspect, in the seventh implementation manner of the first aspect of the present disclosure, the frequency control logic circuit is further used for:

In response to the frequency adjustment count value being 0, the highest frequency of the target processor core is set as the highest frequency of the processor core.

In a second aspect, an embodiment of the present disclosure provides a method for controlling a processor, where the method includes:

Obtain the rate at which at least one processor core of the processor generates a split lock (splitlock) and the upper limit rate corresponding to at least one processor core;

In response to the target processor core in at least one processor core generating a first rate of splitlock greater than or equal to the upper limit rate corresponding to the target processor core, reducing the maximum frequency of the target processor core, and/or causing the target processor core to trigger alignment Check for exceptions.

With reference to the second aspect, in the first implementation manner of the second aspect of the present disclosure, reducing the maximum frequency of the target processor core includes:

With reference to the second aspect or the first implementation manner of the second aspect, the present disclosure is in the second implementation manner of the second aspect, wherein the method further includes:

With reference to the second implementation of the second aspect, the present disclosure is in a third implementation of the second aspect, wherein the method further includes:

Increase the maximum frequency of the target processor core, including:

With reference to the third implementation of the second aspect, in the fourth implementation of the second aspect of the present disclosure, according to the The previous frequency, the third rate, and the frequency adjustment count value obtain the highest frequency after the increase, including:

With reference to the third implementation manner of the second aspect, the present disclosure is in a fourth implementation manner of the second aspect, wherein the method further includes:

In a third aspect, an embodiment of the present disclosure provides an internal processor control device, and the processor control device includes:

A rate acquisition module configured to acquire the rate at which at least one processor core of the processor generates a split lock (splitlock) and the upper limit rate corresponding to at least one processor core;

A frequency control module configured to reduce the maximum frequency of the target processor core in response to the first rate at which the target processor core in the at least one processor core generates a splitlock greater than or equal to the upper limit rate corresponding to the target processor core, and/or Causes the target processor core to trigger an alignment check exception.

In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including a memory and at least one processor; the memory is used to store one or more computer instructions, and one or more computer instructions are executed by at least one processor to implement the first The method steps of any one of the second aspect, the first implementation manner to the fourth implementation manner of the second aspect.

In the fifth aspect, the embodiments of the present disclosure provide a computer-readable storage medium, on which computer instructions are stored, and when the computer instructions are executed by a processor, the second aspect and the first implementation manner to the second aspect of the second aspect are implemented. The method steps of any one of the four implementations.

In the sixth aspect, the embodiments of the present disclosure provide a computer program product, including computer instructions. When the computer instructions are executed by a processor, the second aspect and the first implementation manner to the fourth implementation manner of the second aspect are implemented. Any one of the method steps.

The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:

According to the technical solution provided by the embodiments of the present disclosure, the processor includes at least one processor core and at least one upper limit register; wherein, the upper limit register is used to store the upper limit rate, when the target processor core corresponding to the target upper limit register generates the first splitlock When the rate is greater than or equal to the target upper limit rate in the target upper limit register, the maximum frequency of the target processor core is reduced, and/or the target processor core triggers an alignment check exception, the target upper limit register belongs to at least one upper limit register, and the target processor core belongs to At least one processor core. During use, when the target processor core in the processor generates a splitlock, considering that the rate at which the processor core generates a splitlock is low, the performance of the processor core will not degrade too much, so it can be processed at a faster speed. Read the upper limit rate stored in the upper limit register located in the processor, determine whether the rate at which the corresponding processor core generates the splitlock is higher based on the upper limit rate, so that the first rate at which the target processor core generates the splitlock is greater than or equal to the rate of the splitlock When the target upper limit rate in the target upper limit register corresponding to the target processor core (that is, the rate at which the target processor core generates a splitlock is higher), the maximum frequency of the target processor core is reduced, and/or the target processor core triggers an alignment check abnormal. Among them, due to the frequency of the processor core and the frequency generated by the processor core The rate of splitlock is positively correlated, so only when the first rate of splitlock generated by the target processor core is high, the maximum frequency of the target processor core is reduced, which can ensure that the rate of generating splitlock is low and will not make the target processor When the performance of the core is reduced too much, it will not affect the normal operation of the target processor core (that is, the maximum frequency of the target processor core will not be reduced), but when the rate of generating splitlock is high, the performance of the target processor core may be reduced too much , so that the highest frequency of the target processor core is reduced, so that the rate of splitlock generation is also reduced, to ensure that the performance of the processor core will not be reduced too much due to the generation of splitlock, so that the related applications running on the target processor core (For example, the application program that may cause the splitlock) can be executed normally, and the related application programs running on other processor cores will not be affected too much; When it is high, the target processor core will trigger an alignment check exception, which can ensure that the target processor core will not trigger an alignment check exception when the splitlock rate is low and the performance of the target processor core will not be reduced too much, so that the running in Related applications on the target processor core (for example, applications that may cause splitlock) can be executed normally, while related applications running on other processor cores will not be affected too much, and user experience will not be affected in any way. Damage, and when the rate of splitlock generation is high, which may reduce the performance of the target processor core too much, the target processor core will trigger an alignment check exception to ensure that the performance of the processor core will not be reduced too much due to the generation of splitlock. Therefore, on the premise of not affecting the normal execution of user applications running on the processor, the above solution ensures that the performance of the processor core will not be reduced too much due to the generation of splitlock, which improves the user experience.

According to the technical solution provided by the embodiments of the present disclosure, the processor further includes a frequency control logic circuit, wherein at least one processor core and at least one upper limit register are both connected to the frequency control logic circuit, and the frequency control logic circuit is used to obtain at least one processor core A splitlock rate is generated, and the upper limit rate is read from at least one upper limit register, and the maximum frequency of the target processor core is reduced in response to the first rate being greater than or equal to the target upper limit rate. Since the frequency control logic circuit is set in the processor, the time-consuming for the frequency control logic circuit to obtain the rate at which at least one processor core generates the splitlock and to read the upper limit rate from at least one upper limit register is relatively short, so that the frequency control logic circuit responds Because the first rate is greater than or equal to the target upper limit rate, the reaction speed of the process of reducing the maximum frequency of the target processor core is faster, which reduces the processing delay and improves the processing efficiency.

According to the technical solution provided by the embodiments of the present disclosure, the frequency control logic circuit acquires the reduced maximum frequency of the target processor core, and adjusts the maximum frequency of the target processor core to the reduced maximum frequency until the target processor core generates a splitlock The second rate is lower than the target upper limit rate, which can ensure that the target processor core is continuously reduced in real time according to the target processor core corresponding target upper limit rate, the real-time rate at which the target processor core generates splitlock, that is, the first rate, and the real-time frequency of the target processor core. The final highest frequency is the highest frequency after reduction, and the highest frequency of the target processor core is adjusted to the highest frequency after reduction until the rate at which the target processor core generates splitlock, that is, the second rate is less than the target upper limit rate, ensuring that the target processor core The highest frequency can be steadily decreased in stages to a range that meets the requirements, avoiding large fluctuations in the performance of the target processor core caused by a sharp decrease.

According to the technical solution provided by the embodiments of the present disclosure, the frequency control logic circuit obtains the third rate of splitlock generated by the current target processor core, and increases the maximum rate of the target processor core in response to the third rate being less than the target upper limit rate. Frequency, which can ensure that after the highest frequency of the target processor core is increased, the rate at which the target processor core generates splitlock can approach the target upper limit rate, ensuring that the performance of the processor core will not be reduced too much due to the excessive generation of splitlock Under this condition, try to increase the highest frequency of the target processor core to improve the performance of the target processor core.

According to the technical solution provided by the embodiments of the present disclosure, by obtaining the current frequency adjustment count value and the pre-increase frequency of the current target processor core, the highest frequency after the increase is obtained according to the pre-increase frequency, the third rate, and the frequency adjustment count value , and set the highest frequency of the target processor core as the highest frequency after the increase, and the third rate and the frequency adjustment count value are negatively correlated with the highest frequency after the increase. Among them, considering that when the third rate is already in a relatively high state, if the maximum frequency obtained after the increase is high, it may cause that after the maximum frequency of the target processor core is set to the maximum frequency after the increase, the target processing The frequency of the processor core is too high, which in turn causes the target processor core to generate a splitlock at a higher rate, and even the rate at which the target processor core generates a splitlock may be greater than or equal to the target upper limit rate. Therefore, by making the third rate and the increased maximum frequency negative Correlation, it can avoid that the highest frequency is also higher after the increase when the third rate is already in a higher state; and the frequency adjustment count value is inversely proportional to the time length from the moment when the frequency of the control target processor core is lowered to the current moment, the The longer the length of time, the smaller the frequency adjustment count value, and considering that the longer the length of time, the greater the impact on the execution of normal application programs by the target processor core, so by making the third rate negatively correlated with the frequency adjustment count value, it can be Prevent the frequency of the target processor core from being too low for a long time, so that the normal application programs executed by the target processor core will not be affected too much.

In the technical solution provided by the embodiments of the present disclosure, by obtaining the highest frequency after the rise by Ft ₂ =Fc ₂ +Fc ₂ *(R/C ₂ -1)*((T-Tc)/T), it is more convenient to obtain the rise The highest frequency after high, improve the efficiency of obtaining the highest frequency after boost.

According to the technical solution provided by the embodiments of the present disclosure, the processor further includes a frequency adjustment count threshold register for storing the frequency adjustment count threshold, a frequency adjustment count value register for storing the frequency adjustment count value, a frequency adjustment count threshold register, and a frequency adjustment count threshold register. The count value registers are all connected with the frequency control logic circuit, wherein since the frequency adjustment count threshold register and the frequency adjustment count value register are all located in the processor, the frequency control logic circuit in the processor reads the frequency adjustment from the frequency adjustment count threshold register. When the counting threshold and the frequency adjustment counting threshold in the frequency adjustment count value register are continuously decremented according to the counting decrement speed, the time delay is short, thereby improving the processing efficiency of the frequency control logic circuit.

According to the technical solution provided by the embodiments of the present disclosure, when the frequency adjustment count value is 0, it indicates that the maximum frequency allowed for the target processor core has been reached in the time period from the moment when the frequency of the target processor core is reduced to the current moment. The maximum length of time for limitation. If the maximum frequency of the target processor core continues to be limited, it may affect the normal application program execution of the target processor core. Therefore, the frequency control logic circuit adjusts the count value to 0 by responding to the frequency , set the maximum frequency of the target processor core to the maximum frequency of the processor core, that is, no longer impose any restrictions on the maximum frequency of the target processor core, which can ensure that the normal application execution of the target processor core will not be affected in any way.

According to the technical solution provided by the embodiments of the present disclosure, by obtaining the rate at which at least one processor core generates a splitlock and the upper limit rate corresponding to at least one processor core, considering that the rate at which the processor core generates a splitlock is low, the processor The performance of the core will not be reduced too much, so it can be determined based on the upper limit rate whether the rate at which the corresponding processor core generates a splitlock is higher, so that the first rate at which the target processor core generates a splitlock is greater than or equal to When the target upper limit rate corresponding to the target processor core (that is, the rate at which the target processor core generates splitlock is higher), the maximum frequency of the target processor core is reduced, and/or the target processor core triggers an alignment check exception . Wherein, since the frequency of the processor core is positively correlated with the rate at which the processor core produces the splitlock, only when the first rate at which the target processor core produces the splitlock is relatively high, the highest frequency of the target processor core is reduced to ensure When the rate at which the splitlock is generated is low and the performance of the target processor core will not be reduced too much, it will not affect the normal operation of the target processor core (that is, the highest frequency of the target processor core will not be reduced), and the rate at which the splitlock will be generated is relatively high. High, when the performance of the target processor core may be reduced too much, the maximum frequency of the target processor core will be reduced, and the rate of splitlock generation will also be reduced to ensure that the performance of the processor core will not be reduced too much due to the generation of splitlock Many, so that related applications running on the target processor core (such as applications that may cause splitlock) can be executed normally, and related applications running on other processor cores will not be affected too much; in addition , only when the first rate of splitlock generated by the target processor core is high, the target processor core triggers an alignment check exception, which can ensure that when the rate of splitlock generated is low and the performance of the target processor core will not be reduced too much, The target processor core will not trigger an alignment check exception, so that related applications running on the target processor core (such as applications that may cause splitlocks) can be executed normally, while related applications running on other processor cores It will not be affected too much, and the user experience will not be damaged in any way. When the rate of splitlock generation is high, which may reduce the performance of the target processor core too much, the target processor core will trigger an alignment check exception to ensure processing The performance of the core will not be degraded too much due to the splitlock. Therefore, the above solution ensures that the performance of the processor core will not be degraded too much due to the generation of the splitlock without affecting the normal execution of the user application program running on the processor as much as possible, thereby improving the user experience.

According to the technical solution provided by the embodiments of the present disclosure, by obtaining the reduced maximum frequency of the target processor core, and adjusting the maximum frequency of the target processor core to the reduced maximum frequency, until the second rate at which the target processor core generates a splitlock is less than The target upper limit rate can ensure continuous real-time acquisition of the highest frequency of the target processor core after reduction according to the target upper limit rate corresponding to the target processor core, the real-time rate at which the target processor core generates splitlock (the first rate), and the real-time frequency of the target processor core That is, the highest frequency after the reduction, and adjust the highest frequency of the target processor core to the highest frequency after the reduction, until the rate at which the target processor core generates splitlock, that is, the second rate is less than the target upper limit rate, to ensure that the highest frequency of the target processor core can reach the stage The stability drops to a range that meets the requirements, and avoids large fluctuations in the performance of the target processor core caused by a sharp drop.

According to the technical solution provided by the embodiments of the present disclosure, by obtaining the third rate at which the current target processor core generates a splitlock, and in response to the fact that the third rate is less than the target upper limit rate, increasing the maximum frequency of the target processor core can ensure that the target processor core After the maximum frequency of the core is increased, the rate at which the target processor core generates splitlocks can approach the target upper limit rate, ensuring that the performance of the processor core will not be reduced too much due to the generation of splitlocks. Maximum frequency to improve the performance of the target processor core.

According to the technical solution provided by the embodiments of the present disclosure, by obtaining the current frequency adjustment count value and the pre-increase frequency of the current target processor core, the highest frequency after the increase is obtained according to the pre-increase frequency, the third rate, and the frequency adjustment count value , and set the maximum frequency of the target processor core to the maximum frequency after the boost, the third rate and the frequency adjustment count value Both were negatively correlated with the highest frequency after elevation. Among them, considering that when the third rate is already in a relatively high state, if the maximum frequency obtained after the increase is high, it may cause that after the maximum frequency of the target processor core is set to the maximum frequency after the increase, the target processing The frequency of the processor core is too high, which in turn causes the target processor core to generate a splitlock at a higher rate, and even the rate at which the target processor core generates a splitlock may be greater than or equal to the target upper limit rate. Therefore, by making the third rate and the increased maximum frequency negative Correlation, it can avoid that the highest frequency is also higher after the increase when the first rate is already in a higher state; and the frequency adjustment count value is inversely proportional to the time length from the moment when the frequency of the control target processor core is lowered to the current moment, the The longer the time length is, the smaller the frequency adjustment count value is, and considering that the longer the time length is, the greater the impact on the normal application program execution of the target processor core is, so by making the highest frequency after the increase negatively correlated with the frequency adjustment count value , can prevent the frequency of the target processor core from being too low for a long time, so that the normal application programs executed by the target processor core will not be too much affected.

According to the technical solution provided by the embodiments of the present disclosure, when the frequency adjustment count value is 0, it indicates that the maximum frequency allowed for the target processor core has been reached in the time period from the moment when the frequency of the target processor core is reduced to the current moment. The maximum length of time for limitation. If the maximum frequency of the target processor core continues to be limited, it may affect the normal application execution of the target processor core. Therefore, by adjusting the count value to 0 in response to the frequency, the target processing The highest frequency of the processor core is set to the highest frequency of the processor core, that is, there is no longer any restriction on the highest frequency of the target processor core, which can ensure that the normal application execution of the target processor core will not be affected in any way.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

Description of drawings

Other features, objects and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the attached picture:

Fig. 1 shows a schematic structural block diagram of a processor according to an embodiment of the present disclosure.

Fig. 2 shows a schematic structural block diagram of a processor according to an embodiment of the present disclosure.

Fig. 3 shows a schematic structural block diagram of a processor according to an embodiment of the present disclosure.

FIG. 4 shows a flowchart of a processor control method according to an embodiment of the present disclosure.

Fig. 5 shows a structural block diagram of a processor control device according to an embodiment of the present disclosure.

Fig. 6 shows a structural block diagram of an electronic device according to an embodiment of the present disclosure.

FIG. 7 is a schematic structural diagram of a computer system suitable for implementing a method according to an embodiment of the present disclosure.

Detailed ways

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. Also, for clarity, parts not related to describing the exemplary embodiments are omitted in the drawings.

In the present disclosure, it should be understood that terms such as "comprising" or "having" are intended to indicate the existence of labels, numbers, steps, acts, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude one or multiple other labels, numbers, steps, acts, parts, parts or combinations thereof exist or are added to the possibility.

In addition, it should be noted that, in the case of no conflict, the embodiments in the present disclosure and the labels in the embodiments can be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and embodiments.

In order to protect other applications running on the processor on the premise that the performance of the processor will not be too much affected by the splitlock when running an application that may generate a splitlock, so that other applications can work normally In operation, the inventors of the present disclosure considered the following solutions.

Disadvantages of this solution: In the above-mentioned solution, although the probability of bus locking can be reduced, in scenarios where applications cannot be controlled, such as cloud computing scenarios, cloud computing service providers cannot monitor applications running on processors. Therefore, when an application program that may generate a splitlock is running on the processor, on the premise that the performance of the processor will not be too much affected by the generation of the splitlock, protect other applications running on the processor, so that other applications It is an urgent problem to be solved in related technologies that the program can run normally.

Considering the shortcomings of the above schemes, the inventors of the present disclosure have proposed a new scheme: the processor in this scheme includes at least one processor core and at least one upper limit register; wherein, the upper limit register is used to store the upper limit rate, when the target upper limit register corresponds to When the first rate at which the target processor core generates a splitlock is greater than or equal to the target upper limit rate in the target upper limit register, the maximum frequency of the target processor core is reduced, and/or the target processor core triggers an alignment check exception, and the target upper limit register belongs to At least one upper limit register, the target processor core belongs to at least one processor core. During use, when the target processor core in the processor generates a splitlock, considering that the rate at which the processor core generates a splitlock is low, the performance of the processor core will not degrade too much, so it can be processed at a faster speed. Read the upper limit rate stored in the upper limit register in the processor, determine whether the rate at which the corresponding processor core generates the splitlock is higher based on the upper limit rate, thereby generating the first rate at the target processor core at the first rate of the splitlock greater than or When it is equal to the target upper limit rate in the target upper limit register corresponding to the target processor core (that is, the rate at which the target processor core generates splitlock is higher), the maximum frequency of the target processor core is reduced, and/or the target processor core Trigger an alignment check exception. Wherein, since the frequency of the processor core is positively correlated with the rate at which the processor core produces the splitlock, only when the first rate at which the target processor core produces the splitlock is relatively high, the highest frequency of the target processor core is reduced to ensure When the rate at which the splitlock is generated is low and the performance of the target processor core will not be reduced too much, it will not affect the normal operation of the target processor core (that is, the highest frequency of the target processor core will not be reduced), and the rate at which the splitlock will be generated is relatively high. High, may reduce the performance of the target processor core too much, so that the maximum frequency of the target processor core is reduced, so that the speed of splitlock The rate is also reduced accordingly to ensure that the performance of the processor core will not be reduced too much due to the generation of splitlock; in addition, only when the first rate of splitlock generation by the target processor core is high, the target processor core will trigger an alignment check exception, It can ensure that when the rate of splitlock is low and the performance of the target processor core will not be reduced too much, the target processor core will not trigger an alignment check exception, so that the user's related applications (such as applications that may cause splitlock) It can be executed normally, and the user experience will not be damaged in any way. When the rate of splitlock generation is high, which may reduce the performance of the target processor core too much, the target processor core will trigger an alignment check exception to ensure the processor core. Performance will not be degraded too much due to splitlock. Therefore, on the premise of not affecting the normal execution of user applications running on the processor, the above solution ensures that the performance of the processor core will not be reduced too much due to the generation of splitlock, which improves the user experience.

In order to solve the above problems, the present disclosure proposes a processor, a control method, a device, and a medium.

FIG. 1 shows a schematic structural block diagram of a processor according to an embodiment of the present disclosure. As shown in FIG. 1 , the processor 100 includes at least one processor core 101 and at least one upper limit register 102 .

Wherein, the upper limit register 102 is used to store the upper limit rate. When the first rate at which the target processor core corresponding to the target upper limit register generates a split lock (splitlock) is greater than or equal to the target upper limit rate in the target upper limit register, the target The highest frequency of the processor core is reduced, and/or the target processor core triggers an alignment check exception, the target upper limit register belongs to at least one upper limit register 102 , and the target processor core belongs to at least one processor core 101 .

In one embodiment of the present disclosure, the processor may include one or more processor cores (Core), and each processor core may be configured with a cache (Cach), and the cache is located in the processor execution unit and the main memory (Dynamic Random Access Memory, DRAM) is usually composed of static memory (Static RAM, SRAM), which is small in scale but fast in access speed. The cache can be used to save a copy of some data in the memory. When the processor reads and writes data, it first accesses the cache, and when the required data does not exist in the cache, it accesses the memory again. The cache is usually divided into multiple groups, and each group is divided into multiple cache lines (cacheline). When fetching a unit from the memory into the cache, a memory area of the size of a cache line is taken to the cache at a time. , and then stored in the corresponding cache data line.

In one embodiment of the present disclosure, the generation of splitlock by the processor core can be understood as that the processor core generates data read across two cache data lines (cache lines). In order to ensure the atomicity of data read, it is necessary Lock the entire bus of the processor. This situation can be understood as a splitlock generated by the processor core. Among them, the atomicity of data reading can be understood as that data reading cannot be interrupted. The sequence cannot be shuffled, and part of the data read cannot be cut off or only part of the data read can be performed.

In one embodiment of the present disclosure, the upper limit rate can be understood as an upper limit for indicating the number of times a corresponding processor core is allowed to generate a splitlock within a unit time. Exemplarily, the unit of the upper limit rate may be times/second. If the number of splitlocks generated by the corresponding processor core per unit time is greater than or equal to the upper limit rate, the performance of the corresponding processor core may be greatly degraded.

In an embodiment of the present disclosure, the upper limit rate can be stored in the upper limit register in advance, or it can be The processor itself is calculated based on the historical log of the processor according to a corresponding algorithm or model, and written into the upper limit register, or written into the upper limit register by other devices or systems.

In an embodiment of the present disclosure, the first rate may be to determine whether the target processor core generates a splitlock by performing real-time detection on the target processor core, and obtain the first rate according to the detection result, wherein the target processor core The real-time detection of the processor core may be to periodically perform real-time detection on the target processor core at intervals of a preset detection time threshold, and the preset detection time threshold may be 1 ms. Exemplarily, at an interval of 1 ms, the instruction information used to indicate whether the corresponding processor core generates a splitlock is periodically obtained through the power management unit (Power Management Unit) in the processor, and the corresponding processor core is determined according to the instruction information Whether to generate a splitlock, and further obtain the rate at which the corresponding processor core generates a splitlock.

In one embodiment of the present disclosure, the reduction of the highest frequency of the target processor core can be understood as setting the highest frequency of the target processor core to a preset frequency; Level setting, and set the corresponding relationship between the speed level and the highest frequency, determine the target speed level corresponding to the first speed before reducing the highest frequency of the target processor core, obtain the highest frequency corresponding to the target speed level, and set the target processor core The highest frequency of set the highest frequency corresponding to the target rate level.

According to the technical solution provided by the embodiments of the present disclosure, the processor includes at least one processor core and at least one upper limit register; wherein, the upper limit register is used to store the upper limit rate, when the target processor core corresponding to the target upper limit register generates the first splitlock When the rate is greater than or equal to the target upper limit rate in the target upper limit register, the maximum frequency of the target processor core is reduced, and/or the target processor core triggers an alignment check exception, the target upper limit register belongs to at least one upper limit register, and the target processor core belongs to At least one processor core. During use, when the target processor core in the processor generates a splitlock, considering that the rate at which the processor core generates a splitlock is low, the performance of the processor core will not degrade too much, so it can be processed at a faster speed. Read the upper limit rate stored in the upper limit register located in the processor, determine whether the rate at which the corresponding processor core generates the splitlock is higher based on the upper limit rate, so that the first rate at which the target processor core generates the splitlock is greater than or equal to the rate of the splitlock When the target upper limit rate in the target upper limit register corresponding to the target processor core (that is, the rate at which the target processor core generates a splitlock is higher), the maximum frequency of the target processor core is reduced, and/or the target processor core triggers an alignment check abnormal. Wherein, since the frequency of the processor core is positively correlated with the rate at which the processor core produces the splitlock, only when the first rate at which the target processor core produces the splitlock is relatively high, the highest frequency of the target processor core is reduced to ensure When the rate at which the splitlock is generated is low and the performance of the target processor core will not be reduced too much, it will not affect the normal operation of the target processor core (that is, the highest frequency of the target processor core will not be reduced), and the rate at which the splitlock will be generated is relatively high. High, when the performance of the target processor core may be reduced too much, the maximum frequency of the target processor core will be reduced, and the rate of splitlock generation will also be reduced to ensure that the performance of the processor core will not be reduced too much due to the generation of splitlock Many, so that related applications running on the target processor core (such as applications that may cause splitlock) can be executed normally, and related applications running on other processor cores will not be affected too much; in addition , only when the first rate of splitlock generated by the target processor core is high, the target processor core triggers an alignment check exception, which can ensure that the performance of the target processor core will not be reduced when the rate of splitlock generated is low. When the reduction is too high, the target processor core will not trigger an alignment check exception, so that related applications running on the target processor core (such as applications that may cause splitlock) can be executed normally, while running on other processor cores The related applications will not be affected too much, and the user experience will not be damaged in any way. When the rate of splitlock generation is high, which may reduce the performance of the target processor core too much, the target processor core triggers the alignment check. Exception, to ensure that the performance of the processor core will not be degraded too much due to splitlock. Therefore, on the premise of not affecting the normal execution of user applications running on the processor, the above solution ensures that the performance of the processor core will not be reduced too much due to the generation of splitlock, which improves the user experience.

In an embodiment of the present disclosure, FIG. 2 shows a schematic structural block diagram of a processor according to an embodiment of the present disclosure. As shown in FIG. 2 , the processor 100 further includes a frequency control logic circuit 103, at least one processor core 101 and at least one upper limit register 102 are both connected to a frequency control logic circuit 103 .

A frequency control logic circuit 103, configured to obtain the rate at which at least one processor core generates splitlock, and read the upper limit rate from at least one upper limit register, and reduce the maximum frequency of the target processor core in response to the first rate being greater than or equal to the target upper limit rate .

In one embodiment of the present disclosure, the frequency control logic circuit can be understood as a circuit located in a processor and having a logic operation function. By connecting with at least one processor core, the frequency control logic circuit can perform information interaction with the corresponding processor core, for example, obtain the splitlock generation rate of the corresponding processor core, and send the highest frequency control information to the target processor core, so that the target The processor core lowers its own maximum frequency in response to the maximum frequency control information. And by connecting with at least one upper limit register, the frequency control logic circuit can read the upper limit rate stored in the upper limit register from the corresponding upper limit register.

In one embodiment of the present disclosure, reducing the maximum frequency of the target processor core includes:

In an embodiment of the present disclosure, the frequency of the target processor core before reduction may be understood as the frequency of the target processor core at a moment before the highest frequency of the target processor core is reduced. The pre-reduced frequency of the target processor core can be determined by The frequency control logic circuit is obtained from the target processor core, or the frequency control logic circuit may be obtained from other devices or systems.

In one embodiment of the present disclosure, the reduced maximum frequency of the target processor core is obtained, and the maximum frequency of the target processor core is adjusted to the reduced maximum frequency until the second rate at which the target processor core generates splitlocks is less than the target upper limit Rate, it can be understood that the preset frequency is lowered by the time threshold as an interval, and the first rate of the target processor core and the frequency of the target processor core are obtained periodically in real time, that is, the frequency before the reduction, and according to the target read from the target upper limit register The upper limit rate, the first rate of real-time acquisition, and the frequency before reduction of real-time acquisition are calculated to obtain the highest frequency of the target processor core after reduction, and the highest frequency of the target processor core is adjusted to the highest frequency after reduction. Wherein, after adjusting the maximum frequency of the target processor core to the reduced maximum frequency, if the rate at which the target processor core generates a splitlock is lower than the target upper limit rate, stop obtaining the reduced maximum frequency of the target processor core.

In one embodiment of the present disclosure, the frequency control logic circuit is also used for:

In an embodiment of the present disclosure, the third rate can be understood as the rate at which the target processor core generates a splitlock at the moment after the frequency control logic circuit reduces the highest frequency of the target processor core.

In an embodiment of the present disclosure, acquiring the third rate may be by performing real-time detection on the target processor core to determine whether the target processor core generates a splitlock, and acquiring the third rate according to the detection result.

In one embodiment of the present disclosure, increasing the maximum frequency of the target processor core can be understood as increasing the threshold value of the frequency according to the preset frequency, and periodically increasing the target processor core at intervals of the preset increase time threshold. Or, it can also be calculated according to the preset frequency increase speed threshold and the highest frequency of the current target processor core to obtain the highest frequency of the target processor core at different times after the increase, and at the corresponding time The maximum frequency of the target processor core is adjusted.

According to the technical solution provided by the embodiments of the present disclosure, the frequency control logic circuit obtains the third rate at which the current target processor core generates splitlock, and increases the maximum frequency of the target processor core in response to the third rate being less than the target upper limit rate, which can Ensure that after the maximum frequency of the target processor core is increased, the rate at which the target processor core generates splitlocks can approach the target upper limit rate, ensuring that the performance of the processor core will not be reduced too much due to the excessive generation of splitlocks Under this condition, try to increase the highest frequency of the target processor core to improve the performance of the target processor core.

Increase the maximum frequency of the target processor core, including:

Obtain the highest frequency after the increase according to the frequency before the increase, the third rate after adjustment, and the frequency adjustment count value, and set the highest frequency of the target processor core as the highest frequency after the increase, adjust the third rate and the frequency adjustment count value Negatively correlated with the highest frequency after elevation.

In an embodiment of the present disclosure, the frequency control logic circuit may start from the moment when the frequency of the target processor core is controlled to decrease, and continuously decrement the frequency adjustment count threshold according to the count decrement speed, so as to obtain the frequency of the target processor core under control. The frequency adjusts the count value at any time after the moment of decrease. Wherein, the frequency adjustment counting threshold and the counting decrement speed may be preset, or may be obtained from other devices or systems.

In one embodiment of the present disclosure, the highest frequency after the increase is obtained according to the frequency before the increase, the third rate and the frequency adjustment count value, which can be used to bring the frequency before the increase, the third rate and the frequency adjustment count value into the preset According to the algorithm, the highest frequency after the increase is calculated; the frequency before the increase, the third rate and the frequency adjustment count value can also be used as input to input the pre-trained model to obtain the output of the model after the increase highest frequency.

In an embodiment of the present disclosure, the highest frequency after the increase is obtained according to the frequency before the increase, the third rate and the frequency adjustment count value, including:

In an embodiment of the present disclosure, FIG. 3 shows a schematic structural block diagram of a processor according to an embodiment of the present disclosure. As shown in FIG. 3 , the processor 100 further includes a frequency adjustment count for storing the frequency adjustment count threshold The threshold register 104 and the frequency adjustment count value register 105 for storing the frequency adjustment count value, the frequency adjustment count threshold register 104 and the frequency adjustment count value register 105 are all connected to the frequency control logic circuit 103;

The frequency control logic circuit 103 is used to store the frequency adjustment count threshold read from the frequency adjustment count threshold register 104 in the frequency adjustment count value register 105 at the moment when the frequency of the control target processor core is lowered, and decrement according to the counting speed Continuously decrementing the frequency adjustment count threshold in the frequency adjustment count value register 105;

Get the current frequency adjustment count value, including:

The current frequency adjustment count value is read from the frequency adjustment count value register 105 .

In an embodiment of the present disclosure, the frequency adjustment count threshold stored in the frequency adjustment count threshold register may be written into the frequency adjustment count threshold register in advance, or may be written by the processor itself or other devices or systems. Adjust count threshold register.

In an embodiment of the present disclosure, the highest frequency of the processor core may be understood as the highest frequency that the target processor core itself can achieve. Setting the maximum frequency of the target processor core to the maximum frequency of the processor core can be understood as no longer restricting the maximum frequency of the target processor core.

FIG. 4 shows a flow chart of a processor control method according to an embodiment of the present disclosure. As shown in FIG. 4 , the processor control The manufacturing method includes steps S101 and S102.

In step S101, a rate at which at least one processor core of a processor generates a split lock (splitlock) and an upper limit rate corresponding to at least one processor core are acquired.

In step S102, in response to the first rate at which the target processor core in at least one processor core generates a splitlock is greater than or equal to the upper limit rate corresponding to the target processor core, reduce the highest frequency of the target processor core, and/or make the target The processor core triggered an alignment check exception.

In one embodiment of the present disclosure, the processor may include one or more processor cores (Core), and each CPU Core may be configured with a cache (Cach), and the cache is located between the processor execution unit and the main memory ( The memory between Dynamic Random Access Memory (DRAM) is usually composed of static memory (Static RAM, SRAM), which is small in scale but fast in access speed. The cache can be used to save a copy of some data in the memory. When the processor reads and writes data, it first accesses the cache, and when the required data does not exist in the cache, it accesses the memory again. The cache is usually divided into multiple groups, and each group is divided into multiple cache lines (cacheline). When fetching a unit from the memory into the cache, a memory area of the size of a cache line is taken to the cache at a time. , and then stored in the corresponding cache data line.

In an embodiment of the present disclosure, the upper limit rate can be stored in the upper limit register in advance, or can be calculated by the processor itself based on the processor's history log according to a corresponding algorithm or model, and written into the upper limit register, or It can be written into the upper limit register by other devices or systems.

In one embodiment of the present disclosure, the reduction of the maximum frequency of the target processor core can be understood as, the target processing The highest frequency of the processor core is set to the preset frequency; or, it is also possible to pre-set the rate level for different rates of splitlock generation, and set the corresponding relationship between the rate level and the highest frequency, which is determined before reducing the highest frequency of the target processor core The target speed level corresponding to the first rate, obtaining the highest frequency corresponding to the target speed level, and setting the highest frequency of the target processor core to the highest frequency corresponding to the target speed level.

According to the technical solution provided by the embodiments of the present disclosure, by obtaining the rate at which at least one processor core generates a splitlock and the upper limit rate corresponding to at least one processor core, when considering that the rate at which the processor core generates a splitlock is low, the processing The performance of the processor core will not be reduced too much, so it can be determined based on the upper limit rate whether the rate at which the corresponding processor core generates a splitlock is higher, so that the first rate at which the target processor core generates a splitlock is greater than or equal to that of the target processor When the target upper limit rate corresponding to the core (that is, the rate at which the target processor core generates splitlocks is relatively high), the maximum frequency of the target processor core is reduced, and/or the target processor core triggers an alignment check exception. Wherein, since the frequency of the processor core is positively correlated with the rate at which the processor core produces the splitlock, only when the first rate at which the target processor core produces the splitlock is relatively high, the highest frequency of the target processor core is reduced to ensure When the rate at which the splitlock is generated is low and the performance of the target processor core will not be reduced too much, it will not affect the normal operation of the target processor core (that is, the highest frequency of the target processor core will not be reduced), and the rate at which the splitlock will be generated is relatively high. High, when the performance of the target processor core may be reduced too much, the maximum frequency of the target processor core will be reduced, and the rate of splitlock generation will also be reduced to ensure that the performance of the processor core will not be reduced too much due to the generation of splitlock Many, so that related applications running on the target processor core (such as applications that may cause splitlock) can be executed normally, and related applications running on other processor cores will not be affected too much; in addition , only when the first rate of splitlock generated by the target processor core is high, the target processor core triggers an alignment check exception, which can ensure that when the rate of splitlock generated is low and the performance of the target processor core will not be reduced too much, The target processor core will not trigger an alignment check exception, so that related applications running on the target processor core (such as applications that may cause splitlocks) can be executed normally, while related applications running on other processor cores It will not be affected too much, and the user experience will not be damaged in any way. When the rate of splitlock generation is high, which may reduce the performance of the target processor core too much, the target processor core will trigger an alignment check exception to ensure processing The performance of the core will not be degraded too much due to the splitlock. Therefore, the above solution ensures that the performance of the processor core will not be degraded too much due to the generation of the splitlock without affecting the normal execution of the user application program running on the processor as much as possible, thereby improving the user experience.

In one embodiment of the present disclosure, in step S102, reducing the maximum frequency of the target processor core may be achieved through the following steps:

In an embodiment of the present disclosure, the frequency of the target processor core before reduction may be understood as the frequency of the target processor core at a moment before the highest frequency of the target processor core is reduced. The pre-reduced frequency of the target processor core can be changed from The target processor core can also be obtained from other devices or systems.

In one embodiment of the present disclosure, the reduced maximum frequency of the target processor core is obtained, and the maximum frequency of the target processor core is adjusted to the reduced maximum frequency until the second rate at which the target processor core generates splitlocks is less than the target upper limit Rate, it can be understood that the preset frequency is lowered by the time threshold as an interval, and the first rate of the target processor core and the frequency of the target processor core are obtained periodically in real time, that is, the frequency before the reduction, and according to the target read from the target upper limit register The upper limit rate, the first rate of real-time acquisition, and the frequency before reduction of real-time acquisition are calculated to obtain the highest frequency of the target processor core after reduction, and the highest frequency of the target processor core is adjusted to the highest frequency after reduction. Wherein, after the highest frequency of the target processor core is adjusted to the highest frequency after the reduction, if the rate at which the target processor core generates the splitlock, that is, the first rate is less than the target upper limit rate, stop obtaining the highest frequency after the reduction of the target processor core .

In one embodiment of the present disclosure, the method further includes the following steps:

In an embodiment of the present disclosure, the third rate may be understood as the rate at which the target processor core generates a splitlock at the moment after the highest frequency of the target processor core is reduced.

In an embodiment of the present disclosure, obtaining the third rate may be by performing real-time detection on the target processor core to determine whether the target processor core generates a splitlock, and obtaining the third rate according to the detection result,

Increase the maximum frequency of the target processor core, including:

Obtain the highest frequency after the increase according to the frequency before the increase, the third rate and the frequency adjustment count value, and set the maximum frequency of the target processor core as the highest frequency after the increase, and the third and frequency adjustment count values are the same as after the increase The highest frequency is negatively correlated.

In an embodiment of the present disclosure, the frequency adjustment count threshold can be continuously decremented according to the count decrement speed from the moment when the frequency of the target processor core is lowered, so as to obtain the Frequency adjustment count value at any time. Wherein, the frequency adjustment counting threshold and the counting decrement speed may be preset, or may be obtained from other devices or systems.

According to the technical solution provided by the embodiments of the present disclosure, by obtaining the current frequency adjustment count value and the pre-increase frequency of the current target processor core, the highest frequency after the increase is obtained according to the pre-increase frequency, the third rate, and the frequency adjustment count value , and set the highest frequency of the target processor core as the highest frequency after the increase, and the third rate and the frequency adjustment count value are negatively correlated with the highest frequency after the increase. Among them, considering that when the third rate is already in a relatively high state, if the maximum frequency obtained after the increase is high, it may cause that after the maximum frequency of the target processor core is set to the maximum frequency after the increase, the target processing The frequency of the processor core is too high, which in turn causes the target processor core to generate a splitlock at a higher rate, and even the rate at which the target processor core generates a splitlock may be greater than or equal to the target upper limit rate. Therefore, by making the third rate and the increased maximum frequency negative Correlation, it can avoid that the highest frequency is also higher after the increase when the first rate is already in a higher state; and the frequency adjustment count value is inversely proportional to the time length from the moment when the frequency of the control target processor core is lowered to the current moment, the The longer the time length is, the smaller the frequency adjustment count value is, and considering that the longer the time length is, the greater the impact on the normal application program execution of the target processor core is, so by making the highest frequency after the increase negatively correlated with the frequency adjustment count value , can prevent the frequency of the target processor core from being too low for a long time, so that the normal application programs executed by the target processor core will not be too much affected.

In an embodiment of the present disclosure, obtaining the highest frequency after the increase according to the frequency before the increase, the third rate and the frequency adjustment count value can be achieved through the following steps:

According to Ft ₂ =Fc ₂ +Fc ₂ *(R/C ₂ -1)*((T-Tc)/T), obtain the highest frequency Ft ₂ after the increase, where Fc ₂ is the frequency before the increase, and R is the target upper limit rate, C ₂ is the adjusted third rate, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.

A processor control device according to an embodiment of the present disclosure will be described below with reference to FIG. 5 , and FIG. 5 shows a structural block diagram of a processor control device 200 according to an embodiment of the present disclosure.

As shown in Figure 5, the processor control device 200 includes:

The rate acquisition module 201 is configured to acquire the rate at which at least one processor core of the processor generates a split lock (splitlock) and the upper limit rate corresponding to at least one processor core;

The frequency control module 202 is configured to reduce the maximum frequency of the target processor core in response to the first rate at which the target processor core in the at least one processor core generates a splitlock is greater than or equal to the upper limit rate corresponding to the target processor core, and/or Or cause the target processor core to trigger an alignment check exception.

According to the technical solution provided by the embodiments of the present disclosure, by obtaining the rate at which at least one processor core generates a splitlock and the upper limit rate corresponding to at least one processor core, considering that the rate at which the processor core generates a splitlock is low, the processor The performance of the core will not be reduced too much, so it can be determined based on the upper limit rate whether the rate at which the corresponding processor core generates the splitlock is higher, so that the first rate at which the target processor core generates the splitlock is greater than or equal to that of the target processor core When the corresponding target upper limit rate (that is, the rate at which the target processor core generates splitlocks is relatively high), the maximum frequency of the target processor core is reduced, and/or the target processor core triggers an alignment check exception. Wherein, since the frequency of the processor core is positively correlated with the rate at which the processor core produces the splitlock, only when the first rate at which the target processor core produces the splitlock is relatively high, the highest frequency of the target processor core is reduced to ensure When the rate at which the splitlock is generated is low and the performance of the target processor core will not be reduced too much, it will not affect the normal operation of the target processor core (that is, the highest frequency of the target processor core will not be reduced), and the rate at which the splitlock will be generated is relatively high. High, when the performance of the target processor core may be reduced too much, the maximum frequency of the target processor core will be reduced, and the rate of splitlock generation will also be reduced to ensure that the performance of the processor core will not be reduced too much due to the generation of splitlock multiple, so that the phase running on the target processor core Related applications (such as applications that may cause splitlocks) can be executed normally, and related applications running on other processor cores will not be affected too much; in addition, only the first splitlock generated by the target processor core When the rate is high, the target processor core will trigger an alignment check exception, which can ensure that the target processor core will not trigger an alignment check exception when the splitlock rate is low and the performance of the target processor core will not be reduced too much. The relevant applications running on the target processor core (for example, the applications that may cause splitlock) can be executed normally, while the related applications running on other processor cores will not be affected too much, and the user experience will be improved. It will not suffer any damage, and when the rate of splitlock generation is high, which may reduce the performance of the target processor core too much, the target processor core will trigger an alignment check exception to ensure that the performance of the processor core will not be reduced due to the generation of splitlock excessive. Therefore, the above solution ensures that the performance of the processor core will not be degraded too much due to the generation of the splitlock without affecting the normal execution of the user application program running on the processor as much as possible, thereby improving the user experience.

Those skilled in the art can understand that the technical solution described with reference to FIG. 5 can be combined with any embodiment described above, so as to have the technical effect achieved by any embodiment described above. For specific content, reference may be made to the description of the foregoing embodiments, and the specific content is not repeated here.

The embodiment of the present disclosure also provides an electronic device. FIG. 6 shows a structural block diagram of the electronic device according to an embodiment of the present disclosure. As shown in FIG. 6 , the electronic device 303 includes at least one processor 301; The memory 302 connected to the device 301 in communication; wherein, the memory 302 stores instructions that can be executed by at least one processor 301, and the instructions are executed by at least one processor 301 to implement the following steps:

An embodiment of the present disclosure provides a method for controlling a processor, wherein the method includes:

Obtain the rate at which at least one processor core of the processor generates a splitlock and the upper limit rate corresponding to at least one processor core;

Increase the maximum frequency of the target processor core, including:

In combination with the third implementation of the second aspect, in the fourth implementation of the second aspect of the present disclosure, the highest frequency after the increase is obtained according to the frequency before the increase, the third rate, and the frequency adjustment count value, including:

FIG. 7 is a schematic structural diagram of a computer system suitable for implementing a method according to an embodiment of the present disclosure. As shown in FIG. 7 , a computer system 400 includes a processing unit 401 that can execute the above-mentioned additional processing unit 401 according to a program stored in a read-only memory (ROM) 402 or a program loaded from a storage section 408 into a random access memory (RAM) 403. Various processes in the embodiment shown in the figure. In the RAM 403, various programs and data necessary for the operation of the system 400 are also stored. The processing unit 401 , ROM 402 and RAM 403 are connected to each other through a bus 404 . An input/output (I/O) interface 405 is also connected to bus 404 .

The following components are connected to the I/O interface 405: an input section 406 including a keyboard, a mouse, etc.; an output section 407 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 408 including a hard disk, etc. and a communication section 409 including a network interface card such as a LAN card, a modem, or the like. The communication section 409 performs communication processing via a network such as the Internet. A drive 410 is also connected to the I/O interface 405 as needed. A removable medium 411 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is mounted on the drive 410 as necessary so that a computer program read therefrom is installed into the storage section 408 as necessary. Wherein, the processing unit 401 may be implemented as a processing unit such as a CPU, GPU, TPU, FPGA, or NPU.

In particular, according to the embodiments of the present disclosure, the methods described above with reference to the accompanying drawings can be implemented as computer software programs. Exemplarily, the embodiments of the present disclosure include a computer program product including a computer program tangibly embodied on a readable medium thereof, the computer program including program code for performing the methods in the accompanying drawings. At this In such an embodiment, the computer program may be downloaded and installed from the network through the communication part 409, and/or may be installed from the removable medium 411. Exemplarily, the embodiments of the present disclosure include a readable storage medium on which computer instructions are stored, and when the computer instructions are executed by a processor, program codes for executing the methods in the drawings are implemented.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in a roadmap or block diagram may represent a module, program segment, or part of code that contains one or more Executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified functions or operations , or may be implemented by a combination of dedicated hardware and computer instructions.

The units or modules involved in the embodiments described in the present disclosure may be implemented by means of software or hardware. The described units or modules may also be set in the processor, and the names of these units or modules do not constitute limitations on the units or modules themselves in some cases.

As another aspect, the present disclosure also provides a computer-readable storage medium, which may be a computer-readable storage medium included in the computer system described in the above-mentioned implementation manners; or exist independently, A computer-readable storage medium that is not incorporated into a device. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the methods described in the present disclosure.

The above description is only a preferred embodiment of the present disclosure and an illustration of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to the technical solution formed by the specific combination of the above-mentioned technical features, but should also cover the technical solutions made by the above-mentioned technical features without departing from the inventive concept. Other technical solutions formed by any combination of or equivalent features thereof. A technical solution formed by replacing the exemplary above-mentioned features with technical features disclosed in this disclosure (but not limited to) having similar functions.

Claims

A processor, wherein the processor includes at least one processor core and at least one upper limit register;

The upper limit register is used to store the upper limit rate. When the first rate at which the target processor core corresponding to the target upper limit register generates a split lock (splitlock) is greater than or equal to the target upper limit rate in the target upper limit register, the target processing The highest frequency of the processor core is reduced, and/or the target processor core triggers an alignment check exception, the target upper limit register belongs to the at least one upper limit register, and the target processor core belongs to the at least one processor core.
The processor according to claim 1, wherein the processor further comprises a frequency control logic circuit, and both the at least one processor core and the at least one upper limit register are connected to the frequency control logic circuit;

The frequency control logic circuit is configured to obtain the rate at which at least one processor core generates a splitlock, and read the upper limit rate from at least one upper limit register, and reduce the The maximum frequency of the target processor core.
The processor according to claim 2, wherein said reducing the highest frequency of the target processor core comprises:

Acquiring the reduced maximum frequency of the target processor core, and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates a splitlock is less than the target upper limit rate;

Wherein, the highest frequency after the reduction is obtained according to Ft 1 =Fc 1 *R/C 1 , where Ft 1 is the highest frequency after the reduction, Fc 1 is the frequency before reduction of the target processor core, and R is the Target upper limit rate, C1 is the first rate.
The processor according to claim 2 or 3, wherein the frequency control logic circuit is further used for:

Obtain the third rate at which the current target processor core generates a splitlock;

In response to the third rate being less than the target upper limit rate, increasing the maximum frequency of the target processor core.
The processor according to claim 4, wherein the frequency control logic circuit is further used for:

Obtain the current frequency adjustment count value and the current frequency before the increase of the target processor core, the frequency adjustment count value starts from the moment when the frequency of the target processor core is controlled, and adjusts the frequency according to the count decrement speed The counting threshold is continuously decremented;

Said raising the highest frequency of said target processor core includes:

Obtain the highest frequency after the increase according to the frequency before the increase, the third rate and the frequency adjustment count value, and set the highest frequency of the target processor core as the highest frequency after the increase, the Both the third rate and the frequency adjustment count value are negatively correlated with the increased highest frequency.
The processor according to claim 5, wherein said frequency before said boosting, said third rate at And the frequency adjustment count value obtains the highest frequency after the increase, including:

According to Ft 2 =Fc 2 +Fc 2 *(R/C 2 -1)*((T-Tc)/T), the highest frequency Ft 2 after the increase is obtained, wherein Fc 2 is the frequency before the increase, and R is The target upper limit rate, C 2 is the third rate, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.
The processor according to claim 5, wherein the processor further comprises a frequency adjustment count threshold register for storing the frequency adjustment count threshold and a frequency adjustment count value register for storing the frequency adjustment count value, Both the frequency adjustment count threshold register and the frequency adjustment count value register are connected to the frequency control logic circuit;

The frequency control logic circuit is configured to store the frequency adjustment count threshold read from the frequency adjustment count threshold register in the frequency adjustment count value register when controlling the frequency reduction of the target processor core, and continuously decrementing the frequency adjustment count threshold in the frequency adjustment count value register according to the count decrement speed;

The acquisition of the current frequency adjustment count value includes:

Read the current frequency adjustment count value from the frequency adjustment count value register.
A processor control method, wherein the method comprises:

Obtain the rate at which at least one processor core of the processor generates a split lock (splitlock) and the upper limit rate corresponding to at least one processor core;

In response to the first rate at which the target processor core in the at least one processor core generates a splitlock is greater than or equal to the upper limit rate corresponding to the target processor core, reduce the maximum frequency of the target processor core, and/or enable The target processor core triggers an alignment check exception.
The processor control method according to claim 8, wherein said reducing the highest frequency of the target processor core comprises:

Acquiring the reduced maximum frequency of the target processor core, and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates a splitlock is less than the target upper limit rate;

Wherein, the highest frequency after the reduction is obtained according to Ft 1 =Fc 1 *R/C 1 , where Ft 1 is the highest frequency after the reduction, Fc 1 is the frequency before reduction of the target processor core, and R is the Target upper limit rate, C1 is the first rate.
The processor control method according to claim 8 or 9, wherein the method further comprises:

Obtain the third rate at which the current target processor core generates a splitlock;

In response to the third rate being less than the target upper limit rate, increasing the maximum frequency of the target processor core.
The processor control method according to claim 10, wherein said method further comprises:

Obtain the current frequency adjustment count value and the current frequency before the increase of the target processor core, the frequency adjustment count value starts from the moment when the frequency of the target processor core is controlled, and adjusts the frequency according to the count decrement speed The counting threshold is continuously decremented;

Said raising the highest frequency of said target processor core includes:

Obtain the highest frequency after the increase according to the frequency before the increase, the third rate and the frequency adjustment count value, and set the highest frequency of the target processor core as the highest frequency after the increase, the Both the third rate and the frequency adjustment count value are negatively correlated with the increased highest frequency.
The processor control method according to claim 11, wherein said obtaining the highest frequency after the increase according to the frequency before the increase, the third rate and the frequency adjustment count value comprises:

According to Ft 2 =Fc 2 +Fc 2 *(R/C 2 -1)*((T-Tc)/T), the highest frequency Ft 2 after the increase is obtained, wherein Fc 2 is the frequency before the increase, and R is The target upper limit rate, C 2 is the third rate, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.
An electronic device, characterized by comprising a memory and at least one processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the at least one processor To realize the method steps described in any one of claims 8-12.
A computer-readable storage medium on which computer instructions are stored, wherein the computer instructions are executed by a processor to implement the method steps described in any one of claims 8-12.