WO2023155480A1 - Circuit intégré et procédé d'essai pour circuit intégré - Google Patents

Circuit intégré et procédé d'essai pour circuit intégré Download PDF

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Publication number
WO2023155480A1
WO2023155480A1 PCT/CN2022/128643 CN2022128643W WO2023155480A1 WO 2023155480 A1 WO2023155480 A1 WO 2023155480A1 CN 2022128643 W CN2022128643 W CN 2022128643W WO 2023155480 A1 WO2023155480 A1 WO 2023155480A1
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Prior art keywords
test
option
memory
read
integrated circuit
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PCT/CN2022/128643
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English (en)
Chinese (zh)
Inventor
崔昌明
张志方
黄俊林
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华为技术有限公司
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Publication of WO2023155480A1 publication Critical patent/WO2023155480A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of semiconductors, in particular to an integrated circuit and a testing method for the integrated circuit.
  • Built-in self-test means that the circuit has a self-test function that generates test vectors by itself and checks the test results by itself.
  • BIST is realized by building test-related functional circuits into the circuit.
  • BIST is also used in more and more integrated circuits, and the vast majority of integrated circuits use a built-in BIST controller in the integrated circuit to control the module to be tested in the integrated circuit. test.
  • the BIST controller is usually mounted under the test access port (TAP) controller, and the TAP controller receives the test configuration sequence, which includes multiple test options, and the TAP controller
  • TAP test access port
  • the multiple test options are transmitted to the BIST controller, so that the BIST controller controls the module to be tested in the integrated circuit to perform self-test according to the multiple test options.
  • the joint test action group (joint test action group, JTAG) pin in the integrated circuit is turned on, and the integrated circuit automatic test machine (automatic test equipment, ATE) can be connected to the JTAG pin , so that the ATE transmits the generated test configuration sequence to the TAP controller through the JTAG pin, and at this time, the ATE can modify one or more test options in the test configuration sequence according to the current test requirement.
  • the JTAG pins in the integrated circuit are generally closed.
  • the processor in the integrated circuit can then be used to transmit the test configuration sequence to the TAP controller when the integrated circuit is powered on and operating normally.
  • test configuration sequence preset in the read-only memory (ROM) is transmitted to the TAP controller.
  • the test configuration sequence preset in the read-only memory ROM cannot be changed, so that the integrated circuit needs to be tested after power-on, and when the processor in the integrated circuit is not running normally, it cannot be tested according to the actual situation.
  • the test requirement modifies one or more test options in the sequence of test configurations retrieved from the read-only memory ROM.
  • the embodiment of the present application provides an integrated circuit and an integrated circuit testing method, so that the integrated circuit needs to be tested after it is powered on, and when the processor in the integrated circuit is not running normally at this time, it can be tested according to the actual testing requirements Modify one or more test options in a sequence of test configurations retrieved from read-only memory.
  • the embodiment of the present application provides an integrated circuit, including: a read-only memory, an output circuit, and at least one programmable memory; the read-only memory is used to store a first test configuration sequence, and the first test configuration sequence includes a plurality of a test value of a test option; at least one programmable memory for storing a programmed value of a target test option of the plurality of test options; an output circuit configured to read a first test configuration sequence after power-up; the output circuit is also configured by configured to read programmed values of the target test options; the output circuit is further configured to generate a second sequence of test configurations based on the first sequence of test configurations and the programmed values of the target test options.
  • the output circuit reads the first test configuration sequence stored in the read-only memory after power-on, there are multiple test options in the first test configuration sequence, and the output circuit also reads at least one programmable memory
  • the programming value of the target test option stored in since the target test option is the test option that needs to be modified in the first test configuration sequence, after the output circuit obtains the programming value of the first test configuration sequence and the target test sequence, the output circuit can be based on The first test configuration sequence and the programming value of the target test option generate the second test configuration sequence, then when the output circuit sends the second test configuration sequence to the test equipment, the test equipment can perform the test on the module to be tested according to the second test configuration sequence Test, so that the integrated circuit needs to be tested after power-on, and at this time, when the processor in the integrated circuit is not running normally, one of the test configuration sequences obtained from the read-only memory can be modified according to the actual test requirements or multiple test options.
  • At least one programmable memory includes a first storage area and a second storage area, the first storage area is used to store the position of the target test option in the read-only memory, and the second storage area is used to store the programming of the target test option value; the output circuit is also configured to read the location of the target test option in the read-only memory; the output circuit is specifically configured to be based on the first test configuration sequence, the location of the target test option in the read-only memory, and the target test option The programmed value of generates the second test configuration sequence.
  • At least one programmable memory includes two storage areas, the first storage area in the two storage areas stores the position of the target test option in the read-only memory, and the second storage area is used to store the target test option
  • the programming value of the target test option then after the integrated circuit is powered on, the output circuit can read the position of the target test option in the read-only memory from the first storage area, and can also read the programming value of the target test option from the second storage area , since the target test option is the test option that needs to be modified in the first test configuration sequence, the output circuit can specify which test options in the first test configuration sequence need to be modified according to the position of the target test option in the read-only memory, and output The circuit generates a second sequence of test configurations based on the first sequence of test configurations, the location of the target test option in the read-only memory, and the programmed value of the target test option.
  • the output circuit includes a flipper and a selector; the flipper is specifically configured to generate an enable signal according to the position of the target test option in the read-only memory and other positions; wherein the enable signal is in the read-only memory of the target test option The location in the memory is in the first state, the enable signal is in the second state at other locations, and the other locations include the locations in the read-only memory of test options other than the target test option in the first configuration sequence; the selector, Used to obtain the programming value of the target test option in the second storage area when the enable signal is in the first state, and obtain the test values of other test options when the enable signal is in the second state, according to the programming value of the target test option and The test values of the other test options generate a second sequence of test configurations.
  • the flipper In this optional mode, the flipper generates an enable signal according to the position of the target test option in the programmable memory in the read-only memory, and the first state in the enable signal represents the position of the target test option in the read-only memory, The second state of the enable signal indicates the positions of other test options in the read-only memory except the target test option among the plurality of test options, so that the selector can accurately obtain the programming of the target test option according to the different states of the enable signal value and test values of other test options except the target test option, thereby generating a second test configuration sequence.
  • the at least one programmable memory includes a first programmable memory and a second programmable memory; the first programmable memory provides a first storage area, and the second programmable memory provides a second storage area.
  • the programming value of the target test option and the position of the target test option in the read-only memory can be stored in different programmable memories to expand the storage space, so that the integrated circuit can test more targets. Test options are modified.
  • the multiple test options include: a list of modules to be tested, a test intensity parameter, and a test configuration.
  • the target test option includes one or more of the following: a list of modules to be tested, a test intensity parameter, and a test configuration.
  • a method for testing an integrated circuit includes: a read-only memory, an output circuit, and at least one programmable memory; the read-only memory is used to store a first test configuration sequence, and the first test configuration sequence includes multiple The test value of a test option; at least one programmable memory is used to store the programming value of the target test option in the plurality of test options; the test method of the integrated circuit includes: reading the first test configuration sequence after power-on; reading the target Programmed values of test options; generating a second sequence of test configurations based on the first sequence of test configurations and the programmed values of target test options.
  • At least one programmable memory includes a first storage area and a second storage area, the first storage area is used to store the position of the target test option in the read-only memory, and the second storage area is used to store the programming of the target test option value;
  • the test method of the integrated circuit also includes: reading the position of the target test option in the read-only memory; then generating the second test configuration sequence according to the programming value of the first test configuration sequence and the target test option specifically includes: according to the first test The configuration sequence, the location of the target test option in the read-only memory, and the programmed value of the target test option generate a second test configuration sequence.
  • the second test configuration sequence is generated according to the first test configuration sequence, the position of the target test option in the read-only memory, and the programming value of the target test option, specifically including: according to the position of the target test option in the read-only memory and Generate enable signals at other locations; wherein the enable signals are in a first state at locations in the read-only memory of the target test option, and the enable signals are in a second state at other locations, including those in the first configuration sequence except for the target The location of other test options other than the test option in the read-only memory; when the enable signal is in the first state, obtain the programming value of the target test option in the second storage area, and obtain other test options when the enable signal is in the second state Test values for options; generating a second sequence of test configurations based on the programmed values of the target test options and the test values of the other test options.
  • the multiple test options include: a list of modules to be tested, a test intensity parameter, and a test configuration.
  • the target test option includes one or more of the following: a list of modules to be tested, a test intensity parameter, and a test configuration.
  • an electronic device including a printed circuit board and the integrated circuit according to any one of the above-mentioned first aspect disposed on the printed circuit board.
  • a computer-readable storage medium including computer instructions.
  • the computer instructions When the computer instructions are run on an electronic device, the electronic device is made to execute the method described in any one of the above-mentioned second aspects.
  • a computer program product is provided.
  • the computer program product is run on an electronic device, the electronic device is made to execute the method described in any one of the above-mentioned second aspects.
  • the technical effect brought about by any possible implementation manner of the second aspect to the fifth aspect may refer to the technical effect brought about by any one of the different implementation manners of the above-mentioned first aspect, which will not be repeated here.
  • FIG. 1 is a schematic structural diagram of an integrated circuit provided in Embodiment 1 of the present application.
  • FIG. 2 is a schematic structural diagram of an integrated circuit provided in Embodiment 2 of the present application.
  • FIG. 3 is a schematic structural diagram of the BIST provided in Embodiment 2 of the present application.
  • FIG. 4 is a schematic structural diagram of an integrated circuit provided in Embodiment 3 of the present application.
  • FIG. 5 is another schematic structural diagram of the integrated circuit provided in Embodiment 3 of the present application.
  • FIG. 6 is another structural schematic diagram of the integrated circuit provided in Embodiment 3 of the present application.
  • FIG. 7 is a schematic structural diagram of an integrated circuit provided in Embodiment 4 of the present application.
  • FIG. 8 is a schematic structural diagram of an integrated circuit provided in Embodiment 5 of the present application.
  • FIG. 9 is a schematic flowchart of a testing method for an integrated circuit provided in Embodiment 6 of the present application.
  • At least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be It can be single or multiple.
  • words such as "first" and "second” do not limit the quantity and order.
  • JTAG joint test action group
  • TAP Test Access Port
  • Built-in self-test means that the circuit has a self-test function that generates test vectors by itself and checks the test results by itself.
  • BIST is realized by building test-related functional circuits into the circuit.
  • BIST is also used in more and more integrated circuits, and the vast majority of integrated circuits use a built-in BIST controller in the integrated circuit to control the module to be tested in the integrated circuit. test.
  • the embodiment of the present application provides the structural representation of integrated circuit 100, and this integrated circuit 100 comprises processor 101, read-only memory (read-only memory, ROM) 102, test equipment 103 and module 104 to be tested .
  • the processor 101 is configured to generate a test configuration sequence
  • the test configuration sequence is stored in the read-only memory 102
  • the above-mentioned test configuration sequence includes a plurality of test options.
  • the test device 103 can receive the test configuration sequence in the processor 101 or receive the test configuration sequence stored in the read-only memory 102, so that the test device 103 treats it according to the test configuration sequence Test module 104 for testing.
  • Fig. 2 provides the schematic structural diagram of the principle of integrated circuit 200, and in this integrated circuit 200, comprise JTAG pin 201, processor 202, read-only memory (read-only memory, ROM) 203, selector 204, TAP controller 205 and BIST controller 206, wherein, JTAG pin 201, processor 202 and ROM 203 are all connected to selector 204, and selector 204 is also connected to TAP controller 205, and TAP controller 205 is connected to the BIST controller 206 .
  • JTAG pin 201, processor 202 and ROM 203 are all connected to selector 204, and selector 204 is also connected to TAP controller 205, and TAP controller 205 is connected to the BIST controller 206 .
  • the BIST controller 206 includes a BIST controller 206a, a BIST controller 206b, and a BIST controller 206c, and each BIST controller includes a logic built in self test (logic built in self test, LBIST) 2061 and/or memory built-in Self-test (memory build in self test, MBIST) 2062.
  • the JTAG pin 201 includes a test data input (test data input, TDI) pin, a test mode selection (test mode selection input, TMS) pin, a test clock input (test clock input, TCK) pin and a test data output (test data output, TDO) pins, these four pins are mandatory pins stipulated in the IEEE1149.1 standard. Wherein, the JTAG pin 201 can also transmit the test configuration sequence.
  • the selector 204 and the TAP controller 205 constitute the testing device 103
  • each MBIST or LBIST in the BIST controller 206 constitutes the module under test 104 .
  • BIST controllers there may be more or fewer BIST controllers in the integrated circuit shown in FIG.
  • Other functional circuits may be included, and the embodiment of the present application does not limit the number of BIST controllers 206 and the functional circuits included in the BIST controller.
  • the selector 204 can select any one of the JTAG pin 201 , the processor 202 or the ROM 203 to transmit the test configuration sequence conforming to the IEEE 1149.1 standard to the TAP controller 205 .
  • an integrated circuit automatic tester (automatic test equipment, ATE) is generally connected to the JTAG pin 201.
  • the selector 204 selects the JTAG pin 201 to transmit the information generated by ATE that complies with IEEE
  • the 1149.1 standard test configuration sequence is sent to the TAP controller, the test configuration sequence includes multiple test options, and the TAP controller transmits the multiple test options to the BIST controller, so that the BIST controller performs self-test according to the multiple test options.
  • the above test configuration sequence also includes the TDI control signal transmitted by the ATE to the TDI pin, the TMS control signal transmitted by the ATE to the TMS pin, and the TCK control signal transmitted by the ATE to the TCK pin.
  • the control signal, the TMS control signal and the TCK control signal are transmitted to the TAP controller 205 so that the TAP control sequence realizes the access to the internal registers of the integrated circuit.
  • the TAP controller connects a selected register between the TDI pin and the TDO pin, and then is driven by the TCK control signal, and transmits the TDI control signal through the TDI pin.
  • the TDI control signal includes the register that needs to be written to the selected The data in one of the registers is used to write the data that needs to be written into the selected register to the selected register, or to read the data in the selected register through the TDO pin .
  • the registers inside the integrated circuit include an instruction register (instruction register, IR) and a data register (data register, DR), and the TMS control signal transmitted by the ATE is kept at a high level and the transmission of the TCK control signal includes at least 5 strobe pulses (A strobe pulse is that the TCK control signal first changes to a high level and then changes to a low level).
  • a strobe pulse is that the TCK control signal first changes to a high level and then changes to a low level.
  • the TAP controller 205 is in the test logic reset state (test logic reset), and then the TAP controller 205 drives according to the rising edge of the TCK control signal.
  • the TAP controller can select the instruction register, write data to the instruction register, read the data in the instruction register, select the data register, and write data to the data register. Write data, read data in the data register and other different functions. It should be noted that, for specific functions that can be realized by switching among the 16 states of the TAP controller, reference may be made to the function description of the existing TAP controller, which will not be repeated here.
  • the ATE transmits the test configuration sequence conforming to the IEEE 1149.1 standard through the JTAG pin 201 and also includes the TRST transmitted to the TRST pin. control signal, and the TAP controller 205 is in a test logic reset state when the TRST control signal is at a high level.
  • TRST test reset input
  • the data registers also include some user-defined data registers (user defined data registers), and the TAP controller 205 can access the user-defined data registers by switching between the above 16 states.
  • selector 204 selects the test configuration sequence that conforms to IEEE 1149.1 standard that JTAG pin 201 transmission ATE generates to TAP controller, and this test configuration sequence also includes a plurality of test options, TAP controller 205 The access to the user-defined registers inside the integrated circuit is realized through the switching of the above 16 states.
  • the TAP controller transmits a plurality of test options through the TDI pin, writes the plurality of test options into different user-defined registers, and then, the TAP controller 205 controls the user-defined data registers to realize user-defined
  • the test options written in the definition register are transmitted to the BIST controller 206, so that the BIST controller performs self-test according to a plurality of test options.
  • test vector generation module 301 includes a linear feedback shift register (linear feedback shift register, LFSR), the test vector generation module 301 can generate test vectors according to the test options, and transmit the generated test vectors to the circuit under test 302.
  • LFSR linear feedback shift register
  • the test vector may be a signal controlling a logic function circuit module in an integrated circuit; in MBIST2062, the test vector may be stored information stored in a memory of the integrated circuit.
  • the circuit under test 302 generates an output value according to the test vector.
  • the circuit under test 302 can be any logic function circuit module in an integrated circuit; in MBIST2062, the circuit under test 302 can specifically be an integrated circuit any of the memory.
  • the output response analysis module 303 includes a multi-input signature register (multiple-input signature register, MISR), and the multi-input signature register MISR obtains an output value from the circuit under test 302, and generates a compressed output vector, which is called a feature , and the output response analysis module 303 compares this characteristic with a known characteristic obtained from a module under test without failure, determines the correctness of the circuit under test 302 according to the comparison result, and generates a test result.
  • MISR multi-input signature register
  • the test result generated by the output response analysis module 303 is transmitted to the BIST controller 206, and the BIST controller 206 is also connected to the user-defined register in the integrated circuit, then the ATE can control the TAP controller 205 so that the user-defined register connected to the BIST controller 206 acquires the test result generated by the output response analysis module 303 in the BIST controller 206, and transmits the test result to the ATE through the TDO pin.
  • the multiple test options in the test configuration sequence transmitted by the ATE to the TAP controller 205 include a list of modules to be tested, a test intensity, and a test configuration.
  • the ATE can modify one or more test options in the test configuration sequence according to actual test requirements, so as to make the self-test of the BIST controller 206 more flexible.
  • the ATE is connected to the JTAG pin 201, and the selector 204 selects the JTAG pin 201 to transmit the test configuration sequence generated by the ATE and conforming to the IEEE 1149.1 standard to the TAP controller.
  • the test configuration sequence Including multiple test options, the BIST controller performs self-test according to multiple test options. It should be noted that after the integrated circuit is manufactured, the JTAG pin 201 in the integrated circuit will be closed, the purpose of which is to prevent the integrated circuit from being maliciously damaged during the application process.
  • the selector 204 can select the test configuration sequence generated by the processor 202 and transmit the IEEE 1149.1 standard to the TAP controller 205, the test configuration sequence Including multiple test options, the BIST controller performs self-test according to multiple test options. Moreover, the processor 202 may modify one or more test options in the test configuration sequence according to actual test requirements, so as to make the self-test of the BIST controller 206 more flexible.
  • processor 202 may be a central processing unit (central processing unit, CPU), a general-purpose processor, a network processor (network processor, NP), a digital signal processor (digital signal processing, DSP), a microprocessor , microcontroller, programmable logic device (programmable logic device, PLD), or any combination of them.
  • the processor 202 may also be any other device with processing functions, such as a circuit, device or software module, and the embodiment of the present application does not specifically limit the specific form of the processor.
  • the selector 204 can select the read-only memory 203 to transmit the test configuration sequence conforming to the IEEE 1149.1 standard to the TAP controller 205, the test configuration sequence includes a plurality of test options, and the BIST controller performs self-test according to the plurality of test options, usually,
  • the test configuration sequence in accordance with the IEEE 1149.1 standard will be preset in the read-only memory 203, and the storage locations of multiple test options in the preset test configuration sequence in the read-only memory 203 will also be stored.
  • test configuration sequence preset in the read-only memory 203 cannot be changed, so that the integrated circuit needs to be tested after being powered on.
  • the test requirement modifies one or more test options in the sequence of test configurations retrieved from the read-only memory ROM.
  • the self-test performed when the integrated circuit is first powered on is also called power-on built-in self-test (power-on BIST).
  • the embodiment of the present application provides an integrated circuit, as shown in FIG.
  • the first test configuration sequence includes the test value of a plurality of test options; the programmable memory 402 is used to store the programming value of the target test option; the output circuit 403 is configured to read the first test configuration sequence; the output circuit 403 is further configured to read the programmed value of the target test option; the output circuit 403 is further configured to generate a second test configuration sequence according to the first test configuration sequence and the programmed value of the target test option.
  • the first test configuration sequence stored in the read-only memory 401 is a test configuration sequence that is preset in the read-only memory 401 and conforms to the IEEE 1149.1 standard when the integrated circuit 400 is produced and manufactured, and the production of the integrated circuit 400
  • the description will show in detail the storage locations and test values of multiple test options in the test configuration sequence preset in the ROM 401 .
  • the multiple test options include: a list of modules to be tested, test intensity and test configuration, the list of modules to be tested is used to indicate which modules to be tested need to be tested, and the test intensity includes: test coverage, test vector number and test time etc., wherein, the test coverage rate indicates the percentage of the module to be tested that can be tested, for example, the test target coverage is 100%, which means that all the modules to be tested are tested, the number of test vectors indicates the test data, and the test time indicates how long it takes to complete the test;
  • the test configuration includes: linear feedback shift register LFSR seed, open clock domain, multi-input feature register MISR comparison value, and test algorithm, etc., where the linear feedback shift register LFSR seed represents the initial value of the linear feedback shift register, and the clock domain is opened Indicates that the test is started when the clock signal is on the rising or falling edge.
  • the comparison value of the multi-input characteristic register MISR represents the characteristic value obtained in the module under test without failure.
  • the test algorithm includes March algorithm and Checkerboard algorithm. Wherein, the test value is specifically used to limit the content or scope of the corresponding test option.
  • the test option may be a list of modules to be tested, and the test value may be the identification of LBIST or MBIST; for another example, the test option may be a test time, and the test value may be a specific time range.
  • the target test option is the test option that needs to be changed.
  • the target test option includes: the list of modules to be tested, the test intensity and the test configuration.
  • the programmable memory 402 is used to store the programming values of the target test options among the plurality of test options. Among them, the programming value is specifically used to limit the content or scope of the corresponding test option change. For example, the test option is the test time, and the test value is 5 seconds, then the programming value can be 10 seconds, which means that the current test time is changed from 5 seconds to 10 seconds.
  • the programmable memory 402 includes one or more of the following memories: programmable read-only memory (programmable read-only memory, PROM), electrically rewritable read-only memory (electrically alterable read only memory, EAROM), erasable programmable Read-only memory (erasable programmable read only memory, EPROM), electrically erasable programmable read-only memory (Electrically erasable programmable read only memory, EEPROM), one time programmable read-only memory (OTPROM) and electronic fuse (electric-fuse, EFUSE).
  • PROM programmable read-only memory
  • PROM electrically rewritable read-only memory
  • EAROM electrically alterable read only memory
  • EPROM erasable programmable Read-only memory
  • EEPROM Electrically erasable programmable read-only memory
  • OTPROM one time programmable read-only memory
  • OTPROM electronic fuse
  • the output circuit 403 is configured to read the first test configuration sequence after power-on; the output circuit 403 is also configured to read the programming value of the target test option; the output circuit 403 is also configured to read the first test configuration sequence according to the first test configuration sequence; and the programmed values of the target test options generate a second sequence of test configurations.
  • the output circuit 403 can transmit the second test configuration sequence to the device under test through a standard interface, and then the device under test is tested according to the second test configuration sequence The module is tested.
  • the output circuit 403 may transmit the second test configuration sequence to the test device 404 , so that the test device 404 tests the module to be tested 405 according to the second test configuration sequence.
  • the output circuit reads the first test configuration sequence stored in the read-only memory after power-on, the first test configuration sequence includes a plurality of test options, and the output circuit also reads the first test configuration sequence stored in at least one programmable memory
  • the programming value of the stored target test option since the target test option is the test option that needs to be modified in the first test configuration sequence, after the output circuit obtains the first test configuration sequence and the programming value of the target test option, the output circuit can be used according to the first test configuration sequence.
  • test configuration sequence and the programming value of the target test option generate a second test configuration sequence, then when the output circuit sends the second test configuration sequence to the test equipment, the test equipment can test the module to be tested according to the second test configuration sequence , so that the integrated circuit needs to be tested after power-on, and at this time, when the processor in the integrated circuit is not running normally, one or Multiple testing options.
  • the programmable memory 402 may include a first storage area and a second storage area, the first storage area is used to store the position of the target test option in the read-only memory, and the second storage area is used to store the programming of the target test option value; then the output circuit 403 is also configured to read the position of the target test option in the read-only memory 401; the output circuit 403 is specifically configured as according to the first test configuration sequence, the position of the target test option in the read-only memory 401 The programmed values of the location and target test options generate a second sequence of test configurations.
  • the target test option can be found according to the content recorded in the production manual of the integrated circuit 400.
  • the position and the test value in the read memory 401 then, store the position of the target test option in the read-only memory 401 in the first storage area of the programmable memory 402, store the target test in the second storage area of the programmable memory 402
  • the programmatic value of the option when it is necessary to change the test value of one or more test options in the multiple test options stored in the read-only memory 401 according to different test requirements, the target test option can be found according to the content recorded in the production manual of the integrated circuit 400.
  • the position and the test value in the read memory 401 then, store the position of the target test option in the read-only memory 401 in the first storage area of the programmable memory 402, store the target test in the second storage area of the programmable memory 402
  • the programmatic value of the option when it is necessary to change the test value of one or more test options in the multiple test options stored in the read-only memory 401 according to different test
  • only one programmable memory 402 may be provided, and the storage space of the programmable memory 402 is divided into a first storage area and a second storage area, and stored in the first storage area The location of the target test option in the read-only memory 401, and the programming value of the target test option is stored in the second storage area.
  • the programmable memory 402 in the integrated circuit 400 Including a first programmable memory 4021 and a second programmable memory 4022, the first programmable memory 4021 provides a first storage area, and stores the position of the target test option in the read-only memory 401 in the first programmable memory 4021;
  • the second programmable memory 4022 provides a second storage area, and the programmed values of the target test options are stored in the second programmable memory 4022 .
  • the first storage area is provided by multiple programmable memories
  • the second storage area is provided by multiple programmable memories
  • the first storage area stores the target
  • the second storage area stores the programming value of the target test option.
  • the embodiments of the present application do not limit the number of programmable memories.
  • the output circuit 403 is also configured to read the position of the target test option in the read-only memory 401; the output circuit 403 is specifically configured to read the position of the target test option in the read-only memory 401 according to the first test configuration sequence. and the programmed values of the target test options generate a second sequence of test configurations.
  • the output circuit 403 can read the location of the target test option in the read-only memory from the first storage area, or read the programming value of the target test option from the second storage area, Since the target test option is the test option that needs to be modified in the first test configuration sequence, the output circuit 403 can specify which test options in the first test configuration sequence need to be modified according to the position of the target test option in the read-only memory 401, and The output circuit 403 generates a second test configuration sequence according to the first test configuration sequence, the location of the target test option in the ROM, and the programmed value of the target test option.
  • the output circuit 403 includes a flipper 4031 and a selector 4032; the flipper 4031 is specifically configured to generate an enable signal according to the position of the target test option in the read-only memory 401 and other positions; Wherein the enable signal is in a first state at the position of the target test option in the read-only memory, and the enable signal is in a second state at other positions, the other positions including other test options in the first configuration sequence except the target test option Position in read-only memory 401; selector 4032, used to obtain the programming value of the target test option in the second storage area when the enable signal is in the first state, and obtain other tests when the enable signal is in the second state Test values for the options, generating a second sequence of test configurations based on the programmed values of the target test options and the test values of the other test options.
  • the embodiment of the present application provides a schematic structural diagram of the integrated circuit 400 , the first programmable memory 4021 provides a first storage area, and the second programmable memory 4022 provides a second storage area.
  • the order of bits in the read-only memory 401 and the second programmable memory 4022 in FIG. 7 is from right to left, starting from 1 each time
  • the order of increasing by 1 is sorted
  • the order of storage addresses of the first programmable memory 4021 in FIG. 7 is sorted from right to left, starting from 1 and increasing by 1 each time.
  • 24-bit binary data are stored in the read-only memory 401, which are respectively "010101000111001101110010", each bit of binary data is 1 bit, and the 24-bit binary data is the first test configuration sequence.
  • Multiple test options are included in the first test configuration sequence, as shown in the figure, the 3rd bit to the 6th bit in the 24-bit binary data is the test value "0101" of the first test option, in the 24-bit binary data
  • the 11th to 13th bits are the test value "110" of the second test option, and the 19th to 23rd bits in the 24-bit binary data are the test value "11001" of the third test option, except the above
  • other bits can be other test configuration sequences, or TDI control signals, TMS control signals, and TCK control signals, etc.
  • the test options that need to be modified among the multiple test options are The first test option, the second test option and the third test option are the target test options. Then it is necessary to first find the position of the target test option in the production specification of the integrated circuit 400 , and then store the position of the target test option in the ROM 401 in the first programmable memory 4021 .
  • each 8-bit binary number in the first programmable memory 4021 is regarded as a storage address (8' as shown in FIG. 7 represents 8-bit binary data), and the storage value of each storage address is the The decimal number converted from 8-bit binary data (d2 as shown in FIG. 7 represents the decimal number 2). Referring to Fig. 7, the first programmable memory 4021 in Fig.
  • the binary data stored in the first storage address is "00000010", which represents the decimal number 2, because in the read-only memory In 401, the test value "01" in the first two bits does not need to be modified;
  • the binary data stored in the second storage address is "00000100", which represents the decimal number 4, because in the read-only memory 401,
  • the 3rd bit to the 6th bit are the test value "0101" of the first test option, and the test value of the first test option needs to be modified;
  • the binary data stored in the third storage address is "00000100", which means Decimal number 4, because in the read-only memory 401, the test value "0001” from the 7th bit to the 10th bit does not need to be modified;
  • the binary data stored in the fourth storage address is "00000011", which means Decimal number 3, because in the read-only memory 401, the 11th bit to the 13th bit is the test value "110" of the second test option, and the test value of the second test option needs to be modified;
  • the first to fourth bits store the programming value "1101" of the first test option
  • the fifth to seventh bits store the programming value of the second test option
  • the 8th bit to the 12th bit store the programming value "01010” of the third test option.
  • the stored value of the storage address respectively represents "the number of bits that need to be modified in the read-only memory 401, the number of bits that do not need to be modified in the read-only memory 401, and the number of bits that do not need to be modified in the read-only memory 401, respectively.
  • the number of bits in 401 that needs to be modified, the number of bits in the read-only memory 401 that do not need to be modified stores the position of the target test option in the read-only memory 401.
  • Programmed values for the target test options are stored in the second programmable memory.
  • the flipper 4031 in the output circuit 403 generates an enable signal according to the position of the target test option in the ROM, and the high level state of the enable signal (that is, the above-mentioned The first state) corresponds to the number of bits that need to be modified in the read-only memory 401, that is, the position of the target test option in the read-only memory 401, and the bit length of the high level is equal to the number of bits that need to be modified; enable
  • the low-level state of the signal (that is, the above-mentioned second state) corresponds to the number of bits that do not need to be modified in the read-only memory, that is, the positions of other test options in the read-only memory 401 except the target test option, and The bit length of the low level is equal to the number of bits that need not be modified.
  • the enable signal shown in Figure 7 is a low level with a length of 2 bits, a high level with a length of 4 bits, a low level with a length of 4 bits, and a high level with a length of 3 bits.
  • the selector 4032 in the output circuit 403 when the enable signal is low level, obtains the test values of other test options except the target test option in the first test configuration sequence equal to the bit length of the low level.
  • the enable signal is at a high level, the programming value of the target test option in the second programmable memory 4022 whose bit length is equal to the high level is acquired.
  • a second sequence of test configurations is generated based on the programmed values of the target test option and the test values of the other test options than the target test option.
  • the selector 4032 obtains the value of the first bit to the second bit in the read-only memory 401 as a test value "01", and then When the enable signal is a high level with a length of 4 bits, the selector 4032 obtains the value from the first bit to the fourth bit in the second programmable memory 4022 as a programming value "1101", and when the enable signal is 4 When the low level of the bit length, the selector 4032 obtains the value of the 7th bit to the 10th bit in the read-only memory 401 as a test value "0001", when the enable signal is a high level of 3 bit length level, the selector 4032 obtains the value of the 4th bit to the 6th bit in the second programmable memory 4022 as a programming value "010", and when the enable signal is a low level with a length of 5 bits, select The selector 4032 obtains the value of the 14th bit to the 18th bit in the read-
  • the selector 4032 When the enable signal is a high level with a length of 5 bits, the selector 4032 obtains the second programmable The value of the 8th bit to the 12th bit in the memory 4022 is used as a programming value "01010"; The bit value is used as a test value "0", and the second test configuration sequence "011101000110101101010100" is sequentially generated. It also proves that the read-only memory 401 transmits 1-bit binary data to the selector 4032 within each bit length of the enable signal, and the second programmable memory 4022 transmits 1-bit binary data to the selector 4032 during a high-level bit length of the enable signal. 1-bit binary data is transmitted to the selector 4032.
  • the flipper 4031 can flip the stored value of the even-numbered storage address in the first programmable memory 4021 according to flipping the stored value of the odd-numbered storage address in the first programmable memory 4021 to a low level.
  • the enable signal is generated according to the rule of high level, and the bit length of the low level/high level of the enable signal is equal to the storage value of the corresponding storage address in the first programmable memory 4021 .
  • the storage value of each storage address in the first programmable memory 4021 is the decimal number corresponding to the binary number stored in the current storage address.
  • each 8-bit binary number in the first programmable memory 4021 is regarded as a storage address. When the 8-bit binary number is all 1, it is "11111111", and the corresponding decimal number is 255.
  • the flipper 4031 can flip the stored value of the even-numbered storage address in the first programmable memory 4021 according to flipping the stored value of the odd-numbered storage address in the first programmable memory 4021 to a low level.
  • the enable signal is generated according to the rule of high level, and the bit length of the low level/high level of the enable signal is equal to the storage value of the corresponding storage address in the first programmable memory 4021 .
  • the storage value of each storage address in the first programmable memory 4021 is the decimal number corresponding to the binary number stored in the current storage address.
  • the read-only memory 401 a total of 1000 bits are included, and the test value of the 1st bit to the 550th bit does not need to be modified, and the test value of the 551st bit to the 790th bit needs to be modified.
  • the test values from the 791st bit to the 1000th bit do not need to be modified, which means that the first programmable memory 4021 needs to store decimal numbers 550, 240, 210.
  • Each 8-bit binary number in the first programmable memory 4021 is regarded as a storage address. When the 8-bit binary number is all 1, it is "11111111", and the corresponding decimal number is 255.
  • FIG. 7 is an example in which each storage address in the first programmable memory 4021 contains 8 bits.
  • the bits contained in each storage address of the first programmable memory 4021 The number may be any positive integer number of bits, which is not limited in the embodiment of the present application.
  • the flipper 4031 can flip the odd-numbered decimal number transmitted from the first programmable memory 4021 to the flipper 4031 to a low level, and transfer the first programmable memory 4021 to the even-numbered decimal number of the flipper 4031.
  • the enable signal is generated according to the rule that the number is flipped to a high level, and the bit length of the low level/high level of the enable signal is equal to the decimal number transmitted from the corresponding first programmable memory 4021 to the flipper 4031 .
  • a total of 1000 bits are included, and the test value of the 1st bit to the 500th bit does not need to be modified, and the test value of the 501st bit to the 754th bit needs to be modified.
  • the test values from the 755th bit to the 1000th bit do not need to be modified, which means that the first programmable memory 4021 needs to store decimal numbers 500, 254, 246.
  • every 8 binary digits in the first programmable memory 4021 is regarded as a storage address, and the maximum decimal number that can be stored in a storage address in the first programmable memory 4021 is 254, for example, the first programmable
  • the binary number stored in the nth storage address of the programming memory 4021 is "11111111"
  • the binary numbers stored in the nth storage address are all "1"
  • the upper 7 binary numbers are "1" to indicate that the binary number stored in the nth storage address is "1".
  • the binary number stored in n storage addresses is actually "11111110", which corresponds to the decimal number 254, and the lower 1-bit binary number is "1", which means that the current nth storage address is continuous with the n+1th storage address.
  • the binary number stored in the n+1 storage address is "00101010", corresponding to the decimal number 42, and the first programmable memory 4021 adds the decimal number stored in the nth storage address to the decimal number stored in the n+1th storage address, That is, 254+42, the decimal number 296 is transmitted to the flipper 4031 .
  • the binary number stored in the first storage address is "11111111” corresponding to the decimal number 254, and the second storage address The stored binary number is "11110110” corresponding to the decimal number 246.
  • the first programmable memory 4021 transmits the decimal number 254+246, that is, 500, to the flipper 4031 , so that the flipper 4031 flips the decimal number 500 into a low level with a length of 500 bits, indicating that the 500 bits do not need to be modified;
  • the binary number stored in the third storage address is "11111110” corresponding to the decimal number 254,
  • the first programmable memory 4021 transmits the decimal number 254 to the flipper 4031, so that the flipper 4031 flips the decimal number 254 into a high level with a length of 254 bits, indicating that 254 bits need to be modified;
  • the fourth storage The binary number stored in the address is "11110110" corresponding to the decimal number 246, and the first programmable memory 4021 transmits the decimal number 246 to the flipper 4031, so that the flipper 4031 flips the decimal number 246 into a low level with a length of 246 bits ,
  • the flipper 4031 in the output circuit 403 when the integrated circuit 400 is powered on, the flipper 4031 in the output circuit 403 generates an enable signal according to the location of the target test option in the read-only memory, or the enable signal can be in a low-level state Corresponding to the number of bits that need to be modified in the read-only memory 401, that is, the position of the target test option in the read-only memory 401, and the bit length of the low level is equal to the number of bits that need to be modified; the high level of the enable signal
  • the level state corresponds to the number of bits that do not need to be modified in the read-only memory, that is, the positions of other test options in the read-only memory 401 except the target test option, and the bit length of the high level is equal to the number of bits that need not be modified.
  • the selector 4032 in the output circuit 403 when the enable signal is high level, obtains the test values of other test options except the target test option in the first test configuration sequence equal to the bit length of the high level.
  • the enable signal is at low level, the programming value of the target test option in the second programmable memory 4022 whose bit length is equal to the low level is acquired.
  • a second sequence of test configurations is generated based on the programmed values of the target test option and the test values of the other test options than the target test option.
  • the embodiment of the present application provides a schematic structural diagram of an integrated circuit 800.
  • the integrated circuit 800 needs to be tested after power-on, but the The processor 802 is not running normally, and the JTAG pin 801 in the integrated circuit 800 is also closed, then, the selector 803 can select the second test configuration sequence in accordance with the IEEE 1149.1 standard transmitted by the selector 4032 to the TAP controller 804 , wherein, the flipper 4031 generates an enable signal according to the position of the target test option in the read-only memory 401, and the high level state of the enable signal corresponds to the number of bits to be modified in the read-only memory 401, that is, The target test option is at the position in the read-only memory 401, and the bit length of the high level is equal to the number of bits that need to be modified; the low-level state of the enable signal corresponds to the number of bits that do not need to be modified in the read-only memory , that is, the positions of other test options
  • the first test configuration sequence is stored in the read-only memory 401, the first test configuration sequence includes the test values of a plurality of test options, and the read-only memory 401 is in each bit length of the enable signal (no matter it is a high level The bit length is also a low level bit length) to transmit 1-bit binary data to the selector 4032 .
  • the second programmable memory 4022 stores the programming value of the target test option, and the second programmable memory 4022 transmits 1-bit binary data to the selector 4032 within a high level bit length of the enable signal.
  • the selector 4032 obtains the test values of other test options except the target test option in the first test configuration sequence equal to the bit length of the low level when the enable signal is at a low level, and when the enable signal is at a high level , acquire the programming value of the target test option in the second programmable memory 4022 whose bit length is equal to that of the high level.
  • the TAP controller 804 selects a user-defined data register in the integrated circuit according to the TMS control signal and the TCK control signal, and transmits multiple test options through the TDI pin , write a plurality of test options into the selected user-defined registers, then, the TAP controller 804 transmits the test options written in the user-defined registers to the BIST controller 805 according to the TMS control signal and the TCK control signal, and then Causes the BIST controller 805 to perform a self-test according to a number of test options.
  • the ATE can be connected to the JTAG pin 801, and the selector 804 selects the JTAG pin 801 to transmit the test configuration sequence generated by the ATE and conforming to the IEEE 1149.1 standard to the TAP.
  • the test configuration sequence includes a TDI control signal, a TMS control signal, a TCK control signal and a plurality of test options, wherein the TAP controller 804 selects a user-defined data register in the integrated circuit according to the TMS control signal and the TCK control signal , and transmit multiple test options through the TDI pin, and write multiple test options into the selected user-defined register, and then, the TAP controller 804 writes the user-defined register according to the TMS control signal and the TCK control signal
  • the test options are transmitted to the BIST controller 805, so that the BIST controller 805 performs a self-test according to the plurality of test options. It should be noted that after the integrated circuit is manufactured, the JTAG pin 801 in the integrated circuit will be closed, the purpose of which is to prevent the integrated circuit from being maliciously damaged during the application process.
  • the selector 803 can select the processor 802 to transmit the test configuration sequence generated by the processor 802 to the TAP controller 804 in accordance with the IEEE 1149.1 standard, the test configuration sequence Including TDI control signal, TMS control signal, TCK control signal and multiple test options, wherein, the TAP controller 804 selects the user-defined data register in the integrated circuit according to the TMS control signal and the TCK control signal, and transmits multiple data registers through the TDI pin.
  • test option multiple test options are written into the selected user-defined register, and then, the TAP controller 804 transmits the test option written in the user-defined register to the BIST controller according to the TMS control signal and the TCK control signal 805, further enabling the BIST controller 805 to perform a self-test according to multiple test options.
  • an embodiment of the present application provides a method for testing an integrated circuit, wherein the integrated circuit includes: a read-only memory, an output circuit, and at least one programmable memory; the read-only memory is used to store the first test configuration sequence , the first test configuration sequence includes test values of a plurality of test options; at least one programmable memory is used to store the programmed values of the target test options.
  • the testing method of this integrated circuit comprises:
  • the second test configuration sequence may be transmitted to the test equipment, so that the test equipment performs a test on the module to be tested according to the second test configuration sequence.
  • At least one programmable memory includes a first storage area and a second storage area, the first storage area is used to store the position of the target test option in the read-only memory, and the second storage area is used to store the programming value of the target test option;
  • the method for testing an integrated circuit further includes reading the location of the target test option in the ROM before step 903 .
  • step 903 specifically includes: generating a second test configuration sequence according to the first test configuration sequence, the location of the target test option in the ROM, and the programming value of the target test option.
  • the output circuit in the integrated circuit includes a flipper and a selector, then the above step 903 specifically includes:
  • the enable signal is in a first state at the position of the target test option in the read-only memory, and the enable signal is in a second state at other positions, the other positions including other test options in the first configuration sequence except the target test option location in read-only memory.
  • the multiple test options include: a list of modules to be tested, test intensity and test configuration, the list of modules to be tested is used to indicate which modules to be tested need to be tested, and the test intensity includes: test coverage, test vector number and test time etc., wherein, the test coverage rate indicates the percentage of the module to be tested that can be tested, for example, the test target coverage is 100%, which means that all the modules to be tested are tested, the number of test vectors indicates the test data, and the test time indicates how long it takes to complete the test;
  • the test configuration includes: linear feedback shift register LFSR seed, open clock domain, multi-input feature register MISR comparison value, and test algorithm, etc., where the linear feedback shift register LFSR seed represents the initial value of the linear feedback shift register, and the clock domain is opened Indicates that the test is started when the clock signal is on the rising or falling edge.
  • the comparison value of the multi-input characteristic register MISR represents the characteristic value obtained in the module under test without failure.
  • the test algorithm includes "March algorithm, Checkerboard algorithm.
  • the target test option is multiple One or more of the test options that need to be modified.
  • the target test options include one or more of the following: list of modules to be tested, test intensity parameters, and test configuration.
  • the embodiment of the present application provides an electronic device, the electronic device includes a printed circuit board (printed circuit board, PCB) and an integrated circuit arranged on the PCB, the integrated circuit can be any one of the aforementioned integrated circuit, the electronic device includes, for example, a mobile phone, a tablet computer, a personal digital assistant (personal digital assistant, PDA), a vehicle-mounted computer, and the like.
  • the embodiment of the present application does not specifically limit the specific form of the electronic device.
  • the integrated circuit in the electronic device can execute the above-mentioned integrated circuit testing method.
  • the embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores computer program code, and when the electronic device executes the computer program code, the electronic device executes the integrated circuit testing method in the above-mentioned embodiments.
  • the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the software product is stored in a storage medium Among them, several instructions are included to make a device (which may be a single-chip microcomputer, a chip, etc.) or a processor (processor) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: various media that can store program codes such as U disk, mobile hard disk, read only memory (ROM), random access memory (random access memory, RAM), magnetic disk or optical disk.
  • Embodiments of the present application also provide a computer program product, which, when running on an electronic device, causes the electronic device to execute the above-mentioned related steps, so as to implement the method for testing an integrated circuit in the above-mentioned embodiment.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be Incorporation or may be integrated into another device, or some features may be omitted, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the unit described as a separate component may or may not be physically separated, and the component displayed as a unit may be one physical unit or multiple physical units, that is, it may be located in one place, or may be distributed to multiple different places . Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a readable storage medium.
  • the above content is only the specific implementation of the application, but the scope of protection of the application is not limited thereto.
  • anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application, and should covered within the scope of protection of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

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Abstract

L'invention concerne un circuit intégré et un procédé d'essai pour un circuit intégré, qui se rapportent au domaine technique des semi-conducteurs. Un circuit intégré doit être testé après que le circuit intégré est mis sous tension, et à ce moment, lorsqu'un processeur dans le circuit intégré ne fonctionne pas normalement, une ou plusieurs options d'essai dans une séquence de configuration d'essai obtenue à partir d'une mémoire morte (401) peuvent être modifiées en fonction des exigences d'essai réelles. Le circuit intégré comprend la mémoire morte (401), un circuit de sortie (403) et au moins une mémoire programmable (402). La mémoire morte (401) stocke une première séquence de configuration d'essai, et la première séquence de configuration d'essai comprend des valeurs d'essai de la pluralité d'options d'essai. La ou les mémoires programmables (402) stockent une valeur de programmation d'une option d'essai cible parmi la pluralité d'options d'essai. Le circuit de sortie (403) est configuré pour lire la première séquence de configuration d'essai après avoir été mis sous tension (901). Le circuit de sortie (403) est en outre configuré pour lire la valeur de programmation de l'option d'essai cible (902). Le circuit de sortie (403) est en outre configuré pour générer une seconde séquence de configuration d'essai selon la première séquence de configuration d'essai et la valeur de programmation de l'option d'essai cible (903).
PCT/CN2022/128643 2022-02-15 2022-10-31 Circuit intégré et procédé d'essai pour circuit intégré WO2023155480A1 (fr)

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