WO2023151356A1

WO2023151356A1 - Capacitor and manufacturing method therefor

Info

Publication number: WO2023151356A1
Application number: PCT/CN2022/136120
Authority: WO
Inventors: 彭敏
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-02-14
Filing date: 2022-12-02
Publication date: 2023-08-17
Also published as: CN114512446A

Abstract

A manufacturing method for a capacitor, comprising: providing a substrate (200), and stacking a first sacrificial layer (210), an intermediate support layer (220), and a second sacrificial layer (230) on the substrate (200); forming a lower electrode (240), the lower electrode (240) penetrating through the second sacrificial layer (230), the intermediate support layer (220), and the first sacrificial layer (210), and the lower electrode (240) being electrically connected with a conductive pad (201) in the substrate (200); forming a top support layer (250) on the top surfaces of the second sacrificial layer (230) and the lower electrode (240); patterning the top support layer (250), and removing the second sacrificial layer (230); patterning the intermediate support layer (220), and removing the first sacrificial layer (210); forming a dielectric layer (260), the dielectric layer (260) covering the exposed surfaces of the substrate (200), the lower electrode (240), and the intermediate support layer (220) and the exposed surface of the top support layer (250); and forming an upper electrode (270), the upper electrode (270) covering the surface of the dielectric layer (260). According to the manufacturing method provided by embodiments of the present disclosure, the top support layer (250) only covering the top surface of the lower electrode (240) can be formed, and the side surface of the lower electrode (240) is not covered by the top support layer (250), such that the area of the exposed region of the lower electrode (240) is increased, the storage capacitance of the capacitor is further increased, the capacitor can be kept from tilting, and the user requirement is met.

Description

Capacitor and its preparation method

Related Application Citation Statement

This application claims the priority of the Chinese patent application number 202210132879.X submitted on February 14, 2022, and the application name is "Capacitor and its preparation method", the entire content of which is attached hereby in the form of reference.

technical field

The present disclosure relates to the technical field of semiconductors, in particular to a capacitor and a preparation method thereof.

Background technique

Dynamic random access memory (Dynamic Random Access Memory, referred to as: DRAM) is a semiconductor storage device commonly used in computers, consisting of many repeated storage units. In the DRAM process below 20nm, most DRAMs use a stacked capacitor structure, and the capacitor (Capacitor) is a vertical cylindrical capacitor with a high aspect ratio.

Due to the high aspect ratio of the columnar capacitor, in order to increase the stability of the columnar capacitor, it is usually necessary to provide at least two support layers to support the columnar capacitor. However, this design will reduce the storage capacity of the capacitor to a certain extent, so that the capacitor cannot meet the need.

Contents of the invention

Embodiments of the present disclosure provide a capacitor and a manufacturing method thereof, which can improve the storage capacity of the capacitor.

On the one hand, an embodiment of the present disclosure provides a method for manufacturing a capacitor. The method includes: providing a substrate on which a first sacrificial layer, an intermediate support layer, and a second sacrificial layer are stacked; forming a lower electrode , the lower electrode runs through the second sacrificial layer, the intermediate support layer and the first sacrificial layer, and the lower electrode is electrically connected to the conductive pad in the substrate; between the second sacrificial layer and the forming a top support layer on the top surface of the lower electrode; patterning the top support layer, and removing the second sacrificial layer; patterning the middle support layer, and removing the first sacrificial layer; forming a dielectric layer, and The dielectric layer covers the substrate, the lower electrode, the exposed surface of the middle support layer and the exposed surface of the top support layer; an upper electrode is formed, and the upper electrode covers the surface of the dielectric layer.

In one embodiment, the method for forming the first sacrificial layer includes the following steps: forming a first material layer on the substrate, wherein the first type dopant in the first material layer has a first doping concentration; forming a second material layer on the first material layer, wherein the first type dopant in the second material layer has a second doping concentration, and the second doping concentration is greater than the the first doping concentration.

In one embodiment, the first type dopant includes boron.

In one embodiment, the first doping concentration is 2-7%, and the second doping concentration is 5-10%.

In one embodiment, both the first material layer and the second material layer are phosphorus-doped silicate glass, and the phosphorus doping concentration in the silicate glass is 3-5%.

In one embodiment, the method for forming the lower electrode further includes: forming a capacitor hole, the capacitor hole penetrates through the second sacrificial layer, the intermediate support layer, and the first sacrificial layer, and exposes the a conductive pad; forming a lower electrode in the capacitor hole.

In one embodiment, the top surface of the lower electrode is flush with the surface of the second sacrificial layer.

In one embodiment, the second sacrificial layer includes a first sublayer disposed on the surface of the middle support layer and a second sublayer disposed on the surface of the first sublayer, and the top support layer is patterned In the step, simultaneously patterning the second sub-layer and exposing part of the first sub-layer.

In one embodiment, the thickness of the second sublayer is less than or equal to the thickness of the top support layer, and the second sublayer and the top support layer are made of the same material.

In one embodiment, the density of the second sublayer is less than that of the top support layer.

In one embodiment, the film forming temperature of the second sub-layer is lower than the film forming temperatures of the top support layer and the middle support layer.

In one embodiment, the step of patterning the top support layer and removing the second sacrificial layer further includes the steps of: patterning the top support layer to form a first opening; removing the second sacrificial layer along the first opening. the second sacrificial layer, exposing the middle supporting layer.

In one embodiment, in the step of removing the second sacrificial layer along the first opening to expose the intermediate supporting layer, the first sublayer is removed, and the second sublayer and the The top support layer is partially removed, and in the step of removing said second sacrificial layer, the remaining said second sub-layer is completely removed.

In one embodiment, after the steps of patterning the middle support layer and removing the first sacrificial layer, the thickness of the remaining top support layer is 1 nm˜10 nm.

In one embodiment, the step of patterning the intermediate support layer and removing the first sacrificial layer further includes: patterning the intermediate support layer to form a second opening; removing the first sacrificial layer along the second opening. A sacrificial layer exposing the conductive pads of the substrate.

In one embodiment, the step of patterning the intermediate support layer and forming the second opening further includes: removing part of the first sacrificial layer when forming the second opening.

In one embodiment, the removed part of the first sacrificial layer has a thickness of 1 nm˜10 nm.

In one embodiment, the following steps are further included: forming a bottom support layer, the top surface of the bottom support layer is flush with the top surface of the conductive pad; forming the first bottom support layer on the bottom support layer and the conductive pad A sacrificial layer, the intermediate support layer and the second sacrificial layer.

On the other hand, an embodiment of the present disclosure also provides a capacitor, and the capacitor includes: a substrate, a conductive pad is arranged in the substrate; a middle support layer is arranged at a preset distance above the substrate; a top support layer, disposed at a predetermined distance above the intermediate support layer; a lower electrode, disposed on the substrate, and electrically connected to a conductive pad in the substrate, the lower electrode passing through the intermediate support layer, And the top supporting layer is arranged on the top surface of the lower electrode; the dielectric layer covers the surface of the lower electrode, the middle supporting layer and the top supporting layer; the upper electrode covers the surface of the dielectric layer.

In one embodiment, the thickness of the top support layer is 1 nm˜10 nm.

In one embodiment, the capacitor further includes: a bottom support layer located in the substrate, and a top surface of the bottom support layer is flush with a top surface of the conductive pad.

The method for preparing a capacitor provided by an embodiment of the present disclosure can form a top supporting layer that only covers the top surface of the lower electrode, and the side surfaces of the lower electrode are not covered by the top supporting layer, which increases the area of the exposed area of the lower electrode, thereby increasing the size of the capacitor. The storage capacitor can maintain the capacitor without tilting, which meets the needs of users.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the accompanying drawings required in the embodiments of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic diagram of the steps of the method for manufacturing a capacitor provided in the first embodiment of the present disclosure;

2A to 2G are cross-sectional schematic diagrams of semiconductor structures corresponding to the main process of forming capacitors provided by the first embodiment of the present invention;

3A to 3D are schematic cross-sectional views of semiconductor structures corresponding to the main process of forming capacitors provided by the second embodiment of the present invention.

Detailed ways

In order to make the purpose, technical means and effects of the present disclosure clearer, the present disclosure will be further elaborated below in conjunction with the accompanying drawings. It should be understood that the embodiments described here are only some of the embodiments of the present disclosure, not all of the embodiments, and are not intended to limit the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present disclosure.

Fig. 1 is a schematic diagram of the steps of the manufacturing method of the capacitor provided by the first embodiment of the present disclosure, please refer to Fig. 1 , the manufacturing method includes: step S10, providing a substrate, and a first sacrificial layer is stacked on the substrate , an intermediate support layer, and a second sacrificial layer; step S11, forming a lower electrode, the lower electrode runs through the second sacrificial layer, the intermediate support layer, and the first sacrificial layer, and the lower electrode and the lining The conductive pads in the bottom are electrically connected; step S12, forming a top support layer on the second sacrificial layer and the top surface of the lower electrode; step S13, patterning the top support layer, and removing the second sacrificial layer; Step S14, patterning the intermediate support layer, and removing the first sacrificial layer; Step S15, forming a dielectric layer, the dielectric layer covering the exposed surface of the substrate, the lower electrode, and the intermediate support layer and the exposed surface of the top support layer; step S16, forming an upper electrode, and the upper electrode covers the surface of the dielectric layer.

2A to 2G are schematic cross-sectional views of semiconductor structures corresponding to the main process of forming capacitors provided by the first embodiment of the present invention.

Referring to step S10 and FIG. 2A , a substrate 200 is provided, on which a first sacrificial layer 210 , an intermediate support layer 220 and a second sacrificial layer 230 are stacked.

The substrate 200 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc.; the substrate The bottom 200 can also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc., and the substrate 200 can also be a stacked structure, such as a silicon/germanium silicon stack, etc.; In addition, the substrate 200 may be a substrate after ion doping, which may be doped with P-type or N-type doped; multiple peripheral devices may also be formed in the substrate 200, such as field Effect transistors, capacitors, inductors and/or pn junction diodes, etc. In this embodiment, the substrate 200 is a silicon substrate, which also includes other device structures, such as bit line structures, transistor structures, etc., but since they are irrelevant to the present invention, they are not shown.

Conductive pads 201 are provided in the substrate 200, and the conductive pads 201 can be used as electrical connection pads between capacitors and other device structures.

As an example, in this embodiment, the first sacrificial layer 210 is a double-layer structure composed of a first material layer 211 and a second material layer 212 . This embodiment also provides a method for forming the first sacrificial layer 210 . The method comprises the steps of:

A first material layer 211 is formed on the substrate 200, the first material layer 211 has a first type dopant, and the first type dopant has a first doping concentration. In this step, the first material layer 211 may be formed by spin coating or chemical vapor deposition. In this embodiment, the first material layer 211 is doped silicate glass, the first type dopant is boron, and the boron has a first doping concentration. As an example, the first doping concentration is 2-7%. As an example, the first material layer 211 is doped with phosphorus in addition to boron, and the doping concentration of phosphorus is 3-5%.

A second material layer 212 is formed on the first material layer 211, the second material layer 212 has a first type dopant, and the first type dopant has a second doping concentration. In this step, the second material layer 212 may be formed by spin coating or chemical vapor deposition. In this embodiment, the second material layer 212 is doped silicate glass, the first type dopant is boron, and the boron has a second doping concentration. As an example, the second doping concentration is 5-10%. As an example, the second material layer 212 is doped with phosphorus in addition to boron, and the doping concentration of phosphorus is 3-5%. In this embodiment, the phosphorus doping concentration in the first material layer 211 and the second material layer 212 is the same, in other embodiments, the first material layer 211 and the second material layer 212 The phosphorus doping concentration in the medium can also be different.

Wherein, the second doping concentration is greater than the first doping concentration, that is, the doping concentration of the first material layer 211 (the lower layer of the first sacrificial layer 210) is smaller than that of the second material layer 212 (the first sacrificial layer 210). Layer 210 upper layer) doping concentration, so that the etching rate of the first material layer 211 is greater than the etching rate of the second material layer 212, then when the subsequent etching process is performed to remove the first sacrificial layer 210, the lower layer The first material layer 211 is easily removed due to the high etching rate, which greatly reduces the residual amount of the first material layer 211 , that is, greatly reduces the residual amount of the first sacrificial layer 210 .

The above is only an example of the first sacrificial layer 210 , and in other embodiments of the present disclosure, the first sacrificial layer 210 may also be phosphosilicate glass with uniform boron doping concentration, or silicon oxide.

The material of the intermediate support layer 220 may be silicon nitride (SiN) or silicon carbon nitride (SiCN). As an example, this embodiment also provides a method for forming the intermediate support layer 220, the method includes: using NH ₃ and SIH ₄ as the main reaction gases, and mixing them with silicon-containing substances or trimethylsilane to form silicon Nitrogen layer or silicon carbon nitride layer. Wherein, the film-forming temperature of the intermediate support layer 220 is between 500°C and 550°C. The intermediate support layer 220 formed at this temperature has a higher density, which improves the support strength of the intermediate support layer 220 for the subsequently formed capacitor, and further avoids The capacitor is tilted. In this embodiment, the density of the formed intermediate support layer 220 can be adjusted by adjusting the flow rate of the silicon-containing substance or trimethylsilane.

The second sacrificial layer 230 may be oxide (OX), such as silicon oxide. As an example, this embodiment also provides a method for forming the second sacrificial layer 230, the method includes: depositing orthoethyl silicate (TEOS) on the intermediate support layer 220, forming the second sacrificial layer 230. The process of depositing tetraethyl orthosilicate includes high-density plasma chemical vapor deposition, atomic layer deposition, furnace tube deposition and other processes, and the deposition temperature can be 300°C-630°C.

In this embodiment, the substrate 200 is further provided with a bottom support layer 202, the bottom support layer 202 exposes the conductive pad 201, and the first sacrificial layer 210 covers the bottom support layer 202 and the Conductive pad 201. In some embodiments, the top surface of the bottom support layer 202 is flush with the top surface of the conductive pad 201, so as to prevent the bottom support layer 202 from covering the conductive pad 201, and improve The contact area between the lower electrode and the conductive pad 201 improves the electrical contact performance. In this embodiment, the material of the bottom support layer 202 and the middle support layer 220 is the same, for example, both are nitride layers, such as silicon nitrogen carbon layers. The formation process of the bottom support layer 202 is the same as the formation process of the middle support layer.

It can be understood that the first sacrificial layer 210 and the second sacrificial layer 230 can be formed of materials that have etching selectivity with respect to the intermediate support layer 220 and can be easily removed by a wet etching process, so that the removal of the first sacrificial layer can be performed later. 210 and the second sacrificial layer 230 to prevent the first sacrificial layer 210 and the second sacrificial layer 230 from remaining, and also prevent the intermediate support layer 220 from being greatly thinned, which affects the supporting strength of the intermediate support layer 220 .

Referring to step S11 and FIG. 2B , the lower electrode 240 is formed, the lower electrode 240 penetrates through the second sacrificial layer 230 , the intermediate support layer 220 and the first sacrificial layer 210 , and the lower electrode 240 and the The conductive pads 201 within the substrate 200 are electrically connected.

As an example, this embodiment provides a method for forming the lower electrode 240, and the method includes the following steps:

A capacitor hole (not shown in the drawings) is formed, the capacitor hole penetrates through the second sacrificial layer 230 , the intermediate supporting layer 220 and the first sacrificial layer 210 , and exposes the conductive pad 201 in the substrate 200 . In this step, processes such as photolithography and etching may be used to form the capacitor holes.

The lower electrode 240 is formed in the capacitor hole. As an example, this step specifically includes the following step: filling the capacitor hole with a conductive material, and the conductive material not only fills the capacitor hole, but also covers the surface of the second sacrificial layer 230 . The conductive material can be titanium nitride or other materials that can serve as the bottom electrode 240 of the capacitor. The conductive material is etched back to expose the second sacrificial layer 230 , and the conductive material in the capacitor hole forms the lower electrode 240 . In this embodiment, in this step, the conductive material is etched back using a titanium nitride etch-back process to remove the conductive material on the surface of the second sacrificial layer 230 and expose the second sacrificial layer 230 .

In this embodiment, the top surface of the lower electrode 240 is flush with the surface of the second sacrificial layer 230, then the top support layer 250 (see FIG. 2C) formed in the subsequent process only covers the top surface of the lower electrode 240, Not covering the sidewall of the lower electrode 240 further improves the storage capacity of the capacitor.

Referring to step S12 and FIG. 2C , a top support layer 250 is formed on the top surfaces of the second sacrificial layer 230 and the bottom electrode 240 . The top support layer 250 covers top surfaces of the second sacrificial layer 230 and the bottom electrode 240 .

The top support layer 250 may be a silicon nitride layer (SiN) or a silicon carbon nitride layer (SiCN) as an example, and this embodiment provides a method for forming the top support layer 250 . The method includes: using NH ₃ and SIH ₄ as main reaction gases, and mixing them with silicon-containing substances or trimethylsilane to form a silicon nitrogen layer or a silicon carbon nitrogen layer. Wherein, the film-forming temperature of the top support layer 250 is between 500°C and 550°C. The top support layer 250 formed at this temperature has a higher density, which improves the support strength of the top support layer 250 for the subsequently formed capacitor, and further avoids The capacitor is tilted. In this embodiment, the density of the formed top support layer 250 can be adjusted by adjusting the flow rate of the silicon-containing substance or trimethylsilane.

In this embodiment, the formation process of the top support layer 250 is the same as the formation process of the middle support layer 220 . In some other embodiments, the formation process of the top support layer 250 and the formation process of the middle support layer 220 may also be different, or there are differences in process parameters between the two.

Referring to step S13 and FIG. 2D , the top supporting layer 250 is patterned, and the second sacrificial layer 230 is removed.

Specifically, in this step, the top support layer 250 is patterned to form a first opening 251 ; the second sacrificial layer 230 is removed along the first opening 251 to expose the middle support layer 220 . Wherein, the process of patterning the top support layer 250 can be a photolithography and dry etching process, that is, a patterned mask layer is formed on the top support layer 250, and the mask layer is used as a shield to engrave The portion of the top support layer 250 is etched away to form the top support layer 250 with the first opening 251 . The mask layer may be removed after the first opening 251 is formed, or may remain. The mask layer can provide a mask for subsequent removal of the second sacrificial layer 230 . The method for removing the second sacrificial layer 230 may be a wet etching process, that is, using the mask layer and the top support layer 250 as a mask, the second sacrificial layer 230 is removed by a wet etching process. . In this embodiment, after the second opening is formed, the mask layer is removed, and when the second sacrificial layer 230 is removed, the top support layer 250 is used as a mask to remove the second sacrificial layer 230 . sacrificial layer 230 . It can be understood that, during the process of removing the second sacrificial layer 230, the top support layer 250 is also thinned, therefore, the thickness of the top support layer 250 formed in step S12 is greater than the top of the finally formed capacitor The thickness of the supporting layer 250 is to provide sufficient thinning amount for subsequent steps and reduce the difficulty of the process caused by the insufficient thickness of the top supporting layer 250 .

Referring to step S14 and FIG. 2E , the intermediate support layer 220 is patterned, and the first sacrificial layer 210 is removed.

Specifically, in this step, the intermediate support layer 220 is patterned to form the second opening 221 . Wherein, the position of the second opening 221 corresponds to that of the first opening 251 . The first sacrificial layer 210 is removed along the second opening 221 to expose the substrate 200 . The process of patterning the intermediate support layer 220 may be a photolithography and dry etching process, and the method of removing the first sacrificial layer 210 may be a wet etching process.

It can be understood that, during the step of patterning the middle support layer 220, the top support layer 250 is also thinned. After the step of removing the first sacrificial layer 210, the thickness of the remaining top support layer 250 is 1nm-10nm. If the thickness of the top support layer 250 is less than 1nm, it cannot provide sufficient support for the capacitor. If the top support layer The thickness of the layer 250 is greater than 10 nm. Although the supporting force is strong, it will increase the occupied volume of the capacitor and cannot meet the requirement of device miniaturization.

In this embodiment, the first sacrificial layer 210 is composed of a first material layer 211 and a second material layer 212, and the doping concentration of the first type dopant in the first material layer 211 is lower than that of the second material layer 211. The doping concentration of the first type dopant in the layer 212 makes the bottom layer of the first sacrificial layer 210 easy to be removed, greatly reducing the residual amount of the first sacrificial layer 210 .

In this embodiment, after the first sacrificial layer 210 is removed, the bottom supporting layer 202 is exposed.

Referring to step S15 and FIG. 2F, a dielectric layer 260 is formed, and the dielectric layer 260 covers the exposed surface of the substrate 200, the lower electrode 240, the middle support layer 220 and the exposed surface of the top support layer 250. . In this embodiment, due to the existence of the bottom support layer 202, the dielectric layer 260 covers the exposed surface of the bottom support layer 202, the lower electrode 240, the middle support layer 220 and the top support layer. 250 exposed surfaces.

Wherein, the dielectric layer 260 may be a high-K dielectric layer to improve the performance of the capacitor. For example, Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , ZrO ₂ , the dielectric layer 260 can use chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process or metal organic chemical vapor deposition (MOCVD) process etc.

Referring to step S16 and FIG. 2G , an upper electrode 270 is formed, and the upper electrode 270 covers the surface of the dielectric layer 260 .

In this embodiment, a conductive material is formed in the gap between the bottom support layer 202, the middle support layer 220, and the top support layer 250 and the surface of the top support layer 250, and the conductive material is used as the The above electrode 270 is used. It can be understood that, in some embodiments, a step of thinning and planarizing the top surface of the conductive material is also included, so as to make the top surface of the formed bottom electrode 240 flat.

The upper electrode 270 , the dielectric layer 260 and the lower electrode 240 form a columnar capacitor, and a plurality of the capacitors are arranged in an array to form a capacitor array structure.

The capacitor manufacturing method provided by the embodiments of the present disclosure can form the top supporting layer 250 covering only the top surface of the lower electrode 240, and the side of the lower electrode 240 is not covered by the top supporting layer 250, which increases the area of the exposed area of the lower electrode 240, Furthermore, the storage capacitance of the capacitor is increased, and the capacitor can be kept from inclining, which meets the needs of users.

In the first embodiment of the present disclosure, the second sacrificial layer 230 is a single-layer structure, such as an oxide layer, while in other embodiments of the present disclosure, the second sacrificial layer 230 may be a multi-layer structure. Therefore, the second embodiment of the present disclosure provides a method for manufacturing a capacitor.

Referring to FIG. 3A , a first sacrificial layer 210 , an intermediate support layer 220 and a second sacrificial layer 230 are stacked on a substrate 200 , and a lower electrode 240 runs through the second sacrificial layer 230 , the intermediate support layer 220 and the second sacrificial layer 230 . The first sacrificial layer 210 , the lower electrode 240 is electrically connected to the conductive pad 201 in the substrate 200 , and the top supporting layer 250 covers the second sacrificial layer 230 and the lower electrode 240 .

Wherein, the second sacrificial layer 230 includes a first sublayer 231 disposed on the surface of the middle support layer 220 and a second sublayer 232 disposed on the surface of the first sublayer 231, and the top support layer 250 covers The second sub-layer 232 and the lower electrode 240 .

In this embodiment, the method for forming the first sacrificial layer 210 , the middle support layer 220 , the top support layer 250 and the bottom electrode 240 is the same as that of the first embodiment, and will not be repeated here. As an example, this embodiment provides a method for forming the second sacrificial layer 230 . The methods include:

After forming the intermediate support layer 220 and before forming the lower electrode 240, deposit tetraethyl orthosilicate (TEOS) on the intermediate support layer 220 to form the first sub-layer 231. The process of depositing tetraethyl orthosilicate includes High-density plasma chemical vapor deposition, atomic layer deposition, furnace tube deposition and other processes, the deposition temperature can be 300°C-630°C.

The second sublayer 232 is formed on the first sublayer 231 . The material of the second sub-layer 232 may be a silicon nitride layer (SiN) or a silicon carbon nitride layer (SiCN). As an example, this embodiment also provides a method for forming the second sub-layer 232, the method includes: using NH ₃ and SIH ₄ as the main reaction gases, and mixing them with silicon-containing substances or trimethylsilane to form Silicon nitride layer or silicon carbon nitride layer. Wherein, the film-forming temperature of the second sub-layer 232 is between 300°C and 550°C, and the film-forming temperature of the second sub-layer 232 is lower than the film-forming reaction temperature of the middle support layer 220 and the top support layer 250, so that the formed The density of the second sub-layer 232 is smaller than that of the middle support layer 220 and the top support layer 250, thereby reducing the thinning amount of the middle support layer 220 and the top support layer 250 when the second sub-layer 232 is subsequently removed To prevent the middle support layer 220 and the top support layer 250 from being too thin and affecting the support strength of the middle support layer 220 and the top support layer 250 to the capacitor. In this embodiment, the density of the formed second sub-layer 232 can also be adjusted by adjusting the flow rate of the silicon-containing substance or trimethylsilane.

In the subsequent process of removing the first sub-layer 231, the second sub-layer 232 can support the lower electrode 240 together with the middle support layer 220 and the top support layer 250, so as to prevent the lower electrode 240 from forming during the process. dump.

In this embodiment, the second sublayer 232 is made of the same material as the top support layer 250, for example, the top support layer 250 is a silicon nitride layer (SiN) or a silicon carbon nitride layer (SiCN), then The second sub-layer 232 is also a silicon nitride layer (SiN) or a silicon carbon nitride layer (SiCN).

Since the second sub-layer 232 plays the role of assisting support, the thickness of the second sub-layer 232 should not be too thick. If the second sub-layer 232 is too thick, there may be intermediate The support layer 220 and the top support layer 250 are excessively thinned, therefore, the thickness of the second sub-layer 232 is less than or equal to the thickness of the top support layer 250, so as to avoid the middle support layer 220 and the top support layer 250 being Excessive thinning occurs.

In this embodiment, since the second sublayer 232 is made of the same material as the top support layer 250, in order to avoid excessive thinning of the top support layer 250 when the second sacrificial layer 230 is removed, the second sublayer The thickness of the sub-layer 232 is set to be smaller than the thickness of the first sub-layer 231 .

Referring to FIG. 3B , the top support layer 250 is patterned, and the first sub-layer 231 is removed. In this step, the second sub-layer 232 is patterned simultaneously.

Specifically, in this step, the top support layer 250 and the second sub-layer 232 are patterned to form a first opening 251; the first sub-layer 231 is removed along the first opening 251, and exposed out of the middle support layer 220. Wherein, the process of patterning the top support layer 250 may be photolithography and dry etching process.

During the process of removing the first sub-layer 231, the second sub-layer 232 and the top support layer 250 are partially removed. In this embodiment, since the density of the second sub-layer 232 is less than the If the density of the top support layer 250 is high, then in this step, the removed thickness of the second sub-layer 232 is greater than the thickness removed by the top support layer 250, thereby further avoiding the excessive thinning of the top support layer 250, and also This prevents the second sub-layer 232 from being uncleanly removed and remaining in the subsequent process.

Referring to FIG. 3D , the intermediate support layer 220 is patterned, and the first sacrificial layer 210 is removed, and at the same time, the remaining second sub-layer 232 is completely removed.

Specifically, in this step, the intermediate support layer 220 is patterned to form the second opening 221 . Wherein, the position of the second opening 221 corresponds to that of the first opening 251 . The first sacrificial layer 210 and the remaining second sub-layer 232 are removed along the first opening 251 and the second opening 221 to expose the bottom supporting layer 202 . The process of patterning the intermediate support layer 220 may be a photolithography and dry etching process, and the method of removing the first sacrificial layer 210 may be a wet etching process.

In this embodiment, the material of the second sub-layer 232 is the same as that of the intermediate support layer 220, or the etching rate of the two is similar, then when the intermediate support layer 220 is patterned, the second sub-layer 232 is also thinned at the same time, in order to further ensure that the second sub-layer 232 is completely removed after the step of removing the first sacrificial layer 210 is performed. In this step, when the second opening 221 is formed, the patterned When the intermediate support layer 220 is mentioned above, the first sacrificial layer 210 is partially removed. Please refer to FIG. The thinning amount of the second sub-layer 232 is increased, so as to ensure that the second sub-layer 232 can be completely removed after the first sacrificial layer 210 is removed, so as to avoid the residue of the second sub-layer 232 .

If the removed thickness of the first sacrificial layer 210 is too large, it means that the etching time is longer, and although the second sub-layer 232 can be further thinned, it may cause the top support layer 250 to be excessively thinned. Therefore, in this embodiment, the thickness of the removed part of the first sacrificial layer 210 is set to be 1 nm˜10 nm.

After the first sacrificial layer 210 is removed, the steps of forming the dielectric layer 260 and the upper electrode 270 are performed. These steps are the same as the corresponding steps of the first embodiment, and will not be repeated here.

The preparation method provided by the second embodiment of the present disclosure can form the second sub-layer 232 supporting the sidewall of the lower electrode 240 at the top region of the lower electrode 240, and the second sub-layer 232 can support the lower electrode 240 during the process flow, Prevent the lower electrode 240 from tilting, and before forming the dielectric layer 260, the second sub-layer 232 is gradually thinned to be removed as the process progresses, and also prevents the sidewall of the lower electrode 240 from being blocked, so that it will not be caused by the second The presence of the sublayer 232 affects the storage capacity of the capacitor.

An embodiment of the present disclosure also provides a capacitor prepared by the above-mentioned preparation method. Please refer to FIG. 2G , the capacitor includes a substrate 200 , a middle supporting layer 220 , a top supporting layer 250 , a lower electrode 240 , a dielectric layer 260 and an upper electrode 270 .

The substrate 200 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc.; the substrate The bottom 200 can also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc., and the substrate 200 can also be a stacked structure, such as a silicon/germanium silicon stack, etc.; In addition, the substrate 200 may be a substrate after ion doping, which may be doped with P-type or N-type doped; multiple peripheral devices may also be formed in the substrate 200, such as field Effect transistors, capacitors, inductors and/or pn junction diodes, etc. In this embodiment, the substrate 200 is a silicon substrate, which also includes other device structures, such as bit line structures, transistor structures, etc., but since they are irrelevant to the present invention, they are not shown. Conductive pads 201 are provided in the substrate, and the conductive pads 201 can serve as electrical connection pads between capacitors and other device structures.

The intermediate support layer 220 is disposed at a predetermined distance above the substrate 200 . That is, the intermediate support layer 220 is not disposed on the surface of the substrate 200 , but is spaced apart from the substrate 200 . The preset distance can be determined according to the actual structure of the capacitor.

The top support layer 250 is disposed at a predetermined distance above the middle support layer 220 . That is, the top support layer 250 is not disposed on the surface of the middle support layer 220 , but is spaced apart from the middle support layer 220 . The preset distance can be determined according to the actual structure of the capacitor. In this embodiment, the material of the top support layer 250 is the same as that of the middle support layer 220 , and the density is the same or similar. For example, both materials are SiCN.

In this embodiment, the thickness of the top support layer 250 is 1 nm˜10 nm. If the thickness of the top support layer 250 is less than 1nm, it cannot provide sufficient support for the capacitor; if the thickness of the top support layer 250 is greater than 10nm, although the support force is strong, the occupied volume of the capacitor will be increased, which cannot meet the requirements of device miniaturization. Require.

The lower electrode 240 is disposed on the substrate 200 and electrically connected to the conductive pad 201 in the substrate 200 . The lower electrode 240 runs through the middle support layer 220, and the top support layer 250 is disposed on the top surface of the lower electrode 240, that is, the top support layer 250 does not cover the sidewall of the lower electrode 240, so that The area of the sidewall of the lower electrode 240 covered by the dielectric layer 260 is maximized to increase the storage capacity of the capacitor.

The dielectric layer 260 covers the surfaces of the bottom electrode 240 , the middle support layer 220 and the top support layer 250 . The dielectric layer 260 can be a high-K dielectric layer to improve the performance of the capacitor. For example, Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , ZrO ₂ .

The upper electrode 270 covers the surface of the dielectric layer 260 . In this embodiment, the upper electrode 270 also fills the gap between the substrate 200 , the middle support layer 220 and the top support layer 250 , and covers the surface of the top support layer 250 .

In this embodiment, the capacitor further includes a bottom support layer 202 . The bottom support layer 202 covers the substrate 200 and exposes the conductive pad 201 . The top surface of the bottom support layer 202 is flush with the top surface of the conductive pad 201, thereby preventing the bottom support layer 202 from covering the conductive pad 201 and increasing the contact area between the lower electrode 240 and the conductive pad 201 , Improve electrical contact performance. In this embodiment, the material of the bottom support layer 202 and the middle support layer 220 is the same, for example, both are nitride layers, such as silicon nitrogen carbon layers.

In the capacitor provided by the embodiment of the present disclosure, the top supporting layer 250 is only provided on the top surface of the lower electrode 240, the sidewall of the lower electrode 240 is not covered by the top supporting layer 250, and the sidewall of the lower electrode 240 is exposed to the maximum extent, without changing The critical dimensions of the capacitor lower electrode 240 improve the storage capacity of the capacitor.

The above descriptions are only preferred implementations of the present disclosure. It should be pointed out that those skilled in the art can make some improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications should also be regarded as It is the scope of protection of this disclosure.

Claims

A method for preparing a capacitor, comprising:

providing a substrate on which a first sacrificial layer, an intermediate support layer and a second sacrificial layer are stacked;

forming a lower electrode, the lower electrode runs through the second sacrificial layer, the intermediate support layer, and the first sacrificial layer, and the lower electrode is electrically connected to the conductive pad in the substrate;

forming a top support layer on the second sacrificial layer and the top surface of the lower electrode;

patterning the top support layer, and removing the second sacrificial layer;

patterning the intermediate support layer, and removing the first sacrificial layer;

forming a dielectric layer covering the substrate, the lower electrode, the exposed surface of the middle support layer, and the exposed surface of the top support layer;

An upper electrode is formed, and the upper electrode covers the surface of the dielectric layer.
The method for manufacturing a capacitor according to claim 1, wherein the method for forming the first sacrificial layer comprises the following steps:

forming a first material layer on the substrate, wherein the first type dopant in the first material layer has a first doping concentration;

A second material layer is formed on the first material layer, wherein the first type dopant in the second material layer has a second dopant concentration, and the second dopant concentration is greater than the first dopant concentration. impurity concentration.
The method of manufacturing a capacitor according to claim 2, wherein the first type dopant includes boron.
The method for manufacturing a capacitor according to claim 2, wherein the first doping concentration is 2-7%, and the second doping concentration is 5-10%.
The method for preparing a capacitor according to claim 2, wherein both the first material layer and the second material layer are phosphorus-doped silicate glass, and the phosphorus doping concentration in the silicate glass is 3 to 5%.
The method for manufacturing a capacitor according to claim 1, wherein the method for forming the lower electrode further comprises:

forming a capacitor hole, the capacitor hole penetrates through the second sacrificial layer, the intermediate support layer and the first sacrificial layer, and exposes the conductive pad in the substrate;

A lower electrode is formed in the capacitor hole.
The method for manufacturing a capacitor according to claim 1, wherein the top surface of the lower electrode is flush with the surface of the second sacrificial layer.
The method for manufacturing a capacitor according to claim 1, wherein the second sacrificial layer comprises a first sublayer disposed on the surface of the intermediate support layer and a second sublayer disposed on the surface of the first sublayer, In the step of patterning the top supporting layer, the second sublayer is patterned simultaneously, and part of the first sublayer is exposed.
The method for manufacturing a capacitor according to claim 8, wherein the thickness of the second sublayer is less than or equal to the thickness of the top support layer, and the second sublayer and the top support layer are made of the same material .
The method for manufacturing a capacitor according to claim 9, wherein the density of the second sublayer is smaller than that of the top supporting layer.
The method for manufacturing a capacitor according to claim 10, wherein the film-forming temperature of the second sublayer is lower than the film-forming temperatures of the top support layer and the middle support layer.
The method for manufacturing a capacitor according to claim 8, wherein the step of patterning the top support layer and removing the second sacrificial layer further comprises the following steps:

patterning the top support layer to form a first opening;

The second sacrificial layer is removed along the first opening, exposing the middle supporting layer.
The method for manufacturing a capacitor according to claim 12, wherein, in the step of removing the second sacrificial layer along the first opening to expose the intermediate support layer, the first sublayer is removed, so The second sublayer and the top support layer are partially removed, and in the step of removing the first sacrificial layer, the remaining second sublayer is completely removed.
The method for manufacturing a capacitor according to claim 12, wherein after the step of patterning the middle support layer and removing the first sacrificial layer, the thickness of the remaining top support layer is 1 nm˜10 nm.
The method for manufacturing a capacitor according to claim 1, wherein the step of patterning the intermediate support layer and removing the first sacrificial layer further comprises:

patterning the intermediate support layer to form a second opening;

The first sacrificial layer is removed along the second opening, exposing the conductive pad of the substrate.
The method for manufacturing a capacitor according to claim 15, wherein the step of patterning the intermediate support layer and forming the second opening further comprises:

When forming the second opening, part of the first sacrificial layer is removed.
The method for manufacturing a capacitor according to claim 16, wherein the removed part of the first sacrificial layer has a thickness of 1 nm˜10 nm.
The method for preparing a capacitor according to claim 1, further comprising the steps of:

forming a bottom support layer, the top surface of the bottom support layer is flush with the top surface of the conductive pad;

The first sacrificial layer, the middle support layer and the second sacrificial layer are formed on the bottom support layer and the conductive pad.
A capacitor, comprising:

a substrate within which a conductive pad is disposed;

an intermediate support layer disposed at a preset distance above the substrate;

a top support layer arranged at a preset distance above the middle support layer;

The lower electrode is arranged on the substrate and is electrically connected to the conductive pad in the substrate, the lower electrode runs through the middle support layer, and the top support layer is arranged on the top surface of the lower electrode;

a dielectric layer covering the surface of the lower electrode, the middle support layer and the top support layer;

The upper electrode covers the surface of the dielectric layer.
The capacitor according to claim 19, wherein the thickness of the top support layer is 1 nm to 10 nm.
The capacitor of claim 19, wherein the capacitor further comprises:

The bottom support layer is located in the substrate, and the top surface of the bottom support layer is flush with the top surface of the conductive pad.