WO2023147700A1

WO2023147700A1 - Memory cell, preparation method, memory, and electronic device

Info

Publication number: WO2023147700A1
Application number: PCT/CN2022/075371
Authority: WO
Inventors: 韩秋华; 宋伟基; 许俊豪
Original assignee: 华为技术有限公司
Priority date: 2022-02-07
Filing date: 2022-02-07
Publication date: 2023-08-10
Also published as: CN116897428A

Abstract

A memory cell, a preparation method, a memory, and an electronic device, used for reducing the preparation difficulty of memory cells. The memory cell comprises a hole, a stacked structure surrounding the hole, a second metal layer provided in the hole, an isolation layer provided in the hole and surrounding the second metal layer, and a memory film layer at least partially surrounding the isolation layer; the stacked structure comprises at least one dielectric layer and at least one first metal layer alternately stacked, and each first metal layer is recessed with respect to the adjacent dielectric layer along the radial direction of the hole; the side of the memory film layer opposite to the isolation layer makes contact with the first metal layer in the stacked structure. The memory film layer at least fills a recess of the first metal layer with respect to the adjacent dielectric layer, and in the process of etching the memory film layer at the bottom, even if the hole is inclined, the memory film layer located in the recess can still be protected due to the presence of the recess, and the structure does not need to be etched to form a strict vertical hole, so that the preparation difficulty of memory cells can be reduced.

Description

A storage unit, preparation method, storage device and electronic device

technical field

The present application relates to the technical field of memory, and in particular to a memory unit, a manufacturing method, memory and electronic equipment.

Background technique

In recent years, with the development and popularization of semiconductor technology, many new types of memory are emerging, such as ferroelectric random access memory (FeRAM), phase change random access memory (phase change random access memory, PCRAM) , magnetic random access memory (magnetic random access memory, MRAM) and resistive random access memory (resistive random access memory, ReRAM), etc. These new types of memories have smaller storage unit sizes and can achieve faster access speeds with lower power consumption, and are being used more and more widely at this stage.

However, in the prior art, memory cells usually have strict manufacturing processes and a narrow process window. For example, in an existing storage unit preparation method, it is necessary to ensure that the holes in the storage unit are etched into strictly vertical holes, so as to ensure that the material on the hole wall will not be etched away by mistake when etching the material at the bottom of the hole. . However, vertical holes in the strict sense are very difficult to fabricate. Once a problem occurs in the fabrication, the overall structure of the memory cell will be affected, which is not conducive to realizing the storage performance of the memory cell.

In view of this, the present application provides a storage unit to reduce the difficulty of manufacturing the storage unit.

Contents of the invention

The present application provides a storage unit, a preparation method, a storage device and an electronic device, which are used to reduce the difficulty of preparing the storage unit.

In a first aspect, the present application provides a memory cell, comprising: a hole, a stack structure surrounding the hole, a second metal layer disposed in the hole, an isolation layer disposed in the hole and surrounding the second metal layer, and at least partially surrounding the The storage film layer of the isolation layer. Wherein, the stack structure includes at least one dielectric layer and at least one first metal layer alternately stacked, and each layer of the first metal layer is recessed relative to the adjacent dielectric layer along the direction of the aperture of the hole, and the storage film layer is relatively The side away from the isolation layer is in contact with the first metal layer in the stack structure.

In the above design, by setting the first metal layer to be recessed relative to the adjacent dielectric layer, the storage film layer can at least be filled in the recess. In this way, during the process of etching the storage film layer at the bottom, even if the hole is inclined , also can protect the memory film layer located in the recess due to the existence of the recess, so as to maintain the memory performance of the memory cell. It can be seen that since the structure does not need to be etched to form a strictly vertical hole, it can reduce the difficulty of manufacturing the memory cell.

In a possible design, the storage film layer can be realized in any of the following ways:

Mode 1, the storage film layer includes the first sub-film layer but does not include other sub-film layers, and the first sub-film layer fills the accommodation space formed by two adjacent dielectric layers and the first metal layer. In this way, this method can not only protect the filled first sub-film layer through the accommodating space formed by the adjacent dielectric layer and the first metal layer, but also use as few storage film layers as possible when preparing the memory unit. The cost of preparing storage units is saved.

Method 2, the storage film layer includes a first sub-film layer and a second sub-film layer, the first sub-film layer fills the accommodation space formed by two adjacent dielectric layers and the first metal layer, and the second sub-film layer It is located between the first sub-film layer, the dielectric layer and the isolation layer. In this way, by making the storage film not only fill in the recess of the adjacent dielectric layer and the first metal layer, but also fill the outside of the recess, during the process of etching the storage film at the bottom, even if the etching ions reach the side of the hole wall, it is also necessary to etch the storage film layer filling the outside of the depression before etching the storage film layer located in the depression. Obviously, this method can further protect the storage film located in the depression by filling the storage film layer outside the depression The layer helps to maintain the storage performance of the memory unit while further reducing the manufacturing difficulty of the memory unit.

In a possible design, the memory unit may further include a stop layer surrounding the hole, and the stop layer is located at the bottom of the stacked structure. Wherein, the stop layer can be only located at the bottom of the stacked structure in order to save material, and can also be located at the bottom of the stacked structure and at the bottom of the hole so as to isolate the second metal layer filled in the hole from the printed circuit board ( printed circuit board, PCB) board, the specific is not limited.

In a possible design, the side walls of the holes may be inclined in the stacking direction of the stacked structures. In this way, when the isolation layer or the second metal layer is deposited in the hole, the deposited material can be filled without gaps along the inclined hole wall, so as to effectively ensure the deposition quality.

In a possible design, the thickness of each dielectric layer and/or each first metal layer in the stacking direction of the stacked structure may be a value between 100 angstroms and 2000 angstroms.

In a possible design, in the direction of the aperture of the hole, each first metal layer may be recessed by a value between 1 nm and 10 nm relative to the adjacent dielectric layer.

In a possible design, the accommodating space formed by two adjacent dielectric layers and the first metal layer can be realized by dry etching, for example, by Pressure 2-100mt, source bias 100-1000w, bias power 20-200w , NF ₃ 2-200 SCCM, O ₂ 2-100 SCCM or Cl ₂ 2-100 SCCM to achieve any etching parameter. In this way, the directional rapid etching of the dry etching can be used to obtain the recess of the first metal layer relative to the dielectric layer, and it can also avoid mis-etching of layers other than the first metal layer.

In a second aspect, the present application provides a method for preparing a memory cell, the method comprising: first forming a stack structure by alternately stacking at least one dielectric layer and at least one first metal layer, and then etching the stack structure to form a stack surrounded by the stack structure After that, at least one first metal layer is etched back in the hole, so that each layer of the first metal layer is recessed relative to the adjacent dielectric layer along the direction of the hole diameter, and finally the memory layer is deposited between the stack structure and the hole. film layer, and deposit an isolation layer and a second metal layer surrounded by the isolation layer in the hole, wherein the storage film layer at least partially surrounds the isolation layer, and the side of the storage film layer opposite to the isolation layer contacts the first metal layer in the stack structure. metal layer.

In a possible design, a storage film layer is deposited between the stack structure and the hole, and an isolation layer and a second metal layer surrounded by the isolation layer are deposited in the hole, including: first depositing in the hole to form the first metal layer after etching back A storage film layer of a metal layer, and then etches the bottom of the storage film layer in the hole, and then deposits in the hole to form a first isolation layer surrounded by the bottom-etched storage film layer, and finally deposits in the hole to form a first A second metal layer surrounded by an isolation layer.

In a possible design, after depositing and forming a storage film layer in the hole to contact the first metal layer after etching back, before performing bottom etching on the storage film layer in the hole, a storage film layer can also be deposited in the hole Wrap-around second insulation layer. In this case, performing bottom etching on the storage film layer in the hole includes: performing bottom etching on the second isolation layer and the storage film layer in the hole.

In this design, by depositing an isolation layer on the inner side of the storage film before etching the storage film at the bottom, even if etching ions are sprayed to the sidewall of the hole when the storage film is etched at the bottom, it needs to be etched first. The storage film layer on the hole wall can be etched only after the first isolation layer located inside the storage film layer is finished. It can be seen that this design can further reduce the probability of etching the storage film layer on the hole wall by sacrificing the isolation layer, and further achieve the purpose of protecting the storage film layer on the hole wall.

In a possible design, before at least one dielectric layer and at least one first metal layer are alternately stacked to form a stacked structure, a stop layer may also be deposited to form a stop layer. In this case, at least one dielectric layer and at least one first metal layer are alternately stacked. Layering the first metal layer to form a stack structure includes: alternately stacking at least one dielectric layer and at least one first metal layer on the stop layer to form a stack structure deposited on the stop layer. In this way, the stacked structure and the PCB board on which the memory cells are placed can also be isolated by the stop layer.

In a possible design, the bottom-etched storage film layer may include a first sub-film layer, and the first sub-film layer fills the accommodating space formed by the adjacent dielectric layer and the first metal layer.

In a possible design, the storage film layer after bottom etching may include a first sub-film layer and a second sub-film layer, and the first sub-film layer is filled in the space formed by the adjacent dielectric layer and the first metal layer. The accommodating space, and the second sub-film layer is located in the accommodating space formed by the first sub-film layer, the dielectric layer and the second isolation layer.

In a possible design, the side walls of the holes may be inclined in the stacking direction of the stacked structures.

In a possible design, in the stacking direction of the stack structure, the thickness of each dielectric layer and/or each first metal layer may be a value between 100 angstroms and 2000 angstroms.

In a possible design, etching back at least one first metal layer in the hole includes: etching back a value between 1 nm and 10 nm for each layer of the first metal layer along the direction of the aperture of the hole.

In a possible design, etching back at least one first metal layer in the hole includes: etching back at least one first metal layer in the hole by dry etching.

In a third aspect, the present application provides a memory, including a storage array and a controller coupled to the storage array. The storage array includes a plurality of storage units as described in any one of the above-mentioned first aspects, and the storage units are configured according to Array deployment. Wherein, the storage array is used for storing data, and the controller is used for writing data into the storage array, or reading data from the storage array.

In a fourth aspect, the present application provides an electronic device, including a printed circuit board PCB and the memory described in the above third aspect, wherein the memory is arranged on the surface of the PCB.

Specifically, the electronic equipment includes, but is not limited to: smart phones, smart watches, tablet computers, virtual reality (virtual reality, VR) equipment, augmented reality (augmented reality, AR) equipment, vehicle equipment, desktop computers, personal computers, handheld desktop computer or personal digital assistant.

The above aspects or other aspects of the present application will be described in detail in the following embodiments.

Description of drawings

FIG. 1 exemplarily shows a schematic diagram of an internal structure of a memory applicable to an embodiment of the present application;

FIG. 2 exemplarily shows a schematic structural diagram of a storage unit provided by an embodiment of the present application;

FIG. 3 exemplarily shows a schematic diagram of a preparation process of a storage unit provided in an embodiment of the present application;

FIG. 4 exemplarily shows a schematic structural diagram of another storage unit provided by an embodiment of the present application;

FIG. 5 exemplarily shows a possible structural schematic diagram of a stack structure provided by an embodiment of the present application;

FIG. 6 exemplarily shows a schematic structural diagram of another storage unit provided by the embodiment of the present application;

FIG. 7 exemplarily shows another schematic flow chart for preparing a storage unit provided by the embodiment of the present application;

FIG. 8 exemplarily shows a schematic structural diagram of a storage array provided by an embodiment of the present application.

Detailed ways

The storage scheme disclosed in this application can be applied to devices with storage functions, for example, it can be applied to storage devices with only storage functions, such as memory, or it can also be applied to devices with storage functions and other functions (such as read and write functions). Electronic equipment. The electronic device may be a portable electronic device including functions such as a personal digital assistant and/or a music player, such as a mobile phone, a tablet computer, a wearable device (such as a smart watch) with a wireless communication function, or a vehicle-mounted device. Exemplary embodiments of portable electronic devices include, but are not limited to

Or portable electronic devices with other operating systems. The aforementioned portable electronic device may also be, for example, a laptop computer (Laptop) with a touch-sensitive surface (such as a touch panel). It should also be understood that, in some other embodiments of the present application, the above-mentioned electronic device may also be a desktop computer with a touch-sensitive surface (such as a touch panel).

For example, memory can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. Volatile memory can be random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available, such as static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), flash memory (flash eprom, FE), Synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection Dynamic random access memory (synchlink DRAM, SLDRAM) and direct memory bus random access memory (direct rambus RAM, DR RAM), such as ferroelectric random access memory (ferroelectric random access memory, FeRAM), phase change random access memory Phase change random access memory (PCRAM), magnetic random access memory (magnetic random access memory, MRAM) or resistive random access memory (resistive random access memory, ReRAM) and other new types of memory. Non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable Programmable read-only memory (electrically EPROM, EEPROM) or flash memory. It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

FIG. 1 exemplarily shows a schematic diagram of an internal structure of a memory applicable to an embodiment of the present application.

It should be understood that the illustrated memory 100 is only one example, and that the memory 100 may have more or fewer components than shown, may combine two or more components, or may have a different configuration of components . The various components shown in the figures may be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and/or application specific integrated circuits.

Each component in the memory 100 is described in detail below in conjunction with FIG. 1:

As shown in FIG. 1 , the memory 100 may include a storage array 110 and a controller 120 . The storage array 110 is used to store data, and is a matrix array formed by a plurality of storage units arranged in rows and columns. Each storage unit can be used to store 1 or more bits of binary data, such as "0" and/or or "1". Wherein, the multiple storage units may be located on different tracks of the same disk, or may be located on different disks, which is not specifically limited. The controller 120 is used to read or write data in the storage array 110 and is a device with control capability. The controller 120 may be connected to the storage array 110 in a bus connection, for example. The controller 120 may include multiple functional components, such as but not limited to a drive circuit, a decoding circuit, and an amplifier circuit. These functional components may be provided as separate devices, or may be implemented in one device, or may be provided in at least two devices in any combination, which is not specifically limited.

Continuing to refer to FIG. 1 , the controller 120 may also be connected to an external device 200 , and the external device 200 may be, for example, a read-write device or a processor. When reading/writing data, the external device 200 may send a read/write request to the controller 120, the read/write request carrying row address information and column address information of the target storage unit to be read/written. The controller 120 decodes the row address information in the read/write request to determine the row where the target storage unit is located, and turns on all the storage units corresponding to the row where the target storage unit is located by decoding the selection signal, and then decodes the read/write request. The column address information in the request obtains the column where the target storage unit is located, and then reads the data stored in the target storage unit at the column and sends it to the external device 200, or writes the data to be written sent by the external device 200 into the column target storage unit at .

Although not shown in FIG. 1, the memory 100 may also include other components, such as a main memory data register (memory data register, MDR) and a main memory address register (memory address register, MAR), etc., which will not be described in detail here.

Fig. 2 exemplarily shows a schematic structural view of a storage unit provided by an embodiment of the present application, wherein (A) in Fig. 2 shows a front view obtained by cutting the storage unit along the _P1 plane, and in Fig. 2 (B) shows the top view obtained by cutting the storage unit along the _P2 plane. FIG. 3 exemplarily shows a schematic diagram of the preparation process corresponding to the storage unit. Referring to FIGS. 2 and 3, the preparation of the storage unit The process mainly includes the following steps:

Step 1, depositing alternately stacked dielectric layers and first metal layers on the stop layer to obtain the structure shown in (A) in Figure 3;

Step 2, etching the dielectric layer and the first metal layer to form holes to obtain the structure shown in (B) in Figure 3;

Step 3, depositing a storage film layer in the hole to obtain the structure shown in (C) in Figure 3;

Step 4, etching the bottom of the storage film layer in the hole so that the storage film layer only exists on the sidewall of the hole to obtain the structure shown in (D) in Figure 3;

Step 5, depositing an isolation layer on the inner side of the etched bottom storage film layer to obtain the structure shown in (E) in Figure 3;

Step 6, depositing a second metal layer inside the isolation layer to obtain the structure shown in (F) in FIG. 3 .

In the above memory cell, the memory film layer on the sidewall of the hole is used to store data. However, in the above preparation process, only when the holes are strictly vertical holes, can all the etching ions reach the bottom storage film layer along the inside of the vertical holes when etching the storage film layer at the bottom of the hole, As long as the holes are slightly inclined along the direction of stacking (the up-and-down direction in Figure 3), etching ions may reach the sidewalls of the holes during the process of spraying to the bottom of the holes, thereby making the sidewalls of the holes The storage film layer will also be etched away. However, in the process of forming holes by etching, the larger the aspect ratio of the memory cell, the more limited the number of etching ions reaching the bottom, and the closer to the bottom of the hole, the smaller the aperture of the hole etched, It is also easier to form an inclined hole with a wide top and a narrow bottom. It can be seen that the process of forming vertical holes by etching is very difficult, so the memory cell shown in FIG. 2 has a relatively strict process window, and it is difficult to achieve mass production. Once the process requirements are relaxed so that the holes are not made into vertical holes, the storage film layer on the sidewall of the hole will be etched away in the subsequent manufacturing process, thereby affecting the storage performance of the storage unit.

Based on this, an embodiment of the present application provides a memory cell, which is used to make the first metal layer recess relative to the adjacent dielectric layer along the direction of the hole diameter, and at least fill the memory film layer in the recess, so that, In the process of etching the storage film layer at the bottom, even if the hole is inclined, the storage film layer located in the recess can be protected due to the existence of the recess, so as to maintain the storage performance of the memory cell. It can be seen that since the structure does not need to be etched to form a strictly vertical hole, it can reduce the difficulty of manufacturing the memory cell.

A possible structure of the storage unit in the embodiment of the present application will be introduced below through specific embodiments.

It should be noted that in the following description of the present application, "a plurality" can be understood as "at least two". "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist at the same time, and B exists alone, where A, B can be singular or plural. "The following item(s) or multiple items(s)" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural item(s). For example, one item (unit) or multiple items (units) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single, It can also be multiple.

And, unless otherwise specified, the ordinal numerals such as "first" and "second" mentioned in the embodiments of the present application are only used for the purpose of distinguishing descriptions, and cannot be interpreted as indicating or implying relative importance, nor as indicating or imply order. For example, the "first sub-layer" and "second sub-layer" mentioned below are only used to indicate storage layers in different positions, and do not have a difference in order, priority or importance.

[Example 1]

Fig. 4 exemplarily shows a schematic structural view of a storage unit provided by an embodiment of the present application, wherein (A) in Fig. 4 shows a front view obtained by cutting the storage unit along the _M11 plane shown in the illustration, and Fig. 4 (B) shows a top view obtained by cutting the memory cell along the _M12 plane. As shown in FIG. 4 , in this example, the memory cell includes a hole, a stacked structure surrounding the hole, a second metal layer disposed in the hole, an isolation layer disposed in the hole and surrounding the second metal layer, and a part of the isolation layer surrounding the hole. storage film. Wherein, the stacked structure includes at least one dielectric layer and at least one first metal layer alternately stacked, and in the direction of the aperture of the hole (that is, the V ₁ direction shown in (A) in FIG. 4 ), each layer of the first The metal layer is recessed relative to the adjacent medium layer, and the storage film layer is filled in the recess. In this way, by making the storage film layer fill in the recesses of the adjacent dielectric layer and the first metal layer, in the process of etching the storage film layer at the bottom, even if the hole is inclined, the existence of the recess can protect the hole located in the recess. The internal storage film layer to maintain the storage performance of the storage unit. It can be seen that since the structure does not need to be etched to form a strictly vertical hole, it can reduce the difficulty of manufacturing the memory cell.

In an optional implementation manner, the stack structure may include _N1 dielectric layers and _N2 first metal layers, for example, _N1 and _N2 may be integers greater than or equal to 1 and less than or equal to 50 , and since the dielectric layer and the first metal layer are alternately stacked, the values of N ₁ and N ₂ are the same or different by 1, for example, when N ₁ is 1 greater than N ₂ , it means that the dielectric layer is one more layer than the first metal layer , when N ₂ is 1 greater than N ₁ , it means that the first metal layer is one more layer than the dielectric layer. For example, Fig. 5 exemplarily shows a possible structural schematic diagram of a stack structure provided by the embodiment of the present application, as shown in Fig. 5: when N ₁ and N ₂ are both 1, the stack structure can be as shown in Fig. 5 The one shown in (A) only includes one dielectric layer and one first metal layer, and the dielectric layer is located on the upper side of the first metal layer, or only one dielectric layer is included as shown in (B) in Figure 5 layer and a layer of the first metal layer, and the first metal layer is located on the upper side of the dielectric layer; when N ₁ takes a value of 2 and N ₂ takes a value of 1, the stacked structure can be as shown in (C) in Figure 5 It includes two dielectric layers and a first metal layer, and the first metal layer is sandwiched between the two dielectric layers; when _N1 takes a value of 1 and _N2 takes a value of 2, the stacked structure can be as shown in Figure 5 ( D) schematically includes a dielectric layer and two first metal layers, and the dielectric layer is sandwiched between the two first metal layers. It should be understood that when the values of _N1 and _N2 are both greater than or equal to 2, the stack structure includes at least two dielectric layers and at least two first metal layers, at least two dielectric layers and at least two first metal layers It can be alternately stacked in the manner of dielectric layer, first metal layer, dielectric layer, first metal layer, ..., or alternately stacked in the manner of first metal layer, dielectric layer, first metal layer, dielectric layer, ... , specifically can be realized by one or more combinations of (A) in FIG. 5 to (C) in FIG. 5 , which will not be listed here.

In the above embodiment, continue to refer to FIG. 5 , when the stacked structure only includes one dielectric layer and one first metal layer, the first metal layer can be relative to the _adjacent only One dielectric layer is recessed, as shown in (A) or (B) in FIG. 5 . When the stacked structure contains two layers of dielectric layers and a layer of first metal layer, the first metal layer can be relative to the leftmost layer of the right edge of the two adjacent dielectric layers along the V ₁ direction shown in the figure. The layer is recessed, as shown in (C) of FIG. 5 , so that two adjacent dielectric layers and the first metal layer sandwiched in between can form an accommodating space for accommodating the storage film layer. When the stacked structure contains one dielectric layer and two first metal layers, no matter whether it is the first metal layer above the dielectric layer or _the first metal layer below the dielectric layer, the It is recessed relative to a dielectric layer sandwiched in the middle, as shown in (D) in FIG. 5 .

In an optional embodiment, continue referring to FIG. 4 , in the stacking direction of the stacked structure (that is, the _V2 direction shown in FIG. 4 ), the sidewall of the hole can be inclined, and the inclination angle can be determined by those skilled in the art. A skilled person may determine it based on experience, or may obtain it through verification of bottom etching experiments, and may be, for example, a value between 0° and 5°. In this way, when the isolation layer or the second metal layer is deposited in the hole, the deposited material can be filled without gaps along the inclined hole wall, so as to effectively ensure the deposition quality.

It should be understood that the sidewalls of the holes may also be vertical along the stacking direction of the stacked structure if the process can be guaranteed, which is not specifically limited.

In an optional implementation manner, continuing to refer to FIG. 4 , the memory unit may further include a stop layer surrounding the hole, and the stop layer is located at the bottom of the stack structure. It should be noted that the stop layer can be located only at the bottom of the stack structure as shown in Figure 4 in order to save material, or it can be located at both the bottom of the stack structure and the bottom of the hole as shown in Figure 2 so that the isolation holes can be filled The second metal layer and the printed circuit board (printed circuit board, PCB) board on which the storage unit is placed are not specifically limited.

In an optional implementation manner, continue to refer to FIG. 4 , in the direction in which the stack structure is stacked (that is, the _V2 direction shown in FIG. 4 ), the thickness of each dielectric layer and/or each first metal layer It can be a value between 100 angstroms and 2000 angstroms. Among them, the full name of Angstrom is Eggstrand.

is a unit of length.

In an optional implementation manner, in the direction of the hole diameter (the _V1 direction shown in FIG. 4 ), the depression of each first metal layer relative to the adjacent dielectric layer can be realized by dry etching. Among them, the etching direction of dry etching can be set to the opposite direction of the aperture of the hole, that is, the opposite direction of V ₁ shown in Figure 4, and you can choose Pressure 2～100mt, source bias 100～1000w, bias power 20～ 200w, NF ₃ 2～200SCCM, O ₂ 2～100SCCM or Cl ₂ 2～100sccm any etching parameter can be realized. In this way, the directional rapid etching of the dry etching can be used to obtain the recess of each first metal layer relative to the dielectric layer, and it is also possible to avoid mis-etching of layers other than the first metal layer.

It should be understood that, if the etching efficiency is not considered, the above-mentioned recesses can also be realized by non-directional wet etching, for example, NH ₄ OH can be selected as the etching material.

In an optional implementation manner, continue to refer to FIG. 4, in the direction of the aperture of the hole (the _V1 direction shown in FIG. 4), each first metal layer can be recessed by 1 nm relative to the adjacent dielectric layer A value between ~10nm. Wherein, nm is the unit of length, that is, nanometer.

In an optional implementation manner, in the stacking direction (the _V2 direction shown in FIG. 4 ) of the stacked structure, the depth of the hole may be a value between 10 nm and 1000 nm.

In an optional implementation manner, in the direction of the pore diameter (the V ₁ direction shown in FIG. 4 ), the thickness of the storage film layer and/or the metal isolation layer may be a value between 2nm and 20nm.

In an optional embodiment, in the process of forming the above storage unit, the storage film layer can be realized by bottom etching, the bottom etching is preferably dry etching, and the etching direction of dry etching can be set to stack The stacking direction of the structure is the direction of V ₂ shown in Figure 4, and any of BCl ₃ 10-200sccm, Cl ₂ 10-200sccm, pressure 2-100mt, source power 100-1000w or bias power 20-1000w can be selected. An etch parameter is realized. In this way, the directionality of dry etching can be used to quickly etch away the storage film layer at the bottom of the hole, and it is also possible to avoid wrong etching of the storage film layer on the hole wall.

In an optional implementation manner, each layer in the storage unit may be implemented by one or more of the following:

The dielectric layer is realized by _SiO2 ;

The storage film layer is realized by capacitive material;

The isolation layer is realized by TiN;

The stop layer is realized _by _Al2O3 ;

The first metal layer is realized by tungsten (W) or molybdenum (Mo);

or,

The second metal layer is realized by tungsten (W).

Exemplarily, when the storage unit is a ferroelectric storage unit, the storage film layer may specifically be made of a ferroelectric material, such as a ferroelectric thin film. When the storage unit is a magnetic storage unit, the storage film layer may specifically be made of a magnetic material, such as an oxide magnetic powder thin film, a metal alloy magnetic powder thin film, or a metal thin film. When the memory cell is a phase-change memory cell, the memory film layer may specifically be made of a phase-change material, such as a germanium antimony tellurium (Ge-Sb-Te, GST) film or an oxygen-doped GST film. When the storage unit is a resistive switching storage unit, the storage film layer may specifically be made of a resistive switching material, such as a perovskite oxide film, a zinc-manganese oxide film, and the like. It should be understood that the storage unit and the corresponding storage film layer may also be of other types, which will not be listed here.

It should be noted that the above-mentioned introduction to the material, thickness, width or length of each layer in the storage unit is only an exemplary description. In actual operation, the specific implementation of each layer can be set according to the actual storage requirements. The embodiment of the present application does not limit that each layer must have the above features.

In the first embodiment above, the storage film layer is only filled in the accommodating space formed by the adjacent dielectric layer and the first metal layer, and the storage film layer in the accommodating space is also called the first sub-film layer. In this way, the above-mentioned embodiment 1 can not only protect the filled first sub-film layer through the accommodating space formed by the adjacent dielectric layer and the first metal layer, but also use as little storage film as possible when manufacturing the storage unit layer, saving the cost of preparing the storage unit.

In the embodiment of the present application, the storage film layer may include other sub-film layers besides the first sub-film layer filled in the accommodating space formed by the adjacent first metal layer and the dielectric layer. Example 2 introduces the possible structure of this storage unit in detail.

[Example 2]

Fig. 6 exemplarily shows a schematic structural diagram of another storage unit provided by the embodiment of the present application, wherein (A) in Fig. 6 shows a front view obtained by cutting the storage unit along the M ₂₁ plane shown in the illustration, and Fig. 6(B) shows a top view obtained by cutting the memory cell along the _M22 plane. As shown in FIG. 6, in this example, the memory cell includes a hole, a memory film layer surrounding the hole, a second metal layer disposed in the hole, an isolation layer disposed in the hole and surrounding the second metal layer, and an isolation layer completely surrounding the hole. layer of storage film. Wherein, the stacked structure includes at least one dielectric layer and at least one first metal layer stacked alternately _. The metal layer is recessed relative to the adjacent medium layer, and the storage film layer not only includes the first sub-film layer filled in the accommodating space formed by the adjacent first metal layer and the medium layer, but also includes the first sub-film layer filled in the medium layer, the second The second sub-film layer in the accommodating space formed by the first sub-film layer and the isolation layer.

In the second embodiment, by making the storage film not only fill the recesses of the adjacent dielectric layer and the first metal layer, but also fill the outside of the recesses, in the process of etching the storage film at the bottom, even if the etching ions To reach the side wall of the hole, it is also necessary to etch the storage film layer filled outside the depression before etching the storage film layer located in the depression. Obviously, the second embodiment can further protect the storage film layer located outside the depression. The storage film layer in the recess helps to maintain the storage performance of the storage unit while further reducing the difficulty of manufacturing the storage unit.

It should be noted that the various implementation manners in the first embodiment above are also applicable to the second embodiment, and this application will not repeat them one by one.

Based on the storage unit shown in Embodiment 1 or Embodiment 2, the present application also provides a method for preparing the storage unit. Fig. 7 exemplarily shows a schematic flow chart of preparing a storage unit provided in the embodiment of the present application. As shown in Fig. 7, the preparation process includes:

Step 1, depositing a stop layer to obtain a structure as shown in (A) of FIG. 7 .

Step 2, alternately stacking at least one dielectric layer and at least one first metal layer on the stop layer to obtain a stacked structure as shown in (B) in FIG. 7 .

Step 3, forming holes surrounded by the stacked structure by etching the stacked structure, and obtaining the structure shown in (C) in FIG. 7 . Wherein, the hole formed by etching may be an inclined hole as shown in (C) in FIG. 7 , or a vertical hole as shown in (B) in FIG. 3 , which is not specifically limited.

Step 4, etching back at least one first metal layer in the hole, so that each layer of the first metal layer is recessed relative to the adjacent dielectric layer along the direction of the hole diameter, as shown in (D) in Figure 7 Structure.

Step five, depositing a storage film layer on the bottom of the hole and the side wall of the hole, the storage film layer deposited on the side wall of the hole includes the part filled in the depression and the part connected to the depression, as shown in (E) in Figure 7 The structure shown.

Step 6: Etching the bottom of the storage film layer at the bottom of the hole, for example, it can be etched to the bottom of the stop layer as shown in (C) in Figure 7, or as shown in (D) in Figure 3 Etching into the stop layer and still retaining a part of the bottom of the stop layer, which is not limited.

In the above step 6, when the hole is an inclined hole as shown in (E) in Fig. 7, the etching ions used for bottom etching will be sprayed onto the sidewall of the hole, thereby causing the storage layer located on the sidewall of the hole The film layer will also be etched. In this case, if the storage film layer on the sidewall of the hole is etched away, a structure as shown in (G1) in Figure 7 can be obtained. At this time, the storage film layer after bottom etching only includes filling The first sub-film layer in the recess of the stacked structure. Conversely, if the storage film layer on the sidewall of the hole is not completely etched away, a structure as shown in (G2) in Figure 7 can be obtained. The first sub-film layer in the recess of the stack structure and the second sub-film layer connected to the first sub-film layer in the recess.

Step 7, depositing and forming an isolation layer (also referred to as a second isolation layer) surrounded by the bottom-etched storage film layer and a second metal layer surrounded by the isolation layer in the hole, to obtain (H1) or Structure as schematically shown in (H2) in FIG. 7 .

Step 8, remove the second metal layer on the surface of the memory cell by chemical mechanical polishing (CMP) technology, and polish the surface to be flat and free of scratches, to obtain (I ₁ ) as shown in Figure 7 or as shown in Figure 7 The structure shown in (I ₂ ). Wherein, the storage unit shown by (I ₁ ) in FIG. 7 is the storage unit in the first embodiment above, and the storage unit shown by (I ₂ ) in FIG. 7 is the storage unit in the second embodiment above.

In the above preparation process, by etching back the first metal layer, a recessed accommodating space can be formed between the first metal layer and the adjacent dielectric layer, so that even if the etched hole is an inclined hole, As a result, the etching ions sprayed onto the sidewall of the hole when etching the storage film layer at the bottom, the storage film layer filled in the accommodating space can also be protected by the recessed accommodating space from being etched. It can be seen that, by adopting this method for preparing the memory unit, it is not necessary to etch the vertical holes in the third step, thereby reducing the difficulty of preparing the memory unit. In addition, since memory cells with larger aspect ratios are easier to etch to form oblique holes with narrow upper widths, this fabrication method is especially suitable for fabricating memory cells with high aspect ratios.

In an optional embodiment, after obtaining the structure shown in (E) in Figure 7 according to the above step five, the following steps can also be performed:

Step 9, depositing and forming an isolation layer (also referred to as a first isolation layer) surrounded by the storage film layer in the hole to obtain a structure as shown in (F) in FIG. 7 .

Correspondingly, the above step six is adjusted to: perform bottom etching on the isolation layer and the storage film layer at the bottom of the hole to obtain the structure as shown in (G1) or (G2) in FIG. 7 .

In the above embodiments, by depositing an isolation layer on the inner side of the storage film layer before etching the storage film layer at the bottom, even if etching ions are sprayed to the sidewall of the hole when the storage film layer is etched at the bottom, it is necessary to first etch the storage film layer. The storage film layer on the hole wall can only be etched after the first isolation layer located inside the storage film layer is etched. It can be seen that this embodiment can further reduce the probability of etching the storage film layer on the hole wall by sacrificing the isolation layer, and further achieve the purpose of protecting the storage film layer on the hole wall.

It should be noted that the above step 1 is an optional step. In other embodiments, the stop layer may not be deposited, but the structure without the stop layer may be directly arranged on the PCB, which is not specifically limited in the present application. The fifth step above is also an optional step. In other embodiments, the second metal layer can only be deposited in the hole without depositing the second metal layer on the surface, or the second metal layer deposited on the surface can also be retained, or Other technical methods may also be used to remove the second metal layer deposited on the surface, etc., which are not specifically limited.

In addition, the relevant implementation methods in the above-mentioned Embodiment 1 and Embodiment 2 are also applicable to the preparation method, and the embodiments of the present application will not repeat them one by one.

In the embodiment of the present application, a memory array can be obtained by combining a plurality of memory cells according to at least two directions of row, column, or stacking. Fig. 8 exemplarily shows a schematic structural diagram of a memory array provided by an embodiment of the present application. The memory array is obtained by combining four memory cells as shown in Fig. 4 in the row and column directions. These four memory cells are respectively The unit 11, the storage unit 12, the storage unit 21 and the storage unit 22, and the storage unit 11, the storage unit 12, the storage unit 21 and the storage unit 22 are arranged in a row-column structure of two rows and two columns. Among them, (A) in FIG. 8 shows a cross-sectional front view obtained by cutting the memory array along the plane _M31 in the diagram, and (B) in FIG. 8 shows that the memory array is cut along the plane _M32 in the diagram. The cross-sectional side view obtained by the array, FIG. 8(C) shows the cross-sectional top view obtained by cutting the memory array along the _M33 plane in the illustration. In implementation, the memory array can be connected to the controller, and the controller includes a word line circuit and a bit line circuit. As shown in FIG. 8, the first metal layer of each memory cell in the memory array can be connected to the bit line circuit in the controller. Line circuit, the second metal layer of each memory cell in the memory array can be connected to the word line circuit in the controller, so that the controller can open the target memory through the word line circuit and the bit line circuit when it needs to perform read and write operations. unit, and then write data to the target storage unit, or read data in the target storage unit.

It should be noted that, FIG. 8 only introduces the specific structure of the memory array by combining multiple memory cells according to the row and column directions as an example, and the memory array formed in this way has a single-layer structure. Furthermore, the present application can also stack memory cells to obtain a memory array with a multi-layer structure, such as combining the two directions of row and stacking, or combining the two directions of column and stacking to form a two-dimensional memory array with a multi-layer structure Arrays, such as three-dimensional storage arrays that are combined in three directions of row, column and stacking to form a multi-layer structure, further increase the storage density and storage capacity of the storage array.

The present application also provides a memory, which includes the storage array as described above, and a controller coupled to the storage array, where the controller is used to read and write data in the storage array.

The present application also provides an electronic device, including a PCB and the memory as described above, wherein the memory is arranged on the surface of the PCB.

Exemplarily, the electronic device includes, but is not limited to: a smart phone, a smart watch, a tablet computer, a VR device, an AR device, a vehicle device, a desktop computer, a personal computer, a handheld computer or a personal digital assistant.

While a few possible embodiments of the present application have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once the basic inventive concept is appreciated. Therefore, the appended claims are intended to be construed as including the embodiments of the present application and all changes and modifications that fall within the scope of the present application.

Apparently, those skilled in the art can make various changes and modifications to this application without departing from the protection scope of this application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A storage unit, characterized in that it comprises:

hole;

a stacked structure surrounding the aperture;

a second metal layer and an isolation layer disposed within the hole, and the isolation layer surrounds the second metal layer;

as well as,

a memory film layer at least partially surrounding the isolation layer;

Wherein, the stacked structure includes at least one dielectric layer and at least one first metal layer alternately stacked, and each layer of the first metal layer is relative to the adjacent The dielectric layer is recessed, and the side of the storage film layer opposite to the isolation layer is in contact with the first metal layer in the stacked structure.
The storage unit according to claim 1, wherein the storage film layer comprises a first sub-film layer, and the first sub-film layer is filled in two adjacent layers of the dielectric layer and the first metal layer. The accommodation space formed.
The storage unit according to claim 2, wherein the storage film layer further comprises a second sub-film layer, and the second sub-film layer is located between the first sub-film layer and the isolation layer.
The memory cell according to any one of claims 1 to 3, further comprising a stop layer surrounding the hole, the stop layer being located at the bottom of the stacked structure.
The storage unit according to any one of claims 1 to 4, wherein the side walls of the holes are inclined relative to the direction in which the stacked structures are stacked.
The memory cell according to any one of claims 1 to 5, wherein the thickness of each layer of the dielectric layer and/or each layer of the first metal layer in the stacking direction of the stacked structure is 100 Å A value between ~2000A.
The memory cell according to any one of claims 1 to 6, characterized in that each layer of the first metal layer is recessed relative to the adjacent dielectric layer by 1-10 nm along the direction of the aperture of the hole a value between.
The storage unit according to any one of claims 1 to 7, wherein the accommodating space formed by two adjacent layers of the dielectric layer and the first metal layer is realized by dry etching.
A method for preparing a storage unit, comprising:

alternately stacking at least one dielectric layer and at least one first metal layer to form a stacked structure;

etching the stack structure to form a hole surrounded by the stack structure;

Etching back the at least one first metal layer in the hole, so that each layer of the first metal layer is recessed relative to the adjacent dielectric layer along the direction of the hole diameter;

depositing a storage film layer between the stack structure and the hole, and depositing an isolation layer and a second metal layer surrounded by the isolation layer in the hole, the storage film layer at least partially surrounding the isolation layer, And the side of the storage film layer opposite to the isolation layer is in contact with the first metal layer in the stack structure.
The method according to claim 9, characterized in that a storage film layer is deposited between the stacked structure and the hole, and an isolation layer and a second metal layer surrounded by the isolation layer are deposited in the hole, include:

Depositing a storage film layer in the hole to form a contact with the first metal layer after etching back;

performing bottom etching on the storage film layer in the hole;

Depositing and forming a first isolation layer surrounded by the storage film layer after bottom etching in the hole;

A second metal layer surrounding the first isolation layer is formed by depositing in the hole.
The method of claim 10, wherein

After depositing and forming a storage film layer in the hole in contact with the first metal layer after etching back, before performing bottom etching on the storage film layer in the hole, further comprising:

depositing and forming a second isolation layer surrounded by the storage film layer in the hole;

The bottom etching of the storage film layer in the hole includes:

Bottom etching is performed on the second isolation layer and the storage film layer in the hole.
The method according to any one of claims 9 to 11, wherein the alternately stacking at least one dielectric layer and at least one first metal layer to form a stacked structure includes:

At least one dielectric layer and at least one first metal layer are alternately stacked on the stop layer to form the stacked structure.
The method according to any one of claims 9 to 12, wherein the storage film layer after bottom etching includes a first sub-film layer, and the first sub-film layer fills the adjacent The accommodating space formed by the dielectric layer and the first metal layer.
The method according to claim 13, wherein the storage film layer after bottom etching further includes a second sub-film layer, and the second sub-film layer is located between the first sub-film layer and the second sub-film layer. Between the two isolation layers.
The method according to any one of claims 9 to 14, characterized in that the side walls of the holes are inclined relative to the direction in which the stacked structures are stacked.
The method according to any one of claims 9 to 15, wherein the thickness of each layer of the dielectric layer and/or each layer of the first metal layer in the stacking direction of the stacked structure is 100 Å to 100 Å. A value between 2000A.
The method according to any one of claims 9 to 16, wherein said etching back said at least one first metal layer in said hole comprises:

A value between 1 nm and 10 nm is etched back on each layer of the first metal layer along the direction of the aperture of the hole.
The method according to any one of claims 9 to 17, wherein said etching back said at least one first metal layer in said hole comprises:

At least one layer of the first metal layer is etched back in the hole by dry etching.
A memory, characterized by comprising a storage array and a controller coupled to the storage array, the storage array includes a plurality of storage units according to any one of claims 1 to 8, the plurality of Storage units are deployed in an array;

The storage array is used to store data;

The controller is configured to write data into the storage array, or read data from the storage array.
An electronic device, characterized by comprising a printed circuit board (PCB) and the memory according to claim 19, wherein the memory is arranged on the surface of the PCB.