WO2023143693A1

WO2023143693A1 - Optoelectronic device and method of processing the same

Info

Publication number: WO2023143693A1
Application number: PCT/EP2022/051579
Authority: WO
Inventors: Christoph Klemp
Original assignee: Ams-Osram International Gmbh
Priority date: 2022-01-25
Filing date: 2022-01-25
Publication date: 2023-08-03

Abstract

The invention concerns an optoelectronic device, comprising a first semiconductor layer (11) of a first doping type and a second semiconductor layer (12) of a second doping type. An active region (13) is arranged between the first and the second semiconductor layers and light emission surface (11a) is formed by a surface of the first semiconductor layer (11) opposite the second semiconductor layer (12). A contact layer (20) is arranged on the second semiconductor layer (12) opposite the active region (13). The device comprises a passivation layer (30) deposited on sidewalls (50) of the second semiconductor layer (12), side- walls of the active region (13) and at least partially on sidewalls (50) of the first semiconductor layer (11), wherein the passivation layer (30) comprises MgF2 and wherein the first and second semiconductor layer (12) comprise a phosphide material system.

Description

OPTOELECTRONIC DEVICE AND METHOD OF PROCESSING THE SAME

The present invention concerns an optoelectronic device and a method of processing the same .

BACKGROUND

Processing of p-LEDs with an edge length of less than 70mm down to a few pm provides various challenges . Particular for pLED emitting red light , e . g . based on the phosphide material system, issues arise not only form challenges during epitaxial growth, but also from the size and the emitting behaviour itself . pLEDs have the tendency to emit light into all directions , thus becoming a volume emitter rather than a top or bottom emitter . While in some applications , a volume emitter is preferred, other applications require a top emitter, with -generally speaking- the emission of light in a pre-determined direction . This requirement is often present in cases , in which optical crosstalk should be avoided but also to improve the emission gain into said pre-determined direction .

Various measures have been taken to improve the efficiency for top emitter pLEDs with various degrees of success . Consequently, there is still a need for solutions offering an improvement of the top emission efficiency, preferably with additional benefits resulting in a simpler and less complex manufacturing process .

SUMMARY OF THE INVENTION

This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

The inventor proposes using a low refractive index material as cover for the sidewalls along the p-side , the active region and the n-side of the optoelectronic device . Such low refractive index material will cause an increase in the overall internal reflection between the semiconductor material and the cover material , thus leading to an increased emission from a main emission surface . It has been found that MgF2 is a suitable material for said purpose due to its low refractive index and its compatibility with phosphide-based material systems . Further surprisingly MgF2 has properties suitable for passivation the edges of the active region in such material system offering a low density of non-radiative recombination centres at the edge regions . Consequently, the deposition process of MgF₂ can be tuned and fits into already established cleaning and annealing processes during processing of an optoelectronic device .

In some instances , the inventor proposes an optoelectronic device . The device comprises a first semiconductor layer of a first doping type , a second p-doped semiconductor layer of a second doping type and an active region arranged between the first and the second semiconductor layers . A light emission surface is formed by a surface of the first semiconductor layer opposite the second semiconductor layer . Further, the optoelectronic device comprises a contact layer arranged on the second semiconductor layer opposite the active region . A passivation layer comprising MgF2 is deposited on sidewalls of the second semiconductor layer , on sidewalls of the active region and at least partially on sidewalls of the first semiconductor layer . The first and second semiconductor layer comprise a phosphide-based material system, in particular one of AlGaP, InGaP and AlInGaP .

In some instances , the first doping type is an n-doping, the second doping type is a p-doping . Consequently, the main light emission surface is defined by the surface of the n-doped semiconductor layer . In this regard, the surface can be roughened or otherwise processed to improve the emission behaviour . In addition or alternatively, outcoupling structures like photonic elements or meta lenses can be arranged and attached on the surface of the first semiconductor layer . In some other instances contact layers are arranged on or adj acent to the main emission surface of the first semiconductor layer .

Some aspects concern the passivation layer including MgF2 . In some instances , the passivation layer extends partially onto the surface of the second semiconductor layer opposite the active region and surrounding the contact layer . In other words , the passivation layer covers the sidewalls of the device as well as the surface of the device opposite the main emission surface . Hence , the overall total reflection is increased . In some instances , a contact layer is arranged on the second semiconductor surface . The contact layer can be at least partially covered by the passivation layer as well .

In some aspects , the passivation layer comprises a larger thickness on the surface of the second semiconductor layer than on the sidewalls of the second semiconductor layer . This may be due to processing of the device , in which more material of the passivation layer is deposited on the surface than on the sidewalls . If needed, the material can be removed during processing such that the thickness becomes equal . In some instances , the thickness on the surface of the second semiconductor layer is equal to a thickness of a contact layer on the second semiconductor layer adj acent to the passivation layer . Hence , passivation layer and contact layer create an equal and smooth surface .

In some further aspects , the optoelectronic device further comprises a reflective metal layer on the contact layer and optionally on the passivation layer surrounding the contact layer . The metal layer forms a contact for the optoelectronic device .

The overall thickness of the passivation layer is in the range of a few ten nm and may be in the range of 30 nm to 500 nm and in particular between 50 nm and 300 nm and more particularly between 50 nm and 150 nm. In some instances , the optoelectronic device further comprises a layer between the sidewalls and the passivation layer . Said layer may comprise one of A12O3 , HfOx and SiO2 and is used to cure and reduce the non- radiative recombination centres close to the active region . The thickness is significantly smaller than the thickness of the passivation layer and does not interfere with the optical and reflective behaviour . As such the characteristics of the interface between the passivation layer and the semiconductor material is maintained . For example the thickness may be less than 10 nm and particularly less than 5 nm.

Some other aspects concern a method for processing an optoelectronic device . The method provides a semiconductor stack on a growth substrate . The semiconductor stack is processed with well-known technologies for the phosphide-based material systems and includes one or more steps of epitaxial growth of semiconductor material , photo structuring steps and the like . Suitable base material includes , but are not limited to InGaP, AlGaP and InAlGaP . The semiconductor stack includes a first semiconductor layer of a first doping type deposited on the growth substrate . An active region is formed on the first semiconductor layer and a second semiconductor layer is deposited on the active region . The second semiconductor layer is of a different doping type than the doping tape of the first semiconductor layer .

The various semiconductor layers may comprise different doping profile to achieve various functionalities like current spreading and current distribution . Some layer may even be undoped or slightly doped as needed . Further layers like buffer layers and sacrificial layers can be provided if needed . A contact layer is deposited on the second semiconductor layer . In some instances , the contact layer comprises a layer stack including a metal or highly doped semiconductor layer and a transparent conductive oxide layer , the transparent conductive layer being the topmost layer .

Then, a photo resist is deposited and structured to expose areas on the second semiconductor layer and/or the contact layer . A mesa structure is provided within the contact layer and the semiconductor stack extending through the second semiconductor layer, the active region and at least partially through the first semiconductor layer . In a subsequent step, a passivation layer is deposited on the mesa structure and on the surface of the contact layer and/or the second semiconductor layer . The passivation layer comprises a layer of MgF2 . Finally, the passivation layer is removed on the surface of the contact layer and/or the second semiconductor layer as to expose at least portions of the contact layer to provide access to the second semiconductor layer .

The removal process is performed for example by CMP ( chemical mechanical polishing ) to sustain the even and smooth surface until the surface of the contact layer is reached . In this regard, the passivation layer on the bottom of mesa structure can also be removed, such that the passivation layer remains only on sidewalls of the mesa structure . In some instances , quantum well intermixing is generated during epitaxial growth of the semiconductor stack . For this purpose , a dopant may be induced by depositing Zn onto the surface and diffusing the dopant through the second semiconductor layer into the active region . The quantum well intermixed areas are located in region subsequently being etched and forming the edges of the mesa structure .

In this regard, a Zn/Te pn j unction may be formed after the mesa etching step generating a possible small leakage . The use of MgF2 allow to pre passivate such j unction reducing the leakage and thus increasing the performance . In some instances , MgF2 is also used as material for a layer in a DBR stack arranged on the sidewalls of the device further improving the reflective behaviour . In some instances , the step of providing a mesa structure comprises the steps of depositing a structured photoresist layer on the contact layer and subsequently removing portions of the structured photoresist layer to expose surface portions of the contact layer . Then, the exposed surface portions are etched exposing the second semiconductor layer beneath . The semiconductor layer stack beneath the etched surface portions is also etched .

In this regard, the etching process of the semiconductor layer stack can comprise several sub-steps . For example , a first etching step is performed to expose sidewalls of the active region . Hence , this etching step etches through the second semiconductor layer and the active region . It may also partially etch into the first semiconductor layer . The edges of the active region are sensitive and may contain due to the etching method a relatively hight density of defects . Consequently, some annealing process is performed after the first etching process using for instance KOH etching .

In some aspects , the annealed and cleaned sidewalls of the active region are covered by a thin layer of A12O3 prior to performing a second etching step . The A12O3 layer can be later removed or left behind on the sidewalls when the passivation layer is deposited thereupon . Subsequently, a second etching step is conducted through remaining parts of the first semiconductor layer . The second etching step can reach into a buffer layer to ensure separation of the respective optoelectronic elements . In some other instances , the photo resist is removed after the etching of the mesa structure is completed . Then, a new photoresist layer is deposited on the contact layer and into the mesa structure and subsequently structured . Removal of the photo resist may be necessary as the resist cannot be restructured . In any case , the structured photoresist layer is processed to expose surface portions of the contact layer arranged on the second semiconductor layer . The exposed portions are subsequently removed . In some instances , the second semiconductor layer is exposed by the removal process , in some other instances , in which the contact layer comprises several sub-layers , one or more of those sublayers are partially removed, leaving some layers , e . g . for current distribution purposes behind . This process results in a contact portion on top of the semiconductor layer .

In some further aspects , the semiconductor layer stack is re-bonded after the contact layer is exposed or at least after the mesa structure and the passivation layer on the sidewalls of the mesa structure has been formed . The growth substrate is removed to expose a surface of the first semiconductor layer . After getting access to the surface of the first semiconductor layer further processing can be conducted to form the light emission surface .

For growth of the passivation layer and MgF2 in particular, various deposition method are available . For example , Mgf2 can be deposited from the gas phase using two different precursors . Depositing MgF2 may result in an uneven deposition rate on the side wall compared to the top surface with MgF2 growing faster on the top surfaces than on the sidewalls .

SHORT DESCRIPTION OF THE DRAWINGS

Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

Figure 1 shows a first embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ; Figures 2A to 2C illustrate several further embodiments of optoelectronic devices in accordance with some aspects of the proposed principle ;

Figure 3 shows a structure of optoelectronic devices in accordance with some aspects of the proposed principle during the processing thereof ;

Figures 4A to 4 J illustrate an embodiment of processing an optoelectronic device in accordance with some aspects of the proposed principle .

DETAILED DESCRIPTION

The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea .

In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However, terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

Figure 1 illustrates an embodiment of an optoelectronic device in accordance with the proposed principle . The optoelectronic device 1 comprises a first semiconductor layer 11 , a second semiconductor layer 12 and an active region 13 arranged between the first and second semiconductor layers , respectively . The first semiconductor layer is an n-doped and defines the light emission surface on its surface opposite the active region . Semiconductor layer 12 is a p-doped layer . Both semiconductor layers may include a constant doping concentration but also a doping gradient depending on the required needs . A contact layer 20 is arranged on the surface of second semiconductor layer 12 opposite the active region 13 . Contact layer 20 comprises layer stack having a metal layer 21 and a transparent conductive oxide layer 22 arranged on top, the transparent conductive layer 22 forming the outermost layer .

In operation of the optoelectronic device according to Figure 1 light is generated within the active region 13 and will emit in all directions . To improve the efficiency for top light emission, that is out of main emission surface 112 , light being emitted towards the sidewalls 50 of the optoelectronic device one as to be reflected towards the main emission surface . For this purpose , the present application proposes a passivation layer 30 arranged on the sidewalls 50 as well as a second passivation layer 31 arranged on the bottom surface of the second semiconductor layer 12 . Passivation layers 30 and 31 include MgF₂ as material covering the sidewalls 50 and the bottom surface surround contact 20 .

The passivation material comprises the lowest refractive index available for being deposited on semiconductor material based on a phosphide material system . While MgF₂ may also be deposited on surfaces of different material systems , it has been found that for material systems based on phosphide like AlGaP, InGaP or InAlGaP, MgF₂ as material is suitable for passivation due to its low impact on the defect density on the sidewalls 50 . In addition, the difference of the refractive indices between the semiconductor material and MgF₂ is suitably large to increase the overall internal reflection thus enhancing the top emission gain . Furthermore , MgF₂ is a material suitable for being processed with conventional techniques like for example chemical mechanical polishing . Hence , complex lithographical and etching process steps can be omitted .

The optoelectronic device in accordance with Figure 1 comprises a passivation layer 31 on its bottom surface surrounding contact 20 . The thickness of this passivation layer equals the thickness of contact layer 20 , thus providing an even surface , on which second metal layer contact 23 is deposited thereupon . Metal layer contact 23 of the optoelectronic device forms the contact for the p-doped semiconductor layer 12 . The thickness of passivation layer 31 is larger than the thickness of passivation layer 30 on sidewalls 50 of the devices .

Figure 2A to 2C illustrates a further example of optoelectronic devices utilizing MgF2 as a passivation layer on its sidewalls and its bottom surface , respectively . Figure 2A illustrates an example of passivation layer 30 being deposited on the inclined sidewalls of semiconductor layer stack 10 . The bottom surface of the second semiconductor layer 12 surrounding the p-contact 21 remains free of passivation material MgF2 . However, a different passivation material like SiO2 or any other suitable material can be deposited on the bottom surface .

Figure 2B illustrates a further example similar to the embodiment of figure 1 . In the present example , contact layer 20 comprises a single contact material forming layer 21 , which is even to the surface of passivation layer 31 . In this embodiment , metal contact layer 33 is omitted and the optoelectronic device is contacted directly with layer 21 . Like in the previous embodiment of Figure 1 , the thickness of passivation layer 31 a slightly larger than the thickness of passivation layer 30 on the inclined sidewalls .

Figure 2C illustrates a further example , on which the passivation material is only deposited surrounding the bottom contact 21 , thus forming passivation layer 31 .

Figure 3 illustrates several optoelectronic devices 1 during the processing of such devices . The devices are epitaxially grown on a growth substrate 14 including a suitable growth material for the n-doped semiconductor layer 11 and the p-doped semiconductor layer 12 . The two optoelectronic devices 1 are separated by a respective mesa structure 5 forming sidewalls 50 of the optoelectronic devices . The area close to the edges of active region 13 , a quantum well intermixing 130 has been conducted to adj ust the bandgap close to the edge regions in order to reduce the non-radiative recombination . As illustrated MgF2 is deposited on the sidewalls 50 and on the bottom of the mesa structure ( forming element 32 ) as well as on the surface of second semiconductor layer 12 . It covers contact layer 20 as well . However , during the subsequent processing steps , passivation layer 33 and 32 are removed . The passivation layer 31 on the bottom surface of the second semiconductor layer 12 equals the thickness of contact layer 20 . Furthermore , the thickness of passivation layer 31 is larger than the thickness of passivation layer 30 on the sidewalls .

Figures 4A to 4J provide an example for processing a plurality of optoelectronic devices in accordance with the proposed principle . Figure 4A shows the first steps of the method, whereby a growth substrate 14 is provided . The growth substrate 14 comprises one or more semiconductor layers used for example as a buffered layer or a sacrificial layer . The lattice constant of growth substrate 14 is similar to the subsequently epitaxially grown semiconductor layers 11 and 12 . In the present example , the material used for semiconductors layer 11 and 12 is based on the phosphide material system including ternary semiconductor material like AlGaP , InGaP , or quaternary system like InAlGaP . Particularly, the later material may be suitable to adj ust the wavelength but also to provide a multi-quantum well structure is an active region by adj usting the Al content during growth of the quantum well structure .

On top of the surface of growth substrate 14 an n-doped layer 11 is deposited . The doping concentration of n-doped layer 11 includes a gradient to ensure current distribution and inj ection into the active region 13 . Active region 13 is deposited on top of n-doped layer 11 . Active region 13 includes for example one or more quantum wells made of InAlGaP quantum well and barrier structures of different Al content . A p-doped semiconductor layer 12 is deposited on top of active region 13 . Like for the n-doped layer 11 , p-doped semiconductor layer 12 comprises a doping concentration gradient to distribute the charge carriers into the active region 30 .

Figure 4B illustrates the next process step , in which a contact layer 20 is deposited on the top surface of second semiconductor layer 12 . Contact layer 20 comprises a first metal contact layer 21 and a transparent conductive oxide layer 22 deposited on metal layer 21 . Metal contact layer 21 also acts as a current distribution to distribute the charge carrier along the overall surface of the p-doped semiconductor layer 12 . A photo resist material 3 is arranged on top of contact layer 20 . Contact layer 20 will later be structured and etched to form a contact portion for p-doped semiconductor layer 12 .

In a subsequent step, the photoresist layer on top of contact layer 20 is structured as to expose certain areas of contact layer 20 and particular of the transparent oxide 22 . The structured photo layer 3 ' is illustrated in Figure 4C . In some instances the structured photo mas k 3 ' is a so-called hard mask to allow an additional -doping using Zn as dopant for providing a quantum well intermixing in the active region 13 . In such circumstances Zn is diffused through the exposed area of contact 20 and the p-doped semiconductor region 12 into active region 30 causing a quantum well intermixing in active region 30 .

In a subsequent step illustrated in Figure 4D, a mesa etching is performed . The resulting mesa structure extends from the structured photo resist layer 3 ' all the way into a buffer layer of growth substrate 14 , including contact layer 20 , p-doped semiconductor layer 12 , active region 13 and n-doped semiconductor layer 11 . The etching process is performed in two steps , not illustrated herein . A so-called shallow Mesa etching process is conducted in a first step exposing sidewalls 50 of contact layer 20 , p-doped semiconductor layer 12 as well as active region 13 . The first etching process will cause crystal defects on the edges particularly at active region 30 . Consequently, an annealing and cleaning process will be performed afterwards using for instance KOH . The etching process , the sidewalls of active region 13 and P doped semiconductor layer 12 are annealed reducing the overall crystal defect density .

The annealed sidewalls 50 are covered to by a thin A12O3 layer to avoid further etching during the subsequent deep Mesa etching process . The thickness of the A12O3 layer is in the range of a few nanometers and should not extend 30 nm, but stay below 10 nm . At such thickness , the optical behaviour of the A12O3 layer does not impact the optical properties and its behaviour of the subsequently passivation layer of MgF2 . The second mesa etching process removes material of the n-doped semiconductor layer 11 and extends into the buffer layers of growth substrate 14 . The sidewalls 50 of the resulting optoelectronic devices are cleaned after the second etching process , annealed and optionally covered by very thin the passivation layer of SiO2 . For this purpose , the A12O3 layer can be removed . Alternatively, the A12O3 layer remains on the surface of the sidewalls .

In cases in which a Quantum well intermixing step was conducted, the bandgap within the active region close to the edges is increased thus effectively preventing charge carriers from reaching the edges and the crystals defects .

The remaining structured photoresist layer 3 ' is removed and other second photoresist layer is deposited covering the top surface of protective layer 20 as well as the sidewalls 50 and the bottom of mesa structure 5 . Figure 4D illustrates the result of this process . In an alternative embodiment , this step can be completely omitted, if a selective etching process can be conducted, removing the material of contact layer 20 beneath the structured photo resist 3 ' .

The newly added photoresist layer 4 as shown in Figure 4E is then structured to remove portions of the resist on top of contact layer 20 , leaving only the centred portion 4 ' of photo resist on the top surface . This step will expose areas of contact layer 20 which are subsequently removed to obtain a contact structure on the second semiconductor layer

12 .

Figure 4 F illustrates the resulting structure with the remaining portions of photo resist 4 ' covering the contact 20 as well as the sidewalls 50 of the optoelectronic devices and the bottom of the mesa structure . The photoresist material is removed in Figure 4G and a passivation layer comprising MgF2 is deposited covering the sidewalls 50 of the optoelectronic devices , the bottom of mesa structure 5 as well as the top surface of the second semiconductor layer 12 and contact 20 . The material in areas 32 at the bottom of the mesa structure as well as on the top surface of semiconductor layer 12 and contact 20 are thicker than the material in areas 30 on the respective sidewalls 50 due to the deposition process of the passivation layer . The thickness is in the range between 50 nm and 250 nm on the sidewall 50 and approximately 200 nm to 350 nm on the bottom. In some instances , the thickness on the bottom and areas 32 , corresponds substantially to a thickness of the passivation layer on the top surface of layer 12 .

The deposition process of passivation layer is continued until the top surface particularly above the respective optoelectronic devices is smooth and even to allow a subsequent simple processing by chemical or mechanical means . In a subsequent step illustrated in Figure 41 , chemical mechanical polishing (CMP ) is conducted to remove material MgF2 of passivation layer until the transparent conductive oxide 22 of contact layer 20 is reached . This will expose the contact 20 for the doped semiconductor layer 12 .

The optoelectronic devices are then re-bonded by attaching the top surface of passivation layer 31 and contact 22 to a temporary substrate . The growth substrate 14 of the optoelectronic devices together with any additional buffer or sacrificial layer is then removed to provide the main emission surface of the optoelectronic devices . Figure 4 J illustrates an intermediate result of that process , in which a portion of the growth substrate 14 has already been removed . As the mesa structure 5 extends into the buffer layers and the growth substrate 14 , removal of the growth substrate will separate the devices and in this regard also remove the remaining material in areas 32 at the bottom of mesa structure 5 . The then separated optoelectronic devices can then be processed further . For example , the main emission surface formed by the surface of the semiconductor 11 is a roughened to improve the out-coupling of light during operation of devices .

The material at the sidewalls provides an increased internal reflection due to its lower refractive index compared to the semiconductor material . LIST OF REFERENCES

I optoelectronic device

3 photo resist layer

3 ' structured photo resist

4 photoresist layer

4 ' structured photoresist

5 mesa structure

10 semiconductor layer stack

II first semiconductor layer , n-doped

Ila light emission surface

12 second semiconductor layer, p-doped

13 active region

14 growth substrate

20 contact layer

21 metal layer

22 transparent conductive layer

23 metal layer

30 , 31 passivation layer

32 , 33 passivation layer

50 sidewall

111 , 122 sidewalls

112 main emission surface

130 quantum well intermixing

300 passivation material

Claims

CLAIMS Optoelectronic device, comprising

- a first semiconductor layer (11) of a first doping type;

- a second semiconductor layer (12) of a second doping type;

- an active region (13) arranged between the first and the second semiconductor layers (11, 12) ;

- a light emission surface (Ila) formed by a surface of the first semiconductor layer (11) opposite the second semiconductor layer (12) ;

- a contact layer (20) arranged on the second semiconductor layer

(12) opposite the active region (13) ;

- a passivation layer (30) deposited on sidewalls (50) of the second semiconductor layer (12) , sidewalls (50) of the active region

(13) and at least partially on sidewalls (50) of the first semiconductor layer (11) , wherein the passivation layer (30, 31, 32, 33) comprises MgF2 and wherein the first and second semiconductor layer (12) comprise a phosphide material system. Optoelectronic device according to claim 1, wherein the first doping type is n-doped, and the second doping type is p-doped. Optoelectronic device according to any of the preceding claims, wherein the passivation layer extends partially onto the surface of the second semiconductor layer (12) opposite the active region and surrounding the contact layer (20) . Optoelectronic device according to claim 3, wherein the passivation layer comprises a larger thickness on the surface of the second semiconductor layer (12) than on the sidewalls (50) of the second semiconductor layer (12) . Optoelectronic device according to any of the preceding claims, wherein the thickness of the passivation layer (30) on the side- walls (50) is in the range of 30 nm to 500 nm and in particular between 50 nm and 300 nm and more particularly between 50 nm and 150 nm.

6. Optoelectronic device according to any of the preceding claims, further comprising a reflective metal layer (23) on the contact layer (20) and optionally on the passivation layer (31) surrounding the contact layer (20) .

7. Optoelectronic device according to any of the preceding claims, wherein the sidewalls (50) are inclined opening towards the light emission surface.

8. Optoelectronic device according to any of the preceding claims, further comprising a layer between the sidewalls and the passivation layer, the layer comprising one of A12O3, HfOx and SiO2 with a thickness of less than 10 nm and particularly less than 5 nm.

9. Optoelectronic device according to any of the preceding claims, wherein the first and second semiconductor layer comprises at least one of:

AlGaP,

InGaP; and InAlGaP.

10. Method processing an optoelectronic device comprising the steps of

- providing a semiconductor stack (10) on a growth substrate (14) comprising :

- a first semiconductor layer (11) of a first doping type arranged on the growth substrate (14) ;

- a second semiconductor layer (12) on the first semiconductor layer ( 11 ) ;

- an active region (13) between the first and second semiconductor layer (11, 12) ;

- providing a contact layer (20) on the second semiconductor layer - providing a mesa structure within the semiconductor stack extending through the second semiconductor layer (12) , the active region and at least partially through the first semiconductor layer (11) ;

- depositing a passivation layer (32, 30, 31, 33) in the mesa structure and on the surface of the contact layer and/or the second semiconductor layer, the passivation layer comprising MgF2.

- removing the passivation layer (33) on the surface of the second semiconductor layer (12) until the contact layer is exposed. Method according to claim 10, wherein providing a semiconductor stack comprises the steps of performing a quantum well intermixing (130) in areas of the active region (13) adjacent to the subsequent mesa structure (5) . Method according to any of claims 10 to 11, wherein the steps of providing a mesa structure comprises the steps of

- depositing a structured photoresist layer (3, 3' ) on the contact layer ( 20 ) ;

- removing portions of the structured photoresist layer (3, 3' ) to expose surface portions of the contact layer (20) ;

- etching the exposed surface portions; and

- etching portions of the semiconductor layer (10) stack beneath the etched surface portions . Method according to claim 12, further comprising:

- removing the photoresist;

- depositing a structured photoresist layer (4, 4' ) on the contact layer and into the mesa structure (5) ; and

- removing portions of the structured photoresist layer (4, 4' ) as to expose surface portions of the contact layer (20) ;

- removing the exposed surface portions to expose top surface portions of the second semiconductor layer (12) . Method according to any of claims 10 to 13, wherein the steps of providing a mesa structure comprises :

- conducting a first etching steps to expose sidewalls of the active region (13) ; and - conducting a subsequent second etching step, in particular through the first semiconductor layer; wherein a step of depositing a layer of A12O3 on the exposed sidewalls (50) of the active region (13) is optionally performed between the first and second etching step. Method according to claim 14, wherein depositing a layer of A12O3 also comprises

- etching the sidewalls (50) with KOH; and

- optionally wherein the layer of A12O3 is removed after the second etching step is conducted. Method according to any of claims 10 to 14, wherein removing the passivation layer comprises:

- chemical-mechanical polishing the passivation layer (33) until the contact layer (20) is reached. Method according to any of claims 10 to 16, wherein the contact layer (20) comprises a layer stack including a metal or highly doped semiconductor layer (21) and a transparent conductive oxide layer (22) , the transparent conductive layer (22) being the topmost layer . Method according to any of claims 10 to 17, wherein the passivation layer (32) on the bottom of mesa structure (5) is removed. Method according to any of claims 10 to 18, further comprising:

- re-bonding the semiconductor layer stack (10) ;

- removing the growth substrate to expose a surface of the first semiconductor layer (11) ;

- processing a surface of the first semiconductor layer (11) to form the light emission surface. Method according to any of claims 10 to 18, wherein the step of depositing a passivation layer (30, 31, 32, 33) comprises: - gas phase depositing MgF2 on the sidewalls (50) and the top surface, wherein MgF2 is grown faster on the top surfaces than on the sidewalls . 21. Method according to any of claims 10 to 18, wherein the first and second semiconductor layer (12) comprise at least one of: AlGaP, InGaP; and InAlGaP.