WO2023142573A1 - Backside illumination image sensor, manufacturing method therefor, and electronic device - Google Patents

Abstract

Provided in the present application are a backside illumination image sensor, a manufacturing method therefor and an electronic device, which relate to the field of sensors. By means of arranging a metal layer on a detection surface, the backside illumination image sensor enables the intermediate energy level caused by interface defects to be far away from the Fermi level, thereby reducing the dark current of a sensor, and enhancing the anti-radiation performance. The backside illumination image sensor comprises a substrate, and a metal wiring layer, a semiconductor layer and a metal layer which are sequentially arranged on the substrate. A pixel array is distributed in the semiconductor layer, and the surface, away from the substrate, of the semiconductor layer is a detection surface for the pixel array. The metal layer is arranged on the detection surface, and the work function of a metal material used by the metal layer is greater than that of a semiconductor material in the semiconductor layer.

Description

Back-illuminated image sensor, manufacturing method thereof, and electronic device

This application claims priority to a Chinese patent application filed with the China Patent Office on January 28, 2022, with application number 202210109230.6, and the title of the invention is "Back-illuminated image sensor and its manufacturing method, and electronic equipment", the entire contents of which are incorporated by reference incorporated in this application.

technical field

The present application relates to the field of sensors, in particular to a back-illuminated image sensor, a manufacturing method thereof, and electronic equipment.

Background technique

Backside illumination (BSI) image sensor can be used as a high-energy particle or photon detection device, and has a wide range of applications in medical imaging, nondestructive testing, electron microscopy, mass spectrometry, particle physics and other fields.

Referring to Fig. 1, in a traditional BSI sensor, the back surface B (i.e., the radiation incident surface and the detection surface) will be in the The electronic energy level is formed in the forbidden band at the surface, so that the intermediate energy level is introduced into the forbidden band, which becomes a channel for electronic transition, thereby generating a large dark current and affecting the performance of the sensor.

Therefore, as shown in FIG. 1 , in the related art, a dielectric stack 10 (SiO ₂ /Al ₂ O ₃ /SiO ₂ ) is grown on the back surface of the BSI image sensor as a passivation layer to reduce dark current. However, in the process of high-energy particle detection, the dielectric layer will cause the total ionizing dose (TID) effect, so that holes accumulate in the dielectric layer near the interface near the interface, and the interface state density increases, resulting in the dark current increasing with the irradiation dose. The increase will make the sensor's anti-radiation performance decrease or even fail.

Contents of the invention

The present application provides a back-illuminated image sensor, a manufacturing method thereof, and an electronic device, which can reduce dark current and enhance radiation resistance.

The present application provides a back-illuminated image sensor, which includes a substrate and a metal wiring layer, a semiconductor layer, and a metal layer sequentially disposed on the substrate. A pixel array is distributed in the semiconductor layer, the surface of the semiconductor layer away from the substrate is the detection surface of the pixel array, and the metal layer is arranged on the detection surface; the radiation signal from the side of the metal layer away from the substrate is detected through the pixel array. The work function of the metal material used in the metal layer is greater than the work function of the semiconductor material in the semiconductor layer. In this case, field-effect passivation is formed based on the difference in work function between the metal layer and the semiconductor layer, and the surface potential of the detection surface is regulated, which can make the intermediate energy level caused by interface defects far away from the Fermi level, reduce (or suppress) ) reduces the dark current, and at the same time weakens (or even eliminates) the total ionizing dose effect (TID), that is, improves the anti-irradiation performance of the sensor.

In some possible implementation manners, the metal layer and the semiconductor layer are components of a metal semiconductor (MS) structure. In this case, the intermediate energy level caused by interface defects can be kept away from the Fermi level through the metal layer, which reduces (or suppresses) the dark current, and at the same time weakens (or even eliminates) the total ionization dose effect, that is, improves the sensor’s sensitivity. Radiation resistance.

In some possible implementation manners, when the metal layer and the semiconductor layer are components of the MS structure, the metal layer is deposited on the detection surface; in this case, the semiconductor layer and the metal layer constitute the MS structure.

In some possible implementation manners, the metal layer and the semiconductor layer are components of a metal-insulator-semiconductor (metal insulator semiconductor, MIS) structure. In this case, for some semiconductor layers with high defect density on the surface, by setting a dielectric layer between the metal layer and the semiconductor layer, the interface state density can be reduced through the dielectric layer, and the pinning effect can be removed at the same time, so that the metal layer can be ensured. Regulatory effect on the surface energy band of the semiconductor layer.

In some possible implementations, when the metal layer and the semiconductor layer are components of the MIS structure, the back-illuminated image sensor further includes a dielectric layer; the dielectric layer is deposited on the detection surface, and the metal layer is deposited on the dielectric layer away from On the surface of the semiconductor layer; the semiconductor layer, the dielectric layer, and the metal layer constitute the MIS structure.

In some possible implementation manners, the thickness of the dielectric layer is 1 nm˜5 nm. Wherein, by setting the thickness of the dielectric layer to be greater than or equal to 1 nm, the continuity of the film layer is ensured and the interface state density is reduced. By setting the thickness of the dielectric layer to be less than or equal to 5nm, it is ensured that the dielectric layer will not significantly affect the radiation resistance performance of the sensor.

In some possible implementation manners, the dielectric layer is at least one of SiO ₂ , Al ₂ O ₃ , HfO ₂ , Si ₃ N ₄ , Ta ₂ O ₅ , ZrO ₂ , and TiO ₂ .

In some possible implementation manners, the metal material used for the metal layer is at least one of Pt, Pd, Au, Ni, Se, Ir, Rh, Be, and TiN.

In some possible implementation manners, the thickness of the metal layer is 5nm-20nm. Wherein, by setting the thickness of the metal layer to be greater than or equal to 5 nm, the continuity of the film layer and better conductivity are ensured. By setting the thickness of the metal layer to be less than or equal to 20 nm, excessive energy loss due to excessive thickness of the metal layer can be avoided when high-energy particles/photons pass through the metal layer and reach the semiconductor layer.

In some possible implementations, the metal layer is coupled to the ground to prevent charges from accumulating on the metal layer, causing voltage drift to form a local electric field, affecting the performance of the sensor, thereby ensuring the normal operation of the sensor.

In some possible implementation manners, the semiconductor layer is made of high-resistance silicon with a resistivity greater than 100Ω·cm.

An embodiment of the present application also provides an electronic device, including a circuit board and a back-illuminated image sensor as provided in any one of the foregoing possible implementation manners; the circuit board is electrically connected to the back-illuminated image sensor.

The embodiment of the present application also provides a method for fabricating a back-illuminated image sensor, which may include: providing a substrate, and fabricating a metal wiring layer and a semiconductor layer on the substrate; wherein, the metal wiring layer is located between the substrate and the semiconductor layer. Between layers, and a pixel array is fabricated in the semiconductor layer, and the surface of the semiconductor layer away from the substrate is the detection surface of the pixel array. A metal layer is formed on the surface of the semiconductor layer; the work function of the metal material used in the metal layer is greater than the work function of the semiconductor material in the semiconductor layer.

In some possible implementations, the formation of the metal layer on the detection surface of the semiconductor layer may include: using at least one metal material among Pt, Pd, Au, Ni, Se, Ir, Rh, Be, and TiN, The detection surface of the layer forms a metal layer with a thickness of 5 nm to 20 nm.

The embodiment of the present application also provides a method for fabricating a back-illuminated image sensor, which may include: providing a substrate, and fabricating a metal wiring layer on the substrate; fabricating a semiconductor layer on the metal wiring layer, and A pixel array is fabricated in the semiconductor layer; wherein, the surface of the semiconductor layer away from the substrate is the detection surface of the pixel array. A dielectric layer and a metal layer are sequentially formed on the detection surface of the semiconductor layer; wherein, the work function of the metal material used in the metal layer is greater than the work function of the semiconductor material in the semiconductor layer.

In some possible implementations, the above-mentioned sequential formation of the dielectric layer and the metal layer on the detection surface of the semiconductor layer may include: using SiO ₂ , Al ₂ O ₃ , HfO ₂ , Si ₃ N ₄ , Ta ₂ O ₅ , ZrO ₂ , TiO ₂ at least one dielectric material, forming a dielectric layer with a thickness of 1nm to 5nm on the detection surface of the semiconductor layer; using at least one of Pt, Pd, Au, Ni, Se, Ir, Rh, Be, TiN As for the metal material, a metal layer with a thickness of 5nm-20nm is formed on the surface of the medium layer.

Description of drawings

FIG. 1 is a schematic structural diagram of an image sensor provided in the related art of the present application;

FIG. 2 is a schematic structural diagram of an image sensor provided by an embodiment of the present application;

Figure 3 is a schematic diagram of energy bands before and after metal and semiconductor contact;

FIG. 4 is a schematic structural diagram of an image sensor provided in an embodiment of the present application;

Figure 5 is a schematic diagram of the pinning effect and the energy band of the MIS structure;

FIG. 6 is a flow chart of a manufacturing method of an image sensor provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of a manufacturing process of an image sensor provided in an embodiment of the present application;

FIG. 8 is a schematic diagram of a manufacturing process of an image sensor provided in an embodiment of the present application;

FIG. 9 is a flow chart of a manufacturing method of an image sensor provided in an embodiment of the present application;

FIG. 10 is a schematic diagram of a manufacturing process of an image sensor provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application , but not all examples. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The terms "first" and "second" in the description, embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be interpreted as indicating or implying relative importance, nor can they be interpreted as indicating or imply order. "And/or" is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, "A and/or B" can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item (piece) of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c ", where a, b, c can be single or multiple. "Installation", "connection" and "connection" should be understood in a broad sense, for example, it can be fixed connection, detachable connection, or integral connection; it can be direct connection, indirect connection through an intermediary, or is the connection between two components. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, of a sequence of steps or elements. A method, system, product or device is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to the process, method, product or device. "Up", "Down", "Left", "Right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts, and they are used for description and clarification relative to , which may change accordingly according to changes in the orientation in which components are placed in the drawings.

An embodiment of the present application provides an electronic device, which includes a printed circuit board (printed circuit board, PCB; also referred to as a circuit board) and an image sensor electrically connected to the printed circuit board.

Certainly, other devices may also be provided in the electronic device, which is not specifically limited in the present application. Schematically, in some embodiments, the electronic device may further include a controller, a processor, etc. that are electrically connected to the image sensor, so as to control related signals (such as input and output signals, etc.) of the image sensor through the controller, And through the processor, related signals (such as image signals, etc.) are calculated and processed.

The present application does not limit the application detection range and field of the above-mentioned image sensor. Schematically, the image sensor can be used for detection of high-energy particles (such as high-energy electrons, α particles, heavy ions, etc.), photons (such as X-rays, γ-rays, etc.) and the like. The image sensor can be applied to fields such as medical X-ray image detection, electron detectors in electron microscopes, radiation detectors in high-energy physics research, and the like.

The image sensor used in the electronic device of the embodiment of the present application adjusts the surface potential of the detection surface (i.e., the semiconductor surface) by arranging a metal layer with a high work function on the detection surface of the image sensor to form a field passivation effect, so that the interface of the semiconductor surface states and other defect states are far away from the Fermi level, thereby reducing the dark current of the sensor and improving the irradiation performance of the sensor.

Taking the detection of high-energy particles by a back-illuminated image sensor (hereinafter referred to as a sensor) as an example, the specific arrangement structure of the sensor provided in the embodiment of the present application will be described below.

First, a brief description of back-illuminated image sensors and related terms is given as follows:

Back-illuminated (BSI) image sensor: It is a sensor structure in which the metal wiring layer (that is, the circuit wiring layer) is located below the pixel area, and the radiation is directly incident on the pixel area.

Radiation resistance: It is the ability of the sensor to maintain stable device performance under the irradiation of high-energy particles. It is an important index in high-energy detection and directly affects the performance and service life of the device.

Total ionizing dose effect (total ionizing dose, TID): a large number of radiation particles (or photons) enter the interior of the semiconductor device material, and ionize with the electrons outside the nucleus of the material to generate additional charges. These charges accumulate on the oxide layer in the device, Or the interface state is induced at the semiconductor/insulating layer interface, leading to the gradual degradation of device performance, and even the eventual loss of the phenomenon.

FIG. 2 is a schematic structural diagram of a back-illuminated image sensor provided by an embodiment of the present application. As shown in FIG. 2, the sensor includes a substrate 1 and a metal wiring layer 2 and a semiconductor layer 3 sequentially arranged on the substrate 1, that is, the metal wiring layer 2 is located between the substrate 1 and the semiconductor layer 3. The wiring layer 2 transmits relevant signals in the sensor.

A pixel array formed by a plurality of pixel units P is distributed in the above-mentioned semiconductor layer 3, and the surface of the semiconductor layer 3 away from the substrate 1 is used as the detection surface S (that is, the radiation incident surface) of the pixel array, so that the pixel array can The irradiation signal from above the semiconductor layer 3 (that is, the side away from the substrate) is converted into an electrical signal to realize image detection.

Schematically, in the above pixel array, a partition wall a may be formed between two adjacent pixel units P for isolation by means of doping or filling. The pixel unit P may be a photodiode structure obtained by N-type doping and P-type doping. The present application does not limit the specific arrangement forms of the pixel unit P and the partition wall a.

Due to the existence of interface states and other defects on the semiconductor surface (that is, the detection surface S), the intermediate energy level will be introduced into the forbidden band, which will become a channel for electronic transitions, resulting in a large dark current and affecting the performance of the sensor. In related technologies, in order to reduce the dark current, a dielectric stack is grown on the surface of the semiconductor (that is, the detection surface S) (refer to Figure 1). On the one hand, the interface state density is reduced through chemical passivation; on the other hand, the field passivation The electron blocking layer is formed by changing the potential of the semiconductor surface through the fixed charge in the dielectric layer, thereby reducing the probability of electrons being captured and released by the intermediate energy level; thereby achieving the purpose of reducing the dark current.

However, due to the non-conductive properties of the dielectric layer itself, the radiation resistance of the semiconductor surface is poor. Especially in the process of high-energy particle detection, the ionization of high-energy particles in the dielectric layer produces a large number of electron-hole pairs. The mobility of electrons in the dielectric layer is much greater than that of holes. Electrons can move in the dielectric layer, while holes Holes are then trapped by the traps, resulting in a total ionizing dose effect (TID). Eventually, holes accumulate near the interface of the dielectric layer, and the interface state density increases, which makes the dark current increase with the increase of the radiation dose, resulting in the decrease of the radiation resistance of the sensor or even failure.

In contrast, as shown in FIG. 2, in the sensor provided by the embodiment of the present application, a metal layer 41 is deposited and formed on the detection surface S of the semiconductor layer 3, that is, the metal layer 41 covers the detection surface S; in this case Next, the irradiation signal from above the metal layer 41 (that is, the side away from the substrate) passes through the metal layer 41 and enters the detection surface S, and is converted into an electrical signal by the pixel array. The electrical signal can pass through the metal wiring layer 2. Lines are transmitted to a processor coupled with the sensor for processing to obtain corresponding image information.

In the above sensor, the metal layer 41 and the semiconductor layer 3 form a metal-semiconductor (MS) structure, and the work function of the metal material used in the metal layer 41 is greater than that of the semiconductor material in the semiconductor layer 3 . In this way, field-effect passivation is formed based on the difference in work function between the metal layer 41 and the semiconductor layer 3, and the surface potential of the detection surface S is regulated, so that the intermediate energy level caused by interface defects can be kept away from the Fermi level, reducing ( Or suppress) the dark current, and at the same time weaken (or even eliminate) the total ionizing dose effect (TID), that is, improve the anti-irradiation performance of the sensor.

The principle of reducing the dark current and weakening the effect of the total ionizing dose through the arrangement of the metal layer 41 will be further described below.

(a) in FIG. 3 is the respective energy band diagrams of metals and semiconductors, and (b) in FIG. 3 is the energy band diagrams of metal-semiconductor structures. Those skilled in the art should know that the work function of a material characterizes the energy required for an electron located at the Fermi level of the material to move to the vacuum level. For different materials, since the vacuum energy level is the same, the greater the work function of a material, the smaller the Fermi level of the material. Referring to Figure 3 (a), among metals and semiconductors, the work function (φ _m ) of the metal is greater than the work function (φ _s ) of the semiconductor, and correspondingly, the Fermi level ( _EF ) of the semiconductor is higher than that of the metal The Fermi level (E _F ). In this case, as shown in (b) in Figure 3, using the MS structure formed when the metal and the semiconductor are in contact, the field effect passivation is formed through the energy band regulation effect of the metal on the semiconductor, and electrons are transferred from the semiconductor to the metal, making the metal The side is negatively charged, the semiconductor side is positively charged, and the potential on the semiconductor side is pulled up until the Fermi levels on both sides are at the same level, reaching an equilibrium state. At this time, due to the distribution of charges at the semiconductor interface, a surface electric field is formed, and the surface energy band bends upward, making the interface trap energy level away from the Fermi level, thereby depleting the defect state electrons at the semiconductor interface, thereby reducing the dark current.

Compared with the use of fixed charges in the dielectric layer to form surface field-effect passivation in the related art, the embodiment of the present application utilizes the energy band regulation effect of metals on semiconductors to form field-effect passivation, thus avoiding the problem caused by the dielectric layer. The total ionizing dose effect (TID), thereby improving the radiation resistance performance.

It should be noted here that FIG. 2 only schematically illustrates the MS structure formed by the metal layer 41 and the semiconductor layer 3 as an example, but the present application is not limited thereto. In some possible implementation manners, the MS structure can be provided with other film layers according to actual needs, such as other function adjustment film layers.

The application does not limit the metal material used in the metal layer 41 , as long as the work function of the metal material used in the metal layer 41 is greater than the work function of the semiconductor material in the semiconductor layer 3 . Of course, the greater the work function difference between the metal layer 41 and the semiconductor layer 3, the greater the surface potential formed on the semiconductor surface (ie, the detection surface S), which is more conducive to the reduction of dark current.

Schematically, in some possible implementation manners, the metal material used for the metal layer 41 may be at least one of Pt, Pd, Au, Ni, Se, Ir, Rh, Be, TiN, but is not limited thereto.

It should be understood here that, from the perspective of energy band theory, the metal material used in the metal layer 41 of the present application refers to a metal whose energy band is in a half-full state, the Fermi level is located in the band, and a material with metal properties . For example, for the aforementioned TiN, since the N atoms in the TiN crystal form vacancies or interstitial atoms, the electronic conduction band is half-full, so TiN behaves as a metallic material.

In addition, the present application does not limit the specific thickness of the metal layer 41 , and the thickness of the metal layer 41 can be set according to actual needs. Schematically, the design of the thickness of the metal layer 41 should ensure the continuity of the film layer, better electrical conductivity, and at the same time not cause excessive energy loss of high-energy particles/photons. For example, in some possible implementation manners, the thickness of the metal layer 41 may be set to be 5 nm˜20 nm. By setting the thickness of the metal layer 41 to be greater than or equal to 5nm, thereby ensuring the continuity and better conductivity of the film layer; Energetic particles/photons lose too much energy passing through the metal layer to the semiconductor layer. Schematically, in some embodiments, the thickness of the metal layer 41 can be set to be 5 nm, 10 nm, 15 nm, or 20 nm.

In addition, for some semiconductor layers 3 with relatively high defect density on the surface, such as the semiconductor layer 3 using silicon material, a pinning effect may occur on the semiconductor surface, so that the Fermi level of the semiconductor surface is limited to a specific position, and then As a result, the energy band of the semiconductor surface cannot change with the work function of the metal material, that is, the metal layer 41 may not be able to control the energy band of the semiconductor surface (ie, the detection surface S).

Based on this, compared to the metal layer 41 directly covering the surface of the semiconductor layer 3 (that is, the detection surface S) in FIG. As shown, the surface (S) of the semiconductor layer 3 can be covered with a thinner dielectric layer 42, and the metal layer 41 is covered on the surface of the dielectric layer 42; that is to say, the dielectric layer 42 is deposited on the detection surface S first, and then The metal layer 41 is deposited on the surface of the dielectric layer 42 . In this case, the metal layer 41, the dielectric layer 42, and the semiconductor layer 3 form a metal-insulator-semiconductor (metal insulator semiconductor, MIS) structure. In this way, the interface state density can be reduced through the dielectric layer 42, and the pinning effect can be eliminated at the same time. , so as to ensure the regulating effect of the metal layer 41 on the surface energy band of the semiconductor layer 3 .

It should be noted here that FIG. 4 only schematically illustrates the MIS structure formed by the metal layer 41 , the dielectric layer 42 and the semiconductor layer 3 as an example, but the present application is not limited thereto. In some possible implementation manners, the MIS structure may be provided with other film layers according to actual needs, such as other function adjustment film layers.

Figure 5 (a) is a schematic diagram of the energy band of the MS structure under the pinning effect, and Figure 5 (b) is a schematic diagram of the energy band of the MIS structure. Comparing (a) and (b) in Figure 5, it can be seen that in the absence of a dielectric layer 42, due to the existence of the pinning effect, the metal cannot regulate the energy band of the semiconductor; and in the case of a dielectric layer 42 Under the circumstances, the energy band of the semiconductor can be regulated by the metal, so that the energy band of the semiconductor surface is bent upward, thereby suppressing the interface state and other defect states, and reducing the dark current.

It should be noted here that, in the above-mentioned sensor using the MIS structure, although the dielectric layer 42 is provided on the surface of the semiconductor layer 3, the thickness of the dielectric layer 42 is usually relatively thin, and the radiation effect causes charge accumulation in the dielectric layer. Rarely, in this case, the arrangement of the dielectric layer 42 does not have a significant impact on the radiation resistance of the sensor.

Schematically, the thickness design of the dielectric layer 42 should be based on the principle of reducing the interface state density without affecting the radiation resistance performance. The present application does not limit the specific thickness of the dielectric layer 42 , and the thickness of the dielectric layer 42 can be set according to actual needs. For example, in some possible implementation manners, the thickness of the dielectric layer 42 may be set to be 1 nm˜5 nm. Wherein, by setting the thickness of the dielectric layer 42 to be greater than or equal to 1 nm, the continuity of the film layer is ensured and the interface state density is reduced. By setting the thickness of the dielectric layer 42 to be less than or equal to 5 nm, it is ensured that the dielectric layer 42 will not significantly affect the radiation resistance of the sensor. Schematically, in some embodiments, the thickness of the dielectric layer 42 can be set to 1 nm, 2 nm, 3 nm, 4 nm, 5 nm.

In addition, the present application does not limit the dielectric material used for the dielectric layer 42 . Schematically, in some possible implementation manners, the dielectric layer 42 may use at least one of SiO ₂ , Al ₂ O ₃ , HfO ₂ , Si ₃ N ₄ , Ta ₂ O ₅ , ZrO ₂ , and TiO ₂ .

In addition, in order to prevent charges from accumulating on the metal layer 41, causing voltage drift to form a local electric field and affecting the performance of the sensor, in some possible implementations, the metal layer 41 can be coupled to ground to ensure the normal operation of the sensor.

The present application does not limit the semiconductor material used for the semiconductor layer 3 in the sensor. For example, in some possible implementation manners, the semiconductor layer 3 may use silicon, germanium, or III-V group semiconductor materials.

Schematically, silicon is used as the semiconductor layer 3 as an example, that is, the pixel array adopts a silicon-based pixel array. In some possible implementation manners, the semiconductor layer 3 can be made of high-resistance silicon material. For example, the resistivity of the high resistance silicon material may be greater than 100Ω·cm.

In practice, the material and thickness of each interlayer structure in the sensor can be selected and set according to the selected sensor structure (such as MIS structure or MS structure), which is not limited in this application.

Schematically, taking the sensor with the above MIS structure as an example, in some embodiments, the metal layer 41 can be made of TiN with a thickness of about 10 nm; the dielectric layer 42 can be made of SiO ₂ with a thickness of about 2 nm; the semiconductor layer 3 can be made of High resistance silicon material. The work function of TiN is about 5eV. Based on the modulation of the metal work function of TiN, a surface potential of about -0.4V can be generated on the side of the semiconductor layer 3 (Si), thereby reducing the dark current.

The embodiment of the present application also provides a manufacturing method of the sensor shown in the foregoing Figure 2, as shown in Figure 6, the manufacturing method may include:

Step 11, referring to FIG. 7 (a), providing a substrate, and fabricating a metal wiring layer 2 and a semiconductor layer 3 on the substrate 1; wherein the metal wiring layer 2 is located between the substrate 1 and the semiconductor layer 3, In addition, a pixel array (ie, a plurality of pixel units P) is formed in the semiconductor layer 3 , and the surface of the semiconductor layer 3 away from the substrate 1 is the detection surface S of the pixel array.

It should be noted that the substrate 1 as a supporting structure of the sensor may be a passive carrier, such as a Si substrate. The metal wiring layer 2 transmits relevant signals in the sensor.

Schematically, in some possible implementation manners, step 11 may include: referring to FIG. ) a plurality of pixel units P and a partition wall between two adjacent pixel units P; then, referring to FIG. 8 (b), a metal wiring layer 2 is formed on the surface of the semiconductor layer 3; next, referring As shown in (c) in FIG. 8, the first substrate 01 formed with the semiconductor layer 3 and the metal wiring layer 2 is reversely attached to the second substrate (i.e. 1), that is, the metal wiring layer 2 and the second substrate (1) Bonding; then, the first substrate 01 is thinned to expose the pixel unit P (that is, the detection surface S).

Of course, in other possible ways, the metal wiring layer 2 and the semiconductor layer 3 can also be fabricated directly on the substrate 1 through step 11. For details, reference can be made to related fabrications, and details will not be repeated here.

Step 12, referring to Fig. 7 (b), form a metal layer 41 on the detection surface S of the semiconductor layer 3; wherein, the work function of the metal material used in the metal layer 41 is greater than the work function of the semiconductor material in the semiconductor layer 3 .

Schematically, in some possible implementation manners, the above step 12 may include: using at least one metal material among Pt, Pd, Au, Ni, Se, Ir, Rh, Be, TiN, on the detection surface of the semiconductor layer 3 S depositing a metal layer 41 with a thickness of 5nm-20nm.

Certainly, before forming the metal layer 41 through step 12, it is usually necessary to process the detection surface S of the semiconductor layer 3, and remove the natural oxide layer if there is one. Schematically, the surface treatment of the semiconductor layer 3 may be performed by means of pickling, plasma bombardment, etc., so as to clean the detection surface S of the semiconductor layer 3 .

The embodiment of the present application also provides a method of manufacturing the sensor shown in the aforementioned Figure 4, as shown in Figure 9, the manufacturing method may include:

Step 21, referring to FIG. 10 (a), provide a substrate, and fabricate a metal wiring layer 2 and a semiconductor layer 3 on the substrate 1; wherein, the metal wiring layer 2 is located between the substrate 1 and the semiconductor layer 3, In addition, a pixel array (ie, a plurality of pixel units P) is formed in the semiconductor layer 3 , and the surface of the semiconductor layer 3 away from the substrate 1 is the detection surface S of the pixel array.

The above step 21 is basically the same as the above step 11, for details, please refer to the relevant description of the above step 11, which will not be repeated here.

Step 22, with reference to (b) and (c) shown in Figure 10, a dielectric layer 42 and a metal layer 41 are sequentially formed on the detection surface of the semiconductor layer 3; wherein, the work function of the metal material used in the metal layer 41 is greater than that of the semiconductor layer 3 Work function of semiconductor materials.

Schematically, in some possible implementation manners, the above step 22 may include: using at least one medium of SiO ₂ , Al ₂ O ₃ , HfO ₂ , Si ₃ N ₄ , Ta ₂ O ₅ , ZrO ₂ , and TiO ₂ Material, form a dielectric layer 42 with a thickness of 1nm to 5nm on the detection surface of the semiconductor layer 3; The metal layer 41 with a thickness of 5nm-20nm is deposited on the surface of the layer 42 .

The present application does not limit the manner of forming the dielectric layer 42 . For example, in some possible implementation manners, the dielectric layer 42 may be deposited on the detection surface of the semiconductor layer (such as Si) by means of decoupled plasma oxide (DPO). For another example, in some possible implementation manners, the dielectric layer 42 may be formed on the detection surface of the semiconductor layer (such as Si) by means of atomic layer deposition (atomic layer deposition, ALD).

Using the above manufacturing method, the MS structure is formed by making a metal layer on the surface of the semiconductor layer, or the MIS structure is formed by sequentially making a dielectric layer and a metal layer on the surface of the semiconductor layer; based on the larger work function of the metal layer and the smaller work function of the semiconductor layer The difference between the formation of field effect passivation, and the regulation of the surface potential of the semiconductor layer can make the intermediate energy level caused by the interface defect far away from the Fermi level, reduce (or suppress) the dark current, and at the same time weaken (or even eliminate) the total ionization Dose effect (TID), that is, the radiation resistance performance of the sensor is improved.

For other relevant content in the above-mentioned embodiment of the manufacturing method, such as the setting of the thickness of the metal layer and the dielectric layer, etc., reference may be made to the corresponding part in the foregoing sensor structure embodiment, and details will not be repeated here. As for the relevant structures in the foregoing sensor structure embodiments, they can be produced by referring to the above-mentioned production method embodiments, or can be produced through appropriate adjustments in combination with related technologies, which is not limited in this application.

It should be noted that the above embodiments are schematically illustrated by taking the image sensor as an example of a back-illuminated image sensor. In other possible implementations, the image sensor may use a stacked sensor, combining the active logic chip and the sensor It is integrated, and the signal of the sensor is read, processed, stored, etc. through the active logic chip.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (14)

1. A back-illuminated image sensor, characterized in that it comprises:

   Substrate;

   a metal wiring layer disposed on the substrate;

   a semiconductor layer disposed on the metal wiring layer, a pixel array is distributed in the semiconductor layer, and the surface of the semiconductor away from the substrate is the detection surface of the pixel array;

   A metal layer is arranged on the detection surface, and the work function of the metal material used in the metal layer is greater than the work function of the semiconductor material used in the semiconductor layer.
2. The back-illuminated image sensor according to claim 1, wherein,

   The metal layer and the semiconductor layer are components of a metal-semiconductor MS structure or a metal-insulator-semiconductor MIS structure.
3. The back-illuminated image sensor according to claim 2, wherein when the metal layer and the semiconductor layer are components of a metal-semiconductor MS structure, the metal layer is deposited on the detection surface superior.
4. The back-illuminated image sensor according to claim 2, wherein,

   In the case where the metal layer and the semiconductor layer are components of a metal-insulator-semiconductor MIS structure, the back-illuminated image sensor further includes: a dielectric layer;

   The dielectric layer is deposited on the detection surface, and the metal layer is deposited on the surface of the dielectric layer away from the semiconductor layer.
5. The back-illuminated image sensor according to claim 4, wherein,

   The thickness of the medium layer is 1nm-5nm.
6. The back-illuminated image sensor according to any one of claims 1-5, characterized in that,

   The metal material used for the metal layer is at least one of Pt, Pd, Au, Ni, Se, Ir, Rh, Be, and TiN.
7. The back-illuminated image sensor according to any one of claims 4-6, characterized in that,

   The dielectric layer adopts at least one of SiO ₂ , Al ₂ O ₃ , HfO ₂ , Si ₃ N ₄ , Ta ₂ O ₅ , ZrO ₂ , and TiO ₂ .
8. The back-illuminated image sensor according to any one of claims 1-7, characterized in that,

   The thickness of the metal layer is 5nm-20nm.
9. The back-illuminated image sensor according to any one of claims 1-8, characterized in that,

   The metal layer is coupled to ground.
10. The back-illuminated image sensor according to any one of claims 1-9, characterized in that,

    The semiconductor layer is made of high-resistance silicon with a resistivity greater than 100Ω·cm.
11. An electronic device, characterized in that it comprises:

    A circuit board and the back-illuminated image sensor according to any one of claims 1-10;

    The circuit board is electrically connected to the back-illuminated image sensor.
12. A method for manufacturing a back-illuminated image sensor, comprising:

    providing a substrate, and fabricating a metal wiring layer and a semiconductor layer on the substrate; wherein the metal wiring layer is located between the substrate and the semiconductor layer, and a pixel array is fabricated in the semiconductor layer, The surface of the semiconductor layer away from the substrate is the detection surface of the pixel array;

    A metal layer is formed on the detection surface of the semiconductor layer; or, a dielectric layer and a metal layer are sequentially formed on the detection surface of the semiconductor layer; wherein, the work function of the metal material used in the metal layer is greater than The work function of the semiconductor material in the semiconductor layer.
13. The method for fabricating a back-illuminated image sensor according to claim 12, wherein:

    The forming a metal layer on the detection surface of the semiconductor layer includes:

    At least one metal material among Pt, Pd, Au, Ni, Se, Ir, Rh, Be, TiN is used to form a metal layer with a thickness of 5nm-20nm on the detection surface of the semiconductor layer.
14. The method for fabricating a back-illuminated image sensor according to claim 12, wherein:

    The sequentially forming a dielectric layer and a metal layer on the detection surface of the semiconductor layer includes:

    Using at least one dielectric material among SiO ₂ , Al ₂ O ₃ , HfO ₂ , Si ₃ N ₄ , Ta ₂ O ₅ , ZrO ₂ , and TiO ₂ , form a layer with a thickness of 1 nm on the detection surface of the semiconductor layer. ~5nm dielectric layer;

    At least one metal material among Pt, Pd, Au, Ni, Se, Ir, Rh, Be and TiN is used to form a metal layer with a thickness of 5 nm to 20 nm on the surface of the dielectric layer.

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