WO2023141045A3 - Computing and displaying a predicted overlap shape in an ic design based on predicted manufacturing contours - Google Patents

Computing and displaying a predicted overlap shape in an ic design based on predicted manufacturing contours Download PDF

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Publication number
WO2023141045A3
WO2023141045A3 PCT/US2023/010630 US2023010630W WO2023141045A3 WO 2023141045 A3 WO2023141045 A3 WO 2023141045A3 US 2023010630 W US2023010630 W US 2023010630W WO 2023141045 A3 WO2023141045 A3 WO 2023141045A3
Authority
WO
WIPO (PCT)
Prior art keywords
predicted
contours
computing
displaying
design based
Prior art date
Application number
PCT/US2023/010630
Other languages
French (fr)
Other versions
WO2023141045A2 (en
Inventor
Donald Oriordan
Akira Fujimura
George JANAC
Original Assignee
D2S, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/992,899 external-priority patent/US20230205972A1/en
Priority claimed from US17/992,906 external-priority patent/US20230229844A1/en
Application filed by D2S, Inc. filed Critical D2S, Inc.
Publication of WO2023141045A2 publication Critical patent/WO2023141045A2/en
Publication of WO2023141045A3 publication Critical patent/WO2023141045A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.
PCT/US2023/010630 2022-01-19 2023-01-11 Computing and displaying a predicted overlap shape in an ic design based on predicted manufacturing contours WO2023141045A2 (en)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US202263300675P 2022-01-19 2022-01-19
US63/300,675 2022-01-19
US17/992,899 US20230205972A1 (en) 2020-10-22 2022-11-22 Computing and displaying a predicted overlap shape in an ic design based on predicted misalignment of metal layers
US17/992,907 2022-11-22
US17/992,899 2022-11-22
US17/992,906 US20230229844A1 (en) 2022-01-19 2022-11-22 Interactively presenting for minimum overlap shapes in an ic design
US17/992,897 US20230229840A1 (en) 2022-01-19 2022-11-22 Computing and displaying a predicted overlap shape in an ic design based on predicted manufacturing contours
US17/992,907 US20230229836A1 (en) 2022-01-19 2022-11-22 Generating and display an animation of a predicted overlap shape in an ic design
US17/992,906 2022-11-22
US17/992,897 2022-11-22

Publications (2)

Publication Number Publication Date
WO2023141045A2 WO2023141045A2 (en) 2023-07-27
WO2023141045A3 true WO2023141045A3 (en) 2023-09-14

Family

ID=87348919

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2023/010630 WO2023141045A2 (en) 2022-01-19 2023-01-11 Computing and displaying a predicted overlap shape in an ic design based on predicted manufacturing contours

Country Status (1)

Country Link
WO (1) WO2023141045A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200184137A1 (en) * 2017-06-22 2020-06-11 Semiconductor Energy Laboratory Co., Ltd. Layout design system and layout design method
US20210173996A1 (en) * 2016-11-18 2021-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method and layout of an integrated circuit
US20210279878A1 (en) * 2019-07-12 2021-09-09 SVXR, Inc. Methods and Systems for Printed Circuit Board Design Based on Automatic Corrections

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210173996A1 (en) * 2016-11-18 2021-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method and layout of an integrated circuit
US20200184137A1 (en) * 2017-06-22 2020-06-11 Semiconductor Energy Laboratory Co., Ltd. Layout design system and layout design method
US20210279878A1 (en) * 2019-07-12 2021-09-09 SVXR, Inc. Methods and Systems for Printed Circuit Board Design Based on Automatic Corrections

Also Published As

Publication number Publication date
WO2023141045A2 (en) 2023-07-27

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