WO2023138215A1 - 可编程数据平面在运行时的更新方法及装置 - Google Patents

可编程数据平面在运行时的更新方法及装置 Download PDF

Info

Publication number
WO2023138215A1
WO2023138215A1 PCT/CN2022/134290 CN2022134290W WO2023138215A1 WO 2023138215 A1 WO2023138215 A1 WO 2023138215A1 CN 2022134290 W CN2022134290 W CN 2022134290W WO 2023138215 A1 WO2023138215 A1 WO 2023138215A1
Authority
WO
WIPO (PCT)
Prior art keywords
pipeline
template
processor
flow table
template processor
Prior art date
Application number
PCT/CN2022/134290
Other languages
English (en)
French (fr)
Inventor
刘斌
冯勇
陈智康
Original Assignee
清华大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 清华大学 filed Critical 清华大学
Publication of WO2023138215A1 publication Critical patent/WO2023138215A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/656—Updates while running

Definitions

  • the present application relates to the technical field of computer networks, in particular to a method and device for updating a programmable data plane during operation.
  • SDN Software Defined Networking, software-defined network
  • programmable switches are gradually commercialized and occupy a mainstream position.
  • the core of programming is the programmable data plane.
  • the data plane is responsible for protocol analysis and reverse analysis, and data packet processing.
  • the external controller is responsible for issuing analysis rules and flow table matching rules. Programmability has brought significant changes to the relationship between equipment suppliers and network operators.
  • the programmable data plane is required to have runtime programmable capabilities, that is, the ability to update data plane functions, protocols, and add, delete, and modify flow tables during runtime without interrupting services.
  • This application provides an update method, device, electronic device and storage medium for a programmable data plane at runtime, so as to solve problems such as how to freely add, delete, and modify protocols, freely configure functions, create flow tables, reclaim flow tables, and modify flow table specifications at runtime.
  • the embodiment of the first aspect of the present application provides a method for updating a programmable data plane at runtime.
  • the programmable data plane includes a distributed on-demand parser, a template processor, a virtual pipeline, a decoupled resource pool, and a fast update controller.
  • the method includes the following steps: based on the distributed on-demand parser, the parsing graph is split into multiple parsing subgraphs, and each parsing subgraph is distributed to each corresponding physical stage in the pipeline.
  • the method further includes: putting the template processor into a preset low power consumption mode when the template processor is not inserted into the pipeline for execution.
  • the performing free configuration action includes: by separating primitives and parameters, each physical stage is a general skeleton composed of primitives, so that when the user configures, corresponding parameters are downloaded to the skeleton according to the added functions.
  • the method further includes: interconnecting the physical stage and the storage resource by using a static reconfigurable crossbar switch, so as to reconfigure the crossbar switch when the template processor or the flow table is updated.
  • the fast update controller suspends data packet processing before the template processor that needs to be updated, and when the template processor has no data packets, configure the template processor or delete the template processor from the pipeline. Deleting all empty-configured template processors down the pipeline, wherein, when deleting the empty-configured template processor, suspending the data packet processing before the empty-configured template processor, and deleting the empty-configured template processor from the pipeline by configuring a configurable crossbar when the data in the empty-configured template processor is empty.
  • the programmable data plane further includes a pipeline-by-pipeline update controller, further comprising: updating the pipelines in the data plane one by one based on the pipeline-by-pipeline update controller, when updating the configuration of any pipeline, pausing data packets to enter the arbitrary pipeline, when there is no data packet in the any pipeline, updating the arbitrary pipeline, and after the update is completed, the data packet normally enters the arbitrary pipeline, and selects the unupdated pipeline for update.
  • the embodiment of the second aspect of the present application provides an update device for a programmable data plane at runtime.
  • the programmable data plane includes a distributed on-demand parser, a template processor, a virtual pipeline, a decoupled resource pool, and a fast update controller, wherein the device includes: a parsing module for splitting a parsing graph into multiple parsing subgraphs based on the distributed on-demand parser, and distributing each parsing subgraph to each corresponding physical stage in the pipeline.
  • a processing module is used to adjust the order between any two processors through the configuration Internet according to the insertion instruction based on the template processor and the virtual pipeline, wherein any processor in all the template processors is used as the physical stage of the inlet pipeline or the physical stage of the outlet pipeline; the free configuration action is performed by configuring the parameters of the template processor; the storage module is used to separate and pool the flow table resources of each physical stage based on the decoupled resource pool.
  • the fast update module is used to suspend the data packet processing before the template processor that needs to be updated based on the fast update controller, and configure the template processor or delete the template processor from the pipeline when there is no data packet in the template processor.
  • a setting module configured to put the template processor into a preset low power consumption mode when the template processor is not inserted into the pipeline for execution.
  • processing module is further used for separating primitives and parameters to form a general skeleton composed of primitives for each physical stage, so that when the user configures, corresponding parameters are downloaded to the skeleton according to the added functions.
  • a crossbar switch module configured to use a static reconfigurable crossbar switch for interconnection between the physical stage and the storage resources before separating and pooling the flow table resources of each physical stage, so as to reconfigure the crossbar switch when the template processor or the flow table is updated.
  • the fast update module is further configured to: when configuring template processors, configure template processors that need to be updated sequentially down the pipeline, wherein, suspend the data packet processing before the first template processor that needs to be configured, and configure the template processor when there is no data packet in the template processor, and configure the template processors that need to be updated sequentially down the pipeline; after the configuration is updated, delete all template processors with empty configurations down the pipeline, wherein, when deleting the template processor with empty configuration, suspend the data packet processing before the template processor with empty configuration, And when the data in the empty-configured template processor is empty, the empty-configured template processor is deleted from the pipeline by configuring a configurable crossbar.
  • the programmable data plane further includes a pipeline-by-pipeline update controller, and further includes: a piece-by-piece update module, configured to update the pipelines in the data plane one by one based on the pipeline-by-pipeline update controller, when updating the configuration of any pipeline, suspend the data packet from entering the any pipeline, and when there is no data packet in the any pipeline, update the arbitrary pipeline, and after the update is completed, the data packet enters the arbitrary pipeline normally, and selects the unupdated pipeline for update.
  • a pipeline-by-pipeline update controller further includes: a piece-by-piece update module, configured to update the pipelines in the data plane one by one based on the pipeline-by-pipeline update controller, when updating the configuration of any pipeline, suspend the data packet from entering the any pipeline, and when there is no data packet in the any pipeline, update the arbitrary pipeline, and after the update is completed, the data packet enters the arbitrary pipeline normally, and selects the unupdated pipeline for update.
  • the embodiment of the third aspect of the present application provides an electronic device, including: a memory, a processor, and a computer program stored on the memory and operable on the processor, and the processor executes the program to implement the method for updating the programmable data plane at runtime as described in the above embodiments.
  • the embodiment of the fourth aspect of the present application provides a computer-readable storage medium, on which a computer program is stored, and the program is executed by a processor, so as to implement the method for updating the programmable data plane during operation as described in the above-mentioned embodiment.
  • Protocols can be added, deleted, and modified at runtime, which is beneficial for users to test or deploy new protocols, and obsolete or redundant protocols can be deleted at the same time; functional logic can be added, deleted, and modified at runtime.
  • network operators can add new user services without affecting other users, or directly delete the user's functions when a user's service expires; create flow tables, recycle flow tables, and modify flow table specifications at runtime to improve the utilization of storage resources in network devices.
  • problems such as how to freely add, delete, and modify protocols, freely configure functions, create flow tables, recycle flow tables, and modify flow table specifications at runtime are solved.
  • Fig. 1 is the RMT technical architecture diagram in the related art
  • FIG. 2 is a technical architecture diagram of dRMT in the related art
  • FIG. 3 is an overall architecture diagram of IPSA provided according to an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for updating a programmable data plane at runtime according to an embodiment of the present application
  • FIG. 5 is a schematic structural diagram of a distributed on-demand resolver provided according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a template processor provided according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a virtual pipeline provided according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a decoupled resource pool provided according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a runtime programming flow provided according to an embodiment of the present application.
  • FIG. 10 is an example diagram of an uninterrupted update provided according to an embodiment of the present application.
  • Fig. 11 is a schematic block diagram of an updating device for a programmable data plane at runtime according to an embodiment of the present application
  • Fig. 12 is a schematic structural diagram of an electronic device provided according to an embodiment of the present application.
  • RMT Reconfigurable Match Tables, reconfigurable matching table
  • P4 protocol-independent language
  • the programmable parser is specified by the user to parse the state transition diagram before running, and the parser parses the protocol and fields after the data packet arrives at the inbound port; the pipeline is composed of a series of serial physical stages, and each physical stage contains multiple MAUs (Match Action Units, matching execution units).
  • MAUs Machine Action Units, matching execution units.
  • Different configurations have different logical behaviors, so as to realize user-specific processing and forwarding functions; the programmable reverse parser reassembles the protocol into the data packet load according to the protocol sequence specified by the user.
  • network functions can be freely customized through the protocol-independent language P4 during design, but after compilation and deployment, the underlying configuration of programmable devices is determined, and reconfiguration requires pausing packet processing, recompiling programs, downloading, and replacing underlying configurations.
  • mainstream applications such as multi-tenant service updates, stateful application updates, and on-network computing hot-swapping, downtime configuration greatly affects service quality.
  • a Tofino switch with 64 100G ports needs 50ms downtime for updating, and will lose 37GiB of data at full speed, and it will take longer to re-download the flow table.
  • POF Protocol-Oblivious Forwarding, protocol-independent forwarding
  • POF uses a specific instruction set to adapt to the "offset + length" protocol abstraction, enhances the packet processing capability of the data plane, and uses simple instruction switching to achieve functional updates.
  • each function is a module, and the user can hot-swap the module through programming with the underlying instruction set to realize runtime reconfiguration.
  • POF is implemented on a software network processor, and its processing speed is far lower than that of an ASIC hardware switch, so it cannot be used on a large scale.
  • dRMT disaggregated Reconfigurable Match-Action Table decouples flow table resources from data packet processing logic resources, and the processor accesses the flow table resources in the memory cluster through the switching network, as shown in Figure 2.
  • dRMT uses multi-processors to process data packets in parallel, each processor contains a complete data packet processing program, and uses a scheduler to avoid memory access conflicts between different processors.
  • dRMT builds a flow table resource pool, which solves the problem that a physical stage in RMT cannot accommodate a large flow table, improves the programmability of the data plane, and supports more network applications; at the same time, dRMT's resource pooling method is conducive to realizing runtime reconfiguration, that is, creating flow tables, recycling flow tables, and modifying flow table specifications at runtime.
  • dRMT adopts the "run-to-completion" (Run-to-Completion, RTC) data packet processing mode, which essentially does not support runtime modification of protocols, functions, and flow tables.
  • RTC run-to-Completion
  • the embodiment of the present application proposes a method and device for implementing a runtime programmable switch chip and fast and uninterrupted update, which mainly solves the following three technical problems:
  • the programmable data plane includes a distributed on-demand parser, a template processor, a virtual pipeline, a decoupled resource pool, and a fast update controller.
  • the fast update controller is responsible for controlling the update of the template processor and the update of the overall pipeline.
  • IPSA In-situ Programmable Switch Architecture
  • step S101 based on the distributed on-demand parser, the parsing graph is split into multiple parsing subgraphs, and each parsing subgraph is distributed to each corresponding physical stage in the pipeline, wherein the parsing subgraph of each physical stage is used to indicate the local parsing process, and at runtime, the protocol specified by the user is parsed out, and the parsing subgraph is configured to perform adding protocol actions, deleting protocol actions and/or modifying protocol actions at the target physical stage.
  • the parsing subgraph of a specific template processor can be configured to perform adding protocol actions, deleting protocol actions, and/or modifying protocol actions.
  • Protocols can be added, deleted, and modified during runtime, which is beneficial for users to test or deploy new protocols.
  • outdated or redundant protocols can be deleted, thereby solving the problem of freely adding, deleting, and modifying protocols during runtime.
  • modularization is the basis for runtime programmability, because there may be multiple functions in the data plane, adding, deleting or modifying functional modules cannot affect the normal operation of other functions.
  • the analysis of the protocol is located before all the functions, and it only realizes the decoupling of the protocol analysis and the function, that is, the vertical decoupling, which leads to the relative coupling between multiple functions, which is not conducive to adding, deleting and modifying a certain function alone.
  • the new architecture of the embodiment of the present application cancels the front-end parser of the traditional programmable data plane, splits the complete parsing graph into sub-graphs and distributes them to each stage of the pipeline, ensuring the self-sufficiency of each pipeline stage and avoiding unnecessary parsing.
  • the parsing cost is allocated at each stage of the pipeline, and the data plane throughput is not limited by the complexity of the parsing graph, making the design more scalable. If related protocols are involved when updating a function, only the functional module needs to be updated without affecting the normal operation of other functions.
  • the parsing subgraph of each stage is used to indicate the local parsing process. What circulates in the pipeline is a fixed number of bytes in the data packet plus the analysis result.
  • the analysis result is the indication information of each packet header, that is, a set of 2-tuples ⁇ packet header ID, packet header length ⁇ ; when the fields inside the packet header are needed, use the configuration parameters ⁇ field internal offset, field length ⁇ to obtain the fields. Parsing results are passed to subsequent stages to avoid unnecessary re-parsing.
  • the data plane can not only support IPv4 routing, but also support IPv6 routing. While canceling the front-end parser, this design also avoids the reassembly of the message header by the back-end reverse parser.
  • the processing logic when the processing logic inserts or deletes the packet header, it also includes: using the offset management module to update the parsing result.
  • the parsing result is updated by using the offset management module.
  • step S102 based on the template processor and the virtual pipeline, the order between any two processors is adjusted through the configuration interconnection network according to the insertion instruction, wherein any processor in all the template processors is used as the physical stage of the entry pipeline or the physical stage of the exit pipeline; the free configuration action is performed by configuring the template parameters.
  • the embodiments of the present application can add, delete, and modify function logic at runtime.
  • network operators can add new user services without affecting other users, or directly delete the user's functions when the service of a user expires, so as to solve the problem of free configuration of functions at runtime.
  • the implementation of the present application can use different types of interconnection networks, such as crossbars (crossbar), CLOS, Bens, etc. to realize virtual pipelines; internetworks of different scales can also be used to realize virtual pipelines, for example, when there are 32 template processors, use one 32*32 crossbar interconnection network, or use two 16*16 crossbar interconnection networks, etc., so as to meet different resource consumption and flexibility requirements.
  • interconnection networks such as crossbars (crossbar), CLOS, Bens, etc.
  • each physical stage of the programmable data plane in the related art is composed of field matching and logic execution, ie, MAU.
  • the embodiment of the present application adopts a distributed on-demand parser, as shown in Figure 6, each physical stage consists of three sub-modules: parser, matcher and executor. Among them, the functions of the matcher and the executor are similar to the matching operation and execution operation in the RMT architecture.
  • the parser is responsible for parsing out the protocol specified by the user and expressing ⁇ offset, length ⁇ in a protocol-independent format.
  • the physical stages of the new architecture pipeline are loosely coupled, so the controller can program each physical stage individually.
  • the free configuration action includes: by separating primitives and parameters, each physical stage is a general skeleton composed of primitives, so that when the user configures, the corresponding parameters are downloaded to the skeleton according to the added functions.
  • the embodiment of the present application separates primitives and parameters, and each physical stage becomes a parameterized skeleton, and adding functions in the user configuration stage is equivalent to downloading corresponding parameters into the skeleton.
  • the new architecture makes the following abstractions: (1) The message header field is abstracted as ⁇ offset, length ⁇ to achieve complete protocol independence; (2) the flow table is abstracted as ⁇ flow table type, flow table depth, flow table item width, matching key ⁇ , so that users can achieve the purpose of matching different flow tables by modifying the flow table abstraction; (3) execution actions are abstracted into a set of ordered execution primitives and execution parameters, and users can also configure execution parameters to achieve the purpose of modifying execution actions.
  • the embodiment of the present application refers to this design as a template-based stage processor (abbreviation: template processor, Templated-based Stage Processor, TSP), and the TSP is a key part for implementing runtime update and configuration.
  • the embodiment of the present application can use a virtual pipeline, that is, a reconfigurable non-blocking interconnection network (for example, a crossbar switch, CLOS network, etc.) is used between the template processors TSP to realize the normal operation of the pipeline.
  • the processors of the RMT architecture are connected in series, which will have a negative impact on the insertion of new functions.
  • the order between the processors is floating, that is, the user can adjust the order between any two processors by configuring the Internet to achieve the purpose of flexibly inserting new functions.
  • adding the data packet input/output module and the traffic management scheduler module to the Internet can dynamically generate any virtual pipeline, that is, any two template processors, the template processor and the data packet input/output module, and the template processor and the traffic manager can be connected to each other.
  • the pipeline sequence in Figure 7 is "input-TSP1-TSP4-TSP2-scheduler-TSP5-output".
  • Any template processor can be used as a physical stage of the ingress pipeline or as a physical stage of the egress pipeline, which improves the flexibility of the ingress and egress design of the data plane.
  • the method of the embodiment of the present application further includes: when the template processor is not inserted into the pipeline for execution, placing the template processor in a preset low power consumption mode.
  • the preset low power consumption mode can be set according to the actual situation, and the comparison is not specifically limited.
  • the processor may be placed in a low power mode.
  • step S103 based on the decoupled resource pool, the flow table resources of each physical stage are separated and pooled, and a new flow table is created, recycled or the specification of the flow table is modified during operation.
  • the embodiment of the present application can create a flow table, recycle the flow table, and modify the flow table specification at runtime, so as to improve the utilization rate of storage resources in the network device, thereby using a decoupled resource pool, and storage resource blocks can be freely combined to create a new flow table, which solves the problem of creating a flow table, recycling the flow table, and modifying the flow table specification at runtime.
  • updating the flow table at runtime refers to realizing the flexible creation, recycling, and modification of flow table specifications without interrupting existing traffic, rather than the addition, deletion, and modification of flow table entries.
  • storage resources TCAM and SRAM
  • this resource allocation method has the disadvantages of unbalanced resource utilization and inability to perform incremental updates.
  • the embodiment of the present application can adopt the technology of a decoupled storage resource pool, separate and pool the flow table resources of each physical stage, and improve the flexibility of flow table management; and in the decoupled resource pool, storage resource blocks are arbitrarily combined and split, so as to realize the creation and recycling of flow tables at runtime.
  • the flow table resources of each physical stage before separating and pooling the flow table resources of each physical stage, it also includes: using a static reconfigurable crossbar switch to interconnect between the physical stage and the storage resources, so as to reconfigure the crossbar switch when the template processor or the flow table is updated.
  • the embodiment of the present application can be based on the storage decoupling method, and the physical stage and the storage resources are interconnected using a static reconfigurable crossbar switch.
  • the update of the template processor or the flow table needs to reconfigure the crossbar switch.
  • IPSA provides an interface to modify the resource pool.
  • the user controls the resource pool to create a new flow table through the interface, that is, to combine multiple SRAM blocks or TCAM blocks. For example, if a flow table with a specification of 2w*4d is required, and each SRAM block has a specification of w*d, 8 SRAMs need to be combined to realize the flow table specified by the user.
  • the template processor and storage resources are divided into multiple clusters, and each cluster has a "template processor-storage resource" cross switch.
  • the one-to-one mapping relationship between processors and flow tables avoids memory access conflicts.
  • the programmable switch supports the P4 language to configure the underlying forwarding processing function.
  • the runtime environment provided by P4 only supports the addition, deletion and modification of flow table items, and does not provide protocol addition and deletion, flow table addition, deletion and logic processing function addition, deletion and modification.
  • the P4 language is extended to design the IPSA control plane. The overall programming process is shown in Figure 9:
  • the P4 program written by the user is translated into an intermediate representation P4IR by the P4 front-end compiler, and then the intermediate representation is handed over to the rP4 compiler.
  • the rP4 front-end compiler translates P4IR into rP4 files for runtime modification, and then the rP4 back-end compiler compiles rP4 into IPSA device-specific json configuration files, and sends them to the IPSA data plane for execution.
  • the IPSA data plane provides users with interfaces for adding, deleting, and modifying protocols, functions, and flow tables. Users write incremental rP4 codes and corresponding configuration instructions.
  • the rP4 back-end compiler compiles, the updated configuration is sent to the data plane, and the updated part is written back to the rP4 program for future updates.
  • the rP4 language is an extension of the P4 language. rP4 divides a physical stage into three parts: "parser-matcher-executor". Users can provide specific parameters for the three-part template to support specific functions. At the same time, rP4 supports code fragment programming. Users can write specific functions as rP4 code fragments without considering the constraints similar to P4, and load the functions represented by the code fragments into the underlying device through instructions.
  • step S104 based on the fast update controller, the data packet processing before the template processor that needs to be updated is suspended, and when the template processor has no data packet, the template processor is configured or the template processor is deleted from the pipeline.
  • the embodiments of the present application can be updated quickly and without interruption: the update of data plane functions, protocols, and flow tables is realized in the shortest possible time, and normal data packet processing and forwarding are not interrupted during the process.
  • step S104 includes updating the configuration of processors and deleting empty processors.
  • step S104 includes: when configuring template processors, sequentially configure template processors that need to be updated along the pipeline, wherein, suspend the data packet processing before the first template processor that needs to be configured, and configure the template processor when there is no data packet in the template processor, and sequentially configure template processors that need to be updated down the pipeline; after updating the configuration, delete all template processors that are empty.
  • the template processor is used, the data packet processing before the template processor with empty configuration is suspended, and when the data in the template processor with empty configuration is empty, the template processor with empty configuration is deleted from the pipeline by configuring a configurable crossbar switch.
  • the embodiment of the present application can be based on the fast update controller, suspend the processing of data packets before the template processors in the pipeline that need to be updated, and update the template processors when there are no data packets in the template processors; when there are empty configuration template processors in the pipeline, in the same way, when the empty configuration processors have no data packets, delete the empty configuration processors from the pipeline by configuring the reconfigurable switching network.
  • the IPSA architecture supports updating the underlying functions at runtime, while using the runtime interface provided by rP4 for users to modify at runtime.
  • an update mechanism is also required so that the update can take effect quickly without affecting the normal operation of traffic.
  • Each function has a different mapping method in the underlying physical stage.
  • a function may be mapped in one physical stage or in different physical stages. When mapped to multiple physical stages, these physical stages may be adjacent or not.
  • the invention proposes a bubble-based pipeline physical stage update scheme.
  • TSP2 and TSP4 together form the source MAC address learning function. If the user wants to delete the function, first suspension of the packet processing before TSP2. After TSP2 processing the remaining data packets, the TSP2 empty, that is, the atmospheric bubbles exist in TSP2. At 2, it will not be treated by the original configuration; the atmospheric bubbles located on TSP2 go back with the assembly line, and the update is directly updated when the TSP to be updated. This way new packets are not processed by old functions and old packets are not processed by new functions.
  • the large bubble update method proposed in this patent only needs to occupy more capacity in the cache (T+d), where T is the number of clock cycles to empty the TSP that needs to be updated, and d is the number of clock cycles to configure the TSP.
  • the update effective time of the update method proposed in this patent is also (T+d) clock cycle.
  • the programmable data plane also includes updating the controller pipeline by pipeline.
  • the method of the embodiment of the present application further includes: updating the pipelines in the data plane one by one based on updating the controller pipeline by pipeline. When updating the configuration of any pipeline, suspend the data packet from entering any pipeline, and when there is no data packet in any pipeline, update any pipeline.
  • the user can choose this update method to update the pipelines in the programmable data plane one by one. Specifically: first select a pipeline, stop the flow of data packets into the pipeline, and update the configuration in the pipeline when there is no data packet processing in the pipeline.
  • the embodiment of this application proposes to use technologies such as distributed on-demand parser, template-based stage processor, virtual pipeline, and decoupled resource pool to realize the runtime update of the data plane of the switch, and proposes a system architecture IPSA that supports runtime update protocols, functions, and flow tables; proposes the rP4 language that extends the P4 language, and provides interfaces for runtime reconfiguration protocols, functions, and flow tables; proposes a pipeline update method based on large bubbles to realize real-time uninterrupted updates of underlying devices.
  • technologies such as distributed on-demand parser, template-based stage processor, virtual pipeline, and decoupled resource pool
  • protocols can be added, deleted, and modified during runtime, which is beneficial for users to test or deploy new protocols, and at the same time, outdated or redundant protocols can be deleted; functional logic can be added, deleted, and modified during runtime.
  • network operators can add new user services without affecting other users, or when a user’s service expires, directly delete the user’s functions; can create flow tables, recycle flow tables, and modify flow table specifications during runtime to improve storage resources in network devices.
  • the utilization rate users can perform runtime updates through rP4, which is an extension of P4, and users can easily and conveniently implement runtime updates; the update process will not affect the normal data packet processing process, and real-time uninterrupted updates can be realized, and the functions take effect immediately.
  • FIG. 11 is a schematic block diagram of an apparatus for updating a programmable data plane during operation according to an embodiment of the present application.
  • the programmable data plane includes a distributed on-demand parser, a template processor, a virtual pipeline, a decoupled resource pool, and a fast update controller, wherein, as shown in FIG.
  • the parsing module 100 is used to split the parsing graph into multiple parsing subgraphs based on the distributed on-demand parser, and distribute each parsing subgraph to each corresponding physical stage in the pipeline, wherein, the parsing subgraph of each physical stage is used to indicate the local parsing process, and at runtime, parse out the protocol specified by the user, so as to perform adding protocol actions, deleting protocol actions, and/or modifying protocol actions;
  • the processing module 200 is used to adjust the order between any two processors through the configuration of the Internet according to the insertion instructions based on the template processor and the virtual pipeline, wherein the template processor serves as an entry The physical stage of the pipeline or the physical stage of the exit pipeline; to perform free configuration actions;
  • the storage module 300 is used to separate and pool the flow table resources of each physical stage based on the decoupled resource pool, and create a new flow table, recycle the flow table or modify the specification of the flow table at runtime;
  • the update module 400 is used to suspend the data packet processing before the
  • the device 10 in the embodiment of the present application further includes: a setting module.
  • the setting module is used to put the template processor into a preset low power consumption mode when the template processor is not inserted into the pipeline for execution.
  • the device 10 in the embodiment of the present application further includes: a detection module.
  • the detection module is used to detect whether the packet length has changed after parsing out the protocol specified by the user; when the packet length is detected to be changed, the offset management module is used to update the parsing result.
  • processing module 200 is further used to separate primitives and parameters to form a general skeleton composed of primitives at each physical stage, so that when users configure, corresponding parameters are downloaded to the skeleton according to added functions.
  • the device 10 in the embodiment of the present application further includes: a crossbar switch module.
  • the crossbar switch module is used to connect the physical stage and the storage resources by using a static reconfigurable crossbar switch before separating and pooling the flow table resources of each physical stage, so as to reconfigure the crossbar switch when the template processor or the flow table is updated.
  • the fast update module 400 is specifically used for: when configuring template processors, configure template processors that need to be updated sequentially down the pipeline, wherein, suspend the data packet processing before the first template processor that needs to be configured, configure the template processor when there is no data packet in the template processor, and configure the template processors that need to be updated sequentially down the pipeline; When the data in the empty-configured template processor is empty, the empty-configured template processor is deleted from the pipeline by configuring a configurable crossbar.
  • the programmable data plane also includes a pipeline-by-pipeline update controller
  • the device 10 in the embodiment of the present application further includes: an item-by-item update module.
  • the item-by-item update module is used to update the pipelines in the data plane one by one based on the pipeline-by-line update controller.
  • the data packet is suspended to enter any pipeline.
  • any pipeline is updated.
  • the data packet normally enters any pipeline, and the unupdated pipeline is selected for update.
  • protocols can be added, deleted, and modified during runtime, which is beneficial for users to test or deploy new protocols, and at the same time delete outdated or redundant protocols; functional logic can be added, deleted, and modified during runtime.
  • network operators can add new user services without affecting other users, or when a user’s service expires, directly delete the user’s functions; it can create flow tables, recycle flow tables, and modify flow table specifications during runtime to improve storage resources in network devices.
  • the utilization rate; users can perform runtime updates through rP4, which is an extension of P4, and users can easily and conveniently implement runtime updates; the update process will not affect the normal data packet processing process, and real-time uninterrupted updates can be realized, and the functions take effect immediately.
  • FIG. 12 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • This electronic equipment can include:
  • a memory 1201 a processor 1202 , and a computer program stored in the memory 1201 and executable on the processor 1202 .
  • the electronic equipment also includes:
  • the communication interface 1203 is used for communication between the memory 1201 and the processor 1202 .
  • the memory 1201 is used to store computer programs that can run on the processor 1202 .
  • the memory 1201 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory.
  • the bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 12 , but it does not mean that there is only one bus or one type of bus.
  • the memory 1201, processor 1202, and communication interface 1203 are integrated on one chip, then the memory 1201, processor 1202, and communication interface 1203 can communicate with each other through the internal interface.
  • the processor 1202 may be a central processing unit (Central Processing Unit, referred to as CPU), or a specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.
  • CPU Central Processing Unit
  • ASIC Application Specific Integrated Circuit
  • the embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the above method for updating the programmable data plane at runtime is implemented.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • “N” means at least two, such as two, three, etc., unless otherwise specifically defined.
  • a "computer-readable medium” may be any device that can contain, store, communicate, propagate or transmit a program for use in or in conjunction with an instruction execution system, device or device.
  • Non-exhaustive list of computer readable media include the following: electrical connection with one or N wires (electronic device), portable computer disk case (magnetic device), random access memory (RAM), read only memory (ROM), erasable editable read only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read only memory (CDROM).
  • the computer readable medium may even be paper or other suitable medium on which the program can be printed, since the program can be obtained electronically, for example, by optical scanning of the paper or other medium, followed by editing, interpretation or other suitable processing as necessary, and then stored in the computer memory.
  • each part of the present application may be realized by hardware, software, firmware or a combination thereof.
  • the N steps or methods may be implemented by software or firmware stored in memory and executed by a suitable instruction execution system.
  • it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit with logic gates for implementing logic functions on data signals, an application specific integrated circuit with suitable combinational logic gates, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.
  • each functional unit in each embodiment of the present application may be integrated into one processing module, each unit may exist separately physically, or two or more units may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. If the integrated modules are implemented in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium.
  • the storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

本申请涉及计算机网络技术领域，特别涉及一种可编程数据平面在运行时更新协议、更新功能及插入删除流表和修改流表规格的方法及装置，方法包括：基于分布式按需解析器，将解析图拆分成多个解析子图，并将每个解析子图分发到流水线中对应的每个物理阶段中；基于模板处理器与虚拟流水线，通过配置参数直接对处理器功能进行配置，根据插入指令通过配置互联网络调整任意两个处理器之间的顺序；基于解耦式资源池，将每个物理阶段的流表资源分离并进行池化，并在运行时，创建新流表、回收流表或者修改流表规格；更新处理器的配置以及删除空的处理器。由此，解决了如何在运行时自由增删改协议、自由配置功能、创建流表、回收流表以及修改流表规格等问题。

Description

可编程数据平面在运行时的更新方法及装置
相关申请的交叉引用
本申请基于申请号为202210055016.7，申请日为2022年01月18日申请的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及计算机网络技术领域，特别涉及一种可编程数据平面在运行时的更新方法及装置。
背景技术
随着SDN(Software Defined Networking，软件定义网络)概念的发展，可编程交换机逐渐商用并占据主流地位。可编程中的核心为可编程数据平面，数据平面负责协议解析与逆解析、数据包处理，由外部控制器负责下发解析规则及流表匹配规则。可编程性为设备供应商和网络运营商之间的关系带来了重大变化。
在可编程设备上推出新功能时，运营商无需等待传统网络设备长达数年的发布周期，同时网络操作者可以使用可编程设备的编程接口直接、快速部署新功能。然而，不同类型的网络需要不同的功能集合，新的协议和功能不断涌现，同时网络环境对吞吐量的需求不断增强，将所有需要的特性和功能集成到单个芯片中变得越来越不经济。未来网络有望向自治化发展，具备自配置、自诊断以及自愈能力，这将使网络运营更加动态和自动化。
然而，在愈加多变的网络环境中，需要可编程数据平面具有运行时可编程的能力，即在不中断服务的情况下运行时更新数据平面功能、协议及增删改流表的能力。
发明内容
本申请提供一种可编程数据平面在运行时的更新方法、装置、电子设备及存储介质，以解决如何在运行时自由增删改协议、自由配置功能、创建流表、回收流表以及修改流表规格等问题。
本申请第一方面实施例提供一种可编程数据平面在运行时的更新方法，所述可编程数据平面包括分布式按需解析器、模板处理器、虚拟流水线、解耦式资源池和快速更新控制器，其中，所述方法包括以下步骤：基于所述分布式按需解析器，将解析图拆分成多个解 析子图，并将每个解析子图分发到流水线中对应的每个物理阶段中，其中，所述每个物理阶段的解析子图用于指示本地解析过程，并在运行时，解析出用户指定的协议，通过配置解析子图以在目标物理阶段以执行增加协议动作、删除协议动作和/或修改协议动作；基于所述模板处理器与所述虚拟流水线，根据插入指令通过配置互联网络调整任意两个处理器之间的顺序，其中，所有模板处理器中任一处理器作为入口流水线的物理阶段或者出口流水线的物理阶段；通过配置模板处理器的参数以执行自由配置动作；基于所述解耦式资源池，将所述每个物理阶段的流表资源分离并进行池化，并在运行时，创建新流表、回收流表或者修改所述流表的规格；基于所述快速更新控制器，暂停需要更新的模板处理器之前的数据包处理，当所述模板处理器无数据包时，对所述模板处理器进行配置或者将所述模板处理器从流水线中删除。
进一步地，还包括：在所述模板处理器没有插入流水线中执行时，将所述模板处理器置于预设的低功耗模式。
进一步地，所述执行自由配置动作，包括：通过分离原语与参数，所述每个物理阶段为原语组成的通用骨架，以在用户配置时，根据添加的功能将相应的参数下载至所述骨架中。
进一步地，在将所述每个物理阶段的流表资源分离并进行池化之前，还包括：在物理阶段与存储资源之间利用静态可重配置交叉开关进行互联，以在所述模板处理器或者所述流表进行更新时，重新配置所述交叉开关。
进一步地，所述基于所述快速更新控制器，暂停需要更新的模板处理器之前的数据包处理，当所述模板处理器无数据包时，对所述模板处理器进行配置或者将所述模板处理器从流水线中删除，配置模板处理器时，顺着流水线向下依次配置需要更新的模板处理器，其中，暂停第一个需要配置的模板处理器之前的数据包处理，在所述模板处理器无数据包时，对所述模板处理器进行配置，并顺着流水线向下依次配置需要更新的模板处理器；在更新完配置之后，顺着流水线向下删除所有空配置的模板处理器，其中，在删除所述空配置的模板处理器时，暂停所述空配置的模板处理器之前的数据包处理，并在所述空配置的模板处理器中的数据为空时将所述空配置的模板处理器从流水线中通过配置可配置交叉开关删除。
进一步地，所述可编程数据平面还包括逐流水线更新控制器，还包括：基于所述逐流水线更新控制器，对数据平面中的流水线进行逐条更新，在更新任意一条流水线配置时，暂停数据包进入所述任意一条流水线，当所述任意一条流水线无数据包时，更新所述任意一条流水线，并在更新完成后，数据包正常进入所述任意一条流水线，并选择未更新的流水线进行更新。
本申请第二方面实施例提供一种可编程数据平面在运行时的更新装置，所述可编程数据平面包括分布式按需解析器、模板处理器、虚拟流水线、解耦式资源池和快速更新控制器，其中，所述装置包括：解析模块，用于基于所述分布式按需解析器，将解析图拆分成多个解析子图，并将每个解析子图分发到流水线中对应的每个物理阶段中，其中，所述每个物理阶段的解析子图用于指示本地解析过程，并在运行时，解析出用户指定的协议，通过配置解析子图以在目标物理阶段以执行增加协议动作、删除协议动作和/或修改协议动作；处理模块，用于基于所述模板处理器与所述虚拟流水线，根据插入指令通过配置互联网络调整任意两个处理器之间的顺序，其中，所有模板处理器中任一处理器作为入口流水线的物理阶段或者出口流水线的物理阶段；通过配置模板处理器的参数以执行自由配置动作；存储模块，用于基于所述解耦式资源池，将所述每个物理阶段的流表资源分离并进行池化，并在运行时，创建新流表、回收流表或者修改所述流表的规格；快速更新模块，用于基于所述快速更新控制器，暂停需要更新的模板处理器之前的数据包处理，当所述模板处理器无数据包时，对所述模板处理器进行配置或者将所述模板处理器从流水线中删除。
进一步地，还包括：设置模块，用于在所述模板处理器没有插入到流水线中执行时，将所述模板处理器置于预设的低功耗模式。
进一步地，所述处理模块进一步用于通过分离原语与参数，由所述每个物理阶段为原语组成的通用骨架，以在用户配置时，根据添加的功能将相应的参数下载至所述骨架中。
进一步地，还包括：交叉开关模块，用于在将所述每个物理阶段的流表资源分离并进行池化之前，在物理阶段与存储资源之间利用静态可重配置交叉开关进行互联，以在所述模板处理器或者所述流表进行更新时，重新配置所述交叉开关。
进一步地，所述快速更新模块进一步用于：配置模板处理器时，顺着流水线向下依次配置需要更新的模板处理器，其中，暂停第一个需要配置的模板处理器之前的数据包处理，在所述模板处理器无数据包时，对所述模板处理器进行配置，并顺着流水线向下依次配置需要更新的模板处理器；在更新完配置之后，顺着流水线向下删除所有空配置的模板处理器，其中，在删除所述空配置的模板处理器时，暂停所述空配置的模板处理器之前的数据包处理，并在所述空配置的模板处理器中的数据为空时将所述空配置的模板处理器从流水线中通过配置可配置交叉开关删除。
进一步地，所述可编程数据平面还包括逐流水线更新控制器，还包括：逐条更新模块，用于基于所述逐流水线更新控制器，对数据平面中的流水线进行逐条更新，在更新任意一条流水线配置时，暂停数据包进入所述任意一条流水线，当所述任意一条流水线无数据包时，更新所述任意一条流水线，并在更新完成后，数据包正常进入所述任意一条流水线，并选择未更新的流水线进行更新。
本申请第三方面实施例提供一种电子设备，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述程序，以实现如上述实施例所述的可编程数据平面在运行时的更新方法。
本申请第四方面实施例提供一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行，以用于实现如上述实施例所述的可编程数据平面在运行时的更新方法。
由此，本申请至少具有如下有益效果：
可以运行时增删改协议，有利于用户测试或部署新的协议，同时删除过时的或冗余的协议；可以运行时增删改功能逻辑，对于提供多租户应用服务的网络设备来说，网络操作者可以在不影响其他用户的情况下添加新的用户服务，或者当一个用户的服务到期时，直接删除该用户的功能；可以运行时创建流表、回收流表及修改流表规格，提高网络设备中存储资源的利用率。由此，解决了如何在运行时自由增删改协议、自由配置功能、创建流表、回收流表以及修改流表规格等问题。
本申请附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为相关技术中RMT技术架构图；
图2为相关技术中dRMT技术架构图；
图3为根据本申请实施例提供的IPSA总体架构图；
图4为根据本申请实施例提供的可编程数据平面在运行时的更新方法的流程图；
图5为根据本申请实施例提供的分布式按需解析器的结构示意图；
图6为根据本申请实施例提供的模板处理器的结构示意图；
图7为根据本申请实施例提供的虚拟流水线示意图；
图8为根据本申请实施例提供的解耦式资源池示意图；
图9为根据本申请实施例提供的运行时编程流程示意图；
图10为根据本申请实施例提供的无中断更新示例图；
图11为根据本申请实施例提供的可编程数据平面在运行时的更新装置的方框示意图；
图12为根据本申请实施例提供的电子设备的结构示意图。
具体实施方式
下面详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。
相关技术中，RMT(Reconfigurable Match Tables，可重配置匹配表)是现有可编程交换机Tofino的技术原型，如图1所示，RMT提供“解析器-流水线-逆解析器”的底层抽象，用户可以通过编写协议无关语言P4程序对底层架构进行编程，从而达到设备可自由定制协议、流表及功能的可编程目标。可编程解析器在运行前由用户指定解析状态转移图，数据包到达入端口之后由解析器解析出协议及字段；流水线由一系列串行的物理阶段组成，每个物理阶段包含多个MAU(Match Action Unit，匹配执行单元)，MAU是该原型的基本可重配置单元，用户可以在P4程序中指定流表规范以及动作原语对MAU进行编程，即在该物理阶段数据包需要查询什么流表，查询得到结果之后应执行怎样的处理逻辑，MAU在不同的配置下有不同的逻辑行为，从而实现用户特定的处理与转发功能；可编程逆解析器是按照用户指定的协议顺序将协议重新组装到数据包负载中。
基于RMT技术，网络功能在设计时可以通过协议无关语言P4进行自由定制，但在编译和部署之后，可编程设备底层配置确定，重配置需要暂停数据包处理、重新编译程序、下载、替换底层配置。对于多租户服务更新、有状态的应用更新、网内计算热插拔等主流应用来说，停机配置极大影响服务质量。据统计，具有64个100G端口的Tofino交换机需要50ms停机时间用于更新，满速状态下会损失37GiB的数据，重新下载流表需要的时间更长。
POF(Protocol-Oblivious Forwarding，协议无关转发)采用“偏移+长度”的抽象来表示一个协议，淡化协议具体内容，消除协议间的依赖，做到完全协议无关，从而实现可编程数据平面，用户可以自由定制自己的协议。同时，POF使用特定的指令集来适配“偏移+长度”的协议抽象，增强数据平面的数据包处理能力，使用简单的指令切换实现功能更新。在POF中，每个功能是一个模块，用户可以通过编程配合底层指令集对模块进行热插拔，实现运行时重配置。但是，POF在软件网络处理器上实现的，处理速度远不及ASIC硬件交换机，从而不能大规模使用。
dRMT(disaggregated Reconfigurable Match-Action Table，分布式可重配置匹配表)在RMT的基础上，将流表资源与数据包处理逻辑资源解耦，处理器通过交换网络访问内存簇中流表资源，如图2所示。与RMT流水线数据包处理方式不同，dRMT采用多处理器并行的方式处理数据包，每个处理器包含一个完整的数据包处理程序，采用调度器避开不同处理器之间的访存冲突问题。dRMT构建流表资源池，解决了RMT中一 个物理阶段不能容纳大流表的问题，使得数据平面可编程性提高，支持更多的网络应用；同时dRMT将资源池化的做法有利于实现运行时可重配置，即在运行时创建流表、回收流表以及修改流表规范等。但是dRMT采用的是“运行至终结”(Run-to-Completion，RTC)的数据包处理模式，这种模式本质上不支持运行时修改协议、功能及流表。dRMT的系统设计未涉及运行时重配置，不能为用户提供运行时重配置接口。
为此，本申请实施例提出了一种实现运行时可编程交换芯片及快速无中断更新的方法和装置主要解决如下三个技术问题：
(1)如何设计底层架构，使得设备支持运行时更新协议、数据包处理功能及流表，即在运行时增加、删除、修改协议，添加、删除、修改数据包处理逻辑，创建流表、回收流表及修改流表规格；
(2)如何支持用户对运行时重配置数据平面进行运行时重配置；
(3)如何快速无中断更新底层设备。
下面将参考附图描述本申请实施例的可编程数据平面在运行时的更新方法、装置、电子设备及存储介质。其中，可编程数据平面包括分布式按需解析器、模板处理器、虚拟流水线、解耦式资源池和快速更新控制器，其中，快速更新控制器负责控制模板处理器更新的进行以及整体流水线的更新。具体地：为了解决运行时数据平面协议、功能及流表规格更新的问题，本申请实施例提出了如图3所示的可编程数据平面IPSA(In-situ Programmable Switch Architecture，原位可重配置交换架构)，可以使得数据平面支持运行时更新，IPSA主要由四部分构成：分布式按需解析器、模板处理器、虚拟流水线、解耦式资源池。
下面将结合图4对可编程数据平面在运行时的更新方法进行阐述，包括以下步骤：
在步骤S101中，基于分布式按需解析器，将解析图拆分成多个解析子图，并将每个解析子图分发到流水线中对应的每个物理阶段中，其中，每个物理阶段的解析子图用于指示本地解析过程，并在运行时，解析出用户指定的协议，通过配置解析子图以在目标物理阶段执行增加协议动作、删除协议动作和/或修改协议动作。
可以理解的是，本申请实施例可以通过配置特定模板处理器的解析子图，以执行增加协议动作、删除协议动作和/或修改协议动作，可以在运行时增删改协议，有利于用户测试或部署新的协议，同时删除过时的或冗余的协议，从而可以解决运行时可以自由增删改协议的问题。
具体而言，模块化是实现运行时可编程的基础，因为在数据平面中可能存在多个功能，增删改功能模块时不能影响其他功能的正常运行。相关技术中协议的解析位于所有功能之前，只是实现了协议解析与功能解耦，即纵向解耦，导致多个功能间是相对耦合的，不利 于单独增删改某个功能。
本申请实施例的新架构取消传统可编程数据平面的前端解析器，将完整的解析图拆分成子图分发到流水线中的每个阶段中，保证每个流水线阶段的自给自足，避免不必要的解析。解析成本分摊在流水线各个阶段，数据平面吞吐不受解析图复杂度的限制，使得设计更具可扩展性。更新功能时如果涉及到相关协议，只需要更新该功能模块，而不会影响其他功能的正常运行。
如图5所示，每个阶段的解析子图用来指示本地解析过程。在流水线中流通的是数据包固定数量的字节加上解析结果，到达相应的物理阶段，就会有指定的协议被解析出来，解析结果为每个报文头的指示信息，即{报文头ID，报文头长度}的二元组集合；当需要报文头内部的字段时，使用配置参数{字段内部偏移量，字段长度}获取字段。解析结果传递到后续各个阶段，以避免不必要的重新解析。在运行时用户将IPv6协议添加到物理阶段3中，则数据平面不仅可支持IPv4路由，还可以支持IPv6路由。该设计在取消前端解析器的同时也避免了后端逆解析器对报文头的重新组装。
在本实施例中，当处理逻辑插入或者删除报文头时，还包括：使用偏移管理模块对解析结果进行更新。
可以理解的是，为了能够保证传递信息的正确性，在报文长度发生变化时(例如，MPLS标签的推入和弹出)，使用偏移管理模块对解析结果进行更新。
在步骤S102中，基于模板处理器与虚拟流水线，根据插入指令通过配置互联网络调整任意两个处理器之间的顺序，其中所有模板处理器中任一处理器作为入口流水线的物理阶段或者出口流水线的物理阶段；通过配置模板参数以执行自由配置动作。
可以理解的是，本申请实施例可以在运行时增删改功能逻辑，对于提供多租户应用服务的网络设备来说，网络操作者可以在不影响其他用户的情况下添加新的用户服务，或者当一个用户的服务到期时，直接删除该用户的功能，从而可以解决运行时可以自由配置功能的问题。
需要说明的是，对于虚拟流水线而言，本申请实施可以使用不同类型的互联网络，例如交叉开关(crossbar)、CLOS、Bens等实现虚拟流水线；也可使用不同规模的互联网络实现虚拟流水线，例如32个模板处理器时，使用1个32*32的交叉开关(crossbar)互联网络，或者使用2个16*16的交叉开关互联网络等，从而可以满足不同的资源消耗及灵活性的需求。
具体而言，相关技术中可编程数据平面的每个物理阶段由字段匹配和逻辑执行两个部分组成，即MAU。本申请实施例采用分布式按需解析器，如图6所示，每个物理阶段由三个子模块组成：解析器、匹配器和执行器。其中，匹配器和执行器的功能与RMT架构中的 匹配操作和执行操作类似，解析器负责解析出用户指定的协议，并使用协议无关格式表示{偏移量，长度}。新架构流水线的各个物理阶段是松耦合的，因此控制器可以对每个物理阶段进行单独编程。
在本实施例中，执行自由配置动作，包括：通过分离原语与参数，每个物理阶段为原语组成的通用骨架，以在用户配置时，根据添加的功能将相应的参数下载至骨架中。
具体而言，如图6中，本申请实施例通过分离原语与参数，每个物理阶段变成一个参数化的骨架，用户配置阶段添加功能相当于将相应的参数下载到骨架中。对于每个阶段中需要的关键元素，新架构做了如下抽象：(1)报文头字段被抽象为{偏移量，长度}，实现完全的协议无关；(2)流表被抽象为{流表类型、流表深度、流表项宽度、匹配键}，使得用户可以通过修改流表抽象来达到匹配不同流表的目的；(3)执行动作被抽象为一组有序的执行原语及执行参数，用户同样可以配置执行参数来达到修改执行动作的目的。本申请实施例将该种设计称为基于模板的阶段处理器(简称：模板处理器，Templated-based Stage Processor，TSP)，TSP是实现运行时更新和配置的关键部分。
进一步而言，在解决运行时配置单个TSP的问题之后，需要解决整条流水线上物理阶段灵活放置的问题。鉴于RMT架构的物理阶段之间硬连线而不能实现功能插入删除的情况，本申请实施例可以采用虚拟流水线，即模板处理器TSP之间采用可重配置非阻塞互联网络(例如，交叉开关，CLOS网络等)实现流水线的正常运行。RMT架构的各个处理器间是串联关系，这会给插入新功能带来负面影响，而使用虚拟流水线，各个处理器之间的顺序是浮动的，即用户可以通过配置互联网络来调整任意两个处理器之间的顺序，以达到灵活插入新功能的目的。
如图7所示，将数据包输入/输出模块和流量管理调度器模块加入到互联网络中，可以动态生成任意的虚拟流水线，即任意两个模板处理器、模板处理器与数据包输入/输出模块、模板处理器与流量管理器可以互相连接，图7中的流水线顺序为“输入-TSP1-TSP4-TSP2-调度器-TSP5-输出”。任何的模板处理器可以作为入口流水线的物理阶段，也可以作为出口流水线的物理阶段，提高数据平面入口出口设计的灵活性。
在本实施例中，本申请实施例的方法还包括：在模板处理器没有插入到流水线中执行时，将模板处理器置于预设的低功耗模式。
其中，预设的低功耗模式可以根据实际情况进行设置，对比不做具体限定。
可以理解的是，当模板处理器没有流水线阶段执行时，可以将该处理器置于低功耗模式。
在步骤S103中，基于解耦式资源池，将每个物理阶段的流表资源分离并进行池化，并在运行时，创建新流表、回收流表或者修改流表的规格。
可以理解的是，本申请实施例可以在运行时创建流表、回收流表及修改流表规格，提高网络设备中存储资源的利用率，从而使用解耦式资源池，存储资源块可以自由组合以创建新流表，解决了运行时创建流表、回收流表以及修改流表规格的问题。
具体而言，运行时更新流表是指在不中断现有流量的情况下，实现灵活创建流表、回收流表以及修改流表规格，而不是流表项的增删改。相关技术中可编程数据平面架构中，存储资源(TCAM和SRAM)在所有物理阶段之间是平均分配的，而每个阶段需要的资源可能不同，因此这种资源分配方式有资源利用不均衡以及无法进行增量更新的缺点。为了实现运行时更新流表，本申请实施例可以采取解耦式存储资源池的技术，将原本每个物理阶段的流表资源分离出来并进行池化，提高流表管理的灵活性；且是在解耦式资源池中对存储资源块进行任意的组合、拆分，以实现运行时创建、回收流表。
在本实施例中，在将每个物理阶段的流表资源分离并进行池化之前，还包括：在物理阶段与存储资源之间利用静态可重配置交叉开关进行互联，以在模板处理器或者流表进行更新时，重新配置交叉开关
具体而言，如图8所示，本申请实施例可以基于存储解耦的方式，物理阶段与存储资源之间使用静态可重配置交叉开关进行互联，模板处理器或者流表的更新需要重新配置交叉开关。IPSA提供资源池修改的接口，当有新流表需要创建时，用户通过接口控制资源池创建新流表，即将多个SRAM块或TCAM块进行组合，比如，需要规格为2w*4d的流表，每个SRAM块规格为w*d，则需要组合8块SRAM，实现用户指定的流表。删除流表及修改流表规格与之同理。为了提高架构可扩展性，将模板处理器和存储资源划分为多个集群，每个集群内都有一个“模板处理器-存储资源”的交叉开关。处理器和流表之间一对一的映射关系避免了访存冲突问题。
进一步而言，在介绍上述实施例的实现运行时可编程数据平面的技术原理和系统架构之后，下面将对供用户运行时重配置的网络编程语言及配置接口进行阐述，具体如下：
相关技术中可编程交换机支持P4语言对底层转发处理功能进行配置，当交换机运行时，P4提供的运行时环境仅支持流表项的增删改，未提供协议增删改、流表增删改及逻辑处理功能增删改。本申请实施例在设计IPSA数据平面之后，对P4语言进行扩展，设计IPSA控制平面。整体的编程流程如图9所示：
首先通过P4前端编译器将用户编写的P4程序翻译成中间表示P4IR，然后将该中间表示交给rP4编译器。首先通过rP4前端编译器将P4IR翻译成rP4文件以供运行时修改，然后rP4后端编译器将rP4编译成特定于IPSA设备的json配置文件，并下发到IPSA数据平面执行。在运行时，IPSA数据平面为用户提供协议、功能及流表的增删改接口，用户编写增量rP4代码以及相应的配置指令，在rP4后端编译器编译之后，将更新配置下发到数据 平面，同时将更新部分写回rP4程序中，以供将来的更新。
rP4语言是对P4语言的扩展，rP4将一个物理阶段分成“解析器-匹配器-执行器”三个部分，用户可以为三部分的模板提供具体参数，以支持具体的功能。同时，rP4支持代码片段编程，用户可以将特定的功能写成rP4代码片段，而无需考虑类似于P4的约束，通过指令将该代码片段所表示的功能加载到底层设备中。
在步骤S104中，基于快速更新控制器，暂停需要更新的模板处理器之前的数据包处理，当模板处理器无数据包时，对模板处理器进行配置或者将模板处理器从流水线中删除。
可以理解的是，本申请实施例可以快速无中断更新：以尽量短的时间实现数据平面功能、协议及流表的更新，在此过程中不中断正常的数据包处理与转发。
其中，步骤S104包括更新处理器的配置以及删除空的处理器，在本实施例中，步骤S104包括：配置模板处理器时，顺着流水线向下依次配置需要更新的模板处理器，其中，暂停第一个需要配置的模板处理器之前的数据包处理，在模板处理器无数据包时，对模板处理器进行配置，并顺着流水线向下依次配置需要更新的模板处理器；在更新完配置之后，顺着流水线向下删除所有空配置的模板处理器，其中，在删除空配置的模板处理器时，暂停空配置的模板处理器之前的数据包处理，并在空配置的模板处理器中的数据为空时将空配置的模板处理器从流水线中通过配置可配置交叉开关删除。
可以理解的是，本申请实施例可以基于快速更新控制器，暂停流水线中需要更新的模板处理器之前的数据包处理，在模板处理器没有数据包时，更新模板处理器；当流水线中有空配置的模板处理器时，按照相同的方式，当空配置处理器无数据包时，将空配置处理器通过配置可重配置交换网络从流水线中删除。
具体而言，IPSA架构支持运行时更新底层功能，同时使用rP4提供的运行时接口供用户进行运行时修改。除以上之外，还需要更新机制，使得更新能够快速生效并且不会影响流量的正常运行。每个功能在底层物理阶段中有不同的映射方式，一个功能可能映射在一个物理阶段，也可能映射在不同的物理阶段，映射到多个物理阶段时这些物理阶段可能是相邻的，可能是不相邻的。当更新一个功能时，要保证数据包处理的一致性，即数据包要么被新功能处理，要么被旧功能处理，不能同时被新功能的一部分和旧功能的一部分一起处理。本发明提出一种基于气泡的流水线物理阶段更新方案。
如图10所示，TSP2与TSP4共同组成源MAC地址学习功能，用户想要删除该功能，首先暂停TSP2之前的数据包处理，待TSP2处理完剩下的数据包之后，TSP2空，即大气泡存在于TSP2，此时删除TSP2内部配置，放开TSP2之前的处理，新数据包到达TSP2时不会再被原配置处理；位于TSP2的大气泡随着流水线向后走，走到待更新的TSP时，直接进行更新。这样，新数据包不会被旧功能处理，旧数据包不会被新功能处理。本专利 提出的大气泡更新方式仅需要多占缓存中(T+d)的容量，T为排空需要更新的TSP的时钟周期数，d为配置该TSP的时钟周期数。另外，本专利提出的更新方式更新生效时间也为(T+d)时钟周期。
在更新完配置之后，需要重新整理流水线，即删除没有配置的TSP。重复进行上述操作，即要删除一个TSP时，暂停该TSP之前的数据包处理，这段时间新进入的数据包由缓存承接，待要删除的TSP空时，删除该TSP；顺着流水线向下，直到删除完所有空配置的TSP为止。这一步更新为背景更新，不会影响数据包的正常处理。
进一步而言，可编程数据平面还包括逐流水线更新控制器，本申请实施例的方法还包括：基于逐流水线更新控制器，对数据平面中的流水线进行逐条更新，在更新任意一条流水线配置时，暂停数据包进入任意一条流水线，当任意一条流水线无数据包时，更新任意一条流水线，并在更新完成后，数据包正常进入任意一条流水线，并选择未更新的流水线进行更新。
可以理解的是，基于逐流水线更新控制器，用户可以选择该更新方法，对可编程数据平面中的流水线进行逐条更新，具体地：首先选择一条流水线，暂停数据包流入该流水线，当该流水线无数据包处理时，对该流水线中的配置进行更新，更新完成后，数据包正常进入该条流水线；继续选择未更新的流水线，重复上述步骤，直到所有的流水线完成更新为止。
综上，本申请实施例提出利用分布式按需解析器、基于模板的阶段处理器、虚拟流水线以及解耦式资源池等技术实现交换机数据平面的运行时更新，提出了支持运行时更新协议、功能及流表的系统架构IPSA；提出扩展P4语言的rP4语言，提供运行时重配置协议、功能及流表的接口；提出基于大气泡的流水线更新方式，实现底层设备的实时无中断更新。
根据本申请实施例提出的可编程数据平面在运行时的更新方法，可以运行时增删改协议，有利于用户测试或部署新的协议，同时删除过时的或冗余的协议；可以运行时增删改功能逻辑，对于提供多租户应用服务的网络设备来说，网络操作者可以在不影响其他用户的情况下添加新的用户服务，或者当一个用户的服务到期时，直接删除该用户的功能；可以运行时创建流表、回收流表及修改流表规格，提高网络设备中存储资源的利用率；用户通过rP4进行运行时更新，rP4是对P4的扩展，用户可以简单便捷的实现运行时更新；更新过程不会影响正常的数据包处理过程，并且可以实现实时无中断更新，功能即时生效。
其次参照附图描述根据本申请实施例提出的可编程数据平面在运行时的更新装置。
图11是本申请实施例的可编程数据平面在运行时的更新装置的方框示意图。
可编程数据平面包括分布式按需解析器、模板处理器、虚拟流水线、解耦式资源池和 快速更新控制器，其中，如图11所示，该可编程数据平面在运行时的更新装置10包括：解析模块100、处理模块200、存储模块300和快速更新模块400。
其中，解析模块100用于基于分布式按需解析器，将解析图拆分成多个解析子图，并将每个解析子图分发到流水线中对应的每个物理阶段中，其中，每个物理阶段的解析子图用于指示本地解析过程，并在运行时，解析出用户指定的协议，以执行增加协议动作、删除协议动作和/或修改协议动作；处理模块200用于基于模板处理器与虚拟流水线，根据插入指令通过配置互联网络调整任意两个处理器之间的顺序，其中，模板处理器作为入口流水线的物理阶段或者出口流水线的物理阶段；以执行自由配置动作；存储模块300用于基于解耦式资源池，将每个物理阶段的流表资源分离并进行池化，并在运行时，创建新流表、回收流表或者修改流表的规格；更新模块400用于基于快速更新控制器，暂停需要更新的模板处理器之前的数据包处理，当模板处理器无数据包时，对模板处理器进行配置或者将模板处理器从流水线中删除。
进一步地，本申请实施例的装置10还包括：设置模块。其中，设置模块用于在模板处理器没有插入到流水线中执行时，将模板处理器置于预设的低功耗模式。
进一步地，本申请实施例的装置10还包括：检测模块。其中，检测模块用于在解析出用户指定的协议之后，检测报文长度是否发生变化；在检测到报文长度发生变化时，使用偏移管理模块对解析结果进行更新。
进一步地，处理模块200进一步用于通过分离原语与参数，由每个物理阶段为原语组成的通用骨架，以在用户配置时，根据添加的功能将相应的参数下载至骨架中。
进一步地，本申请实施例的装置10还包括：交叉开关模块。其中，交叉开关模块用于在将每个物理阶段的流表资源分离并进行池化之前，在物理阶段与存储资源之间利用静态可重配置交叉开关进行互联，以在模板处理器或者流表进行更新时，重新配置交叉开关。
进一步地，快速更新模块400具体用于：配置模板处理器时，顺着流水线向下依次配置需要更新的模板处理器，其中，暂停第一个需要配置的模板处理器之前的数据包处理，在模板处理器无数据包时，对模板处理器进行配置，并顺着流水线向下依次配置需要更新的模板处理器；在更新完配置之后，顺着流水线向下删除所有空配置的模板处理器，其中，在删除空配置的模板处理器时，暂停空配置的模板处理器之前的数据包处理，并在空配置的模板处理器中的数据为空时将空配置的模板处理器从流水线中通过配置可配置交叉开关删除。
进一步地，可编程数据平面还包括逐流水线更新控制器，本申请实施例的装置10还包括：逐条更新模块。其中，逐条更新模块用于基于逐流水线更新控制器，对数据平面中的流水线进行逐条更新，在更新任意一条流水线配置时，暂停数据包进入任意一条流水线， 当任意一条流水线无数据包时，更新任意一条流水线，并在更新完成后，数据包正常进入任意一条流水线，并选择未更新的流水线进行更新。
需要说明的是，前述对可编程数据平面在运行时的更新方法实施例的解释说明也适用于该实施例的可编程数据平面在运行时的更新装置，此处不再赘述。
根据本申请实施例提出的可编程数据平面在运行时的更新装置，可以运行时增删改协议，有利于用户测试或部署新的协议，同时删除过时的或冗余的协议；可以运行时增删改功能逻辑，对于提供多租户应用服务的网络设备来说，网络操作者可以在不影响其他用户的情况下添加新的用户服务，或者当一个用户的服务到期时，直接删除该用户的功能；可以运行时创建流表、回收流表及修改流表规格，提高网络设备中存储资源的利用率；用户通过rP4进行运行时更新，rP4是对P4的扩展，用户可以简单便捷的实现运行时更新；更新过程不会影响正常的数据包处理过程，并且可以实现实时无中断更新，功能即时生效。
图12为本申请实施例提供的电子设备的结构示意图。该电子设备可以包括：
存储器1201、处理器1202及存储在存储器1201上并可在处理器1202上运行的计算机程序。
处理器1202执行程序时实现上述实施例中提供的可编程数据平面在运行时的更新方法。
进一步地，电子设备还包括：
通信接口1203，用于存储器1201和处理器1202之间的通信。
存储器1201，用于存放可在处理器1202上运行的计算机程序。
存储器1201可能包含高速RAM存储器，也可能还包括非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。
如果存储器1201、处理器1202和通信接口1203独立实现，则通信接口1203、存储器1201和处理器1202可以通过总线相互连接并完成相互间的通信。总线可以是工业标准体系结构(Industry Standard Architecture，简称为ISA)总线、外部设备互连(Peripheral Component，简称为PCI)总线或扩展工业标准体系结构(Extended Industry Standard Architecture，简称为EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图12中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
可选的，在具体实现上，如果存储器1201、处理器1202及通信接口1203，集成在一块芯片上实现，则存储器1201、处理器1202及通信接口1203可以通过内部接口完成相互间的通信。
处理器1202可能是一个中央处理器(Central Processing Unit，简称为CPU)，或者是特定集成电路(Application Specific Integrated Circuit，简称为ASIC)，或者是被配置成实施本 申请实施例的一个或多个集成电路。
本申请实施例还提供一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现如上的可编程数据平面在运行时的更新方法。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或N个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“N个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
流程图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或更N个用于实现定制逻辑功能或过程的步骤的可执行指令的代码的模块、片段或部分，并且本申请的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能，这应被本申请的实施例所属技术领域的技术人员所理解。
在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行系统、装置或设备(如基于计算机的系统、包括处理器的系统或其他可以从指令执行系统、装置或设备取指令并执行指令的系统)使用，或结合这些指令执行系统、装置或设备而使用。就本说明书而言，"计算机可读介质"可以是任何可以包含、存储、通信、传播或传输程序以供指令执行系统、装置或设备或结合这些指令执行系统、装置或设备而使用的装置。计算机可读介质的更具体的示例(非穷尽性列表)包括以下：具有一个或N个布线的电连接部(电子装置)，便携式计算机盘盒(磁装置)，随机存取存储器(RAM)，只读存储器(ROM)，可擦除可编辑只读存储器(EPROM或闪速存储器)，光纤装置，以及便携式光盘只读存储器(CDROM)。另外，计算机可读介质甚至可以是可在其上打印所述程序的纸或其他合适的介质，因为可以例如通过对纸或其他介质进行光学扫描，接着进行 编辑、解译或必要时以其他合适方式进行处理来以电子方式获得所述程序，然后将其存储在计算机存储器中。
应当理解，本申请的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，N个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。如，如果用硬件来实现和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
本技术领域的普通技术人员可以理解实现上述实施例方法携带的全部或部分步骤是可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，该程序在执行时，包括方法实施例的步骤之一或其组合。
此外，在本申请各个实施例中的各功能单元可以集成在一个处理模块中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。
上述提到的存储介质可以是只读存储器，磁盘或光盘等。尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (14)

  1. 一种可编程数据平面在运行时的更新方法，其特征在于，所述可编程数据平面包括分布式按需解析器、模板处理器、虚拟流水线、解耦式资源池、快速更新控制器，其中，所述方法包括以下步骤：
    基于所述分布式按需解析器，将解析图拆分成多个解析子图，并将每个解析子图分发到流水线中对应的每个物理阶段中，其中，所述每个物理阶段的解析子图用于指示本地解析过程，并在运行时，解析出用户指定的协议，通过配置解析子图以在目标物理阶段执行增加协议动作、删除协议动作和/或修改协议动作；
    基于所述模板处理器与所述虚拟流水线，根据指令通过配置互联网络调整任意两个处理器之间的顺序，其中，所有模板处理器中任一处理器作为入口流水线的物理阶段或者出口流水线的物理阶段；通过配置模板参数以执行自由配置动作；
    基于所述解耦式资源池，将所述每个物理阶段的流表资源分离并进行池化，并在运行时，创建新流表、回收流表或者修改所述流表的规格；
    基于所述快速更新控制器，暂停需要更新的模板处理器之前的数据包处理，当所述模板处理器无数据包时，对所述模板处理器进行配置或者将所述模板处理器从流水线中删除。
  2. 根据权利要求1所述的方法，其特征在于，还包括：
    在所述模板处理器没有插入到流水线中执行时，将所述模板处理器置于预设的低功耗模式。
  3. 根据权利要求1所述的方法，其特征在于，所述执行自由配置动作，包括：
    通过分离原语与参数，所述每个物理阶段为原语组成的通用骨架，以在用户配置时，根据添加的功能将相应的参数下载至所述骨架中。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，在将所述每个物理阶段的流表资源分离并进行池化之前，还包括：
    在物理阶段与存储资源之间利用静态可重配置交叉开关进行互联，以在所述模板处理器或者所述流表进行更新时，重新配置所述交叉开关。
  5. 根据权利要求1所述的方法，其特征在于，所述基于所述快速更新控制器，暂停需要更新的模板处理器之前的数据包处理，当所述模板处理器无数据包时，对所述模板处理器进行配置或者将所述模板处理器从流水线中删除，包括：
    配置模板处理器时，顺着流水线向下依次配置需要更新的模板处理器，其中，暂停第一个需要配置的模板处理器之前的数据包处理，在所述模板处理器无数据包时，对所述模板处理器进行配置，并顺着流水线向下依次配置需要更新的模板处理器；
    在更新完配置之后，顺着流水线向下删除所有空配置的模板处理器，其中，在删除所述空配置的模板处理器时，暂停所述空配置的模板处理器之前的数据包处理，并在所述空配置的模板处理器中的数据为空时将所述空配置的模板处理器从流水线中通过配置可配置交叉开关删除。
  6. 根据权利要求1所述的方法，其特征在于，所述可编程数据平面还包括逐流水线更新控制器，还包括：
    基于所述逐流水线更新控制器，对数据平面中的流水线进行逐条更新，在更新任意一条流水线配置时，暂停数据包进入所述任意一条流水线，当所述任意一条流水线无数据包时，更新所述任意一条流水线，并在更新完成后，数据包正常进入所述任意一条流水线，并选择未更新的流水线进行更新。
  7. 一种可编程数据平面在运行时的更新装置，其特征在于，所述可编程数据平面包括分布式按需解析器、模板处理器、虚拟流水线、解耦式资源池和快速更新控制器，其中，所述装置包括：
    解析模块，用于基于所述分布式按需解析器，将解析图拆分成多个解析子图，并将每个解析子图分发到流水线中对应的每个物理阶段中，其中，所述每个物理阶段的解析子图用于指示本地解析过程，并在运行时，解析出用户指定的协议，通过配置解析子图以在目标物理阶段以执行增加协议动作、删除协议动作和/或修改协议动作；
    处理模块，用于基于所述模板处理器与所述虚拟流水线，根据插入指令通过配置互联网络调整任意两个处理器之间的顺序，其中，所有模板处理器中任一处理器作为入口流水线的物理阶段或者出口流水线的物理阶段；通过配置模板处理器的参数以执行自由配置动作；以及
    存储模块，用于基于所述解耦式资源池，将所述每个物理阶段的流表资源分离并进行池化，并在运行时，创建新流表、回收流表或者修改所述流表的规格；
    快速更新模块，用于基于所述快速更新控制器，暂停需要更新的模板处理器之前的数据包处理，当所述模板处理器无数据包时，对所述模板处理器进行配置或者将所述模板处理器从流水线中删除。
  8. 根据权利要求7所述的装置，其特征在于，还包括：
    设置模块，用于在所述模板处理器没有插入到流水线中执行时，将所述模板处理器置于预设的低功耗模式。
  9. 根据权利要求7所述的装置，其特征在于，所述处理模块进一步用于通过分离原语与参数，由所述每个物理阶段为原语组成的通用骨架，以在用户配置时，根据添加的功能将相应的参数下载至所述骨架中。
  10. 根据权利要求7-9任一项所述的装置，其特征在于，还包括：
    交叉开关模块，用于在将所述每个物理阶段的流表资源分离并进行池化之前，在物理阶段与存储资源之间利用静态可重配置交叉开关进行互联，以在所述模板处理器或者所述流表进行更新时，重新配置所述交叉开关。
  11. 根据权利要求7所述的装置，其特征在于，所述快速更新模块具体用于：
    配置模板处理器时，顺着流水线向下依次配置需要更新的模板处理器，其中，暂停第一个需要配置的模板处理器之前的数据包处理，在所述模板处理器无数据包时，对所述模板处理器进行配置，并顺着流水线向下依次配置需要更新的模板处理器；在更新完配置之后，顺着流水线向下删除所有空配置的模板处理器，其中，在删除所述空配置的模板处理器时，暂停所述空配置的模板处理器之前的数据包处理，并在所述空配置的模板处理器中的数据为空时将所述空配置的模板处理器从流水线中通过配置可配置交叉开关删除。
  12. 根据权利要求7所述的装置，其特征在于，还包括：
    逐条更新模块，用于基于所述逐流水线更新控制器，对数据平面中的流水线进行逐条更新，在更新任意一条流水线配置时，暂停数据包进入所述任意一条流水线，当所述任意一条流水线无数据包时，更新所述任意一条流水线，并在更新完成后，数据包正常进入所述任意一条流水线，并选择未更新的流水线进行更新。
  13. 一种电子设备，其特征在于，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述程序，以实现如权利要求1-6任一项所述的可编程数据平面在运行时的更新方法。
  14. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，该程序被处理器执行，以用于实现如权利要求1-6任一项所述可编程数据平面在运行时的更新方法。
PCT/CN2022/134290 2022-01-18 2022-11-25 可编程数据平面在运行时的更新方法及装置 WO2023138215A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210055016.7A CN114416150A (zh) 2022-01-18 2022-01-18 可编程数据平面在运行时的更新方法及装置
CN202210055016.7 2022-01-18

Publications (1)

Publication Number Publication Date
WO2023138215A1 true WO2023138215A1 (zh) 2023-07-27

Family

ID=81273780

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/134290 WO2023138215A1 (zh) 2022-01-18 2022-11-25 可编程数据平面在运行时的更新方法及装置

Country Status (2)

Country Link
CN (1) CN114416150A (zh)
WO (1) WO2023138215A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117278403A (zh) * 2023-09-18 2023-12-22 之江实验室 一种基于异构设备的增量式编译方法和系统

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114416150A (zh) * 2022-01-18 2022-04-29 清华大学 可编程数据平面在运行时的更新方法及装置
CN115086392B (zh) * 2022-06-01 2023-07-07 珠海高凌信息科技股份有限公司 一种基于异构芯片的数据平面和交换机

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103347013A (zh) * 2013-06-21 2013-10-09 北京邮电大学 一种增强可编程能力的OpenFlow网络系统和方法
US20200313999A1 (en) * 2019-03-29 2020-10-01 Barefoot Networks, Inc. Network testing using a programmable packet engine
WO2021044191A1 (en) * 2019-09-04 2021-03-11 Telefonaktiebolaget Lm Ericsson (Publ) Method for debugging the parser in programmable routers
US20210336883A1 (en) * 2020-04-28 2021-10-28 Pensando Systems Inc. Systems for providing an lpm implementation for a programmable data plane through a distributed algorithm
CN114416150A (zh) * 2022-01-18 2022-04-29 清华大学 可编程数据平面在运行时的更新方法及装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103347013A (zh) * 2013-06-21 2013-10-09 北京邮电大学 一种增强可编程能力的OpenFlow网络系统和方法
US20200313999A1 (en) * 2019-03-29 2020-10-01 Barefoot Networks, Inc. Network testing using a programmable packet engine
WO2021044191A1 (en) * 2019-09-04 2021-03-11 Telefonaktiebolaget Lm Ericsson (Publ) Method for debugging the parser in programmable routers
US20210336883A1 (en) * 2020-04-28 2021-10-28 Pensando Systems Inc. Systems for providing an lpm implementation for a programmable data plane through a distributed algorithm
CN114416150A (zh) * 2022-01-18 2022-04-29 清华大学 可编程数据平面在运行时的更新方法及装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117278403A (zh) * 2023-09-18 2023-12-22 之江实验室 一种基于异构设备的增量式编译方法和系统
CN117278403B (zh) * 2023-09-18 2024-05-24 之江实验室 一种基于异构设备的增量式编译方法和系统

Also Published As

Publication number Publication date
CN114416150A (zh) 2022-04-29

Similar Documents

Publication Publication Date Title
WO2023138215A1 (zh) 可编程数据平面在运行时的更新方法及装置
US20230289321A1 (en) Chassis controller
JP4856580B2 (ja) ネットワーク・プロセッサにおけるソフトウェアの運転中アップグレードを実行するための方法および装置
CN107181679A (zh) 一种端口绑定实现方法及装置
EP2748993B1 (en) Using transactions to compute and propagate network forwarding state
CN113934660A (zh) 加速网络分组处理
US20080256455A1 (en) Method for Defining the Physical Configuration of a Communication System
Feng et al. Enabling in-situ programmability in network data plane: From architecture to language
Lavasani et al. Compiling high throughput network processors
CN110389711A (zh) 帮助端点设备实现sr-iov功能的方法、设备和计算机程序产品
WO2017162110A1 (en) A topology-based virtual switching model with pluggable flow management protocols
WO2017167151A1 (en) Multiple provider framework for virtual switch data planes and data plane migration
Xue et al. Virtualization of table resources in programmable data plane with global consideration
US20220253583A1 (en) Message passing multi processor network for simulation vector processing
Zhang et al. Adaptive SmartNIC Offloading for Unleashing the Performance of Protocol-Oblivious Forwarding
CN118075118A (zh) 基于p4的可编程交换机任务运行时的重配置方法
Zhao Structure optimization and optimal pipeline placement in programmable data plane virtualization scheme
US8418129B1 (en) Method for automatically generating code to define a system of hardware elements
Unnikrishnan Reconfigurable technologies for next generation internet and cluster computing
Di Proietto et al. Open vSwitch kernel datapath porting from Linux to FreeBSD
Jha et al. Distributed Simulation of Dynamic and Fault Tolerant System
Vollmer A Language for Parallel Programming Definition and Innplementation on a Transputer Network

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22921639

Country of ref document: EP

Kind code of ref document: A1