WO2023137838A1

WO2023137838A1 - Semiconductor structure and manufacturing method therefor

Info

Publication number: WO2023137838A1
Application number: PCT/CN2022/079698
Authority: WO
Inventors: 陈世言
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-01-21
Filing date: 2022-03-08
Publication date: 2023-07-27
Also published as: CN116507196A

Abstract

Disclosed in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor. The manufacturing method comprises: providing a wafer, wherein the wafer comprises an incomplete chip area located at an edge and a complete chip area surrounded by the incomplete chip area; forming a photoresist on the wafer; radiating the photoresist on the incomplete chip area and the complete chip area respectively by using light beams having different energy; developing the photoresist, wherein the photoresist on the incomplete chip area is reserved, and the photoresist on the complete chip area is removed; and performing an etching process on the wafer to form a capacitor hole in the complete chip area.

Description

A kind of semiconductor structure and its manufacturing method

Cross References to Related Applications

This disclosure is based on the Chinese patent application with the application number 202210072188.5, the filing date is January 21, 2022, and the title of the invention is "a semiconductor structure and its manufacturing method", and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated by reference into this disclosure.

technical field

The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof.

Background technique

Semiconductor structures, such as wafers, often include incomplete chip regions in edge regions. When the capacitor hole is formed by etching above the wafer, due to the thinner film thickness and poorer appearance formed above the incomplete chip region, and the faster etching rate during etching, etc., the capacitor hole formed above the incomplete chip region is prone to over-etching, which in turn leads to collapse or peeling off of the finally formed part of the capacitor column, affecting the yield of the semiconductor structure.

In the prior art, the incomplete chip region is usually covered by a wafer edge exposure (Litho Edge Exposure, LEE) process, so as to avoid forming capacitor holes on the incomplete chip region. However, the LEE process has disadvantages such as inability to measure and compensate overlay accuracy (Over Lay, OVL) and high cost.

Contents of the invention

An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:

providing a wafer comprising a non-complete chip region at an edge and a complete chip region surrounded by the non-complete chip region;

forming a photoresist on the wafer;

using beams of different energies to irradiate the photoresist on the incomplete chip region and the complete chip region respectively;

Developing the photoresist; wherein, the photoresist on the incomplete chip area is retained, and the photoresist on the complete chip area is removed;

performing an etching process on the wafer to form capacitor holes in the complete chip area.

In some embodiments, the photoresist is a positive photoresist; the use of beams of different energies to irradiate the photoresist on the incomplete chip region and the complete chip region respectively includes: using beams of first energy and second energy to irradiate the photoresist on the incomplete chip region and the complete chip region respectively; wherein, the value of the first energy is less than the activation threshold of the photoresist, and the value of the second energy is greater than or equal to the activation threshold of the photoresist.

In some embodiments, using beams of first energy and second energy to irradiate the photoresist on the incomplete chip area and the complete chip area respectively includes: acquiring position information of the incomplete chip area and the complete chip area; setting the radiation energy of the beam according to the position information; wherein, setting the energy of the beam radiated to the incomplete chip area as the first energy, and setting the energy of the beam radiated to the complete chip area as the second energy.

In some embodiments, the value of the first energy is zero.

In some embodiments, the photoresist is a negative photoresist; the use of beams of different energies to irradiate the photoresist on the incomplete chip region and the complete chip region respectively includes: using beams of third energy and fourth energy to irradiate the photoresist on the incomplete chip region and the complete chip region respectively; wherein, the value of the third energy is greater than or equal to the activation threshold of the photoresist, and the value of the fourth energy is smaller than the activation threshold of the photoresist.

In some embodiments, using beams of third energy and fourth energy to irradiate the photoresist on the incomplete chip area and the complete chip area respectively includes: acquiring position information of the incomplete chip area and the complete chip area; setting the radiation energy of the beam according to the position information; wherein, setting the energy of the beam radiated to the incomplete chip area as the third energy, and setting the energy of the beam radiated to the complete chip area as the fourth energy.

In some embodiments, prior to forming the photoresist on the wafer, the method further includes forming a mask stack on the wafer.

In some embodiments, the mask stack includes a target mask layer, a first mask layer, and a second mask layer; forming the mask stack includes: forming a target mask layer on the wafer; forming a first mask layer on the target mask layer; and forming a second mask layer on the first mask layer.

In some embodiments, the mask stack further includes a first buffer layer and a second buffer layer; forming a first mask layer on the target mask layer includes: forming a first buffer layer on the target mask layer, and forming a first mask layer on the first buffer layer;

Forming a second mask layer on the first mask layer includes: forming a second buffer layer on the first mask layer, and forming a second mask layer on the second buffer layer.

In some embodiments, the first mask layer includes a plurality of first sidewall layers extending along a first direction, and a buried layer located between the first sidewall layers; forming the first mask layer on the first buffer layer includes:

forming a first sacrificial mask layer on the first buffer layer;

etching the first sacrificial mask layer to form a plurality of first sacrificial mask patterns extending along a first direction;

forming a first initial spacer layer on the first buffer layer and the plurality of first sacrificial mask patterns;

Etching back the first initial spacer layer to form a first spacer layer; the first spacer layer covers side surfaces of the first sacrificial mask pattern;

removing the first sacrificial mask pattern;

A buried layer is formed between the first sidewall layers, and the upper surface of the buried layer is flush with the upper surface of the first sidewall layer.

In some embodiments, the second mask layer includes a plurality of second sacrificial mask patterns extending along a second direction, and a second initial spacer layer covering the second sacrificial mask patterns and the second buffer layer; forming the second mask layer on the second buffer layer includes:

forming a second sacrificial mask layer on the second buffer layer;

etching the second sacrificial mask layer to form a plurality of second sacrificial mask patterns extending along a second direction;

A second initial spacer layer is formed on the second buffer layer and the second sacrificial mask pattern.

In some embodiments, before performing the etching process on the wafer, the method further includes: processing the mask stack to form a target mask pattern.

In some embodiments, processing the mask stack includes:

etching back the second initial spacer layer to form a second sidewall layer covering side surfaces of the second sacrificial mask pattern;

removing the second sacrificial mask pattern;

The target mask layer is etched down by using the second sidewall layer and the first sidewall layer as a mask to form the target mask pattern.

In some embodiments, the target mask layer includes a first sublayer, a second sublayer, and a third sublayer arranged from bottom to top; etching the target mask layer includes:

etching the third sublayer and the second sublayer to form a third subpattern and a second subpattern respectively;

The first sub-layer is etched using the third sub-pattern and the second sub-pattern as a mask to form the target mask pattern.

In some embodiments, the wafer includes a bottom supporting layer, a first sacrificial layer, an intermediate supporting layer, a second sacrificial layer, and a top supporting layer arranged from bottom to top; performing an etching process on the wafer includes:

Using the target mask pattern as a mask, etch the top supporting layer, the second sacrificial layer, the middle supporting layer, the first sacrificial layer and the bottom supporting layer from top to bottom to form capacitor holes in the complete chip area.

An embodiment of the present disclosure also provides a semiconductor structure, which is fabricated by any one of the methods described above.

The semiconductor structure and the manufacturing method thereof provided by the embodiments of the present disclosure, wherein the manufacturing method includes: providing a wafer, the wafer including an incomplete chip region located at the edge and a complete chip region surrounded by the incomplete chip region; forming a photoresist on the wafer; using beams of different energies to irradiate the photoresist on the incomplete chip region and the complete chip region respectively; developing the photoresist; wherein the photoresist on the incomplete chip region is retained, and the photoresist on the complete chip region is removed; etching process to form capacitor holes in the complete chip area. In the embodiments of the present disclosure, light beams with different energies are used to irradiate the photoresist on the incomplete chip area and the complete chip area respectively, so that after the development process, the photoresist on the incomplete chip area is retained, and the photoresist on the complete chip area is removed. This exposure method can perform OVL measurement and OVL compensation during photolithography, which improves the photolithography accuracy and can also reduce costs.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the accompanying drawings used in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative work.

FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a wafer provided by an embodiment of the present disclosure;

FIG. 3 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

4 to 23 are schematic cross-sectional structure diagrams taken along the line AA' of FIG. 3 in various steps in the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment are not described here, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Whereas a second element, component, region, layer or section is discussed, it does not indicate that the present disclosure necessarily presents a first element, component, region, layer or section.

Spatially relative terms such as "under", "beneath", "beneath", "under", "on", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not to be taken as a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, determine the presence of said features, integers, steps, operations, elements and/or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

A semiconductor structure, such as a wafer, generally includes a non-complete chip region located in an edge region and a complete chip region surrounded by the non-complete chip region. When the capacitor holes are etched above the wafer, due to the thinner film thickness and poorer appearance formed above the incomplete chip region, and the faster etching rate during etching, etc., the capacitor holes formed above the incomplete chip region are prone to over-etching, which in turn leads to the collapse or peeling of part of the finally formed capacitor columns, affecting the yield of the semiconductor structure.

In the prior art, the incomplete chip region is usually covered by a wafer edge exposure (Litho Edge Exposure, LEE) process, so as to avoid forming capacitor holes on the incomplete chip region. The LEE process is carried out in a coating and developing device, and the specific steps include: first, coating photoresist on the surface of the wafer; then, exposing the incomplete chip area located at the edge area of the wafer when the wafer is rotated; then, performing a developing process to remove the photoresist located on the complete chip area and retain the photoresist located on the incomplete chip area. However, the LEE process has disadvantages such as inability to perform OVL measurement and compensation, and high cost.

Based on this, the following technical solutions of the disclosed embodiments are proposed:

An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, please refer to FIG. 1 for details. As shown, the method includes the following steps:

Step 101, providing a wafer, the wafer includes an incomplete chip area located at the edge and a complete chip area surrounded by the incomplete chip area;

Step 102, forming a photoresist on the wafer;

Step 103, using beams of different energies to irradiate the photoresist on the incomplete chip area and the complete chip area respectively;

Step 104, developing the photoresist; wherein, the photoresist on the incomplete chip area is retained, and the photoresist on the complete chip area is removed;

Step 105 , performing an etching process on the wafer to form capacitor holes in the complete chip area.

In the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, beams of different energies are used to irradiate the photoresist on the incomplete chip region and the complete chip region respectively, so that after a development process, the photoresist on the incomplete chip region is retained and the photoresist on the complete chip region is removed. This exposure method can perform OVL measurement and OVL compensation during lithography, which can reduce costs while improving lithography precision.

The manufacturing method provided by the embodiment of the present disclosure can be used to manufacture a dynamic random access memory (DRAM), especially a DRAM with a technology node below 19nm. But not limited thereto, the fabrication method can also be used to fabricate any semiconductor structure.

The specific implementation manners of the present disclosure will be described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the convenience of illustration, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present disclosure.

2 is a schematic diagram of a wafer provided by an embodiment of the present disclosure; FIG. 3 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure; FIGS. 4 to 23 are schematic cross-sectional structural diagrams taken along the line AA' of FIG. The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be further described in detail below with reference to FIG. 4 to FIG. 23 .

Firstly, step 101 is executed, as shown in FIG. 2 and FIG. 4 , a wafer 20 is provided, and the wafer 20 includes an incomplete chip area 20 a located at the edge and a complete chip area 20 b surrounded by the incomplete chip area 20 a.

The wafer 20 may be a circular semiconductor wafer, for example, a silicon wafer, and the silicon wafer may be doped or undoped. As shown in FIG. 2 , in one embodiment, the wafer 20 is divided into a plurality of complete chips C2 having a rectangular shape and a plurality of incomplete chips C1 having an irregular shape; the plurality of incomplete chips C1 are located on the edge of the wafer to form the incomplete chip region 20a, and the plurality of complete chips C2 are surrounded by the plurality of incomplete chips C1 to form the complete chip region 20b.

In one embodiment, the wafer 20 has structures such as word lines, bit lines, active regions, isolation structures, and contact layers. In a specific embodiment, the wafer 20 further includes a bottom supporting layer 21 , a first sacrificial layer 22 , a middle supporting layer 23 , a second sacrificial layer 24 and a top supporting layer 25 arranged from bottom to top.

Subsequently, capacitor holes 38 will be formed in the bottom supporting layer 21 , the first sacrificial layer 22 , the middle supporting layer 23 , the second sacrificial layer 24 and the top supporting layer 25 (see FIG. 21 ). Afterwards, capacitive material can be filled in the capacitor hole to form a capacitor column. The bottom support layer 21 , the middle support layer 23 and the top support layer 25 have relatively high hardness for supporting the capacitor column.

In an embodiment, the material of the bottom support layer 21 , the middle support layer 23 and the top support layer 25 may be silicon carbide nitride. But not limited thereto, the material of the bottom support layer 21 , the middle support layer 23 and the top support layer 25 may also be silicon oxynitride or silicon nitride. After forming a lower electrode layer 39 (see Figure 21) in the capacitor holes 39 (see Figure 22), the first sacrifice layer 22 and the second sacrifice layer 24 will be removed through the etching process. Therefore, under the preset etching conditions, the first sacrifice layer 22 and the second sacrifice layer 24 and the underlying support layer 21. 3 and the top layer support layer 25 have a large etching choice ratio, which can include but not limited to silicon oxide.

Next, step 102 is performed, as shown in FIG. 15 , a photoresist 37 is formed on the wafer 20 .

Specifically, the photoresist is formed on the incomplete chip region and the complete chip region. The photoresist can be a positive photoresist or a negative photoresist. The photoresist is photochemically sensitive. Subsequently, the photoresist is irradiated with a beam of a certain wavelength, and then the photoresist is placed in a developing solution for development. The solubility of the photoresist in the developing solution after being irradiated by the beam is related to the energy of the beam. In one embodiment, the photoresist has an activation threshold under the irradiation of a preset beam with a certain wavelength. For the positive photoresist, the activation threshold refers to the minimum radiant energy required for the photoresist to be completely dissolved after the development process; for the negative photoresist, the activation threshold refers to the minimum radiant energy required for the photoresist to be completely insoluble after the development process. In other words, when the energy of the light beam is greater than the activation threshold, the photoresist is fully photosensitive, and when the energy of the light beam is less than the activation threshold, the photoresist is completely insensitive. In an actual process, the activation threshold has a certain distribution interval.

In one embodiment, before forming the photoresist 37 on the wafer 20 , the method further includes: forming a mask stack MS on the wafer 20 , as shown in FIGS. 5 to 14 .

Specifically, the mask stack MS includes a target mask layer 26, a first mask layer 32, and a second mask layer 36; forming the mask stack MS includes:

forming a target mask layer 26 on the wafer 20, as shown in FIG. 5;

forming a first mask layer 32 on the target mask layer 26, as shown in FIGS. 6 to 11;

A second mask layer 36 is formed on the first mask layer 32 , as shown in FIGS. 12 to 14 .

Referring again to FIG. 5 , in one embodiment, the target mask layer 26 includes a first sub-layer 261 , a second sub-layer 262 and a third sub-layer 263 arranged from bottom to top. The target mask layer 26 with a multi-layer structure can improve the accuracy of pattern transfer, thereby ensuring better uniformity of the finally formed capacitor holes 38 (refer to FIG. 21 ). The materials of the first sublayer 261 , the second sublayer 262 and the third sublayer 263 may be different. Specifically, the first sublayer 261 may include but not limited to an amorphous carbon layer; the material of the second sublayer 262 may include but not limited to silicon oxide; the third sublayer 263 may include but not limited to a spin-on hard mask layer, and the spin-on hard mask layer may include an amorphous carbon layer or an amorphous silicon layer.

In an embodiment, the mask stack MS further includes a first buffer layer 27 and a second buffer layer 33; referring again to FIG. 6 to FIG. 11 , forming a first mask layer 32 on the target mask layer 26 includes: forming a first buffer layer 27 on the target mask layer 26, and forming a first mask layer 32 on the first buffer layer 27;

Referring again to FIGS. 12 to 14 , forming the second mask layer 36 on the first mask layer 32 includes: forming a second buffer layer 33 on the first mask layer 32 , and forming a second mask layer 36 on the second buffer layer 33 .

The first buffer layer 27 and the second buffer layer 33 may serve as etching stop layers, and the material of the first buffer layer 27 and the second buffer layer 33 may be silicon oxynitride. But not limited thereto, the material of the first buffer layer 27 and the second buffer layer 33 may also be silicon nitride or silicon carbide nitride.

Referring to FIGS. 6 to 11 again, in one embodiment, the first mask layer 32 includes a plurality of first sidewall layers 29a extending along a first direction (see FIG. 3 ), and the buried layer 31 between the first sidewall layers 29a; the first mask layer 32 is formed on the first buffer layer 27, including:

forming a first sacrificial mask layer 28 on the first buffer layer 27, as shown in FIG. 6;

Etching the first sacrificial mask layer 28 to form a plurality of first sacrificial mask patterns 28a extending along the first direction, as shown in FIG. 7 ;

Forming a first initial spacer layer 29 on the first buffer layer 27 and the plurality of first sacrificial mask patterns 28a, as shown in FIG. 8 ;

Etching back the first initial spacer layer 29 to form a first sidewall layer 29a; the first sidewall layer 29a covers the side surface of the first sacrificial mask pattern 28a, as shown in FIG. 9, the extension direction of the first sidewall layer 29a is the same as that of the first sacrificial mask pattern 28a;

removing the first sacrificial mask pattern 28a, as shown in FIG. 10;

A buried layer 31 is formed between the first sidewall layers 29a, and the upper surface of the buried layer 31 is flush with the upper surface of the first sidewall layer 29a, as shown in FIG. 11 .

The first sacrificial mask layer 28 may be a multilayer structure, for example, the first sacrificial mask layer 28 may include a spin-on hard mask layer (not shown) and a silicon oxynitride layer (not shown) on the spin-on hard mask layer (not shown). The material of the first initial spacer layer 29 may be silicon oxide. The buried layer 31 may be a spin-on hard mask layer.

Referring to FIGS. 12 to 14 again, in one embodiment, the second mask layer 36 includes a plurality of second sacrificial mask patterns 34a extending along a second direction (see FIG. 3 ), and a second initial spacer layer 35 covering the second sacrificial mask patterns 34a and the second buffer layer 33; forming the second mask layer 36 on the second buffer layer 33 includes:

forming a second sacrificial mask layer 34 on the second buffer layer 33, as shown in FIG. 12;

Etching the second sacrificial mask layer 34 to form a plurality of second sacrificial mask patterns 34a extending along the second direction, as shown in Figure 13;

A second initial spacer layer 35 is formed on the second buffer layer 33 and the second sacrificial mask pattern 34a, as shown in FIG. 14 .

In one embodiment, the second direction is oblique to the first direction, that is, the second sacrificial mask pattern 34 a is oblique to the first sidewall layer 29 a.

The second sacrificial mask layer 34 may be a multilayer structure, for example, the second sacrificial mask layer 34 may include a spin-on hard mask layer (not shown) and a silicon oxynitride layer (not shown) on the spin-on hard mask layer (not shown). The material of the second initial spacer layer 35 may be silicon oxide. In one embodiment, the material of the second sacrificial mask layer 34 is the same as that of the first sacrificial mask layer 28 , and the material of the second initial spacer layer 35 is the same as that of the first initial spacer layer 29 .

As shown in FIG. 15 , in one embodiment, the photoresist 37 covers the surface of the second initial spacer layer 35 .

Next, step 103 is executed, as shown in FIG. 16 , beams of different energies are used to irradiate the photoresist 37 on the incomplete chip region 20 a and the complete chip region 20 b respectively.

In one embodiment, the photoresist 37 is a positive photoresist; the use of beams of different energies to irradiate the photoresist 37 on the incomplete chip region 20a and the complete chip region 20b respectively includes: using beams of first energy and second energy to irradiate the photoresist 37 on the incomplete chip region 20a and the complete chip region 20b respectively, as shown in FIG. Glue 37 activation threshold. In this way, the photoresist located on the complete chip region 20b is completely photosensitive, and when the photoresist 37 is subsequently developed, the photoresist located on the complete chip region 20b will be completely dissolved in the developing solution, while the photoresist 37 located on the incomplete chip region 20a will be retained.

More specifically, irradiating the photoresist 37 on the incomplete chip region 20a and the complete chip region 20b with light beams of the first energy and the second energy respectively includes: acquiring position information of the incomplete chip region 20a and the complete chip region 20b; setting the radiation energy of the beam according to the position information; wherein, setting the energy of the beam radiated to the incomplete chip region 20a as the first energy, and setting the energy of the beam radiated to the complete chip region 20b as the second energy. In an embodiment, the value of the first energy is zero.

In another embodiment, the photoresist can also be a negative photoresist; the use of beams of different energies to irradiate the photoresist 37 on the incomplete chip region 20a and the complete chip region 20b respectively includes: using beams of third energy and fourth energy to irradiate the photoresist 37 on the incomplete chip region 20a and the complete chip region 20b respectively; wherein, the value of the third energy is greater than or equal to the activation threshold of the photoresist 37, and the value of the fourth energy is smaller than the activation of the photoresist 37 threshold. In this way, the photoresist located on the incomplete chip region 20a is completely photosensitive, and when the photoresist 37 is subsequently developed, the photoresist located on the incomplete chip region 20a will be retained, while the photoresist 37 located on the complete chip region 20b will be completely dissolved in the developing solution.

More specifically, irradiating the photoresist 37 on the incomplete chip region 20a and the complete chip region 20b with beams of third energy and fourth energy respectively includes: obtaining position information of the incomplete chip region 20a and the complete chip region 20b; setting the radiation energy of the beam according to the position information; wherein, setting the energy of the beam radiated to the incomplete chip region 20a as the third energy, and setting the energy of the beam radiated to the complete chip region 20b as the fourth energy. In an embodiment, the value of the fourth energy is 0.

Next, step 104 is performed, as shown in FIG. 17 , the photoresist 37 is developed; wherein, the photoresist 37 on the incomplete chip region 20a is retained, and the photoresist 37 on the complete chip region 20b is removed.

In this way, the embodiment of the present disclosure uses beams of different energies to irradiate the photoresist 37 on the incomplete chip region 20a and the complete chip region 20b respectively, so that after the development process, the photoresist 37 on the incomplete chip region 20a is retained, and the photoresist 37 on the complete chip region 20b is removed. This exposure method can perform OVL measurement and OVL compensation during photolithography, improving the photolithography accuracy. In addition, the embodiment of the present disclosure saves the process step of LEE and saves the manufacturing cost of the semiconductor structure.

Finally, step 105 is performed, as shown in FIG. 21 , performing an etching process on the wafer 20 to form capacitor holes 38 in the complete chip region 20 b.

In an embodiment, before performing the etching process on the wafer 20 , the method further includes: processing the mask stack MS to form a target mask pattern 261 a , as shown in FIGS. 18 to 20 .

Specifically, processing the mask stack MS includes:

Etching back the second initial spacer layer 35 to form a second sidewall layer 35a, the second sidewall layer 35a covers the side surface of the second sacrificial mask pattern 34a, as shown in FIG. 18, the extension direction of the second sidewall layer 35a is the same as the extension direction of the second sacrificial mask pattern 34a;

removing the second sacrificial mask pattern 34a, as shown in FIG. 19;

The target mask layer 26 is etched down using the second sidewall layer 35 a and the first sidewall layer 29 a as a mask to form the target mask pattern 261 a, as shown in FIG. 20 .

As shown in FIG. 3 , the first sidewall layer 29a extends along a first direction, the second sidewall layer 35a extends along a second direction, and the first direction and the second direction are oblique, so that the target mask pattern 261a having a hole structure can be obtained.

It can be understood that since the incomplete chip region 20a is covered by the photoresist 37, the pattern will not be transferred downward in the incomplete chip region 20a during the process of processing the mask stack MS to transfer the pattern downward.

More specifically, using the second sidewall layer 35a and the first sidewall layer 29a as a mask to etch down the target mask layer 26 includes: first, using the second sidewall layer 35a as a mask to etch the exposed second buffer layer 33; then, using the second sidewall layer 35a and the remaining second buffer layer 33 as a mask to etch the exposed buried layer 31, and the first sidewall layer 29a will not be removed during this process; 35a, the remaining second buffer layer 33, the first sidewall layer 29a and the remaining buried layer 31 are used as masks to sequentially etch the exposed first buffer layer 27 and the target mask layer 26 to form the target mask pattern 261a.

Referring again to FIG. 20 , in one embodiment, etching the target mask layer 26 includes:

Etching the third sub-layer 263 and the second sub-layer 262 to form a third sub-pattern 263a and a second sub-pattern 262a respectively;

Using the third sub-pattern 263a and the second sub-pattern 262a as a mask, the first sub-layer 261 is etched to form the target mask pattern 261a.

In one embodiment, performing an etching process on the wafer 20 includes:

Using the target mask pattern 261a as a mask, etch the top supporting layer 25, the second sacrificial layer 24, the middle supporting layer 23, the first sacrificial layer 22 and the bottom supporting layer 21 from top to bottom to form capacitor holes 38 in the complete chip area 20b, as shown in FIG. 21 . The capacitor hole 38 runs through the top supporting layer 25 , the second sacrificial layer 24 , the middle supporting layer 23 , the first sacrificial layer 22 and the bottom supporting layer 21 .

In one embodiment, after forming the capacitor hole 38 in the complete chip area 20b, it further includes: forming a lower electrode layer 39 on the side surface and the bottom surface of the capacitor hole 38, as shown in FIG. 22; removing the second sacrificial layer 24 and the first sacrificial layer 22 located in the complete chip area 20b, as shown in FIG. 23. Afterwards, the dielectric layer and the upper electrode layer may be continuously filled in the capacitor hole, and the dielectric layer, the upper electrode layer and the lower electrode layer 39 constitute an array capacitor column. The material of the lower electrode layer 39 may be titanium nitride, copper, tungsten or tantalum nitride.

In the embodiment of the present disclosure, by covering the incomplete chip region 20a and forming the capacitor hole 38 only in the complete chip region 20b, the probability of over-etching that occurs when the capacitor hole 38 is formed due to the difference in the shape and etching rate between the incomplete chip region 20a and the complete chip region 20b is effectively reduced or eliminated, thereby reducing or eliminating the possibility of the lower electrode layer 39 collapsing or peeling off after removing the first sacrificial layer 22 and the second sacrificial layer 24, and improving semiconductor performance. Structural yield.

In a specific embodiment, removing the second sacrificial layer 24 and the first sacrificial layer 22 includes: first, forming at least one first opening (not shown) on the top support layer 25 to expose the second sacrificial layer 24; then, performing a wet etching process to remove the second sacrificial layer 24; then, forming at least one second opening (not shown) on the middle support layer 23 to expose the first sacrificial layer 22; then, performing a wet etching process to remove the first sacrificial layer 22.

It should be noted that those skilled in the art can make possible changes between the sequence of the above steps without departing from the protection scope of the present disclosure.

It should be noted that the above descriptions are only optional embodiments of the present disclosure, and are not used to limit the protection scope of the present disclosure. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Industrial Applicability

In the embodiments of the present disclosure, light beams with different energies are used to irradiate the photoresist on the incomplete chip area and the complete chip area respectively, so that after the development process, the photoresist on the incomplete chip area is retained, and the photoresist on the complete chip area is removed. This exposure method can perform OVL measurement and OVL compensation during photolithography, which improves the photolithography precision and can also reduce costs.

Claims

A method of fabricating a semiconductor structure, comprising:

providing a wafer comprising a non-complete chip region at an edge and a complete chip region surrounded by the non-complete chip region;

forming a photoresist on the wafer;

using beams of different energies to irradiate the photoresist on the incomplete chip region and the complete chip region respectively;

Developing the photoresist; wherein, the photoresist on the incomplete chip area is retained, and the photoresist on the complete chip area is removed;

performing an etching process on the wafer to form capacitor holes in the complete chip area.
The manufacturing method according to claim 1, wherein the photoresist is a positive photoresist; said using light beams of different energies to irradiate the photoresist on the incomplete chip region and the complete chip region respectively comprises: using beams of first energy and second energy to irradiate the photoresist on the incomplete chip region and the complete chip region respectively; wherein the value of the first energy is less than the activation threshold of the photoresist, and the value of the second energy is greater than or equal to the activation threshold of the photoresist.
The method according to claim 2, wherein irradiating the photoresist on the incomplete chip area and the complete chip area with light beams of first energy and second energy respectively comprises: obtaining position information of the incomplete chip area and the complete chip area; setting the radiation energy of the beam according to the position information; wherein, setting the energy of the beam radiated to the incomplete chip area as the first energy, and setting the energy of the beam radiated to the complete chip area as the second energy.
The manufacturing method according to claim 2, wherein the value of the first energy is zero.
The manufacturing method according to claim 1, wherein the photoresist is a negative photoresist; said using beams of different energies to irradiate the photoresist on the incomplete chip region and the complete chip region respectively comprises: using beams of third energy and fourth energy to irradiate the photoresist on the incomplete chip region and the complete chip region respectively; wherein the value of the third energy is greater than or equal to the activation threshold of the photoresist, and the value of the fourth energy is smaller than the activation threshold of the photoresist.
The manufacturing method according to claim 5 , wherein irradiating the photoresist on the incomplete chip area and the complete chip area with light beams of third energy and fourth energy respectively comprises: obtaining position information of the incomplete chip area and the complete chip area; setting the radiation energy of the light beam according to the position information; wherein, setting the energy of the beam radiated to the incomplete chip area as the third energy, and setting the energy of the beam radiated to the complete chip area as the fourth energy.
The manufacturing method according to claim 1, wherein, before forming the photoresist on the wafer, the method further comprises: forming a mask stack on the wafer.
The manufacturing method according to claim 7, wherein the mask stack includes a target mask layer, a first mask layer, and a second mask layer; forming the mask stack includes: forming a target mask layer on the wafer; forming a first mask layer on the target mask layer; forming a second mask layer on the first mask layer.
The manufacturing method according to claim 8, wherein the mask stack further includes a first buffer layer and a second buffer layer; forming the first mask layer on the target mask layer comprises: forming a first buffer layer on the target mask layer, and forming a first mask layer on the first buffer layer;

Forming a second mask layer on the first mask layer includes: forming a second buffer layer on the first mask layer, and forming a second mask layer on the second buffer layer.
The manufacturing method according to claim 9, wherein the first mask layer includes a plurality of first sidewall layers extending along a first direction, and a buried layer located between the first sidewall layers; forming the first mask layer on the first buffer layer comprises:

forming a first sacrificial mask layer on the first buffer layer;

etching the first sacrificial mask layer to form a plurality of first sacrificial mask patterns extending along a first direction;

forming a first initial spacer layer on the first buffer layer and the plurality of first sacrificial mask patterns;

Etching back the first initial spacer layer to form a first spacer layer; the first spacer layer covers side surfaces of the first sacrificial mask pattern;

removing the first sacrificial mask pattern;

A buried layer is formed between the first sidewall layers, and the upper surface of the buried layer is flush with the upper surface of the first sidewall layer.
The manufacturing method according to claim 10, wherein the second mask layer comprises a plurality of second sacrificial mask patterns extending along a second direction, and a second initial spacer layer covering the second sacrificial mask patterns and the second buffer layer; forming the second mask layer on the second buffer layer comprises:

forming a second sacrificial mask layer on the second buffer layer;

etching the second sacrificial mask layer to form a plurality of second sacrificial mask patterns extending along a second direction;

A second initial spacer layer is formed on the second buffer layer and the second sacrificial mask pattern.
The manufacturing method according to claim 11 , wherein, before performing the etching process on the wafer, the method further comprises: processing the mask stack to form a target mask pattern.
The manufacturing method according to claim 12, wherein processing the mask stack comprises:

etching back the second initial spacer layer to form a second sidewall layer covering side surfaces of the second sacrificial mask pattern;

removing the second sacrificial mask pattern;

The target mask layer is etched down by using the second sidewall layer and the first sidewall layer as a mask to form the target mask pattern.
The manufacturing method according to claim 13, wherein the target mask layer comprises a first sublayer, a second sublayer and a third sublayer arranged from bottom to top; etching the target mask layer comprises:

etching the third sublayer and the second sublayer to form a third subpattern and a second subpattern respectively;

The first sub-layer is etched using the third sub-pattern and the second sub-pattern as a mask to form the target mask pattern.
The manufacturing method according to claim 12, wherein the wafer comprises a bottom supporting layer, a first sacrificial layer, an intermediate supporting layer, a second sacrificial layer and a top supporting layer arranged from bottom to top; performing an etching process on the wafer comprises:

Using the target mask pattern as a mask, etch the top supporting layer, the second sacrificial layer, the middle supporting layer, the first sacrificial layer and the bottom supporting layer from top to bottom to form capacitor holes in the complete chip area.
A semiconductor structure manufactured by the method according to any one of claims 1-15.