WO2023134966A1 - Method for processing an optoelectronic device and optoelectronic device - Google Patents

Method for processing an optoelectronic device and optoelectronic device Download PDF

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WO2023134966A1
WO2023134966A1 PCT/EP2022/086599 EP2022086599W WO2023134966A1 WO 2023134966 A1 WO2023134966 A1 WO 2023134966A1 EP 2022086599 W EP2022086599 W EP 2022086599W WO 2023134966 A1 WO2023134966 A1 WO 2023134966A1
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catalyst metal
semiconductor layer
layer stack
semiconductor
depositing
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PCT/EP2022/086599
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French (fr)
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Martin Hetzl
Laura KREINER
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Ams-Osram International Gmbh
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
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    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction

Definitions

  • the present invention concerns a method for processing an optoelectronic device and an optoelectronic device .
  • a pLED corresponds to an optoelectronic device with a diameter of smaller than 70pm and particularly in the range of 0 , 5pm to approximately 20pm .
  • NRR non-radiative recombination
  • RR radiative recombination
  • pLEDs which are configured to emit red, or reddish light and which are based on the InGaN, InGaP or InGaAlP material system suffer from these drawbacks .
  • the presence of Indium in such systems with the choice to shift the bandgap to the desired energy causes an increasing charge carrier diffusion length with the above mentioned increased probability for NRR in such material systems .
  • the Fermi level may be pinned to the semiconductor surface .
  • the inventors have come up with another option to reduce the NRR close to the edges of the active region in very small LEDs , which is based on the so called overgrowing principle .
  • the edges of the active region are overgrown with a material having a larger bandgap than the material of the active region . This will prevent charge carrier from reaching the edges and thus reduce NRR .
  • the approach is feasible it requires a high precision and high alignment for the respective structured mas ks to ensure proper overgrowth .
  • the inventors realized that self-structuring and self-positioning during the growth of the functional layer stack as well as the material used for overgrowth would be a solution offering both simplicity and high precision and alignment .
  • the inventors propose a method utilizing transition of the material to be deposited from its vaporous form to a solid form via a liquid .
  • This approach is also referred to as a VLS-process from its three phases ( gas phase , liquid phase and solid phase ) .
  • the material to be deposited for a semiconductor layer is provided in a gas phase and deposited utilizing a liquid catalyst metal .
  • the process parameter for this process are adj usted in such way that a direct deposition of the semiconductor layer material cannot take place . Rather , the material diffuses into the metal catalyst and is -from there- deposited on the surface thus forming the semiconductor layer .
  • semiconductor material is grown at locations of the metal catalyst droplets .
  • Proper choice of the catalyst metal allows the processing of very small pLEDs with high density maintaining high quality for the individual devices .
  • the metal itself is preferably neither consumed nor included in the crystal structure and acts as a catalyst for the overall growth process .
  • the self-organisation of the metal catalyst following the grown semiconductor acts as a benefit , because subsequent layers can be deposited and grown on the same location .
  • the process parameter, for instant temperature and pressure are adj usted in such way that the catalyst metal comprises a certain shape and wetting behaviour . Consequently, the semiconductor material is deposited only at those locations , which are wetted by the catalyst metal but nowhere else ( due to the selected process parameter rendering it impossible to deposit the material somewhere else ) .
  • the shape of the metal catalyst can be adj usted in such way that it can cover not only the top layer surface but also the side surface of the active region grown in previous steps . This coverage allows to overgrow the edges of the active region with a suitable semiconductor material in a precise and high-quality fashion .
  • the metal catalyst can be removed after processing the device , but also reused, e . g . as contact or reflective layers and the like .
  • the presented methods and aspects thereof can be applied to a variety of semiconductor material systems including not only binary but also ternary and even quaterny material systems .
  • Examples for such systems include but are not limited to GaN, GaP, GaAs , AlGaN, AlGaP, AlGaAs , InGaN, InGaP, InGaAs , AlInGaN and AlInGaP as well as any combinations thereof .
  • the content of the individual elements namely Aluminum and Indium may vary throughout the deposition of the various layers .
  • the inventors propose a method for processing an optoelectronic device .
  • the method comprises the step of providing a structured mask including portions covered by mask material and exposed portions on a surface of a doped layer arranged on a growth substrate .
  • exposed portions usually refer to portions of the top surface not covered by any mas k or other material .
  • doped layer refers to a semiconductor layer which includes a deliberately induced dopant e . g . during growth of the layer .
  • the dopant concentration is chosen to provide a certain electric behaviour and may often lie in the range of 3el7 atoms /cm 3 to le! 9 atoms /cm 3 .
  • One or more catalyst metal studs are generated on the exposed portions and catalyst metal droplets are subsequently formed from the catalyst metal studs wetting at least pats of the exposed portions .
  • the expression "wetting” in this regard refers to the ability of a liquid to maintain contact with a solid surface , resulting from intermolecular interactions when the two are brought together .
  • the degree of wetting is determined by a force balance between adhesive and cohesive forces . As it will be explained later in detail , the degree of wetting is adj ustable .
  • the functional layer stack i . e . forming the optoelectronic device can be grown .
  • the expression "functional layer stack” refers to a semiconductor layer stack that provides a certain electrical function .
  • a typical functional semiconductor stack is a diode , a transistor and also an optoelectronic device configured to emit light in operation .
  • an optoelectronic layer stack is used as a nonlimiting example throughout this application .
  • the expression "functional layer stack” and “functional semiconductor layer stack” are used synonymously throughout this application .
  • this application often refers to a single device or layer stack, the invention is not limited thereto . Rather, the principle disclosed herein are applicable to individual devices but also to the processing of whole wafer .
  • the material for a first semiconductor layer is provided from a gas phase .
  • the material liquefies on and in the metal catalyst droplets and solidifies on the surface part of the exposed portion wetted by the catalyst metal droplets , thus depositing as the first semiconductor layer .
  • the first semiconductor layer can be part of a functional semiconductor layer stack including an active region .
  • a functional semiconductor layer stack including an active region can be grown from a gas phase on the first semiconductor layer containing material of the semiconductor layer stack .
  • the catalyst metal droplet "moves" with the grown semiconductor layers ; that is it mainly wets the top surface layer .
  • the semiconductor layer stack can be grown in a self-organized manner similar to conventional approaches by providing the material for the respective layer to be grown .
  • the provided material is offered at a gaseous , vapour phase , transforms into the fluid or liquid phase inside the catalyst metal droplets and solidifies as a layer on the top surface wet by the droplet .
  • the catalyst metal droplets are reshaped such that they wet portions of the surface adj acent the surface of the first semiconductor layer .
  • the catalyst metal droplet has changed its wetting behaviour and now wets the top surface of the functional semiconductor layer stack as well adj acent surface portions . Consequently, the shape of the catalyst metal droplet has changed, enabling to deposit a semiconductor material for its gas phase on the top surface and on the side surface of the functional semiconductor layer stack thereby covering edge areas of the active region .
  • the catalyst metal studs may comprise at least a metal selected from a group consisting of Gold, Nickel , Gallium, Silver , Iridium, Palladium, Platinum, Lead and Titanium or combinations and alloys thereof including those elements . It may be suitable to choose a metal that is inert in regards to the semiconductor material deposited as the optoelectronic device and is not incorporated into the crystal structure . Gold and Nickel may be suitable materials , but other materials and also combinations thereof may be chosen .
  • the composition of the catalyst metal may be adj usted during the process to , for instance , change the wetting behaviour .
  • the step of generating the catalyst metal droplets may comprise increasing the temperature above the melting point of the respective catalyst metal or catalyst metal composition, such that the catalyst metal becomes liquid .
  • the metal droplet and the surface form a contact angle at their respective circumference .
  • the contact angle 0 C is the angle formed by a liquid at the three-phase boundary where the liquid, gas , and solid intersect .
  • the molten catalyst metal forms a contact angle 0 C between 70 ° and 150 ° and in particular between 80 ° and 150 ° and in particular above 85 ° .
  • angles around 90 ° are generally referred to as metal-repellent or "metallo- phobic" , angles smaller than 60 ° to 70 ° as metal-attracting or "metallo-phil” and angles larger than 105 ° to 125 ° as “super-metallo- phobic" .
  • the contact angle 0 C between the catalyst metal droplets and the surface of the exposed portion or more generally of the respective top surface wetted by the droplet is adj ustable .
  • the adj ustment is achieved by setting or varying various parameters . These parameters may include the temperature of the catalyst metal , the surface material , the catalyst material , the ambient pressure or an amount of a second catalyst metal being added to the catalyst metal droplets during a processing step .
  • the contact angle between the catalyst metal droplets and the surface of the exposed portions or any semiconductor layer is around 90 ° .
  • the contact angle between the catalyst metal droplets and the surface of the exposed portion or any semiconductor layer is larger than a contact angle between the catalyst metal droplets and the surface of the exposed portion after the step of reshaping the catalyst metal droplets .
  • the contact angle after the reshaping step may be smaller than 90 ° and can be in the range of 30 ° and 75 ° and in particular between 40 ° and 60 ° .
  • the one or more semiconductor layers may comprise buffer layers to planarize the surface , initial layers for later rebonding or for sacrificial purposes and the like .
  • the top layer of the one or more semiconductor layers (that is the last being grown) comprises a dopant to reduce the resistance value and prepare the structure for being contacted .
  • a mask material is deposited on the surface of said top surface layer and subsequently structured .
  • portions of the mask material are removed, such as to provide covered portions by the mask material and exposed portions .
  • the latter portions expose parts of the surface of the doped layer .
  • the removal of mas k portions can be done in two different variants . In one option, non-exposed portions of the mask are removed . In a second option, exposed portions are removed and the non-exposed portions of the mas k remain on the surface .
  • the mask can comprise of a photo resist or a hard mas material as SiO2 .
  • the latter requires a different application process , but can also remain on the surface for isolation and limiting purposes when the catalyst material is applied . Such approach is explained further below .
  • a catalyst metal is deposited on the surface of the doped layer and the structured mas k in a first sub-step .
  • Deposition can be archived from the gas phase by a MOCVD (Metalorganic chemical vapour deposition ) or a MOVPE (Metalorganic vapour-phase epitaxy) process .
  • MOCVD Metalorganic chemical vapour deposition
  • MOVPE Metalorganic vapour-phase epitaxy
  • Other suitable processes for depositing the catalyst metal are suitable as well .
  • the structured mas k can be removed leaving only the portions of the catalyst metal covering the previously exposed areas on the surface of the top layer .
  • the catalyst metal can be dispensed directly on the exposed portions .
  • the catalyst metal is mixed with a volatile solvent to provide an easier dispense solution .
  • the solvent vaporizes and leaves only the metal catalyst on the surface .
  • the dispense approach may be beneficial when the locations for the functional layer stack to be grown are non-periodic or an epitaxial growth is either too complex or more expensive .
  • the height of the catalyst metal applied on the exposed areas may be larger than a height of the structured mask .
  • the volume of the metal studs may be larger than the cavity volume with the exposed portions created by the structured mas k .
  • the height of the structured mask may be larger than catalyst metal .
  • the structured mask may comprise a dielectric material , particularly when the structured mask is intended to remain on the surface .
  • a dielectric material having a melting point higher than a melting point of the catalyst metal and particularly significantly higher than the melting point of the catalyst metal . This will ensure that the no dislocations or shift in the later grown functional semiconductor layer stack take place .
  • the hard mask will then act as a limitation .
  • the first semiconductor layer and the functional layer stack are formed from a gas phase , liquefies into the catalyst metal drops and then solidifies on the surface wetted by the catalyst metal in the VLS process .
  • the material for the respective layers and the layer stack can be provided in the gas phase by MOCVD (Metalorganic chemical vapour deposition) or a MOVPE (Metalorganic vapour-phase epitaxy) process .
  • MOCVD Metalorganic chemical vapour deposition
  • MOVPE Metalorganic vapour-phase epitaxy
  • At least one process parameter is adj usted to ensure that during the depositions steps the material of the first semiconductor layer and/or the semiconductor layer stack do not deposit on surface parts not covered by the catalyst metal droplets .
  • Those parameters include but are not limited to ambient temperature , surface temperature of the wafer, pressure or combinations thereof .
  • the adj ustment of the process parameter basically prevents conventional epitaxial growth of the semiconductor material on the surface .
  • the temperature and generally the process parameter do not cause dislocations or repositioning of the deposited layer material .
  • the process parameters particularly the ambient temperature is adj usted such that the catalyst metal is mainly liquid and forms the proper wetting area on the surface .
  • the height of the layer grown by the VLS process is adj ustable in an easy way, because the process parameters can be adj usted such that the catalyst metal droplets wets only the surface of the topmost layer . As a result thereof , the VLS process growing the layer will continue as long as the respective material is applied .
  • a further aspect relates to the overgrow approach, in which material with a higher bandgap is applied to the edges of the active region .
  • the shape of the catalyst metal droplet is adj usted such that the catalyst metal also covers at least the area of the active region along the side surfaces of the functional layer stack . In some instances , the metal droplet extends to the surface adj acent to the layer stack .
  • reshaping the catalyst metal droplets comprises forming a shell by the catalyst metal droplet only covering the functional layer stack and optionally including a portion of the first semiconductor layer but not the surface of the exposed portions .
  • the catalyst metal droplet therefore only wets the top layer of the functional layer stack and the side edges as well as portions of the side of the first semiconductor layer, respectively .
  • This embodiment may prevent depositing layer material in the VLS process directly on the exposed portion changing the electrical characteristics of the device .
  • a shell or hood is formed by the catalyst metal droplet covering the functional layer stack and comprising a contact angle of larger than 90 ° on the surface of the doped layer and the exposed portions .
  • Depositing a semiconductor material on the top surface and on the side surface of the semiconductor layer stack comprises providing the semiconductor material from a gas phase through the metal catalyst droplets , subsequently undergoing the VLS process .
  • the semiconductor material covering edge areas of the active region comprises a larger bandgap than the active region .
  • the side edges are re-grown using depositing a semiconductor material resulting in a change of the bandgap characteristics of the active region close to the edges .
  • the semiconductor material comprises a dopant , for example a dopant of a different type than the doped first layer .
  • the material on the side edges covering the active region may comprise a p-dopant , while the first layer includes an n-dopant .
  • Dopant concentration on the side edges may vary .
  • Zn or another suitable dopant is deposited on the side edges using VLS process causing a Quantum well intermixing in edges areas of the active region .
  • Zn may deposit also on the top of the layer stack, but will not cause a significant change due to the larger amount of bulk material therein .
  • the functional layer stack comprises an active region including a quantum well or a multi-quantum well .
  • the active region is formed of AlInGaN or AlInGaP based material with different Aluminum contents for the quantum well barriers and the quantum wells .
  • the devices and functional layer stacks processed by this proposed method can have a very small dimension .
  • diameters of a few pm are possible .
  • Such so called p-LED can have a diameter of 1pm to 15pm for example .
  • pLEDs may be smaller than 10pm in diameter .
  • large diameters in the range of 10pm to 50pm are generally possible .
  • An area may be in the range of 1pm 2 to 2000pm 2 and in particular smaller than 2000pm 2 and in particular between 4pm 2 and 400pm 2 .
  • the footprint of the layer stack is usually circular or at least curved and may comprise a rod or pillar-shaped form .
  • the method may comprise additional steps after depositing the semiconductor layer stack .
  • a transparent conductive material is deposited on at least the top surface of the deposited semiconductor material .
  • a dielectric material is grown on at least the top surface of the deposited semiconductor material .
  • the expression "on the top surface” refers to the topmost surface of the respective layer .
  • the catalyst metal droplet forms a reflective layer around the semiconductor layer stack . Consequently, the catalyst metal is reusable for a reflective layer .
  • an optical spacer element is formed between two adj acent functional layer stacks in particular .
  • the catalyst metal droplet can be utilised for depositing the spacer material , but can also be removed prior to deposition of such spacer .
  • the device comprises a functional layer stack having an active region arranged between two differently doped conductive semiconductor layers .
  • a material of one of the two differently doped semiconductor layers extends along the side surfaces of the functional layer stack covering the side edges of the active region .
  • residuals of a catalyst metal are present in at least one of the functional layer stack and the active region and the material covering the side surfaces of the functional layer .
  • the residuals of the catalyst metal comprise at least one metal selected from a group consisting of Gold, Nickel , Gallium, Silver, Iridium, Palladium, Platinum, Rhodium, Lead and Titanium .
  • the residuals are incorporated into the different semiconductor layers during the VLS process , but its respective concentration is relatively small . However, the residuals are caused by the VLS process , and are not present in such concentration in a conventional growth process .
  • Figures 1A to ID illustrate some steps of a method in accordance with some aspects of the proposed principle ;
  • Figures 2A to 2D show some further steps of the method as illustrated in Figure lin accordance with some aspects of the proposed principle ;
  • FIGS. 3A to 3D illustrate some steps of another method in accordance with some aspects of the proposed principle ;
  • Figure 4A to 4E show several method steps of processing an optoelectronic device in accordance with aspects of the proposed principle ;
  • Figure 5 illustrates an exemplary embodiment of an optoelectronic device with additional optical blocking elements as processed with method steps in accordance with the proposed principle ;
  • Figure 6 shows an exemplary embodiment of an optoelectronic device with a metal reflector as processed with method steps in accordance with the proposed principle .
  • Figure 1A to ID as well as 2A to 2D show several steps of a method for processing an optoelectronic device in accordance with some aspects of the proposed principle .
  • a growth substrate 1 is provided in a first step illustrated in Figure 1A the growth substrate comprises GaAs in this example .
  • Other suitable growth substrates include sapphire , SiO2 and the like .
  • Material of one or more layers 2 acting as buffer and initial layer are epitaxial deposited .
  • AlGaP material is used, on which also Indium may be added .
  • the growth of the initial buffer layer ( s ) 2 is conventional and generally well known .
  • an AlGaN material is used as buffer layers , the AlGaN material including different dopant concentrations and or different Al concentrations .
  • a mask material 4 is sputtered, spinned or otherwise deposited as planar on the surface . It is subsequently structured in such way as to expose a plurality of areas 21 of the surface of the top-most layer 2 .
  • the height of the structure mas k 4 is selected in a suitable way for the subsequent steps .
  • Figure IB illustrates the resulting structure .
  • Figure 1C shows the next processing step , in which a catalyst metal material 5 is deposited on the surface covering the exposed portions 21 as well as the structured remaining mask material 4 .
  • the amount of the catalyst material 5 is sufficiently large to completely cover the exposed portions 21 and also extend slightly over the structured mas k 4 .
  • it is also possible to apply less material by spinning for example which will fill-up the exposed portions 21 , but not remain on the structured mask 4 due to the spinning process .
  • Another possibility is a MOCVD process , in which the catalyst metal 5 undergoes a chemical reaction on the exposed surfaces 21 depositing thereon .
  • the material should not react with the later semiconductor material and should be inert to the following deposition of semiconductor material .
  • the melting point should not be too high to prevent evaporation, dislocations and dissolving already grown layer due to the high temperature .
  • Certain alloys having a relatively low melting point have been found to be suitable .
  • such alloy contains Gold and Nickel .
  • Other suitable metals are Palladium, Platinum, Rhodium, Silver , Titanium, Mercury, Zirconium and to some lesser extend also Copper or Lead .
  • the metal to be used for the VLS process is a catalyst metal , i . e . it is used to facilitate the deposition process , but is neither consumed nor chemically altered in the process itself .
  • the melting point of the alloy or the metal should be high enough to ensure that the semiconductor material cannot be grown directly on the surface , that is cannot be grown without the VLS process , but low enough to avoid re-evaporation of the already grown material .
  • Gallium as a potential material might be suitable , but is consumed in the process when layers based on GaN or GaP ( or material system including Ga ) are grown .
  • Dopant materials like as Zn, Mg, Si or Ge should not be used as catalyst metal , as they are dopants in atomic form and may contaminate the grown semiconductor layers .
  • the next step shown in Figure ID includes the removal of the mask portions and the catalyst metal on top, leaving only the catalyst metal as catalyst metal studs 51 behind on the surface . The height and distance of those metal studs 51 are adj ustable parameters by the previous process steps .
  • FIGS 2A to 2D illustrate the next steps including the VLS process for the processing of a device in accordance with some aspects of the proposed principle .
  • the catalyst metal studs 51 are heated either short below or even above their respective melting points resulting in a transition from their solid stated to a liquid state .
  • the catalyst metal studs 51 become respective catalyst metal droplets 52 .
  • the catalyst metal wets a certain area of its surface .
  • the catalyst metal amount of wetting and particularly the contact angle 0 can be adj usted .
  • the contact angle 0 is the angle at which the liquid-vapour interface meets the solid-liquid interface .
  • the contact angle is determined by the balance between adhesive and cohesive forces . Adhesive forces between a liquid and solid cause a liquid drop to spread across the surface . Cohesive forces within the liquid cause the drop to ball up and avoid contact with the surface . As the tendency of a drop to spread out over a flat , solid surface increases , the contact angle decreases . Thus , the contact angle provides an inverse measure of wettability .
  • the contact angle 0 is slightly larger than 90 ° , which is considered to be repellent or metallo-phobic . Consequently, an angle 0 larger than 90 ° results in an area being wet that is smaller than the maximum diameter of the catalyst metal droplet 52 .
  • the angle 0 can now be adj usted by changing the temperature of the metal droplet , the alloy composition of the metal droplet , the ambient pressure and other parameters . For example increasing the pressure may result in a decreasing angle , i . e . the metal droplet 52 being pushed onto the surface area 21 resulting in a slightly larger diameter and wet area .
  • a proper selection of the process parameters enables adj ustment of the footprint of the device to be processed .
  • the surface area wet by the metal droplet forms a circle and not a rectangular or any other ordered shape . If such footprint shall be achieved, the previously exposed areas 21 should be reduced and may be limited ( i . e . by a surrounding hard mask ) , such that the metal droplet "stays" within the exposed areas 21 .
  • Figure 2B shows the next step in the process including a first VLS process .
  • a semiconductor material is supplied in the gas phase .
  • a suitable approach for such supply might be MBE , MOVPE and the like . Due to the high temperature , the semiconductor material stays in the gas phase or vaporous phase and does not deposit in the areas between the exposed portions 21 ( or it evaporates again due to the high temperature ) .
  • the semiconductor material used for the first layer is based on InAlGaP, whereas the different components Indium, Aluminum Gallium and Phosphorus as well as respective dopants are supplied from the gas phase in their correct stoichiometric quantity .
  • the supplied material diffuses into the catalyst metal droplet due to the concentration gradient and liquefies therein . It subsequently deposits as solid material on the liquid-solid interface between the metal droplet and the surface of buffer layer 2 . This process continues as long as the respective components for the first doped semiconductor layer 6 are supplied .
  • the bandgap can be adj usted .
  • changing the dopant concentration in the supplied material adj usts the conductivity of the layer .
  • the composition is changed and Indium added in the desired amount as to grow a quantum well structure .
  • the Aluminum content is increased, for the quantum well layers decreased again .
  • less material is used, as the material deposition and the layer growth occurs only in the areas covered by the catalyst metal droplets .
  • the catalyst metal droplet moves" with the growing layer, that is it mainly wet the topmost surface .
  • This behaviour can slightly be adj usted by varying the process parameters ( i . e . if the contact angle changes due to variation in the deposited material ) .
  • the behaviour of moving of the catalyst metal droplet when more and more material is deposited is beneficial as it allows some self-structuring and self-alignment .
  • the shape can be varied and different diameters or footprint areas for the different layers can be achieved .
  • Figure 2B illustrates the resulting structure , in which one or more layers of a function layer stack 6 have been grown with the catalyst metal droplet mainly wetting the topmost surface .
  • the supply of the various material components Al , Ga, In and P including dopants for the semiconductor layers continues until at least the active region and the top contact layer of the functional layer stack is grown .
  • the process parameters are changed to spread the catalyst metal droplet extending over the top surface and wetting also the side surface of the grown functional layer stack as shown in Figure 2C .
  • the contact angle 0 is altered by the varied process parameters and decreases either close to 90 ° or even below 90 ° that is shifts towards the metal attractive or metallo-philic phase . Consequently the catalyst metal droplet now "flows" over the topmost edge of the edges of the functional layer stack and -as shown in Figure 2- reaches the surface areas adj acent to the grown functional semiconductor layer stack .
  • the side surfaces are now buried beneath the catalyst metal with a certain amount of metal covering the side surface and the topmost edge of the functional layer stack .
  • the topmost edge and/or the side surface does not lie directly under the surface of the catalyst metal droplet or even intersects the metal surface , but is completely buried with a certain distance D between the edge of the stack and the surface of the metal . Said distance is indicated in Figure 2C .
  • the material covering the side surfaces enables the edges of the active region to be overgrown by a semiconductor material having a larger bandgap than the bandgaps of the active region .
  • the components of a p-side layer in the present example are resupplied and a p-side layer deposited on the active region of the functional layer stack . Due to the reshaped form, the material of the p-side layer 7 does not only deposits on the topmost surface of the functional layer stack, but also on the side edges , thus overgrowing the edges of the active region .
  • the p-side semiconductor material for layer 7 contains a bandgap that is larger than the bandgap for the Indium including quantum well layers of the active region .
  • the deposited material changes the electrical characteristic of the bandgap of the active layer close to the edges . Consequently, charge carriers are facing a repellent force at the edges and are prevented from reaching the edges with its larger defect density .
  • the growth rate of the p-side layer can be adj usted, and is stopped short before it reaches the catalyst metal surface .
  • the shape of the catalyst metal droplet is re-adj usted again to cover now only the topmost surface of the p- side layer 7 for growing a highly doped contact and current distribution layer .
  • the VLS process is finished and the catalyst metal material can be removed . Removal of the metal is performed by etching for example with an etchant corroding the catalyst metal , but leaving the other surfaces of the stack and the buffer layer 2 intact .
  • the catalysts metal may stay on the tip surface of the p-side layers to form a contact area with a very high conductivity .
  • the present method provides a solution for processing optoelectronic devices with a very small footprint in the range of a few pm 2 .
  • the footprint comprises a substantially circular shape
  • the resulting optoelectronic device also contains a circular form .
  • Such material can be either transparent , for example based on SiO2 or reflective . In the latter case , photons emitted to the side can be reabsorbed ad remitted in a vertical direction .
  • a converter material could be arranged surrounding the respective optoelectronic structure . Depending on the thickness , of the converter material the colour temperature of the mixing light is adj ustable .
  • Figures 3A to 3D illustrate a further embodiment showing some aspects of the proposed principle .
  • a growth substrate 1 is provided, on which an initial buffer layer 3 is grown .
  • a doped layer for example a doped AlGaN or AlGaP layer is deposited on the initial buffer layer using known techniques .
  • the doping concentration in the doped layer 2 may vary in vertical direction, thus providing a good conductivity and current distribution .
  • doped layer 2 is used as a common doped layer .
  • a structured hard mas k made of SiO2 or any other resistant mas king material is provided on the doped layer 2 .
  • the structured hard mask 4 is intended to stay on the surface of buffer layer 2 in the subsequent VLS process .
  • the structured hard mas k contains portions covering the surface of doped layer 2 , while other areas 21 of the surface are exposed and free of any mask material .
  • the catalyst metal material 52b is now dispensed onto the exposed portions . More particularly, the catalyst metal material is colloidally dissolved in a solvent .
  • the individual metal particle comprise a size of a few nm .
  • the dispensing operation forms a tiny droplet of colloidal catalyst metal on the exposed areas .
  • the solvent is volatile and vaporizes with a slightly increased temperature .
  • the amount of colloidal catalyst metal and the solvent is selected such that the composition fills the exposed surface are 21 and is limited by the respective hard masks .
  • the composition of solvent and colloidal catalyst metal forms a droplet 53 slightly extending above the height of the surrounding hard mask and forming a dome like shape .
  • adhesion and cohesion forces keep the shape of the droplet and prevent it from wetting the top surface of the hard mas k .
  • the solvent slowly evaporates , a process which can be accelerated by increasing the temperature slightly .
  • the catalyst metal remains inside the respective exposed portions .
  • a dispensing operation allows to fill exposed areas in a quick and rapid fashion . This is particularly useful if the exposed areas are not periodically or not orderly distributed across a wafer . Further dispensing may be preferred over other techniques , if the additionally efforts for creating mas ks , and the like are too high, or a catalyst metal should not be spinned or sputtered in a reactor not suitable for such metal .
  • the dispensing operation can take place outside , because the catalyst metal will remain on the exposed surface areas , once the solvent is fully vaporized .
  • the temperature and other process parameters are increased, such that the catalyst metal is melted inside the exposed areas .
  • the catalyst metal and the surface of the exposed areas form a wetting areas with a contact angle 0 between the liquid-solid and the liquidgas interface .
  • the contact angle 0 is larger than 110 ° , and could therefore be referred to as super-metallo-phobic .
  • the area wet by the catalyst metal is relatively small .
  • FIG. 3D illustrates the grown functional layer stack of the present example .
  • the first layer of the functional layer stack 6 extends above the height of the limiting mask material 4 . Nevertheless , during deposition of said layer, the catalyst metal follows the deposited layer and only wets the top surface . This will enable to grow a functional layer stack extending above the hard mask, while maintaining its shape and dimensions .
  • the catalyst metal is removed prior to isotropically depositing a doped covering layer 71 on the top layer surface of each functional layer stack as well as the side edges of the respective active regions .
  • Covering layer 7 contains a material that comprises a larger bandgap than the bandgaps of the active region of the functional layer stack .
  • the covering layer 71 also extend over the dielectric hard mas k 4 .
  • Figures 4A to 4E illustrate the processing of a single functional layer stack in greater detail .
  • Figure 4A shows the forming of the functional layer stack after forming the doped layer 2 on the growth substrate 1 .
  • the catalyst metal droplet 53 is in its liquid form and rests on the surface of doped layer 2 .
  • a first n-doped layer 61 of the functional layer stack has already been grown using the VLS process .
  • material 61a including a dopant for said n-doped layer 61 is supplied in its gas phase into the space above the top layer surface . It liquefies into the catalyst metal droplet 53 due to a concentration gradient between the material concentration in the space above the surface of layer 2 and the metal droplet .
  • the vapour pressure of the material in the liquid phase in the catalyst metal droplet is also lower than the partial pressure of the material 61a in the space surrounding the catalyst metal droplet 53 , such that material 61a does not evaporate again from the liquid . Rather, the material 61a subsequently solidifies on the interface wet by the catalyst metal droplet . The solidification process is facilitated by the metal droplet and thus continuously removes material 61a from the liquid phase thus maintaining the concentration gradient . Consequently, layer 61 will continue to grow as long as material 61a for layer 61 is supplied .
  • the catalyst metal droplet forms a contact angle 0 on the surface , which is substantially constant during growth of the layer 61 .
  • the contact angle 0 is larger than 90 ° resulting in a metallo-phobic behaviour on the interface wet by the catalyst metal droplet .
  • the catalyst metal droplet stays on the top surface of layer 61 and maintains it shape when the layer 61 is growing because of the material deposition .
  • the mettle-phobic behaviour prevents catalyst metal droplet from "flowing" over the edge of the top surface of layer 61 .
  • material composition 62a comprises a different aluminium contents resulting in a different bandgaps compared to the bandgap of n-doped layer 61 .
  • material composition 62a comprises a different aluminium contents resulting in a different bandgaps compared to the bandgap of n-doped layer 61 .
  • Adj usting the growth rate may be beneficial as it may allow repositioning of the material on the interface wet by the catalyst metal droplet reducing potential defects in particular close to the edges .
  • the process control for depositing a quantum well or a multi quantum well structure having a plurality of quantum barriers and quantum wells is improved . Similar to the previous deposition steps , the contact angle of the catalyst metal droplet does not change , wetting only the top surface of the deposited layer . The resulting structure is shown in Figure 4B .
  • the VLS process continues by supplying the material 53a including a p-dopant into the space around the catalyst metal droplet .
  • the dopant concentration in the p-doped layer 63 is adj ustable by varying the dopant concentration during the growth of layer 63 .
  • the contact angle 0 becomes a little smaller, a reduction caused by the different material composition .
  • the example shows that while the behaviour of the catalyst metal droplet does not significantly change , material composition and particular the surface material may have an influence on the contact angle .
  • the process parameters are changed to adj ust the wetting behaviour of the catalyst metal droplet .
  • the contact angle 0 is reduced, such that the catalyst metal droplet 53 extends over the side edges of the functional layer stack including layers 61 , 62 and 63 .
  • the catalyst metal droplet 53 now covers a small portion of the surface of the doped layer 2 , again with a contact angle close to 90 ° .
  • the contact angle 0 is also dependant on the respective surface material , consequently, it is possible to adj ust the process parameter in order to reduce the contact angle for the surfaces of layers 61 , 62 and 63 ( as they contain Indium for example ) , while the same process parameter still have a contact angle of about 90 ° for a different material surface ( i . e . for doped layer 2 ) . In any way the catalyst metal droplet now covers the functional layer stack from all sides .
  • the area covering the surface of layer 2 is significantly enlarged for illustration purposes .
  • the area may be very small and in the range of the thickness of layer 71 ( see below) .
  • the form of catalyst metal droplet is adj usted in such way that it covers the side edges of the functional layer stack and partially layer 61 , but is still metallo-phobic in regards to surface of layer 2 .
  • the catalyst metal droplet forms a shell wetting the surface of the functional layer stack but not the surface of layer 2 .
  • Material 71a for covering layer 71 is now supplied in a vaporous form and the VLS process continues . Due to the changed shape , the material 71a solidifies along the top surface and the side edges of the functional layer stack including layer 61 , 62 and 63 . Its thickness can either be controlled by the supply of the material 71a . This approach can be used to perform a re-growth of the side edges , particularly along the active region leading to a change in the electrical characteristics of the bandgap within the active region . Such controlled regrowth process by VLS will improve the overall quality of the re-growth process a smooth electrical barrier .
  • a quantum well intermixing can be achieved by depositing a suitable dopant in the VLS process .
  • a suitable dopant for example, Mg or Zn can be added with a suitable precursor entering the liquid phase of the molten metal and then diffusing into the layer stack .
  • the dopant may diffuse into the semiconductor material from all side including top and side edges . On the top side , the dopant will not significantly change the characteristics , but will cause quantumwellintermixing in edge areas of the active region .
  • FIG. 5 illustrates an exemplary embodiment of an optoelectronic device with additional optical blocking elements as processed with method steps in accordance with the proposed principle .
  • the catalyst metal droplets 53 are solidified in a shape covering the respective functional layer stack shown in Figure 5 on the left side .
  • the space between adj acent catalyst metal droplets are now filled up with an optical spacer material 8 , thus optically separating the respective functional layer stacks from each other .
  • the optical separate elements 8 have a rod like structure .
  • the optical spacer elements usually follow the surface of the catalyst metal droplets .
  • the material of the catalyst metal droplets is then removed, leaving the spacers behind .
  • the catalyst metal droplets are removed prior to forming the optical spacer 8 .
  • the functional layer stacks are then covered by a structured mask material and the optical spacer elements formed in a conventional manner .
  • Figure 6 shows an exemplary embodiment of an optoelectronic device with some metal reflectors as processed with method steps in accordance with the proposed principle .
  • This example refers to a so called bottom emitter, in which the previously formed top layers are covered with a reflective material , such that the optoelectronic device emits light through the doped layer 2 .
  • the present example of Figure 6 illustrates an intermediate structure , in which the doped layer 2 and the growth substrate are still present .
  • the growth substrate may remain on the device , for example if transparent growth substrates are used .
  • the n-doped layer is either very thin, or a transparent conductive material is used .
  • the structure is rebonded to enable removal of growth substrate 1 and thinning or removal of layer 2 .
  • the exposed portions are limited by a dielectric material 4 .
  • the catalyst metal forms a droplet for the VLS process , substantially covering the exposed surface .
  • the functional layer stack 6 and the p-side layer 7 are deposited using the VLS process as described above .
  • the shape of the metal catalyst is adj usted such that it covers edge and side portions of the functional layer stack 6 .
  • the catalyst metal can wet the edge of the structured dielectric mask 4 that is the interface between the mas k and the exposed portions .
  • the p-side layer 7 is applied on top of side edges of the functional layer stack and the active region to overgrow the active region to the edges with a higher bandgap .
  • P-side layer can be in contact with the top surface of the exposed portions close to the structured dielectric mask .
  • the dielectric mask reaches to stack 6 and therefore p-side layer extends from the top surface of layer stack 6 along the side edges till the dielectric mas k .
  • the catalyst metal is reused either as contact and/or as reflective coating .
  • the catalyst metal is reshaped again to achieve a non-wetting behaviour of the catalyst metal with respect to the surface of dielectric mask 4 .
  • the shape can be adj usted such that the catalyst metal only wets portions of the side edges , in particular down to the level of the active region or a little closer towards the doped layer 2 . This will on the one side prevent a short circuit later, and on the other still ensure reflection of photons being generated in the active region and emitted sideways .
  • a conductive material is supplied for a VLS process , which is substantially transparent .
  • the conductive transparent material liquefies in the catalyst metal and forms a half-ball structure 54 covering the top surface as well as the side edges of p-side layer 7 .
  • the process is substantial finished if the catalyst metal is of high reflectivity .
  • the catalyst metal is cooled down forming a reflective layer 55 around the conductive transparent material 54 .
  • the photons emitted in the active region 6 are transmitted into every direction . Photons emitted into the transparent conductive material 54 will be reflected at the metal layer 55 and finally leave the device through thin doped layer 2 and -f present- growth substrate 1 .

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Abstract

The invention concerns a method for processing an optoelectronic device comprising the steps of providing a structured mask including portions covered by mask material and exposed portions on a surface of a doped layer (2) arranged on a growth substrate (1) and generating catalyst metal droplets (52) from catalyst metal studs (51) wetting parts of the respective exposed portions. Then first semiconductor layer (61) from a gas phase containing material of the first semiconductor layer (61) is deposited on the surface part of the exposed portion wetted by the catalyst metal droplets (52). A semiconductor layer stack (62, 63, 6) is deposited including an active region (62) on the first semiconductor layer from a gas phase containing material of the semiconductor layer stack, wherein a top surface of the first semiconductor layer is wetted by the catalyst metal droplets (52).

Description

METHOD FOR PROCESSING AN OPTOELECTRONIC DEVICE AND OPTOELECTRONIC
DEVICE
The present invention concerns a method for processing an optoelectronic device and an optoelectronic device .
BACKGROUND
The current manufacture particular of smaller LEDs , also referred to as pLEDs on wafer level suffer from various challenges , which, when not addressed properly decrease the optical and electrical characteristics of a device . In this regard, a pLED corresponds to an optoelectronic device with a diameter of smaller than 70pm and particularly in the range of 0 , 5pm to approximately 20pm . One maj or reason is the non-radiative recombination, NRR of the inj ected charge carrier compared to radiative recombination RR . With smaller sizes , the circumference with its higher defect density increases with regard to the overall area in which recombination takes place .
In particular pLEDs , which are configured to emit red, or reddish light and which are based on the InGaN, InGaP or InGaAlP material system suffer from these drawbacks . The presence of Indium in such systems with the choice to shift the bandgap to the desired energy causes an increasing charge carrier diffusion length with the above mentioned increased probability for NRR in such material systems . In addition, the Fermi level may be pinned to the semiconductor surface .
Various solutions to mitigate these drawbacks have been proposed, including but not limited to passivation of the pixel surface by, e . g . , dielectrics or impurity induced intermixing of the device ' s facets . This approach is generally referred to as quantum well intermixing and results in an increased local bandgap within the device preventing the charge carriers from reaching the surface .
However, there is still a need to further improve the performance of small optoelectronic devices and to further mitigate the above- mentioned negative effect , particularly for material systems having a diffusion length in the range of the dimension of the respective device .
SUMMARY
These and other needs are addressed by the claimed subj ect matter and the principles disclosed in this application .
The inventors have come up with another option to reduce the NRR close to the edges of the active region in very small LEDs , which is based on the so called overgrowing principle . In a conventional approach, the edges of the active region are overgrown with a material having a larger bandgap than the material of the active region . This will prevent charge carrier from reaching the edges and thus reduce NRR . However, while the approach is feasible it requires a high precision and high alignment for the respective structured mas ks to ensure proper overgrowth .
When looking for a simpler and less sophisticated solution, the inventors realized that self-structuring and self-positioning during the growth of the functional layer stack as well as the material used for overgrowth would be a solution offering both simplicity and high precision and alignment . For this purpose , the inventors propose a method utilizing transition of the material to be deposited from its vaporous form to a solid form via a liquid . This approach is also referred to as a VLS-process from its three phases ( gas phase , liquid phase and solid phase ) . The material to be deposited for a semiconductor layer is provided in a gas phase and deposited utilizing a liquid catalyst metal . The process parameter for this process are adj usted in such way that a direct deposition of the semiconductor layer material cannot take place . Rather , the material diffuses into the metal catalyst and is -from there- deposited on the surface thus forming the semiconductor layer .
As a result , semiconductor material is grown at locations of the metal catalyst droplets . Proper choice of the catalyst metal allows the processing of very small pLEDs with high density maintaining high quality for the individual devices . The metal itself is preferably neither consumed nor included in the crystal structure and acts as a catalyst for the overall growth process . The self-organisation of the metal catalyst following the grown semiconductor acts as a benefit , because subsequent layers can be deposited and grown on the same location . The process parameter, for instant temperature and pressure are adj usted in such way that the catalyst metal comprises a certain shape and wetting behaviour . Consequently, the semiconductor material is deposited only at those locations , which are wetted by the catalyst metal but nowhere else ( due to the selected process parameter rendering it impossible to deposit the material somewhere else ) .
Changing the parameter provides the possibility for adj ustment the shape and wetting behaviour of the metal catalyst . More particularly, the shape of the metal catalyst can be adj usted in such way that it can cover not only the top layer surface but also the side surface of the active region grown in previous steps . This coverage allows to overgrow the edges of the active region with a suitable semiconductor material in a precise and high-quality fashion . The metal catalyst can be removed after processing the device , but also reused, e . g . as contact or reflective layers and the like .
The presented methods and aspects thereof can be applied to a variety of semiconductor material systems including not only binary but also ternary and even quaterny material systems . Examples for such systems include but are not limited to GaN, GaP, GaAs , AlGaN, AlGaP, AlGaAs , InGaN, InGaP, InGaAs , AlInGaN and AlInGaP as well as any combinations thereof . The content of the individual elements , namely Aluminum and Indium may vary throughout the deposition of the various layers .
In some aspects , the inventors propose a method for processing an optoelectronic device . The method comprises the step of providing a structured mask including portions covered by mask material and exposed portions on a surface of a doped layer arranged on a growth substrate . The expression "exposed portions" usually refer to portions of the top surface not covered by any mas k or other material . The term "doped layer" refers to a semiconductor layer which includes a deliberately induced dopant e . g . during growth of the layer . The dopant concentration is chosen to provide a certain electric behaviour and may often lie in the range of 3el7 atoms /cm3 to le! 9 atoms /cm3 .
One or more catalyst metal studs are generated on the exposed portions and catalyst metal droplets are subsequently formed from the catalyst metal studs wetting at least pats of the exposed portions . The expression "wetting" in this regard refers to the ability of a liquid to maintain contact with a solid surface , resulting from intermolecular interactions when the two are brought together . The degree of wetting (wettability) is determined by a force balance between adhesive and cohesive forces . As it will be explained later in detail , the degree of wetting is adj ustable . After such preparation of the surface with the catalyst metal droplets , the functional layer stack, i . e . forming the optoelectronic device can be grown .
The expression "functional layer stack" refers to a semiconductor layer stack that provides a certain electrical function . A typical functional semiconductor stack is a diode , a transistor and also an optoelectronic device configured to emit light in operation . For simplicity purposes an optoelectronic layer stack is used as a nonlimiting example throughout this application . The expression "functional layer stack" and "functional semiconductor layer stack" are used synonymously throughout this application . Likewise , while this application often refers to a single device or layer stack, the invention is not limited thereto . Rather, the principle disclosed herein are applicable to individual devices but also to the processing of whole wafer .
For this purpose , the material for a first semiconductor layer is provided from a gas phase . The material liquefies on and in the metal catalyst droplets and solidifies on the surface part of the exposed portion wetted by the catalyst metal droplets , thus depositing as the first semiconductor layer . The first semiconductor layer can be part of a functional semiconductor layer stack including an active region . Likewise in some aspects , a functional semiconductor layer stack including an active region can be grown from a gas phase on the first semiconductor layer containing material of the semiconductor layer stack .
It has been found that the catalyst metal droplet "moves" with the grown semiconductor layers ; that is it mainly wets the top surface layer . As a result the semiconductor layer stack can be grown in a self-organized manner similar to conventional approaches by providing the material for the respective layer to be grown . The provided material is offered at a gaseous , vapour phase , transforms into the fluid or liquid phase inside the catalyst metal droplets and solidifies as a layer on the top surface wet by the droplet .
In a subsequent step following the deposition of various layers of the functional layer stack, the catalyst metal droplets are reshaped such that they wet portions of the surface adj acent the surface of the first semiconductor layer . In other words , the catalyst metal droplet has changed its wetting behaviour and now wets the top surface of the functional semiconductor layer stack as well adj acent surface portions . Consequently, the shape of the catalyst metal droplet has changed, enabling to deposit a semiconductor material for its gas phase on the top surface and on the side surface of the functional semiconductor layer stack thereby covering edge areas of the active region .
Different metals are suitable as catalyst metal for the proposed method . For example , the catalyst metal studs may comprise at least a metal selected from a group consisting of Gold, Nickel , Gallium, Silver , Iridium, Palladium, Platinum, Lead and Titanium or combinations and alloys thereof including those elements . It may be suitable to choose a metal that is inert in regards to the semiconductor material deposited as the optoelectronic device and is not incorporated into the crystal structure . Gold and Nickel may be suitable materials , but other materials and also combinations thereof may be chosen .
In some aspects , the composition of the catalyst metal may be adj usted during the process to , for instance , change the wetting behaviour . In some aspects , the step of generating the catalyst metal droplets may comprise increasing the temperature above the melting point of the respective catalyst metal or catalyst metal composition, such that the catalyst metal becomes liquid . As a result of the process , the metal droplet and the surface form a contact angle at their respective circumference . The contact angle 0C, is the angle formed by a liquid at the three-phase boundary where the liquid, gas , and solid intersect .
In some aspects of the proposed method, the molten catalyst metal forms a contact angle 0C between 70 ° and 150 ° and in particular between 80 ° and 150 ° and in particular above 85 ° . In this regard, angles around 90 ° are generally referred to as metal-repellent or "metallo- phobic" , angles smaller than 60 ° to 70 ° as metal-attracting or "metallo-phil" and angles larger than 105 ° to 125 ° as "super-metallo- phobic" .
In some aspects , the contact angle 0C between the catalyst metal droplets and the surface of the exposed portion or more generally of the respective top surface wetted by the droplet is adj ustable . The adj ustment is achieved by setting or varying various parameters . These parameters may include the temperature of the catalyst metal , the surface material , the catalyst material , the ambient pressure or an amount of a second catalyst metal being added to the catalyst metal droplets during a processing step .
In some aspects , the contact angle between the catalyst metal droplets and the surface of the exposed portions or any semiconductor layer is around 90 ° . In some aspects , the contact angle between the catalyst metal droplets and the surface of the exposed portion or any semiconductor layer is larger than a contact angle between the catalyst metal droplets and the surface of the exposed portion after the step of reshaping the catalyst metal droplets . In particular , the contact angle after the reshaping step may be smaller than 90 ° and can be in the range of 30 ° and 75 ° and in particular between 40 ° and 60 ° . Some aspects concern the provision of a structured mas k . For example , a growth substrate is provided and one or more semiconductor layer deposited thereon . The one or more semiconductor layers may comprise buffer layers to planarize the surface , initial layers for later rebonding or for sacrificial purposes and the like . The top layer of the one or more semiconductor layers ( that is the last being grown) comprises a dopant to reduce the resistance value and prepare the structure for being contacted .
A mask material is deposited on the surface of said top surface layer and subsequently structured . After exposure of the mas k material , portions of the mask material are removed, such as to provide covered portions by the mask material and exposed portions . The latter portions expose parts of the surface of the doped layer . The removal of mas k portions can be done in two different variants . In one option, non-exposed portions of the mask are removed . In a second option, exposed portions are removed and the non-exposed portions of the mas k remain on the surface .
The mask can comprise of a photo resist or a hard mas material as SiO2 . The latter requires a different application process , but can also remain on the surface for isolation and limiting purposes when the catalyst material is applied . Such approach is explained further below .
Another aspects relates to the generation of the catalyst metal studs . A catalyst metal is deposited on the surface of the doped layer and the structured mas k in a first sub-step . Deposition can be archived from the gas phase by a MOCVD (Metalorganic chemical vapour deposition ) or a MOVPE (Metalorganic vapour-phase epitaxy) process . Other suitable processes for depositing the catalyst metal are suitable as well . In a subsequent sub-step , the structured mas k can be removed leaving only the portions of the catalyst metal covering the previously exposed areas on the surface of the top layer .
As an alternative approach, for example in case of a structured hard mas k comprising SiO2 , the catalyst metal can be dispensed directly on the exposed portions . In some instances , the catalyst metal is mixed with a volatile solvent to provide an easier dispense solution . The solvent vaporizes and leaves only the metal catalyst on the surface . The dispense approach may be beneficial when the locations for the functional layer stack to be grown are non-periodic or an epitaxial growth is either too complex or more expensive .
In some instances , the height of the catalyst metal applied on the exposed areas may be larger than a height of the structured mask . In other words , the volume of the metal studs may be larger than the cavity volume with the exposed portions created by the structured mas k . In some instances , for example , in which the structured mas k is a hard mask intended to remain on the surface , the height of the structured mask may be larger than catalyst metal .
As already indicated above , the structured mask may comprise a dielectric material , particularly when the structured mask is intended to remain on the surface . In such cases , it is beneficial to select a dielectric material having a melting point higher than a melting point of the catalyst metal and particularly significantly higher than the melting point of the catalyst metal . This will ensure that the no dislocations or shift in the later grown functional semiconductor layer stack take place . The hard mask will then act as a limitation .
As outlined above , the first semiconductor layer and the functional layer stack are formed from a gas phase , liquefies into the catalyst metal drops and then solidifies on the surface wetted by the catalyst metal in the VLS process . The material for the respective layers and the layer stack can be provided in the gas phase by MOCVD (Metalorganic chemical vapour deposition) or a MOVPE (Metalorganic vapour-phase epitaxy) process . As the process temperature during the VLS deposition is usually higher than for direct epitaxial growth on the surface , the chemical reaction during MOCVD must be suitable to provide the necessary semiconductor material . On the other hand, generally known chemical reactions may be usable simplifying the overall VLS process . In some instances , at least one process parameter is adj usted to ensure that during the depositions steps the material of the first semiconductor layer and/or the semiconductor layer stack do not deposit on surface parts not covered by the catalyst metal droplets . Those parameters include but are not limited to ambient temperature , surface temperature of the wafer, pressure or combinations thereof . The adj ustment of the process parameter basically prevents conventional epitaxial growth of the semiconductor material on the surface . At the same time , the temperature and generally the process parameter do not cause dislocations or repositioning of the deposited layer material . Likewise , the process parameters , particularly the ambient temperature is adj usted such that the catalyst metal is mainly liquid and forms the proper wetting area on the surface .
The height of the layer grown by the VLS process is adj ustable in an easy way, because the process parameters can be adj usted such that the catalyst metal droplets wets only the surface of the topmost layer . As a result thereof , the VLS process growing the layer will continue as long as the respective material is applied .
A further aspect relates to the overgrow approach, in which material with a higher bandgap is applied to the edges of the active region . The shape of the catalyst metal droplet is adj usted such that the catalyst metal also covers at least the area of the active region along the side surfaces of the functional layer stack . In some instances , the metal droplet extends to the surface adj acent to the layer stack .
In some further aspects reshaping the catalyst metal droplets comprises forming a shell by the catalyst metal droplet only covering the functional layer stack and optionally including a portion of the first semiconductor layer but not the surface of the exposed portions . The catalyst metal droplet therefore only wets the top layer of the functional layer stack and the side edges as well as portions of the side of the first semiconductor layer, respectively . This embodiment may prevent depositing layer material in the VLS process directly on the exposed portion changing the electrical characteristics of the device .
In some instances a shell or hood is formed by the catalyst metal droplet covering the functional layer stack and comprising a contact angle of larger than 90 ° on the surface of the doped layer and the exposed portions .
Depositing a semiconductor material on the top surface and on the side surface of the semiconductor layer stack comprises providing the semiconductor material from a gas phase through the metal catalyst droplets , subsequently undergoing the VLS process . The semiconductor material covering edge areas of the active region comprises a larger bandgap than the active region . In some aspects , the side edges are re-grown using depositing a semiconductor material resulting in a change of the bandgap characteristics of the active region close to the edges . In some aspects , the semiconductor material comprises a dopant , for example a dopant of a different type than the doped first layer . In particular , the material on the side edges covering the active region may comprise a p-dopant , while the first layer includes an n-dopant . Dopant concentration on the side edges may vary . In some aspects , Zn or another suitable dopant is deposited on the side edges using VLS process causing a Quantum well intermixing in edges areas of the active region . Zn may deposit also on the top of the layer stack, but will not cause a significant change due to the larger amount of bulk material therein .
In some aspects , the functional layer stack comprises an active region including a quantum well or a multi-quantum well . In some aspects , the active region is formed of AlInGaN or AlInGaP based material with different Aluminum contents for the quantum well barriers and the quantum wells .
The devices and functional layer stacks processed by this proposed method can have a very small dimension . For optoelectronic devices diameters of a few pm are possible . Such so called p-LED can have a diameter of 1pm to 15pm for example . pLEDs may be smaller than 10pm in diameter . However, large diameters in the range of 10pm to 50pm are generally possible . An area may be in the range of 1pm2 to 2000pm2 and in particular smaller than 2000pm2 and in particular between 4pm2 and 400pm2 . The footprint of the layer stack is usually circular or at least curved and may comprise a rod or pillar-shaped form .
In some further aspect , the method may comprise additional steps after depositing the semiconductor layer stack . In some instances , a transparent conductive material is deposited on at least the top surface of the deposited semiconductor material . Alternatively, a dielectric material is grown on at least the top surface of the deposited semiconductor material . In this regard, the expression "on the top surface" refers to the topmost surface of the respective layer . In some instances , the catalyst metal droplet forms a reflective layer around the semiconductor layer stack . Consequently, the catalyst metal is reusable for a reflective layer .
In some other aspects , an optical spacer element is formed between two adj acent functional layer stacks in particular . The catalyst metal droplet can be utilised for depositing the spacer material , but can also be removed prior to deposition of such spacer .
Some other aspects concern an optoelectronic device . The device comprises a functional layer stack having an active region arranged between two differently doped conductive semiconductor layers . A material of one of the two differently doped semiconductor layers extends along the side surfaces of the functional layer stack covering the side edges of the active region . In accordance with the proposed principle residuals of a catalyst metal are present in at least one of the functional layer stack and the active region and the material covering the side surfaces of the functional layer . The residuals of the catalyst metal comprise at least one metal selected from a group consisting of Gold, Nickel , Gallium, Silver, Iridium, Palladium, Platinum, Rhodium, Lead and Titanium .
The residuals are incorporated into the different semiconductor layers during the VLS process , but its respective concentration is relatively small . However, the residuals are caused by the VLS process , and are not present in such concentration in a conventional growth process .
SHORT DESCIRPTION OF THE DRAWINGS
Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which
Figures 1A to ID illustrate some steps of a method in accordance with some aspects of the proposed principle ;
Figures 2A to 2D show some further steps of the method as illustrated in Figure lin accordance with some aspects of the proposed principle ;
Figures 3A to 3D illustrate some steps of another method in accordance with some aspects of the proposed principle ;
Figure 4A to 4E show several method steps of processing an optoelectronic device in accordance with aspects of the proposed principle ;
Figure 5 illustrates an exemplary embodiment of an optoelectronic device with additional optical blocking elements as processed with method steps in accordance with the proposed principle ;
Figure 6 shows an exemplary embodiment of an optoelectronic device with a metal reflector as processed with method steps in accordance with the proposed principle .
DETAILED DESCRIPTION
The following embodiments and examples disclose different aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the Figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form or shape may occur without , however, contradicting the inventive idea .
In addition, the individual Figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However, terms such as "above" , "above" "below" , "below" "larger" , "smaller" and the like are correctly represented with regard to the elements in the Figures . So it is possible to deduce such relations between the elements based on the Figures .
Figure 1A to ID as well as 2A to 2D show several steps of a method for processing an optoelectronic device in accordance with some aspects of the proposed principle . A growth substrate 1 is provided in a first step illustrated in Figure 1A the growth substrate comprises GaAs in this example . Other suitable growth substrates include sapphire , SiO2 and the like . Material of one or more layers 2 , acting as buffer and initial layer are epitaxial deposited . For this purpose AlGaP material is used, on which also Indium may be added . The growth of the initial buffer layer ( s ) 2 is conventional and generally well known . For the present example an AlGaN material is used as buffer layers , the AlGaN material including different dopant concentrations and or different Al concentrations .
Then, a mask material 4 is sputtered, spinned or otherwise deposited as planar on the surface . It is subsequently structured in such way as to expose a plurality of areas 21 of the surface of the top-most layer 2 . The height of the structure mas k 4 is selected in a suitable way for the subsequent steps . Figure IB illustrates the resulting structure .
Figure 1C shows the next processing step , in which a catalyst metal material 5 is deposited on the surface covering the exposed portions 21 as well as the structured remaining mask material 4 . As illustrated the amount of the catalyst material 5 is sufficiently large to completely cover the exposed portions 21 and also extend slightly over the structured mas k 4 . However , it is also possible to apply less material by spinning for example , which will fill-up the exposed portions 21 , but not remain on the structured mask 4 due to the spinning process . Another possibility is a MOCVD process , in which the catalyst metal 5 undergoes a chemical reaction on the exposed surfaces 21 depositing thereon .
Several different metals are potentially suitable as a catalyst metal 5 for the subsequent VSL process . Still , the material should not react with the later semiconductor material and should be inert to the following deposition of semiconductor material . At the same time the melting point should not be too high to prevent evaporation, dislocations and dissolving already grown layer due to the high temperature . Certain alloys having a relatively low melting point have been found to be suitable .
In some examples , such alloy contains Gold and Nickel . Other suitable metals are Palladium, Platinum, Rhodium, Silver , Titanium, Mercury, Zirconium and to some lesser extend also Copper or Lead . The metal to be used for the VLS process is a catalyst metal , i . e . it is used to facilitate the deposition process , but is neither consumed nor chemically altered in the process itself . The melting point of the alloy or the metal should be high enough to ensure that the semiconductor material cannot be grown directly on the surface , that is cannot be grown without the VLS process , but low enough to avoid re-evaporation of the already grown material . Gallium as a potential material might be suitable , but is consumed in the process when layers based on GaN or GaP ( or material system including Ga ) are grown . The same applies to Aluminum or Indium . In such cases proper resupply of such metal is required to still being referred to as catalyst metals .
Dopant materials like as Zn, Mg, Si or Ge should not be used as catalyst metal , as they are dopants in atomic form and may contaminate the grown semiconductor layers . The next step shown in Figure ID includes the removal of the mask portions and the catalyst metal on top, leaving only the catalyst metal as catalyst metal studs 51 behind on the surface . The height and distance of those metal studs 51 are adj ustable parameters by the previous process steps .
Figures 2A to 2D illustrate the next steps including the VLS process for the processing of a device in accordance with some aspects of the proposed principle . The catalyst metal studs 51 are heated either short below or even above their respective melting points resulting in a transition from their solid stated to a liquid state . The catalyst metal studs 51 become respective catalyst metal droplets 52 . As a result of the phase transition, the catalyst metal wets a certain area of its surface . By proper adj usting the various parameter for the melting process and the end temperature , the catalyst metal amount of wetting and particularly the contact angle 0 can be adj usted .
The contact angle 0 , as seen in Figure 2A, is the angle at which the liquid-vapour interface meets the solid-liquid interface . The contact angle is determined by the balance between adhesive and cohesive forces . Adhesive forces between a liquid and solid cause a liquid drop to spread across the surface . Cohesive forces within the liquid cause the drop to ball up and avoid contact with the surface . As the tendency of a drop to spread out over a flat , solid surface increases , the contact angle decreases . Thus , the contact angle provides an inverse measure of wettability .
In the present case , the contact angle 0 is slightly larger than 90 ° , which is considered to be repellent or metallo-phobic . Consequently, an angle 0 larger than 90 ° results in an area being wet that is smaller than the maximum diameter of the catalyst metal droplet 52 . The angle 0 can now be adj usted by changing the temperature of the metal droplet , the alloy composition of the metal droplet , the ambient pressure and other parameters . For example increasing the pressure may result in a decreasing angle , i . e . the metal droplet 52 being pushed onto the surface area 21 resulting in a slightly larger diameter and wet area . Hence , a proper selection of the process parameters enables adj ustment of the footprint of the device to be processed .
As a matter of fact , the surface area wet by the metal droplet forms a circle and not a rectangular or any other ordered shape . If such footprint shall be achieved, the previously exposed areas 21 should be reduced and may be limited ( i . e . by a surrounding hard mask ) , such that the metal droplet "stays" within the exposed areas 21 .
Figure 2B shows the next step in the process including a first VLS process . After the catalyst metal droplets 52 are formed on the exposed areas 21 , a semiconductor material is supplied in the gas phase . A suitable approach for such supply might be MBE , MOVPE and the like . Due to the high temperature , the semiconductor material stays in the gas phase or vaporous phase and does not deposit in the areas between the exposed portions 21 ( or it evaporates again due to the high temperature ) .
The semiconductor material used for the first layer is based on InAlGaP, whereas the different components Indium, Aluminum Gallium and Phosphorus as well as respective dopants are supplied from the gas phase in their correct stoichiometric quantity . The supplied material diffuses into the catalyst metal droplet due to the concentration gradient and liquefies therein . It subsequently deposits as solid material on the liquid-solid interface between the metal droplet and the surface of buffer layer 2 . This process continues as long as the respective components for the first doped semiconductor layer 6 are supplied . By changing the stoichiometric relation, the bandgap can be adj usted . Similarly changing the dopant concentration in the supplied material adj usts the conductivity of the layer .
In a subsequent step , not shown herein, the composition is changed and Indium added in the desired amount as to grow a quantum well structure . For the quantum barrier, the Aluminum content is increased, for the quantum well layers decreased again . In contradiction to conventional approaches , less material is used, as the material deposition and the layer growth occurs only in the areas covered by the catalyst metal droplets .
It has been found that the catalyst metal droplet "moves" with the growing layer, that is it mainly wet the topmost surface . This behaviour can slightly be adj usted by varying the process parameters ( i . e . if the contact angle changes due to variation in the deposited material ) . Nevertheless , the behaviour of moving of the catalyst metal droplet when more and more material is deposited is beneficial as it allows some self-structuring and self-alignment . Even more so , by changing the process parameters for the catalyst metal , the shape can be varied and different diameters or footprint areas for the different layers can be achieved .
Figure 2B illustrates the resulting structure , in which one or more layers of a function layer stack 6 have been grown with the catalyst metal droplet mainly wetting the topmost surface .
The supply of the various material components Al , Ga, In and P including dopants for the semiconductor layers continues until at least the active region and the top contact layer of the functional layer stack is grown . Then, the process parameters are changed to spread the catalyst metal droplet extending over the top surface and wetting also the side surface of the grown functional layer stack as shown in Figure 2C . The contact angle 0 is altered by the varied process parameters and decreases either close to 90 ° or even below 90 ° that is shifts towards the metal attractive or metallo-philic phase . Consequently the catalyst metal droplet now "flows" over the topmost edge of the edges of the functional layer stack and -as shown in Figure 2- reaches the surface areas adj acent to the grown functional semiconductor layer stack .
The side surfaces are now buried beneath the catalyst metal with a certain amount of metal covering the side surface and the topmost edge of the functional layer stack . In other words , the topmost edge and/or the side surface does not lie directly under the surface of the catalyst metal droplet or even intersects the metal surface , but is completely buried with a certain distance D between the edge of the stack and the surface of the metal . Said distance is indicated in Figure 2C . The material covering the side surfaces enables the edges of the active region to be overgrown by a semiconductor material having a larger bandgap than the bandgaps of the active region .
Hence , after changing the process parameter and reshaping the form of the catalyst metal droplet , the components of a p-side layer in the present example are resupplied and a p-side layer deposited on the active region of the functional layer stack . Due to the reshaped form, the material of the p-side layer 7 does not only deposits on the topmost surface of the functional layer stack, but also on the side edges , thus overgrowing the edges of the active region . The p-side semiconductor material for layer 7 contains a bandgap that is larger than the bandgap for the Indium including quantum well layers of the active region . The deposited material changes the electrical characteristic of the bandgap of the active layer close to the edges . Consequently, charge carriers are facing a repellent force at the edges and are prevented from reaching the edges with its larger defect density .
The growth rate of the p-side layer can be adj usted, and is stopped short before it reaches the catalyst metal surface . In a subsequent step ( not illustrated herein ) , the shape of the catalyst metal droplet is re-adj usted again to cover now only the topmost surface of the p- side layer 7 for growing a highly doped contact and current distribution layer . At some point , the VLS process is finished and the catalyst metal material can be removed . Removal of the metal is performed by etching for example with an etchant corroding the catalyst metal , but leaving the other surfaces of the stack and the buffer layer 2 intact . In an alternative aspect , the catalysts metal may stay on the tip surface of the p-side layers to form a contact area with a very high conductivity .
The present method provides a solution for processing optoelectronic devices with a very small footprint in the range of a few pm2 . As the footprint comprises a substantially circular shape , it is likely that the resulting optoelectronic device also contains a circular form . In such circumstances it may be useful to fill the space between the respective optoelectronic devices with an insulating material . Such material can be either transparent , for example based on SiO2 or reflective . In the latter case , photons emitted to the side can be reabsorbed ad remitted in a vertical direction . In a further alternative , a converter material could be arranged surrounding the respective optoelectronic structure . Depending on the thickness , of the converter material the colour temperature of the mixing light is adj ustable .
Figures 3A to 3D illustrate a further embodiment showing some aspects of the proposed principle . Similar to the first embodiment a growth substrate 1 is provided, on which an initial buffer layer 3 is grown . A doped layer , for example a doped AlGaN or AlGaP layer is deposited on the initial buffer layer using known techniques . The doping concentration in the doped layer 2 may vary in vertical direction, thus providing a good conductivity and current distribution . For the present example , doped layer 2 is used as a common doped layer . In a subsequent step a structured hard mas k made of SiO2 or any other resistant mas king material is provided on the doped layer 2 .
In contrary to the previous example , the structured hard mask 4 is intended to stay on the surface of buffer layer 2 in the subsequent VLS process . The structured hard mas k contains portions covering the surface of doped layer 2 , while other areas 21 of the surface are exposed and free of any mask material . In contrast to the previous example , the catalyst metal material 52b is now dispensed onto the exposed portions . More particularly, the catalyst metal material is colloidally dissolved in a solvent . The individual metal particle comprise a size of a few nm . The dispensing operation forms a tiny droplet of colloidal catalyst metal on the exposed areas . In accordance with some aspect , the solvent is volatile and vaporizes with a slightly increased temperature .
Referring now to Figure 3B . The amount of colloidal catalyst metal and the solvent is selected such that the composition fills the exposed surface are 21 and is limited by the respective hard masks . The composition of solvent and colloidal catalyst metal forms a droplet 53 slightly extending above the height of the surrounding hard mask and forming a dome like shape . However, adhesion and cohesion forces keep the shape of the droplet and prevent it from wetting the top surface of the hard mas k . The solvent slowly evaporates , a process which can be accelerated by increasing the temperature slightly . The catalyst metal remains inside the respective exposed portions .
The use of a dispensing operation allows to fill exposed areas in a quick and rapid fashion . This is particularly useful if the exposed areas are not periodically or not orderly distributed across a wafer . Further dispensing may be preferred over other techniques , if the additionally efforts for creating mas ks , and the like are too high, or a catalyst metal should not be spinned or sputtered in a reactor not suitable for such metal . The dispensing operation can take place outside , because the catalyst metal will remain on the exposed surface areas , once the solvent is fully vaporized .
In a subsequent step, shown in Figure 3C , the temperature and other process parameters are increased, such that the catalyst metal is melted inside the exposed areas . Similar to the previous embodiment , the catalyst metal and the surface of the exposed areas form a wetting areas with a contact angle 0 between the liquid-solid and the liquidgas interface . In the present example the contact angle 0 is larger than 110 ° , and could therefore be referred to as super-metallo-phobic . As a result thereof , the area wet by the catalyst metal is relatively small .
The process parameters are changed such that the area wet by the catalyst metal substantially covers the exposed areas , for example by increasing the ambient pressure . After adj usting the proper area for the functional layer stack to be grown, the respective material , for example Al , Ga , In and P are supplied and the VLS process takes place . Figure 3D illustrates the grown functional layer stack of the present example . As shown, the first layer of the functional layer stack 6 extends above the height of the limiting mask material 4 . Nevertheless , during deposition of said layer, the catalyst metal follows the deposited layer and only wets the top surface . This will enable to grow a functional layer stack extending above the hard mask, while maintaining its shape and dimensions .
In this non limiting example , the catalyst metal is removed prior to isotropically depositing a doped covering layer 71 on the top layer surface of each functional layer stack as well as the side edges of the respective active regions . Covering layer 7 contains a material that comprises a larger bandgap than the bandgaps of the active region of the functional layer stack . In addition, the covering layer 71 also extend over the dielectric hard mas k 4 .
While this solution may not be practical per se , it actually illustrates the different variants and possibilities when utilising a VLS process to process a functional layer stack . The various layers of the stack are grown in a self-structured and self-positioned manner without the need for further alignment of various mask layers . The VLS process may therefore be simpler and requires less efforts , while maintaining the flexibility and necessary process control .
Figures 4A to 4E illustrate the processing of a single functional layer stack in greater detail . Figure 4A shows the forming of the functional layer stack after forming the doped layer 2 on the growth substrate 1 .
The catalyst metal droplet 53 is in its liquid form and rests on the surface of doped layer 2 . A first n-doped layer 61 of the functional layer stack has already been grown using the VLS process .
In particular, material 61a including a dopant for said n-doped layer 61 is supplied in its gas phase into the space above the top layer surface . It liquefies into the catalyst metal droplet 53 due to a concentration gradient between the material concentration in the space above the surface of layer 2 and the metal droplet . The vapour pressure of the material in the liquid phase in the catalyst metal droplet is also lower than the partial pressure of the material 61a in the space surrounding the catalyst metal droplet 53 , such that material 61a does not evaporate again from the liquid . Rather, the material 61a subsequently solidifies on the interface wet by the catalyst metal droplet . The solidification process is facilitated by the metal droplet and thus continuously removes material 61a from the liquid phase thus maintaining the concentration gradient . Consequently, layer 61 will continue to grow as long as material 61a for layer 61 is supplied .
The catalyst metal droplet forms a contact angle 0 on the surface , which is substantially constant during growth of the layer 61 . The contact angle 0 is larger than 90 ° resulting in a metallo-phobic behaviour on the interface wet by the catalyst metal droplet . As a result , the catalyst metal droplet stays on the top surface of layer 61 and maintains it shape when the layer 61 is growing because of the material deposition . In particular, the mettle-phobic behaviour prevents catalyst metal droplet from "flowing" over the edge of the top surface of layer 61 .
Once the desired thickness of n-doped layer 61 is achieved, the material composition is changed and a revised material composition 62a for growing the quantum well layer 62 is provided . For example , material composition 62a comprises a different aluminium contents resulting in a different bandgaps compared to the bandgap of n-doped layer 61 . By changing the material composition during the deposition, a plurality of quantum wells and quantum barriers are grown as layer 62 . A slightly smaller supply flow of material 62a causes a variation of the growth rate and in particular in a decreased growth rate . Adj usting the growth rate may be beneficial as it may allow repositioning of the material on the interface wet by the catalyst metal droplet reducing potential defects in particular close to the edges . Further , the process control for depositing a quantum well or a multi quantum well structure having a plurality of quantum barriers and quantum wells is improved . Similar to the previous deposition steps , the contact angle of the catalyst metal droplet does not change , wetting only the top surface of the deposited layer . The resulting structure is shown in Figure 4B .
Referring now to Figure 4C and the VLS process for depositing a p- doped layer 63 onto the grown multi quantum well 62 . The VLS process continues by supplying the material 53a including a p-dopant into the space around the catalyst metal droplet . The dopant concentration in the p-doped layer 63 is adj ustable by varying the dopant concentration during the growth of layer 63 . In the present example , the contact angle 0 becomes a little smaller, a reduction caused by the different material composition . The example shows that while the behaviour of the catalyst metal droplet does not significantly change , material composition and particular the surface material may have an influence on the contact angle .
After the deposition of the p-doped layer is finished, the process parameters are changed to adj ust the wetting behaviour of the catalyst metal droplet . Particularly, illustrated in Figure 4E , the contact angle 0 is reduced, such that the catalyst metal droplet 53 extends over the side edges of the functional layer stack including layers 61 , 62 and 63 . The catalyst metal droplet 53 now covers a small portion of the surface of the doped layer 2 , again with a contact angle close to 90 ° . As previously stated the contact angle 0 is also dependant on the respective surface material , consequently, it is possible to adj ust the process parameter in order to reduce the contact angle for the surfaces of layers 61 , 62 and 63 ( as they contain Indium for example ) , while the same process parameter still have a contact angle of about 90 ° for a different material surface ( i . e . for doped layer 2 ) . In any way the catalyst metal droplet now covers the functional layer stack from all sides .
In the example shown in Figure 4E , the area covering the surface of layer 2 is significantly enlarged for illustration purposes . In practice the area may be very small and in the range of the thickness of layer 71 ( see below) . Further , in some instances , the form of catalyst metal droplet is adj usted in such way that it covers the side edges of the functional layer stack and partially layer 61 , but is still metallo-phobic in regards to surface of layer 2 . In other words , the catalyst metal droplet forms a shell wetting the surface of the functional layer stack but not the surface of layer 2 .
Material 71a for covering layer 71 is now supplied in a vaporous form and the VLS process continues . Due to the changed shape , the material 71a solidifies along the top surface and the side edges of the functional layer stack including layer 61 , 62 and 63 . Its thickness can either be controlled by the supply of the material 71a . This approach can be used to perform a re-growth of the side edges , particularly along the active region leading to a change in the electrical characteristics of the bandgap within the active region . Such controlled regrowth process by VLS will improve the overall quality of the re-growth process a smooth electrical barrier .
Similarly to a regrowth process , a quantum well intermixing can be achieved by depositing a suitable dopant in the VLS process . For example , Mg or Zn can be added with a suitable precursor entering the liquid phase of the molten metal and then diffusing into the layer stack . The dopant may diffuse into the semiconductor material from all side including top and side edges . On the top side , the dopant will not significantly change the characteristics , but will cause quantumwellintermixing in edge areas of the active region .
Figure 5 illustrates an exemplary embodiment of an optoelectronic device with additional optical blocking elements as processed with method steps in accordance with the proposed principle . After the functional layer stack 6 and the covering layer 7 are finished, the catalyst metal droplets 53 are solidified in a shape covering the respective functional layer stack shown in Figure 5 on the left side . The space between adj acent catalyst metal droplets are now filled up with an optical spacer material 8 , thus optically separating the respective functional layer stacks from each other . As illustrated herein, the optical separate elements 8 have a rod like structure . However, when using the catalyst metal droplets , the optical spacer elements usually follow the surface of the catalyst metal droplets . The material of the catalyst metal droplets is then removed, leaving the spacers behind .
Alternatively, the catalyst metal droplets are removed prior to forming the optical spacer 8 . The functional layer stacks are then covered by a structured mask material and the optical spacer elements formed in a conventional manner .
Figure 6 shows an exemplary embodiment of an optoelectronic device with some metal reflectors as processed with method steps in accordance with the proposed principle . This example refers to a so called bottom emitter, in which the previously formed top layers are covered with a reflective material , such that the optoelectronic device emits light through the doped layer 2 . The present example of Figure 6 illustrates an intermediate structure , in which the doped layer 2 and the growth substrate are still present . In some cases , the growth substrate may remain on the device , for example if transparent growth substrates are used . The n-doped layer is either very thin, or a transparent conductive material is used . In other instances , the structure is rebonded to enable removal of growth substrate 1 and thinning or removal of layer 2 .
In this example , the exposed portions are limited by a dielectric material 4 . During the processing of the device the catalyst metal forms a droplet for the VLS process , substantially covering the exposed surface . The functional layer stack 6 and the p-side layer 7 are deposited using the VLS process as described above . During processing of the device , the shape of the metal catalyst is adj usted such that it covers edge and side portions of the functional layer stack 6 . The catalyst metal can wet the edge of the structured dielectric mask 4 that is the interface between the mas k and the exposed portions . Then, the p-side layer 7 is applied on top of side edges of the functional layer stack and the active region to overgrow the active region to the edges with a higher bandgap . P-side layer can be in contact with the top surface of the exposed portions close to the structured dielectric mask . Alternatively, the dielectric mask reaches to stack 6 and therefore p-side layer extends from the top surface of layer stack 6 along the side edges till the dielectric mas k .
In accordance with some aspects , the catalyst metal is reused either as contact and/or as reflective coating . The catalyst metal is reshaped again to achieve a non-wetting behaviour of the catalyst metal with respect to the surface of dielectric mask 4 . In some instances , the shape can be adj usted such that the catalyst metal only wets portions of the side edges , in particular down to the level of the active region or a little closer towards the doped layer 2 . This will on the one side prevent a short circuit later, and on the other still ensure reflection of photons being generated in the active region and emitted sideways .
Then a conductive material is supplied for a VLS process , which is substantially transparent . The conductive transparent material liquefies in the catalyst metal and forms a half-ball structure 54 covering the top surface as well as the side edges of p-side layer 7 . After this step , the process is substantial finished if the catalyst metal is of high reflectivity . In such cases , the catalyst metal is cooled down forming a reflective layer 55 around the conductive transparent material 54 . In operation, the photons emitted in the active region 6 are transmitted into every direction . Photons emitted into the transparent conductive material 54 will be reflected at the metal layer 55 and finally leave the device through thin doped layer 2 and -f present- growth substrate 1 . By adj usting the catalyst metal properties and the contact angle , it is possible to form a reflective layer having certain optical properties .
LIST OF REFERENCES
1 growth substrate
2 doped layer
3 initial buffer layer
4 structured dielectric mas k
5 catalyst metal layer
6 functional layer stack
7 p-side layer
21 exposed surface
51 catalyst metal studs
52 , 52a , 52b catalyst metal droplets
53 catalyst metal droplets
54 transparent contact
55 reflective metal
61 n-doped layer
61a material for layer 61
62 quantum well layer, active region layer
62a material for layer 62
63 p-doped layer
63a material for the p-doped layer
71 doped covering layer

Claims

- 28 -
CLAIMS Method for processing an optoelectronic device, in particular a p- LED comprising the steps of :
Providing a structured mask including portions covered by mask material and exposed portions (21) on a surface of a doped layer (2) arranged on a growth substrate (1) ;
Generating catalyst metal studs on the exposed portions (21) ;
Generating catalyst metal droplets (52) from the catalyst metal studs (51) wetting parts of the respective exposed portions (21) ;
Depositing a first semiconductor layer (61) , from a gas phase containing material of the first semiconductor layer (61) , on the surface part of the exposed portion (21) wetted by the catalyst metal droplets (52) ;
Depositing a semiconductor layer stack (62, 63, 6) including an active region (62) on the first semiconductor layer (61) from a gas phase containing material of the semiconductor layer stack, wherein a top surface of the first semiconductor layer (61) is wetted by the catalyst metal droplets (52) ; wherein the step of depositing a semiconductor layer stack comprises the steps of : o Reshaping the catalyst metal droplets (52) such that it wets at least side surfaces of the portions of the semiconductor layer stack and optionally side surfaces of the first semiconductor layer (61) ; o Depositing a semiconductor material (7) on the top surface and on the side surface of the semiconductor layer stack thereby covering edge areas of the active region (62) . Method according to claim 1, wherein providing a structured mask comprises :
- providing a growth substrate (1) ;
- depositing one or more semiconductor layer (2) on the growth substrate (1) , whereas at last a top surface layer (2) comprises a dopant ; - depositing a mask material ( 4 ) on the surface of the top surface layer ( 2 ) ;
-structuring the mas k and removing portions of the mask material as to provide covered portions and exposed portions ( 21 ) on the surface of the doped layer ( 2 ) . Method according to claim 1 or 2 , wherein generating catalyst metal studs comprises
- depositing a catalyst metal on the surface of a doped layer ( 2 ) and the structured mask;
- removing the structured mask with the catalyst metal deposited thereupon . Method according to claim 1 or 2 , wherein generating catalyst metal studs comprises
- dispensing material containing the catalyst metal on the exposed portions ( 21 ) . Method according to claim 3 or 4 , wherein a height of the remaining catalyst metal studs on the exposed portions ( 21 ) is larger than a height of the structured mas k . Method according to any of the preceding claims , wherein the catalyst metal studs comprises at least a metal selected from a group consisting of :
- Gold;
- Nickel ;
- Gallium;
- Silver ;
- Iridium;
- Palladium;
- Platinum;
- Lead; and
- Titanium . Method according to any of the preceding claims , wherein the structured mask comprises a dielectric material , optionally having a melting point higher than a melting point of the catalyst metal. Method according to any of the preceding claims, wherein generating catalyst metal droplets comprises heating the metal catalyst material above its respective melting point, wherein the molten metal forms a contact angle (0C) between 70° and 150° and in particular between 80° and 150° and in particular above 85° . Method according to any of the preceding claims, wherein a contact angle (0C) between the catalyst metal droplets (52) and the surface of the exposed portion and/or the top surface of the first semiconductor layer is adjustable based on at least one parameter from the group consisting of :
- temperature of the catalyst metal;
- choice of the material of the surface and the catalyst droplet;
- ambient pressure;
- amount of a second catalyst metal being added to the catalyst metal droplets (52) during a processing step. Method according to any of the preceding claims, wherein a contact angle between the catalyst metal droplets (52) and the surface of the exposed portion is larger than 90° and larger than a contact angle between the catalyst metal droplets (52) and the surface of the exposed portion after the step of reshaping the catalyst metal droplets . Method according to any of the preceding claims, wherein a contact angle 0C after the step of reshaping is smaller than 90° and particularly between 40° and 75° . Method according to any of the preceding claims, wherein the steps of depositing a first semiconductor layer (61) and/or depositing a semiconductor layer stack comprises providing the respective material by a MOCVD or MOVPE process. Method according to any of the preceding claims, wherein at least one process parameter is selected from the group consisting of:
- ambient temperature;
- surface temperature; and
- pressure is adjusted during depositions steps such that material of the first semiconductor layer and/or the semiconductor layer stack would not deposit on a respective exposed top surface. Method according to any of the preceding claims, wherein during the steps of depositing a semiconductor layer stack (62, 63, 6) , the catalyst metal droplets wets only the surface of the topmost layer . Method according to any of the preceding claims, wherein reshaping the catalyst metal droplets (52) comprises:
- forming a shell by the catalyst metal droplet only covering the functional layer stack (62, 63, 6) optionally including a portion of the first semiconductor layer (61) ; or forming a shell by the catalyst metal droplet covering the functional layer stack (62, 63, 6) and comprising a contact angle of larger than 90° on the surface of a doped layer (2) . Method according to any of the preceding claims, wherein depositing a semiconductor material on the top surface and on the side surface of the semiconductor layer stack comprises at least one of
- providing the semiconductor material from a gas phase through the metal catalyst droplets (52) ;
- performing a re-growth using a material causing a shift of the bandgap in edge areas of the active region; and
- diffusing a dopant at least into edge areas of the active region cause a quantumwellintermixing thereof. Method according to any of the preceding claims, wherein the semiconductor material covering edge areas of the active region (62) comprises a larger bandgap than the active region. - 32 - Method according to any of the preceding claims, wherein the active region comprises a quantum well. Method according to any of the preceding claims, wherein the active region comprises at least one of the semiconductor materials from the group consisting of :
GaN or GaP;
AlGaN or AlGaP;
InGaN or InGaP;
AlInGaN or AlInGaP;
GaAs or GaP; and AlGaAs or AlGaP . Method according to any of the preceding claims, wherein the semiconductor material on the top surface comprises a different dopant than the first semiconductor layer (61) . Method according to any of the preceding claims, wherein the first semiconductor layer (61) and/or the semiconductor layer stack (62, 63, 6) comprises an area in the range of 4pm2 to 2500pm2 and in particular smaller than 2000pm2 and in particular between 10pm2 and 400pm2 . Method according to any of the preceding claims, wherein the first semiconductor layer (61) and/or the semiconductor layer stack (62, 63, 6) comprises a circular footprint; or wherein the first semiconductor layer (61) and/or the semiconductor layer stack (62, 63, 6) comprises a rod or pillar shape . ethod according to any of the preceding claims further comprising after depositing a semiconductor layer stack:
- depositing a transparent conductive material on at least the top surface of the deposited semiconductor material (7) ; or
- depositing a dielectric material on at least the top surface of the deposited semiconductor material (7) ; 33
- wherein the catalyst metal droplet forms a reflective layer around the semiconductor layer stack . Method according to any of the preceding claims further comprising after depositing a semiconductor layer stack : forming an optical spacer element ( 8 ) between two adj acent functional layer stacks , in particular utilising the catalyst metal droplet . ptoelectronic device comprising :
- a functional layer stack ( 6 ) having an active region arranged between two differently doped conductive semiconductor layers ; wherein material of one ( 7 ) of the two differently doped semiconductor layers extends along the side surfaces of the functional layer stack covering the side edges of the active region; wherein residuals of a catalyst metal are present in at least one of the functional layer stack and the active region and the material covering the side surfaces of the functional layer, the residuals of the catalyst metal comprising at least one metal selected from a group consisting of :
- Gold;
- Nickel ;
- Gallium;
- Silver ;
- Iridium;
- Palladium;
- Platinum;
- Lead; and
- Titanium .
PCT/EP2022/086599 2022-01-14 2022-12-19 Method for processing an optoelectronic device and optoelectronic device WO2023134966A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1613549A1 (en) * 2003-04-04 2006-01-11 Startskottet 22286 AB Precisely positioned nanowhiskers and nanowhisker arrays and method for preparing them
EP3577730A1 (en) * 2017-02-03 2019-12-11 Norwegian University of Science and Technology Lasers or leds based on nanowires grown on graphene type substrates
US20210151498A1 (en) * 2019-11-14 2021-05-20 Facebook Technologies, Llc In situ selective etching and selective regrowth of epitaxial layer for surface recombination velocity reduction in light emitting diodes

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1613549A1 (en) * 2003-04-04 2006-01-11 Startskottet 22286 AB Precisely positioned nanowhiskers and nanowhisker arrays and method for preparing them
EP3577730A1 (en) * 2017-02-03 2019-12-11 Norwegian University of Science and Technology Lasers or leds based on nanowires grown on graphene type substrates
US20210151498A1 (en) * 2019-11-14 2021-05-20 Facebook Technologies, Llc In situ selective etching and selective regrowth of epitaxial layer for surface recombination velocity reduction in light emitting diodes

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