WO2023133725A1

WO2023133725A1 - Transistor and semiconductor integrated circuit

Info

Publication number: WO2023133725A1
Application number: PCT/CN2022/071576
Authority: WO
Inventors: 王学雯; 李泠霏; 吴颖; 许俊豪
Original assignee: 华为技术有限公司
Priority date: 2022-01-12
Filing date: 2022-01-12
Publication date: 2023-07-20
Also published as: CN116762178A

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide a transistor and a semiconductor integrated circuit comprising the transistor. The present application mainly aims to provide a transistor structure having low energy consumption and small size. The transistor comprises: a source, a drain, a channel, and a gate; the channel formed by a semiconductor material is disposed between the source and the drain; the gate is stacked on at least a portion of the surface of the channel. That is to say, the transistor is a three-terminal semiconductor device. In addition, the transistor further comprises a stress layer and a stress gate for applying a voltage to the stress layer, the stress layer is stacked on at least a portion of each of the surfaces of the source and the drain, and a stress control gate layer is stacked on the stress layer.

Description

A kind of transistor, semiconductor integrated circuit

technical field

The embodiments of the present application relate to the technical field of semiconductors, and in particular, to a transistor and a semiconductor integrated circuit including the transistor.

Background technique

With the continuous evolution of semiconductor integrated circuit (integrated circuit, IC) technology, the integration level of integrated circuits is getting higher and higher, and the size of transistors is shrinking continuously. Denard's law of scaling states that as transistors get smaller, their power density (ratio of power to area) remains constant. Therefore, in order to adapt to the development of high integration of integrated circuits, designing a transistor with low energy consumption is a difficult problem to be overcome at key nodes of miniaturization.

Contents of the invention

The present application provides a transistor and a semiconductor integrated circuit including the transistor. The main purpose is to provide a transistor structure that can realize low energy consumption, so as to adapt to the small size of transistors and the development trend of high integration of integrated circuits.

In order to achieve the above object, the embodiments of the present application adopt the following technical solutions:

In a first aspect, the present application provides a transistor, which can be applied in circuit structures such as storage circuits and logic control circuits.

The transistor includes: a source, a drain, a channel, and a gate, and a channel formed of a semiconductor material is disposed between the source and the drain, and the gate is stacked on at least part of the surface of the channel, that is, Said that the transistor here belongs to a three-terminal semiconductor device. In addition, the transistor also includes a stress layer and a stress control gate layer for applying voltage to the stress layer, and the stress layer is stacked on at least part of the surface of the source and the drain, and the stress control gate layer is stacked on the stress layer. superior.

In the transistors given in this application, not only source and drain, channel and gate are included. In particular, the transistor provided in this application further includes a stress layer and a stress control gate layer for controlling the voltage of the stress layer. Then, when a bias voltage is applied to the stress layer through the stress control gate layer, under the action of the voltage, the stress layer will deform and generate stress. This stress can deform the channel, thereby increasing the current carrying capacity of the channel. subrate. Moreover, as the stress increases, the mobility of the channel increases, so that the sub-threshold slope (SS) of the transistor is reduced to below 60mV/dec, thereby reducing the power consumption of the transistor.

In addition, stress layers are stacked on at least part of the surfaces of the source and drain, that is to say, the stress layer is formed on the source and drain instead of the gate. In this way, even if the gate spacing between every two adjacent transistors gradually decreases as the size of the transistor shrinks, the setting of the stress layer and the stress control gate layer will not be affected due to the small accommodation space near the gate. It can also be said that if the stress layer and the stress control gate layer are sequentially stacked on the source and drain, it can be applied to the continuous shrinking of the transistor node, for example, it can be applied to the transistor structure with a node below 14nm.

Based on the above description of the transistor structure, it can be obtained that the transistor structure provided in the present application can not only realize low power consumption, but also realize small size, so as to be applied in the application scenarios of small-node transistors.

In a possible implementation manner, both the source electrode and the drain electrode include a connected first side surface and a second side surface; a stress layer is stacked on both the first side surface and the second side surface.

That is to say, the stress layer belongs to a structure surrounding the contact layer. In this way, the contact area between the stress layer and the corresponding source and drain can be increased, and further, stress can be applied to the source and drain from multiple dimensions to further increase the carrier velocity of the channel. Moreover, as the stress increases, the mobility of the channel increases, further reducing the subthreshold slope of the transistor, thereby further reducing the power consumption of the transistor.

In a possible implementation manner, in the source electrode and the drain electrode, the stress control gate layer is arranged around the periphery of the stress layer.

In this case, the formed stress gate also belongs to a surrounding contact layer structure. With this design, after the stress layer is loaded with a voltage, the stress layers at different positions can be uniformly deformed to generate stress, so that the channel can be uniformly deformed and the carrier flow rate can be more uniform.

In a possible implementation manner, the stress layer includes a connected third side surface and a fourth side surface; both the third side surface and the fourth side surface are covered by the stress control gate layer.

In a possible implementation manner, the transistor further includes a substrate; the channel extends along a direction parallel to the substrate, and a source and a drain are formed on opposite sides of the channel along a direction parallel to the substrate.

In this embodiment, since the channel is arranged in a direction parallel to the substrate, the formed transistor can be called a horizontal channel transistor structure. That is to say, the stress layer and the stress control gate layer provided in this application can be arranged on the source and drain of the horizontal channel transistor. For example, the transistor may be a planar transistor.

In a possible implementation manner, in the source and the drain, the stress layer and the stress control gate layer are sequentially stacked on the source and the drain along a direction perpendicular to the substrate.

When the transistor has a horizontal channel transistor structure, the stress layer and the stress control gate layer are sequentially stacked along a direction perpendicular to the substrate. That is to say, the stress layer and the stress control gate layer are arranged along the height direction perpendicular to the substrate. In this way, the space can be further reduced, the integration density of the piezoelectric transistor can be increased, and the transistor structure of a small node can be adapted.

In a possible implementation manner, the transistor further includes a substrate; the channel extends along a direction perpendicular to the substrate, and a source and a drain are formed on opposite sides of the channel along a direction perpendicular to the substrate.

In this embodiment, since the channel is perpendicular to the substrate, the formed transistor can be called a vertical channel transistor structure. Likewise, the stress layer and the stress control gate layer provided in this application can be disposed on the source and drain electrodes of the vertical channel transistor. For example, the transistor may be a vertical structure nanowire field effect transistor.

In a possible implementation manner, in the source and the drain, the stress layer and the stress control gate layer are sequentially stacked on the source and the drain along a direction parallel to the substrate.

In this way, the stress layer and the stress control gate layer will not occupy the space near the gate.

In a possible implementation manner, the stress layer includes at least one of lead zirconate titanate, aluminum nitride, and titanium nitride.

For example, when titanium nitride is used, the diffusion of metal elements in the source, drain and stress control gate layers can be suppressed, and furthermore, the conductive performance of the transistor will not be affected due to the existence of the stress layer.

In a possible implementation manner, the stress control gate layer, the drain and the source are made of the same material.

For example, at least one of tungsten (W), ruthenium (Ru), molybdenum (Mo), iridium (Ir), nickel (Ni), platinum (Pt), tungsten (W), gold (Au) and other materials can be used be made of.

In a possible implementation manner, the transistor is a gate-around transistor, a vertical structure nanowire field effect transistor, a fin field effect transistor, or a planar transistor manufactured through a doping process.

Certainly, the transistor including the stress layer and the stress control gate layer may also have other types of transistor structures.

In a possible implementation manner, the transistor has a PMOS structure, or the transistor has an NMOS structure.

In a second aspect, the present application provides a semiconductor integrated circuit, the semiconductor integrated circuit includes passive devices, such as inductors, resistors, or capacitors, etc., and may also include the transistor in any implementation manner of the first aspect above, and the The transistor is electrically connected to the passive device.

In the semiconductor integrated circuit given in this embodiment, since the included transistor includes a stress layer and a stress control gate layer for controlling the voltage of the stress layer, in this way, when the stress control gate layer applies a bias voltage to the stress layer, the stress layer Under the action of this voltage, deformation will occur and stress will be generated. This stress can deform the channel, thereby increasing the carrier velocity of the channel. Moreover, as the stress increases, the mobility of the channel increases, so that the sub-threshold slope (Sub-threshold Slope, SS) of the transistor is reduced to below 60mV/dec, thereby reducing the power consumption of the transistor.

In addition, since the transistors in the semiconductor integrated circuit, the stress layer and the stress control gate layer for controlling the voltage of the stress layer are stacked on the source and drain instead of the gate, so that the semiconductor integrated circuit can be improved. The integration density of the circuit. It can also be said that even if the nodes of transistors are continuously shrunk, the transistor structure including the stress layer and the stress control gate layer is also suitable for the development trend of small nodes.

Description of drawings

Fig. 1 is a structural diagram of a transistor;

FIG. 2 is a partial structural diagram of a transistor provided in an embodiment of the present application;

FIG. 3 is a partial structural diagram of a transistor provided in an embodiment of the present application;

Fig. 4 is the A-A sectional view of Fig. 3;

FIG. 5 is a partial structural diagram of two transistors provided in the embodiment of the present application;

Fig. 6 is the I-V curve of the N-type transistor that the embodiment of the present application provides;

FIG. 7 is a partial structural diagram of multiple transistors provided in the embodiment of the present application;

FIG. 8 is a partial structural diagram of multiple transistors provided by the implementation of the present application;

Fig. 9 is a B-B sectional view of Fig. 8;

FIG. 10 is a partial structural diagram of a transistor provided in an embodiment of the present application;

FIG. 11 is a partial structural diagram of a transistor provided in an embodiment of the present application;

Fig. 12 is the D direction view of Fig. 11;

Fig. 13 is the C-C sectional view of Fig. 11;

FIG. 14 is a partial structural diagram of a transistor provided in an embodiment of the present application;

FIG. 15 is a partial structural diagram of a transistor provided in an embodiment of the present application.

Reference signs:

100-substrate;

200-transistor;

301 - first extension;

302 - second extension;

401 - source metal layer;

402—drain metal layer;

500 - dielectric layer;

01-source;

02-drain;

03-channel;

04-grid;

05-stress layer;

06 - Stress control gate layer.

Detailed ways

In some electronic devices, such as a terminal device, such as a mobile phone, a tablet computer, and a smart bracelet, it may also be a personal computer (personal computer, PC), a server, a workstation, and the like. Electronic devices such as those described above may include a system on chip (SOC) and memory.

The system-on-chip SOC can be used to process data, such as processing application data, processing image data, and buffering temporary data. The memory can be used to save data, such as audio files, video files, and so on. The memory may be programmable read-only memory (programmable read-only memory, PROM), erasable programmable read-only memory (erasable programmable read-only memory, EPROM), flash memory (flash memory) and the like.

Integrated circuits (integrated circuits, ICs) with different functions are integrated in the above-mentioned similar SoCs or different types of memories. Integrated circuits are electrically connected through various active devices (such as transistors) and various passive devices (such as capacitors, inductors, and resistors) to form a circuit structure.

With the diversification of functions of electronic equipment, the integration level of integrated circuits is getting higher and higher, and the size of transistors is also shrinking. For example, the node of transistors can reach below 14nm. In order to keep the power density of the transistor constant, since the power density is positively related to the ratio of power to area, furthermore, while reducing the size of the transistor, it is also necessary to reduce the power consumption of the transistor.

In this technical field, the subthreshold state of a transistor is an important working state (also called a working mode) of a semiconductor device, and is also called a subthreshold region of a transistor. In the sub-threshold state of the transistor, the sub-threshold slope (SS) is an important performance indicator, and the sub-threshold slope SS represents the gate-source voltage required for the sub-threshold current to be reduced by 10 times. Obviously, the smaller the value of the subthreshold slope SS, the faster the switching (that is, the transition between the on-state and the off-state) of the device. Therefore, the value of the subthreshold slope SS reflects the switching performance of the transistor in the subthreshold region.

Reducing the sub-threshold slope SS is a very effective way to reduce the operating voltage of the transistor and reduce power consumption. If they are to be suitable for future low-power high-performance chips, these low-power devices also need to maintain a sufficiently high operating current. In some achievable ways, applying stress to the transistor can effectively improve the mobility of the device, thereby reducing the sub-threshold The slope SS can reduce the power consumption of the device while ensuring the working current of the device.

FIG. 1 shows a process structure diagram of a transistor, and the transistor is a fin field-effect transistor (fin field-effect transistor, FinFET) structure. As shown in Fig. 1, the transistor includes a source (source) 01, a drain (drain) 02 formed on a substrate 100, and a channel 03 formed between the source 01 and the drain 02, and the gate 04 is in the form of a fin Type structures are disposed on opposite sides of the channel 03. In addition, the transistor also includes a stress layer 05 formed by lead zirconate titanate (Pb-based lanthanumdoped zirconate titanates, PZT) piezoelectric ceramics, and a stress control gate layer 06 formed on the stress layer 05 . That is, a piezoelectric field-effect transistor (piezoelectric field-effect transistor, PizeoFET) is prepared by using PZT piezoelectric ceramics as a stressor.

In the piezoelectric field effect transistor shown in Figure 1, the bias voltage applied to the PZT piezoelectric ceramic can be adjusted dynamically through the stress control gate layer 06, which can dynamically change the mobility of the transistor, thereby reducing the subthreshold slope SS of the transistor To below 60mV/dec, to achieve high performance and low power consumption.

As shown in Figure 1, the stress source of the transistor is applied to the gate 04 through the stress layer 05. As the integration density of semiconductor devices increases, the distance between the gates 04 of two adjacent transistors gradually decreases, and the gate 04 There is little room nearby for other layer structures. For example, in the structure shown in Figure 1, when the critical node length of the transistor is less than 14nm, the fin pitch (fin pitch) is already less than 30nm, and the space between the gate 04 and the gate 04 is not enough to insert the stress layer 05 and stress Control gate layer 06. This is mainly because the stress layer 05 needs to have a certain thickness (for example, 5 nm) if it is to provide sufficient strain to apply sufficient stress to the gate 04 . In addition, in addition to the stress layer 05, a stress control gate layer 06 needs to be added, which further increases the occupied space, so the stress application scheme shown in FIG. 1 is no longer applicable to advanced nodes smaller than 14nm. That is to say, although the piezoelectric field effect transistor shown in FIG. 1 can achieve low power consumption, it is not suitable for transistor structures with smaller nodes.

However, the embodiment of the present application provides a new type of transistor structure, which can not only achieve low power consumption, but also achieve high-density integration, for example, it can meet the requirements of transistors of advanced nodes below 14nm. The transistor structure involved in the application will be described in detail below with reference to the accompanying drawings.

FIG. 2 is a partial process structure diagram of a transistor 200 integrated on a substrate 100 provided by an embodiment of the present application. In this FIG. 2 , only the source 01 and the drain 02 included in the transistor 200 , and the channel 03 formed between the source 01 and the drain 02 and made of a semiconductor material are shown.

The transistors provided in this application may have a PMOS transistor structure, or may also have an NMOS transistor structure.

In addition to the source 01 and drain 02 shown in FIG. 2, and the channel 03, the transistor 200 may also include a gate and a gate dielectric layer. Used to isolate the channel and gate. As for the specific positions of the gate electrode and the gate dielectric layer, there are many situations that can be realized to form transistor structures with different structures, and several realizable structures will be introduced in detail below.

Continuing as shown in Figure 2, when a voltage is applied to the source 01, drain 02, and gate, under the action of a strong electric field between the source and drain, a large number of electron vacancies will be generated in the channel 03 between the source and drain. pair of holes so that the transistor is turned on or off.

FIG. 3 is a structural diagram after adding other layer structures on the basis of FIG. 2 , and FIG. 4 is a cross-sectional structural diagram cut along the A-A direction in FIG. 3 . Combining FIG. 3 and FIG. 4 together, the transistor 200 includes a stress layer 05 and a stress control gate layer 06 in addition to the source 01 , the drain 02 , and the channel 03 . Specifically, as shown in Figure 4, a stress layer 05 can be stacked on the surface of the first extension portion 301 of the source 01, and the stress control gate layer 06 can be stacked on the stress layer 05; A stress layer 05 is also stacked on the surface of the extension part, and a stress control gate layer 06 is stacked on the stress layer 05 of the drain 02 .

The first extension portion 301 in FIG. 4 is a part of the source electrode 01 , and in an optional process, the first extension portion 301 and the source electrode 01 can be made of the same material.

The stress layer 05 here can be made of piezoelectric material, electrostrictive material and the like. For example, the stress layer 05 can be made of lead zirconate titanate (Pb-based Lanthanumdoped Zirconate Titanates, PZT), aluminum nitride (AlN), titanium nitride (TiN), lead-free piezoelectric materials, and the like.

The stress control gate layer 06 here can be made of tungsten (W), ruthenium (Ru), molybdenum (Mo), iridium (Ir), nickel (Ni), platinum (Pt), tungsten (W), gold (Au) and the like.

Among the optional process means, stress can be obtained by physical vapor deposition (physical vapor deposition, PVD), chemical vapor deposition (chemical vapor deposition, CVD), or atomic layer deposition (atomic layer deposition, ALD) and other film deposition processes. layer 05 and stress control gate layer 06.

In some optional implementations, the source 01 and the drain 02 can also be made of metal materials, such as tungsten (W), ruthenium (Ru), molybdenum (Mo), iridium (Ir), nickel (Ni) , platinum (Pt), tungsten (W), gold (Au), etc.

In an optional material of the transistor, titanium nitride (TiN) can be used as the stress layer 05, in this case, the material interdiffusion of metal can be avoided, and the short circuit between the stress control gate layer 06 and the source and drain can be prevented. .

In some embodiments, the thickness of the stress layer 05 may range from 1 nm to 200 nm. The thickness of the stress control gate layer 06 is in the range of 1 nm to 200 nm. Of course, what is mentioned above is only an achievable size of the stress layer 05 and the stress control gate layer 06 , and other thickness sizes of the stress layer 05 and the stress control gate layer 06 can also be selected.

During specific implementation, the stress control gate layer 06 is electrically connected to the control signal line, and a voltage is applied to the stress control gate layer 06 through the control signal line, and the stress layer 05 will generate mechanical strain due to the inverse piezoelectric effect, and the mechanical strain will act on the On the source 01 stacked with the stress layer 05, and the mechanical strain will cause the channel 03 to be strained accordingly. Similarly, the mechanical strain will also act on the drain 02, and the drain 02 will also act on the On the channel 03, the channel 03 will also be strained.

Then, when a mechanical strain acts on the channel 03, stress will be generated in the channel 03, and the stress will change the mobility of the channel 03 (that is, change the carrier velocity), so that the subthreshold slope SS of the transistor is less than 60mV/dec, thereby reducing the power consumption of the transistor and realizing the low energy consumption of the transistor.

FIG. 5 is based on FIG. 4 with an additional transistor structure, that is, two transistor structures 200 are shown in FIG. 5 . It can be seen from FIG. 4 and FIG. 5 that the added stress layer 05 and stress control gate layer 06 will only occupy the space near the source 01 and the drain 02, and will not occupy the space near the gate (that is, the channel). Furthermore, compared with the stress application scheme shown in FIG. 1 , the stress application structure proposed in the present application can be applied to the continuous shrinking of transistor nodes, for example, it can be applied to transistor structures with nodes below 14nm, thus suitable for high-density integration of transistors. Certainly, the transistor structure provided in the embodiment of the present application may also be applied in a scenario where the node is larger than 14nm.

Combined with Figure 4 and Figure 5, the stress control gate layer 06 can be applied to the stress layer 05 with different magnitudes of voltage, so that the stress layer 05 can obtain dynamic stress, the dynamic stress can regulate the energy band of the channel, and then change the energy in the channel. The effective mass of the carriers, thereby changing the mobility of the channel, so that the subthreshold slope SS of the transistor is less than 60mV/dec. Then, obviously, the embodiments of the present application make use of the inverse piezoelectric effect or the electrostrictive effect to make the subthreshold slope SS of the transistor less than 60mV/dec, thereby reducing the operating voltage of the circuit, and at the same time, the on-state current of the transistor is relatively large, and the transistor The off-state current is relatively small. That is, while the power consumption of the transistor is reduced, the driving current of the transistor will not be reduced.

Figure 6 shows the I-V curve of the N-type PizeoFET device. It can be seen from Figure 6 that the current of the transistor device will change with the change of the stress. For example, in Figure 6, the tensile stress F1<tensile stress F2<tensile stress F3<tensile stress F4, then the current of the transistor device There is an increasing trend. Furthermore, for the NMOS transistor, as the tensile stress gradually increases, the drain current of the device gradually increases, and finally a large driving current can be obtained while ensuring a low off-state current, that is, when the transistor is applied Dynamic tensile stress can effectively reduce the power consumption of the transistor.

In some optional implementation manners, in order to increase the contact area between the stress layer 05 and the corresponding source 01 , the stress layer 05 is arranged around the periphery of the source 01 or the drain 02 . For example, as shown in FIG. 4 and FIG. 5 , the first extension 301 of the source 01 includes opposite first side surfaces M1 and second side surfaces M2, and a connection between the first side surface M1 and the second side surface M2. The first connection surface M3 , and the first side surface M1 , the second side surface M2 and the first connection surface M3 are all covered by the stress layer 05 .

Similarly, in order to increase the contact area between the stress layer 05 and the corresponding drain 02, the drain 02 may also include opposite first side surfaces M1 and second side surfaces M2, and connect the first side surface M1 and the second side surface The first connection surface M3 of the two side surfaces M2 , and the first side surface M1 , the second side surface M2 and the first connection surface M3 are all covered by the stress layer 05 .

The stress layer 05 thus formed on the source 01 and the drain 02 may be called a wrap around contact (WAC) piezoelectric structure. The WAC piezoelectric structure can apply stress to the source 01 and drain 02 from multiple dimensions, further regulate the energy band of the material of the channel 03, and reduce the subthreshold slope of the transistor, thereby further reducing the transistor’s power consumption.

It should be noted that, in FIG. 4 and FIG. 5 , a structure of the first extension 301 of the source 01 with a diamond-shaped cross section is given. Of course, this is only an embodiment. The first extension 301 Other shapes can also be used, as long as the stress layer 05 and the stress control gate layer 06 are sequentially stacked on the source electrode 01 and the drain electrode 02 .

In addition, the stress control gate layer 06 may also be arranged around the periphery of the stress layer 05 . For example, in FIG. 4, the stress layer 05 has a third side surface opposite to the first side surface M1, and a fourth side surface opposite to the second side surface M2, and also has a connecting third side surface and the fourth side surface The second connection surface of the surface, the stress control gate layer 06 covers the third side surface, the fourth side surface, and the second connection surface. The stress control gate layer 06 thus formed may also be referred to as a WAC layer structure.

Alternatively, in some other implementation manners, the stress layer 05 and the stress control gate layer 06 may be sequentially stacked on the connected first side surface and second side surface of the source and drain.

FIG. 7 is a structural diagram of a transistor given in the embodiment of the present application. FIG. 8 is a structural diagram after removing the first extension 301 and the second extension 302 on the basis of FIG. 7 and adding some layer structures. Fig. 9 is a cross-sectional structural view cut along the B-B direction of Fig. 8 . As shown in Fig. 7, it includes a plurality of transistors 200 arranged on the substrate 100, and these plurality of transistors 200 are arranged in a three-dimensional structure along the direction perpendicular to the substrate 100, and each transistor 200 includes a source 01 , the drain 02 and the channel 03, and also include the gate dielectric layer 07 and the gate 04. As shown in FIG. At the interface where the electrode 04 and the channel 03 are in contact, the transistor formed in this way can be called a gate-all-around field effect transistor (GAA FET).

In some usage scenarios, for example, in a high-performance low-power consumption module, as shown in FIG. 7 , it is necessary to electrically connect the sources 01 of multiple transistors 200 , and to electrically connect the drains 02 of multiple transistors 200 . Then, as shown in FIG. 7 , a first extension 301 and a second extension 302 can be provided, the first extension 301 is electrically connected to the sources 01 of multiple transistors 200 , and the second extension 302 is electrically connected to the drains of multiple transistors 200 02. It can also be understood in this way that the first extension 301 may belong to a part of the structure of the source 01 of the transistor 200 , and similarly, the second extension 302 may also belong to a part of the structure of the drain 02 of the transistor 200 .

FIG. 10 is a cross-sectional structure diagram after adding a stress layer 05 and a stress control gate layer 06 on the basis of the first extension portion 301 or the second extension portion 302 shown in FIG. 7 . As shown in FIG. 10 , the stress layer 05 and the stress control gate layer 06 can be sequentially stacked on the first extension 301 , and the stress layer 05 and the stress control gate layer 06 can be sequentially stacked on the second extension 302 . In such a design, when a voltage is applied to the stress control gate layer 06 on the first electrical connection layer 301, mechanical stress will be applied to the first extension layer 301 through the stress layer 05, and further, the channels of the multiple transistors 200 will be 03 Simultaneously apply mechanical stress, regulate the energy bands of the materials of the channel 03 of multiple transistors 200, dynamically change the mobility of these multiple transistors, thereby reducing the subthreshold slope SS of these transistors to below 60mV/dec, and realize these multiple transistors high performance and low power consumption.

Continuing to combine FIG. 7 , FIG. 8 and FIG. 9 together with FIG. 10 , since the stress layer 05 and the stress control gate layer 06 are stacked on the first extension 301 and the second extension 302 instead of stacking on the gate 04 That is to say, the stress layer 05 and the stress control gate layer 06 are stacked along the direction perpendicular to the substrate 100, and further, the space near the gate 04 shown in FIG. 9 will not be occupied, that is, the stress layer 05 and the The stress control gate layer 06 does not occupy the space between the channels of the transistor, so that it does not affect the dense arrangement of the device, and can be applied to the device manufacturing of advanced nodes.

The stress layer 05 shown in FIG. 10 is also a WAC piezoelectric structure, that is, the stress layer 05 is arranged around the source and drain to increase the contact area with the source and drain and increase the mechanical stress applied to the source and drain and the channel. Thus, the power consumption of the transistor is reduced.

Figure 11 is a structural diagram of another transistor according to the embodiment of the present application, and Figure 12 is a cross-sectional structural diagram along the D direction of Figure 11, in this transistor, the channel 03 is located between the source 01 and the drain 02 Between, as shown in Figure 11 and Figure 12, the gate 04 is arranged on the periphery of the channel 03, the gate dielectric layer 07 is formed at the interface where the gate 04 and the channel 03 are in contact, and the channel 03 is in the same shape as the substrate. Arranged in a vertical direction to form a vertical channel, such a transistor can be called a vertical nanowire field effect transistor (vertical NWFET).

FIG. 13 is a cross-sectional structure diagram after adding some layer structures on the basis of FIG. 11 and cutting along the C-C direction of FIG. 11 . As shown in FIG. 13 , the transistor may further include a stress layer 05 and a stress control gate layer 06 , and may further include a first extension 301 and a second extension 302 . The first extension 301 is arranged on the side of the source 01 away from the drain 02 , the second extension 302 is arranged on the side of the drain 02 away from the source 01 , and the first extension 301 and the second extension Stress layer 05 and stress control gate layer 06 are sequentially stacked on the sides of 302 .

Like the above-mentioned gate-all-around field effect transistor (GAA FET) shown in FIG. Part of the structure belonging to the drain 02 of the transistor 200 . That is to say, from a process point of view, the first extension 301 and the source 01 can be made of the same material, and similarly, the second extension 302 and the drain 02 can be made of the same material.

From the vertical structure nanowire field effect transistor (vertical NWFET) shown in Figure 13, it is obvious that the stress layer 05 and the stress control gate layer 06 are stacked on the source and drain electrodes, and will not occupy the space near the gate 04, Furthermore, the development of this kind of piezoelectric field effect transistor will not be restricted due to the miniaturization of the distance between the gates.

FIG. 14 is a structural diagram of another transistor according to an embodiment of the present application. In this transistor, a first doped region 101 and a second doped region 102 are formed by using a doping process on a substrate 100. The substrate 100 The part between the first doped region 101 and the second doped region 102 forms the channel 03, where one of the first doped region 101 and the second doped region 102 forms the source of the transistor pole and the other forms the drain. In addition, a gate dielectric layer 07 and a gate 04 are sequentially formed on the channel 03 through a thin film deposition process, and the transistor formed in this way may be called a planar transistor.

In order to electrically connect the first doped region 101 and the second doped region 102 formed by the previous process with the metal connection layer formed by the subsequent process, a source electrode can be formed in the dielectric layer 500 as shown in FIG. 13 The metal layer 401 and the drain metal layer 402 , and the source metal layer 401 is electrically connected to the first doped region 101 , and the drain metal layer 402 is electrically connected to the second doped region 102 .

FIG. 15 is a cross-sectional structure diagram after adding a stress layer 05 and a stress control gate layer 06 on the basis of the source metal layer 401 and the drain metal layer 402 shown in FIG. 14 . In FIG. 15 , the stress layer 05 is disposed around the source metal layer 401 and the drain metal layer 402 respectively in a WAC structure, and the stress control gate layer 06 is further disposed around the stress layer 05 .

14 and 15 together, in this planar transistor, the stress layer 05 and the stress control gate layer 06 are stacked above the source metal layer 401 of the first doped region 101, similarly, the stress layer 05 and the stress The control gate layer 06 is stacked above the drain metal layer 402 of the second doped region 102 . Instead of being stacked above the area where the gate 04 is located. Furthermore, it does not occupy the space between channels and does not affect the dense arrangement of devices, and can be applied to 14nm advanced nodes.

In the planar transistor shown in FIG. 14 and FIG. 15 , the stress layer 05 is not directly stacked on the surface of the first doped region 101 , but a source electrode is also formed between the stress layer 05 and the first doped region 101 The layer structure of the metal layer 401 , that is, the stress layer 05 is indirectly stacked on the first doped region 101 . In this way, the stress generated by the stress layer 05 can be transmitted to the first doped region 101 through the source metal layer 401 , thereby changing the energy band of the material of the channel 03 and dynamically changing the mobility of the planar transistor.

Based on the above description of different transistor structures, it can be seen that the stress layer 05 can be directly stacked on the source and drain, or other layer structures can also be formed between the stress layer 05 and the source and drain. Regardless of the direct or indirect contact between the stress layer 05 and the source and drain, when the stress is generated in the stress layer 05 under the action of the stress control gate layer 06, it will be transmitted to the source and drain, causing the channel to deform, thereby improving The carrier velocity of the channel reduces the power dissipation of the transistor.

In addition, in the above mentioned fin field effect transistors, ring gate transistors, vertical structure nanowire field effect transistors, and planar transistors, the channels 03 of some transistors are arranged in a direction parallel to the substrate 100, such as planar transistors, Such transistors can be called horizontal channel transistors; and the channel 03 of some transistors is arranged along the direction perpendicular to the substrate 100, such as vertical structure nanowire field effect transistors, such transistors can be called vertical channel transistor.

It can also be said that, whether it is a horizontal channel transistor or a vertical channel transistor, the stress layer 05 and the stress control gate layer 06 are sequentially stacked on the source and drain. Of course, in other exemplary transistor structures, the stress layer 05 and the stress control gate layer 06 may also be stacked sequentially on the source and drain.

In transistors with different structures such as the ones mentioned above, the stress layer 05 and the stress control gate layer 06 mainly occupy the space near the source and drain and at a height perpendicular to the substrate, rather than the control gate spacing, due to the space between the substrate and the substrate The space margin on the vertical height is not tight with respect to the pitch of the control gate, therefore, a field effect transistor with a sub-threshold swing lower than 60mV/dec can be fabricated without affecting the node density. In this way, the transistor with this structure has advantages in terms of energy efficiency and power consumption, and can be used in low-frequency and low-power consumption units.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A transistor, characterized in that it comprises:

source and drain;

a channel formed between the source and the drain;

a gate stacked on at least part of the surface of the channel;

a stress layer, the stress layer is stacked on at least part of the surface of the source and the drain;

The stress control gate layer is stacked on the stress layer.
The transistor according to claim 1, wherein each of the source and the drain includes connected first side surfaces and second side surfaces;

The stress layer is stacked on both the first side surface and the second side surface.
The transistor according to claim 1 or 2, characterized in that, in the source and the drain, the stress control gate layer is arranged around the periphery of the stress layer.
The transistor according to any one of claims 1-3, wherein the transistor further comprises: a substrate;

The channel extends along a direction parallel to the substrate, and the source and drain are formed on opposite sides of the channel along a direction parallel to the substrate.
The transistor according to claim 4, characterized in that, in the source and the drain, the stress layer and the stress control gate layer are sequentially stacked along a direction perpendicular to the substrate.
The transistor according to any one of claims 1-3, wherein the transistor further comprises: a substrate;

The channel extends along a direction perpendicular to the substrate, and the source and drain are formed on opposite sides of the channel along a direction perpendicular to the substrate.
The transistor according to claim 6, wherein in the source and the drain, the stress layer and the stress control gate layer are sequentially stacked along a direction parallel to the substrate.
The transistor according to any one of claims 1-7, wherein the stress layer comprises at least one of lead zirconate titanate, aluminum nitride, and titanium nitride.
The transistor according to any one of claims 1-8, wherein the stress control gate layer, the source and the drain are made of the same material.
The transistor according to any one of claims 1-9, wherein the transistor has a PMOS structure, or the transistor has an NMOS structure.
A semiconductor integrated circuit, characterized in that it comprises:

A transistor according to any one of claims 1-10;

A passive device electrically connected to the transistor.