WO2023132151A1 - Image capturing element and electronic device - Google Patents

Image capturing element and electronic device Download PDF

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Publication number
WO2023132151A1
WO2023132151A1 PCT/JP2022/043667 JP2022043667W WO2023132151A1 WO 2023132151 A1 WO2023132151 A1 WO 2023132151A1 JP 2022043667 W JP2022043667 W JP 2022043667W WO 2023132151 A1 WO2023132151 A1 WO 2023132151A1
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Prior art keywords
pixel block
pixel
color
signal amount
output
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PCT/JP2022/043667
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French (fr)
Japanese (ja)
Inventor
俊久 牧平
秀樹 田中
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ソニーセミコンダクタソリューションズ株式会社
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Priority to JP2023572374A priority Critical patent/JPWO2023132151A1/ja
Publication of WO2023132151A1 publication Critical patent/WO2023132151A1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/10Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/76Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures

Definitions

  • This technology relates to imaging devices. More specifically, the present invention relates to an image pickup device having a pixel structure that obtains an image plane phase difference, and an electronic device having the image pickup device.
  • Electronic devices equipped with imaging functions typified by digital still cameras, employ an autofocus method that automatically focuses on the subject.
  • One of the autofocus methods is a phase difference method
  • one of the phase difference methods is an image plane phase difference method (see, for example, Patent Document 1).
  • the above-described conventional technology discloses an imaging device that includes normal pixels for obtaining pixel signals that form a captured image and phase difference detection pixels for obtaining an image plane phase difference. Since it is desired that the image quality of an image captured by an image sensor is high, it is expected that the pixel size will become finer in the future as the number of pixels increases.
  • the phase difference detection pixel is composed of two pixels adjacent to each other, and the basic configuration is a pixel structure in which one on-chip lens is formed for the two pixels. Therefore, even if the pixel size is miniaturized with the improvement of the image quality of the captured image, there is an image sensor that can contribute to the realization of high-precision autofocus while maintaining the basic pixel structure of the phase difference detection pixel. desired.
  • This technology was created in view of this situation, and even if the pixel size is reduced as the quality of the captured image increases, the basic configuration of the phase difference detection pixel is maintained. It is an object of the present invention to contribute to realization of high-precision autofocus.
  • a first aspect thereof is a first pixel block having a plurality of pixels each including a color filter of a first color that is the same as each other. each of which has a plurality of pixels including a color filter of a second color that is the same as that of the first pixel block and different from that of the first pixel block, and has a number of pixels different from that of the first pixel block. 2 pixel blocks, each of the first pixel block and the second pixel block having a plurality of pixel pairs of two pixels, corresponding to the plurality of pixel pairs.
  • a plurality of lenses are provided at each position, and the first pixel block and the second pixel block have a pixel configuration after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage. It has a pixel-sharing configuration in which an element is shared among a plurality of pixels, and further includes a signal amount adjustment unit for adjusting an output signal amount output from each pixel of the first pixel block and the second pixel block. and the signal amount adjustment unit adjusts the output signal amount for the first color output from the first pixel block and the output signal amount for the second color output from the second pixel block. It is an imaging device that adjusts the output signal amount so that the signal amount matches the signal amount.
  • the signal amount adjustment unit may adjust the output signal amount for the first color output from the first pixel block and the output signal amount for the first color output from the second pixel block.
  • the output signal amount of the second color is adjusted so that the output signal amount of the color with the smaller signal amount matches the output signal amount of the color with the larger signal amount. can be This brings about the effect of being able to absorb the difference in the output signal amount of each color.
  • the signal amount adjusting section is set to a first driving mode for individually reading signals of pixels of the first pixel block and the second pixel block, and a driving mode of the pixel pair.
  • the output signal amount for the first color output from the first pixel block is The output signal amount may be adjusted so as to match the output signal amount for the output second color. This brings about the effect of being able to absorb the difference in the output signal amount of each color in the first drive mode and the second drive mode.
  • the signal amount adjusting section in the third drive mode for adding and reading out the signals of all the pixels in the first pixel block and the second pixel block, may of the output signal amount so as to match the output signal amount of the first color output from the first pixel block with the output signal amount of the second color output from the pixel block of Adjustments may be made.
  • the third drive mode it is possible to absorb the difference in the output signal amount of each color.
  • the signal amount adjustment unit adjusts the output signal amount by converting the analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal. It may be performed by digital gain adjustment in the digital domain after conversion. This brings about the effect that the process of absorbing the difference in the output signal amount of each color can be performed in the digital domain.
  • the signal amount adjustment unit adjusts the output signal amount for each color by converting the analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal. It may be done by analog gain adjustment in the analog domain before conversion to signal. This brings about the effect that the process of absorbing the difference in the output signal amount of each color can be performed in the analog domain.
  • the analog-to-digital converter that converts an analog signal to a digital signal converts a reference signal of a ramp wave whose level changes with a predetermined slope over time during analog-to-digital conversion.
  • a single-slope type analog-to-digital conversion unit used as a reference signal for the signal amount adjustment unit may perform analog gain adjustment by changing the slope of the reference signal of the ramp wave. As a result, by changing the slope of the reference signal of the ramp wave, it is possible to absorb the difference in the output signal amount of each color.
  • the two pixels are arranged side by side in the first direction, and in each of the first pixel block and the second pixel block, a second pixel block intersects the first direction.
  • the two pixel pairs lined up in the direction may be shifted in the first direction. This brings about an effect that the pixels can be arranged densely in the pixel array section.
  • a second aspect of the present technology includes: a first pixel block having a plurality of pixels each including a color filter of a first color that is the same as each other; a second pixel block having a plurality of pixels including a color filter of a second color different from that of the pixel block and having a number of pixels different from that of the first pixel block; and an analog-to-digital converter for converting an analog signal output from each pixel of two pixel blocks into a digital signal, wherein the first pixel block and the second pixel block each include two pixels.
  • a single-slope analog-to-digital conversion unit that uses a ramp wave reference signal given from as a reference signal in analog-to-digital conversion, and the reference signal generation unit is a ramp wave reference signal with a different slope.
  • the imaging device adjusts the output signal amount so that the output signal amount and the output signal amount for the second color output from the second pixel block match.
  • a reference signal generator for adjusting an output signal amount for the first color output from the first pixel block; It may be a reference signal generator for adjusting the output signal amount for the second color output from the second pixel block.
  • a third aspect of the present technology includes: a first pixel block having a plurality of pixels each including a color filter of a first color that is the same as each other; a second pixel block having a plurality of pixels including a color filter of a second color different from the pixel block and having a number of pixels different from that of the first pixel block; and the second pixel blocks each have a plurality of pixel pairs each having two pixels, and a plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs, and the The first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share the pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage.
  • an electronic device having an image sensor. This contributes to the realization of high-precision autofocus while maintaining the basic configuration of the phase-difference detection pixels, even if the pixel size of the image sensor is reduced as the quality of the captured image increases. Furthermore, even if the number of pixels in each color pixel block is different, it is possible to obtain an output signal amount proportional to the exposure time.
  • FIG. 2 is a plan view showing an example of pixel arrangement in a pixel array section of the image pickup device according to the first embodiment
  • FIG. 2 is a cross-sectional view showing an example of a schematic cross-sectional structure of a pixel array portion of the image pickup device according to the first embodiment
  • 3 is a circuit diagram showing an example of a circuit configuration of a green (Gr) pixel block shown in FIG. 2
  • FIG. 3 is a circuit diagram showing an example of a circuit configuration of a red (R) pixel block shown in FIG. 2;
  • FIG. 3 is a block diagram showing an example of the configuration of a readout section of the image sensor in the first embodiment
  • FIG. FIG. 2 is a diagram showing an example of the structure of an image signal Spic output from an imaging element in the first embodiment
  • FIG. 1 is a perspective view schematically showing a flat-type semiconductor chip structure and a stacked-type semiconductor chip structure
  • FIG. 4 is a block diagram showing one configuration example of a signal amount adjustment unit of the image sensor in the first embodiment
  • FIG. FIG. 10 is a diagram illustrating adjustment of the output signal amount in the case of all-pixel readout mode and AF mode;
  • FIG. 10 is a diagram illustrating adjustment of the output signal amount in the case of all-pixel addition mode; It is a circuit diagram showing a configuration example of an analog-digital conversion unit according to a second embodiment of the present technology.
  • FIG. 3 is a waveform diagram showing timing relationships among a waveform of a reference signal RAMP at high gain, a waveform of a reference signal RAMP at low gain, a waveform of a signal line VSL, and clocks of a counter;
  • 1 is a block diagram showing a configuration example of an imaging device, which is an example of electronic equipment to which the present technology is applied;
  • FIG. It is a figure showing an example of a field to which an embodiment of this art is applied.
  • 1 is a block diagram showing a schematic configuration example of a vehicle control system;
  • FIG. FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit;
  • CMOS Complementary Metal Oxide Semiconductor
  • a CMOS image sensor is an imaging device manufactured by applying or partially using a CMOS process.
  • FIG. 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology.
  • the imaging device 1 includes a pixel array section 11, a driving section 12, a reading section 13, a reference signal generating section 14, a signal processing section 15, a storage section (data storage section) 16, and an imaging control section 17. It's becoming
  • the pixel array section 11 has a configuration in which pixels (pixel circuits) 20 including photoelectric conversion sections (photoelectric conversion elements) are two-dimensionally arranged in row and column directions, that is, in a matrix.
  • the row direction refers to the arrangement direction of the pixels 20 in the pixel row
  • the column direction refers to the arrangement direction of the pixels 20 in the pixel column.
  • the pixels 20 perform photoelectric conversion to generate and store photocharges corresponding to the amount of received light.
  • the pixel 20 generates a signal SIG containing a pixel voltage Vpix corresponding to the amount of incident light received.
  • the drive unit 12 is composed of a shift register, an address decoder, and the like, and when selecting each pixel 20 of the pixel array unit 11, based on a timing control signal supplied from the imaging control unit 17, scans the pixel rows and performs pixel row selection. Drive to control the address.
  • a signal SIG including the pixel voltage Vpix is output from each pixel 20 of the pixel array section 11 under the driving by the driving section 12 .
  • the reading unit 13 includes, for example, a single-slope type analog-digital conversion unit, which will be described later. , the signal SIG including the pixel voltage Vpix is subjected to analog-to-digital conversion (AD conversion). The reading unit 13 outputs the analog-digital converted signal as the image signal Spic0.
  • AD conversion analog-to-digital conversion
  • the reference signal generation unit 14 generates a reference signal RAMP that is used as a reference signal for analog-to-digital conversion in the single-slope analog-to-digital conversion unit of the reading unit 13 .
  • the reference signal RAMP is a so-called ramp wave signal whose level (voltage) changes (for example, monotonously decreases) with a predetermined slope over time.
  • the signal processing unit 15 Under the control of the imaging control unit 17, the signal processing unit 15 performs predetermined signal processing on the image signal Spic0 supplied from the reading unit 13, and outputs it as an image signal Spic.
  • the signal processing section 15 is configured to have an image data generation section 151 and a phase difference data generation section 152 .
  • the image data generation unit 151 is configured to generate image data DP representing a captured image by performing predetermined image processing based on the image signal Spic0.
  • the phase difference data generator 152 is configured to generate phase difference data DF indicating the image plane phase difference by performing predetermined image processing based on the image signal Spic0.
  • the signal processing unit 15 outputs an image signal Spic including the image data DP generated by the image data generation unit 151 and the phase difference data DF generated by the phase difference data generation unit 152 .
  • the storage unit (data storage unit) 16 temporarily stores (stores) data necessary for the processing.
  • the imaging control unit 17 generates various timing signals, clock signals, control signals, etc. based on an externally applied control signal Sctl, and based on these generated signals, the driving unit 12, reading unit 13, The operation of the image sensor 1 is controlled by controlling the driving of the reference signal generation unit 14, the signal processing unit 15, and the like.
  • the imaging control unit 17 controls the imaging operation of the imaging element 1 based on the control signal Sctl.
  • FIG. 2 is a plan view showing an example of arrangement of the pixels 20 in the pixel array section 11. As shown in FIG. As shown in FIG. 2 , the pixel array section 11 has a plurality of pixel blocks 100 and a plurality of lenses 101 .
  • the plurality of pixel blocks 100 includes pixel block 100R, pixel block 100Gr, pixel block 100Gb, and pixel block 100B.
  • the plurality of pixels 20 are arranged in units (units U) of four pixel blocks 100 (pixel blocks 100R, 100Gr, 100Gb, and 100B).
  • the pixel block 100R has eight pixels 20R including a red (R) color filter 115 (see FIG. 3).
  • a pixel block 100Gr has ten pixels 20Gr including a green (G) color filter 115 .
  • a pixel block 100Gb has ten pixels 20Gb including a green (G) color filter 115 .
  • Pixel block 100B has eight pixels 20B including blue (B) color filter 115 .
  • the difference in color of the color filters is expressed using hatching.
  • the arrangement pattern of the eight pixels 20R in the pixel block 100R and the arrangement pattern of the eight pixels 20B in the pixel block 100B are the same.
  • the arrangement pattern of the ten pixels 20Gr in the pixel block 100Gr and the arrangement pattern of the ten pixels 20Gb in the pixel block 100Gb are the same.
  • the pixel block 100Gr is located at the upper left
  • the pixel block 100R is located at the upper right
  • the pixel block 100B is located at the lower left
  • the pixel block 100Gb is located at the lower right.
  • the arrangement of the pixel block 100R, the pixel block 100Gr, the pixel block 100Gb, and the pixel block 100B is a so-called RGB Bayer arrangement. That is, the pixel block 100R, the pixel block 100Gr, the pixel block 100Gb, and the pixel block 100B are arrayed in the RGB Bayer array with the pixel block 100 as a unit.
  • Red (R) and blue (B) are examples of the first color described in the claims, and green (Gr, Gb) are examples of the second color described in the claims.
  • the pixel block 100R and the pixel block 100B are examples of the first pixel block described in the claims, and the pixel block 100Gr and the pixel block 100Gb are examples of the second pixel block described in the claims. An example.
  • FIG. 3 is a cross-sectional view showing an example of a schematic cross-sectional structure of the pixel array section 11.
  • the pixel array section 11 includes a plurality of lenses 101, a semiconductor substrate 111, a semiconductor region 112, an insulating layer 113, a multilayer wiring layer 114, a color filter 115, and a light shielding film 116. .
  • the semiconductor substrate 111 is a support substrate on which the imaging element 1 is formed, and is, for example, a P-type semiconductor substrate.
  • the semiconductor region 112 is a semiconductor region provided at a position corresponding to each of the plurality of pixels 20 in the semiconductor substrate 111, and is doped with an N-type impurity to form a photoelectric conversion portion (for example, a photodiode). ) is formed.
  • the insulating layer 113 is provided in the substrate of the semiconductor substrate 111 at the boundary of the plurality of pixels 20 arranged in parallel on the XY plane. be.
  • the multilayer wiring layer 114 is provided on the semiconductor substrate 111 on the side opposite to the light incident side (lens 101 side) of the pixel array section 11, and includes a plurality of wiring layers and interlayer insulating films.
  • the wiring in the multilayer wiring layer 114 is configured to connect, for example, a transistor (not shown) provided on the surface of the semiconductor substrate 111 to the driving section 12 and the reading section 13 .
  • the color filter 115 is provided on the semiconductor substrate 111 on the light incident side of the pixel array section 11 .
  • the light shielding films 116 are arranged side by side in the X direction on the light incident side of the pixel array section 11 . It is provided so as to surround one pixel 20 .
  • the two pixels 20 arranged side by side in the X direction are hereinafter also referred to as a pixel pair 90 .
  • the multiple lenses 101 are so-called on-chip lenses, and are provided on the color filter 115 on the light incident side of the pixel array section 11 .
  • a plurality of lenses 101 are provided above two pixels 20 (pixel pairs 90) arranged side by side in the X direction.
  • Four lenses 101 are provided above the eight pixels 20 of the pixel block 100R.
  • Five lenses 101 are provided above the ten pixels 20 of the pixel block 100Gr.
  • Five lenses 101 are provided above the ten pixels 20 of the pixel block 100Gb.
  • Four lenses 101 are provided above the eight pixels 20 of the pixel block 100B.
  • a plurality of lenses 101 are arranged side by side in the X direction and the Y direction.
  • the lenses 101 arranged in the Y direction are arranged with a shift of one pixel 20 in the X direction.
  • the pixel pairs 90 aligned in the Y direction are shifted by one pixel 20 in the X direction.
  • the imaging device 1 generates phase difference data DF based on so-called image plane phase differences detected by the plurality of pixel pairs 90 . That is, the two pixels 20 of the pixel pair 90 corresponding to one lens 101 are phase difference detection pixels for generating the phase difference data DF based on the image plane phase difference.
  • An electronic device having an imaging function such as a digital still camera determines the defocus amount based on the phase difference data DF, and moves the position of the photographing lens based on the defocus amount. In this manner, autofocus can be realized in an electronic device having an imaging function.
  • FIG. 4 is a circuit diagram showing an example of the circuit configuration of the green (Gr) pixel block 100Gr.
  • FIG. 5 is a circuit diagram showing an example of the circuit configuration of the red (R) pixel block 100R.
  • the pixel array section 11 has a plurality of control lines TRGL, a plurality of control lines RSTL, a plurality of control lines SELL, and a plurality of signal lines VSL.
  • the control line TRGL is wired along the row direction for each pixel row of the pixel array section 11 , and one end is connected to the corresponding output terminal of the driving section 12 .
  • a control signal is appropriately supplied from the drive unit 12 to the control line TRGL.
  • the control line RSTL is wired along the row direction for each pixel row of the pixel array section 11 , and one end is connected to the corresponding output terminal of the driving section 12 .
  • a control signal is appropriately supplied from the drive unit 12 to the control line RSTL.
  • the control line SELL is wired along the row direction for each pixel row of the pixel array section 11 , and one end is connected to the corresponding output terminal of the drive section 12 .
  • a control signal is appropriately supplied from the drive unit 12 to the control line SELL.
  • the signal line VSL is wired along the column direction for each pixel column of the pixel array section 11 , and one end is connected to the readout section 13 . This signal line VSL transmits the signal SIG output from the pixel 20 to the reading unit 13 .
  • a green (Gr) pixel block 100Gr shown in FIG. 4 has ten photoelectric conversion units 21 and ten transfer transistors 22 .
  • the pixel block 100Gr further has one charge-voltage converter 23, one reset transistor 24, one amplifier transistor 25, and one selection transistor 26.
  • FIG. 1 A green (Gr) pixel block 100Gr shown in FIG. 4 has ten photoelectric conversion units 21 and ten transfer transistors 22 .
  • the pixel block 100Gr further has one charge-voltage converter 23, one reset transistor 24, one amplifier transistor 25, and one selection transistor 26.
  • the transfer transistor 22, the reset transistor 24, the amplification transistor 25, and the selection transistor 26, for example, an N-type MOS (Metal Oxide Semiconductor) field effect transistor can be used.
  • N-type MOS Metal Oxide Semiconductor
  • the combination of the conductivity types of the transfer transistor 22, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 illustrated here is merely an example, and the combination is not limited to these combinations.
  • the 10 photoelectric conversion units 21 and the 10 transfer transistors 22 respectively correspond to the 10 pixels 20Gr included in the pixel block 100Gr.
  • the pixel block 100Gr has a configuration of a so-called pixel shared pixel circuit in which the charge-voltage converter 23, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 are shared among the ten pixels 20Gr.
  • the photoelectric conversion unit 21 is a PN junction photodiode (PD: Photo Diode).
  • the photodiode has an anode electrode connected to a low-potential power supply (for example, ground), generates an amount of charge corresponding to the amount of light received, and accumulates the generated charge inside.
  • a cathode electrode of the photodiode 21 is connected to a source electrode of the transfer transistor 22 .
  • the transfer transistor 22 has a gate electrode connected to the control line TRGL, a source electrode connected to the cathode electrode of the photoelectric conversion unit 21 , and a drain electrode connected to the charge-voltage conversion unit 23 .
  • Gate electrodes of ten transfer transistors 22 are connected to different control lines TRGL among ten control lines TRGL (control lines TRGL1 to TRGL6 and TRGL9 to TRGL12 in this example).
  • the charge-voltage converter 23 is a capacitance CFD of a floating diffusion (FD) region formed between the drain region of the transfer transistor 22 and the source region of the reset transistor 24 .
  • the charge-voltage conversion unit 23 converts the charge photoelectrically converted by the photoelectric conversion unit 21 and transferred from the photoelectric conversion unit 21 by the transfer transistor 22 into a voltage.
  • the reset transistor 24 has a gate electrode connected to the control line RSTL and a source electrode connected to the charge-voltage converter 23 .
  • a power supply voltage V DD is supplied to the drain electrode of the reset transistor 24 .
  • the reset transistor 24 resets the charge accumulated in the charge-voltage conversion section 23 according to a control signal given from the drive section 12 through the control line RSTL.
  • the amplification transistor 25 has a gate electrode connected to the charge-voltage converter 23 and a source electrode connected to the drain electrode of the selection transistor 26 .
  • a power supply voltage V DD is supplied to the drain electrode of the amplification transistor 25 .
  • the amplification transistor 25 serves as an input section of a circuit for reading out charges obtained by photoelectric conversion in the photoelectric conversion section 21, that is, a source follower circuit. That is, the amplification transistor 25 is connected to one end of the signal line VSL by connecting the source electrode to the signal line VSL through the selection transistor 26, and the constant current source I (see FIG. 6) and the source are connected to one end of the signal line VSL. Construct a follower circuit.
  • the selection transistor 26 has a gate electrode connected to the control line SELL, a drain electrode connected to the source electrode of the amplification transistor 25, and a source electrode connected to the signal line VSL. Then, the selection transistor 26 selects one of the pixels 20 in the pixel array section 11 under selective scanning by the driving section 12 .
  • the transfer transistor 22 and the reset transistor 24 are turned on, thereby discharging the charge accumulated in the photoelectric conversion section 21. Then, when the transfer transistor 22 and the reset transistor 24 are turned off, an exposure period is started, photoelectric conversion is performed in the photoelectric conversion section 21, and an amount of charge corresponding to the amount of received light is accumulated.
  • the pixel 20 After the exposure period ends, the pixel 20 outputs the signal SIG including the reset voltage Vreset and the pixel voltage Vpix to the signal line VSL. Specifically, first, the pixel 20 is electrically connected to the signal line VSL by turning on the selection transistor 26 . Thereby, the amplification transistor 25 is electrically connected to a constant current source I (see FIG. 6), which will be described later, connected to one end of the signal line VSL at the input portion of the readout portion 13, and operates as a source follower.
  • a constant current source I see FIG. 6
  • the pixel 20 is in the P phase (Pre-charge phase) period after the voltage of the charge-voltage converter 23 is reset by turning on the reset transistor 24, and the charge at that time is
  • the voltage of the voltage converter 23 is output as the reset voltage Vreset.
  • the transfer transistor 22 is turned on, so that the pixel 20 performs the charge-voltage conversion during the D phase (data phase) period after the charge is transferred from the photoelectric conversion unit 21 to the charge-voltage conversion unit 23 .
  • the voltage of the section 23 is output as the pixel voltage Vpix.
  • a difference voltage between the pixel voltage Vpix and the reset voltage Vreset corresponds to the amount of light received by the pixel 20 during the exposure period.
  • the pixel 20 outputs the signal SIG including the reset voltage Vreset and pixel voltage Vpix to the signal line VSL.
  • a red (R) pixel block 100 R shown in FIG. 5 has eight photoelectric conversion units 21 and eight transfer transistors 22 .
  • the pixel block 100R further has one charge-voltage converter 23, one reset transistor 24, one amplifier transistor 25, and one selection transistor 26.
  • FIG. 5 A red (R) pixel block 100 R shown in FIG. 5 has eight photoelectric conversion units 21 and eight transfer transistors 22 .
  • the pixel block 100R further has one charge-voltage converter 23, one reset transistor 24, one amplifier transistor 25, and one selection transistor 26.
  • the transfer transistor 22, the reset transistor 24, the amplification transistor 25, and the selection transistor 26, for example, an N-type MOS field effect transistor can be used.
  • the combination of the conductivity types of the transfer transistor 22, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 illustrated here is merely an example, and the combination is not limited to these combinations.
  • the eight photoelectric conversion units 21 and the eight transfer transistors 22 respectively correspond to the eight pixels 20R included in the pixel block 100R.
  • the pixel block 100R has a pixel circuit configuration in which the charge-voltage converter 23, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 are shared among the ten pixels 20R.
  • the gate electrodes of the eight transfer transistors 22 are connected to different control lines TRGL among the eight control lines TRGL (control lines TRGL1, TRGL2, TRGL5 to TRGL10 in this example).
  • the pixel block 100Gb has 10 photoelectric conversion units 21 and 10 transfer transistors 22, like the pixel block 100Gr shown in FIG.
  • Ten photoelectric conversion units 21 and ten transfer transistors 22 respectively correspond to ten pixels 20Gb included in the pixel block 100Gb.
  • a gate electrode of the transfer transistor 22 is connected to different control lines TRGL among the ten control lines TRGL.
  • the pixel block 100Gb further has one charge-voltage converter 23, one reset transistor 24, one amplifier transistor 25, and one selection transistor 26.
  • the pixel block 100Gb has a pixel circuit configuration in which the charge-voltage converter 23, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 are shared among the ten pixels 20Gb.
  • the pixel block 100B has eight photoelectric conversion units 21 and eight transfer transistors 22, like the pixel block 100R shown in FIG.
  • the eight photoelectric conversion units 21 and the eight transfer transistors 22 respectively correspond to the eight pixels 20B included in the pixel block 100B.
  • a gate electrode of the transfer transistor 22 is connected to different control lines TRGL among the eight control lines TRGL.
  • the pixel block 100B further has one charge-voltage converter 23, one reset transistor 24, one amplifier transistor 25, and one selection transistor 26.
  • the pixel block 100B has a pixel circuit configuration in which the charge-voltage converter 23, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 are shared among the eight pixels 20B.
  • FIG. 6 is a block diagram showing an example of the configuration of the reading section 13 of the imaging device 1 according to the first embodiment.
  • FIG. 6 also shows the reference signal generating unit 14, the signal processing unit 15, and the imaging control unit 17.
  • a signal SIG including a pixel voltage Vpix read from each pixel 20 of the pixel array section 11 via a plurality of signal lines VSL is input to the reading section 13 .
  • a constant current source I is connected to each of the plurality of signal lines VSL in the input section of the reading section 13 .
  • the constant current source I has one end connected to the corresponding signal line VSL and the other end grounded, and acts to supply a predetermined current to the corresponding signal line VSL.
  • the reading unit 13 has a plurality of analog-digital conversion units 31 and transfer control units 32 .
  • a plurality of analog-to-digital converters 31 are provided corresponding to the plurality of signal lines VSL, respectively, and perform analog-to-digital conversion on the signal SIG on the corresponding signal line VSL.
  • the analog-digital converter 31 corresponding to one signal line VSL will be described below.
  • the analog-digital conversion section 31 is configured to have capacitive elements 311 and 312, a comparison circuit 313, a counter 314, and a latch circuit 315.
  • the capacitive element 311 has one end connected to the signal line VSL and the other end connected to one input end of the comparison circuit 313 .
  • a signal SIG including the pixel voltage Vpix is supplied from each pixel 20 of the pixel array section 11 to the capacitive element 311 through the signal line VSL.
  • the capacitive element 312 has one end connected to the signal line 33 that transmits the reference signal RAMP, and the other end connected to the other input end of the comparison circuit 313 .
  • a reference signal RAMP is supplied from the reference signal generator 14 to the capacitive element 312 through the signal line 33 .
  • the comparison circuit 313 is supplied with a signal SIG supplied from each pixel 20 of the pixel array section 11 via the signal line VSL and the capacitive element 311, and supplied from the reference signal generation section 13 via the signal line 33 and the capacitive element 312. It compares with the reference signal RAMP and outputs the signal Vcp as a result of the comparison.
  • the comparison circuit 313 sets the operating point by setting the voltages of the capacitive elements 311 and 312 based on the control signal AZ supplied from the imaging control section 17 through the signal line 34 . After setting the operating point, the comparison circuit 313 performs a comparison operation of comparing the reset voltage Vreset included in the signal SIG and the voltage of the reference signal RAMP in the P-phase period. Also, the comparison circuit 313 performs a comparison operation of comparing the pixel voltage Vpix included in the signal SIG with the voltage of the reference signal RAMP during the D-phase period.
  • the counter 314 is configured to count pulses of the clock signal CLK supplied from the imaging control unit 17 based on the signal Vcp supplied from the comparison circuit 313 . Specifically, the counter 314 generates the count value CNTP by counting the pulses of the clock signal CLK until the signal Vcp output from the comparison circuit 313 transitions during the P-phase period. Output as a digital code with multiple bits. Further, the counter 314 generates a count value CNTD by counting the pulses of the clock signal CLK until the signal Vcp output from the comparison circuit 313 transitions during the D-phase period, and converts the count value CNTD into a plurality of bits. output as a digital code having
  • the latch circuit 315 temporarily holds the digital code supplied from the counter 314 and outputs the digital code to the bus wiring 35 based on the instruction from the transfer control section 32 .
  • the transfer control unit 32 controls the latch circuits 315 of the plurality of analog-digital conversion units 31 to sequentially output the digital code to the bus wiring 35 based on the control signal CTL supplied from the imaging control unit 17 .
  • the reading unit 13 uses the bus wiring 35 to sequentially transfer the plurality of digital codes output from the plurality of analog-digital conversion units 31 to the signal processing unit 15 as the image signal Spic0.
  • the signal processing unit 15 Under the control of the imaging control unit 17, the signal processing unit 15 performs predetermined signal processing on the image signal Spic0 supplied from the reading unit 13 to generate an image signal including the image data DP and the phase difference data DF. Output as Spic. Specifically, as shown in FIG. 7, the signal processing unit 15 generates and outputs the image signal Spic by alternately arranging the phase difference data DF related to the pixels 20 in a plurality of rows.
  • Examples of the semiconductor chip structure of the imaging device 1 having the above-described configuration include a so-called parallel-type semiconductor chip structure and a so-called stacked-type semiconductor chip structure.
  • the pixel structure when the substrate surface on which the wiring layer is formed is defined as the front surface (front surface), it is also possible to adopt a back-illuminated pixel structure in which light emitted from the back surface on the opposite side is taken in. Alternatively, a surface-illuminated pixel structure that captures light emitted from the surface side may be employed.
  • FIG. 8 A in FIG. 8 is a perspective view schematically showing a flat-type chip structure of the imaging device 1 .
  • each component of the peripheral circuit section of the pixel array section 11 is formed on the same semiconductor substrate (semiconductor chip) 41 as the pixel array section 11 in which the pixels 20 are arranged in a matrix. It has become.
  • the driving section 12, the reading section 13, the reference signal generating section 14, the signal processing section 15, the imaging control section 17, and the like are formed.
  • Pads 42 for external connection and power supply are provided, for example, at both left and right ends of the semiconductor substrate 41 .
  • the laminated semiconductor chip structure has a structure in which at least two semiconductor substrates, ie, a first-layer semiconductor substrate 43 and a second-layer semiconductor substrate 44 are laminated.
  • the semiconductor substrate 43 of the first layer is a pixel chip in which the pixel array section 11 in which the pixels 20 are two-dimensionally arranged in a matrix is formed.
  • Pads 42 for external connection and power supply are provided, for example, at both left and right ends of the semiconductor substrate 43 of the first layer.
  • the semiconductor substrate 44 of the second layer is formed with the peripheral circuit portion of the pixel array portion 11, that is, the driving portion 12, the reading portion 13, the reference signal generating portion 14, the signal processing portion 15, the imaging control portion 17, and the like.
  • a circuit chip A circuit chip. Note that the arrangement of the driving section 12, the reading section 13, the reference signal generating section 14, the signal processing section 15, the imaging control section 17, etc. is an example, and is not limited to this arrangement example.
  • the pixel array portion 11 on the semiconductor substrate 43 of the first layer and the peripheral circuit portion on the semiconductor substrate 44 of the second layer are metal-metal junctions including Cu--Cu junctions, Through Silicon Via (TSV) ), and are electrically connected via bonding portions 45 and 46 composed of microbumps or the like.
  • TSV Through Silicon Via
  • a process suitable for manufacturing the pixel array section 11 can be applied to the semiconductor substrate 43 of the first layer, and a process suitable for manufacturing the circuit portion can be applied to the semiconductor substrate 44 of the second layer. process can be applied.
  • the process can be optimized in manufacturing the imaging device 1 .
  • the circuit portion there is an advantage that it is possible to apply advanced processes and to expand the scale of the circuit.
  • the image sensor 1 includes a plurality of pixel blocks 100 each having a plurality of pixels 20 including color filters of the same color.
  • a plurality of pixels 20 in pixel block 100 are partitioned into a plurality of pixel pairs 90 each including two pixels 20 .
  • a plurality of lenses 101 are provided at positions corresponding to the plurality of pixel pairs 90 .
  • the imaging element 1 can generate the phase difference data DF with high resolution over the entire surface of the pixel array section 11 . Therefore, in an electronic device having an imaging function such as a digital still camera equipped with such an imaging device 1, highly accurate autofocus can be realized. As a result, the imaging device 1 can improve the image quality, so that a more legible captured image can be obtained.
  • the number of pixels in a certain pixel block 100 is set to be larger than the number of pixels in another certain pixel block 100.
  • the number of pixels 20Gr in the pixel block 100Gr, the number of pixels 20Gb in the pixel block 100Gb, the number of pixels 20R in the pixel block 100R, and the number of pixels 20G in the pixel block 100B is set larger than the number of pixels 20B in .
  • the two phase difference detection pixels that is, the pixel pairs 90 While maintaining the basic configuration of the pixel 20, it is possible to contribute to the realization of high-precision autofocus in an electronic device having an imaging function such as a digital still camera.
  • the image pickup device 1 is a pixel circuit in which a plurality of pixels 20 share the pixel constituent elements after the charge-voltage converter 23, that is, the reset transistor 24, the amplification transistor 25, and the selection transistor 26. (see FIGS. 4 and 5).
  • the image sensor 1 having the pixel-sharing pixel circuit has a configuration in which three drive modes, for example, a first drive mode, a second drive mode, and a third drive mode, can be set as drive modes. ing.
  • the first mode is an all-pixel readout mode in which a plurality of pixels 20 sharing pixel constituent elements after the charge-voltage converter 23 are read out individually without addition (pixel addition).
  • the second drive mode is an AF (autofocus) mode in which addition is performed between two pixels 20 forming a pair of pixel pairs 90 to generate phase difference data DF.
  • a third drive mode is an all-pixel addition mode in which addition (pixel addition) is performed among all pixels 20 that share the pixel constituent elements after the charge-voltage converter 23 and readout is performed.
  • C is the capacitance of the charge-voltage converter 23 including the capacitance CFD of the floating diffusion region (FD region).
  • the number of pixels sharing the pixel constituent elements after the charge-voltage converter 23 is larger than the red (R) pixel block 100R and the blue (B) pixel block 100R. Therefore, the number of transfer transistors 22 electrically connected to the charge-voltage converter 23 is increased.
  • the capacitance C of the charge-voltage converter 23 increases. is smaller than the conversion efficiency of the pixel block 100R/B having a relatively small number of pixels.
  • the pixel block 100Gr/Gb and the pixel block 100R/B have different wiring layouts (routing), a corresponding difference in conversion efficiency occurs.
  • the number of electrons handled by the charge-voltage converter 23 differs for each color.
  • Control is performed to absorb the difference in output signal amount. More specifically, in the first embodiment, in the digital domain after the analog-to-digital conversion by the analog-to-digital converter 31, control to absorb the difference in the output signal amount for each color is performed by digital gain correction processing. to do.
  • digital gain correction processing for absorbing the difference in output signal amount for each color will be described below.
  • the output signal amount for each color is acquired using an external measuring device (not shown) in the adjustment stage before shipment of the imaging device 1 .
  • the output signal amount for each color is obtained from the pixel addition number for each drive mode and the conversion efficiency used by the charge-voltage converter 23 .
  • the information of the output signal amount for each color obtained in advance in this manner is stored in the storage unit 16 shown in FIG. 1 and shipped.
  • the difference in output signal amount for each color will be explained.
  • the conversion efficiency of the pixel block 100Gr/Gb with a relatively large number of pixels is lower than the conversion efficiency of the pixel block 100R/B with a relatively small number of pixels. Therefore, in the case of the all-pixel readout mode in which pixels are read out individually without performing pixel addition, and the AF mode in which two pixels 20 forming a pair of pixels 90 are added together, as shown in a in FIG.
  • the R and B output signal amounts are greater than the G (Gr, Gb) output signal amount, and a difference in output signal amount occurs between the two.
  • the pixel block 100Gr/Gb having a relatively large number of pixels to be added has the number of electrons handled by the charge-voltage converter 23 by all-pixel addition. will increase. Therefore, as shown by a in FIG. 11, the output signal amount of G (Gr, Gb) is larger than the output signal amount of R and B, and a difference in output signal amount is generated between them.
  • FIG. 9 is a block diagram showing a configuration example of the signal amount adjustment section 50 of the imaging device 1 according to the first embodiment. In addition to the signal amount adjusting section 50, FIG. 9 also shows the reading section 13, the signal processing section 15, and the storage section 16. FIG.
  • FIG. 1 a data receiving and rearranging section 18 is normally provided in the preceding stage of the signal processing section 15.
  • FIG. The data receiving and rearranging unit 18 receives analog-to-digital converted pixel data sequentially output from the signal processing unit 15, and divides the pixel data into a pixel block 100R, a pixel block 100Gr, a pixel block 100Gb, and a pixel block. A process of rearranging the pixels into a pixel array corresponding to the 100B RGB Bayer array is performed.
  • the signal amount adjustment unit 50 has a color-by-color digital gain correction processing unit 51. Under the correction processing by the color-by-color digital gain correction processing unit 51, the signal is acquired in advance at the stage before shipment and stored in the storage unit 16. Correction processing for absorbing the difference in the output signal amount for each color is performed based on the information on the output signal amount for each color. Specifically, the color-by-color digital gain correction processing unit 51 causes the data reception and rearrangement unit 18 to match the signal amounts of the pixels of a predetermined color after the rearrangement process with the output signal amounts of the respective colors. By adjusting the obtained gain, gain adjustment is performed to absorb the difference in output signal amount for each color.
  • “matching” means not only strictly matching but also substantially matching, and various variations caused by design or manufacturing are allowed.
  • the color-specific digital gain correction processing for absorbing the difference in the output signal amount for each color will be described in more detail below.
  • the color-by-color digital gain correction processing unit 51 of the signal amount adjustment unit 50 for example, at the initial stage of startup of the imaging device 1, outputs the output stored in the storage unit 16. Based on the information of the signal amount difference, as shown in b in FIG. The output signal amount is adjusted by digital gain correction so that the signal amount is increased and matched. That is, in this digital gain correction, correction is performed by multiplying the difference in conversion efficiency by the gain of the output signal amount of G(Gr, Gb).
  • the adjustment of the output signal amount by this color-by-color digital gain correction process absorbs the difference between the output signal amount of R, B and the output signal amount of G (Gr, Gb) in the case of all pixel readout mode and AF mode. , both can be matched. As a result, an output signal amount proportional to the exposure time can be obtained for each pixel 20 of the pixel block 100 (100R, 100Gr, Gb, 100B), so that a more legible photographed image can be obtained.
  • the color-by-color digital gain correction processing unit 51 of the signal amount adjustment unit 50 adjusts the output signal amount stored in the storage unit 16 at the initial stage of startup of the imaging device 1, for example. Based on the difference information, as shown in b in FIG.
  • the output signal amount is adjusted by digital gain correction so that the output signal amount is increased and matched. That is, in this digital gain correction, a correction is performed by multiplying the R and B output signal amounts by a predetermined gain by the difference between the conversion efficiency and the number of pixels to be added.
  • FIG. 12 is a circuit diagram showing a configuration example of an analog-digital conversion unit according to the second embodiment of the present technology.
  • the second embodiment is an example in which analog gain correction is performed to absorb the difference in output signal amount for each color. Note that the overall configuration of the imaging device 1 is the same as that of the above-described first embodiment, so detailed description thereof will be omitted.
  • the signal of each pixel 20 of the pixel block 100 (100R, 100Gr, Gb, 100B) is subjected to analog-to-digital conversion by the single-slope analog-to-digital converter 31.
  • a single reference signal generator 14 for generating a reference signal RAMP used as a reference signal is provided for each color. That is, in the first embodiment, the slope of the reference signal RAMP is common to the pixel signals of each color, and the digital gain correction process for each color is performed in the digital domain after the analog-to-digital conversion by the analog-to-digital converter 31. It is configured to do
  • a plurality of reference signal generators 14 in this example, two reference signal generators 14A for R/B and a reference signal generator 14B for Gr/Gb. It has a configuration in which a signal generator is provided.
  • the R/B reference signal generation unit 14A determines the output signal amount for each color of R/B output from the pixel block 100R and the pixel block 100B by analog gain determined by the slope of the generated ramp wave reference signal RAMP.
  • the Gr/Gb reference signal generation unit 14B calculates the output signal amount for each color of Gr/Gb output from the pixel block 100Gr and the pixel block 100Gb, using an analog gain determined by the slope of the generated ramp wave reference signal RAMP.
  • FIG. 12 also shows a DC generating section 19A for R/B and a DC generating section 19B for Gr/Gb.
  • the R/B DC generator 19A generates a DC (Direct Current) voltage to be applied to the ramp wave reference signal RAMP output from the R/B reference signal generator 14A.
  • the Gr/Gb DC generator 19B generates a DC voltage to be applied to the ramp wave reference signal RAMP output from the Gr/Gb reference signal generator 14B.
  • the signal amount adjustment unit 50 has a color-by-color digital gain correction processing unit 51. Under the correction processing by the color-by-color digital gain correction processing unit 51, the signal is acquired in advance at the stage before shipment and stored in the storage unit 16. Correction processing for absorbing the difference in the output signal amount for each color is performed based on the information on the output signal amount for each color. Specifically, the color-by-color digital gain correction processing unit 51 adjusts the slope of the ramp wave reference signal RAMP generated by each of the R/B reference signal generation unit 14A and the Gr/Gb reference signal generation unit 14B. By controlling the analog gain determined by the gain adjustment that absorbs the difference in the amount of output signal for each color.
  • FIG. 13 shows timing relationships among the waveform of the reference signal RAMP at high gain (RAMP waveform), the waveform of the reference signal RAMP at low gain, the waveform of the signal line VSL (VSL waveform), and the clock of the counter 314 (counter clock).
  • RAMP waveform the waveform of the reference signal RAMP at high gain
  • VSL waveform the waveform of the signal line VSL
  • VSL waveform the waveform of the signal line VSL
  • clock of the counter 314 counter clock
  • the concept of the color-by-color digital gain correction processing for absorbing the difference in the output signal amount by color performed by the color-by-color digital gain correction processing unit 51 of the signal amount adjustment unit 50 is basically the same as that of the first embodiment. is the same as for the form of
  • the output signal amounts of R and B are larger than the output signal amount of G (Gr, Gb).
  • the color-by-color digital gain correction processing unit 51 of the signal amount adjustment unit 50 for example, in the initial stage of startup of the imaging device 1, based on the information of the difference in the output signal amount stored in the storage unit 16.
  • a low gain is set for the relatively large R and B output signal amounts, and a high gain is set for the relatively small G (Gr, Gb) output signal amount.
  • the low gain and high gain set here are determined by the slope of the ramp wave reference signal RAMP generated by the R/B reference signal generation unit 13A and the Gr/Gb reference signal generation unit 13B, respectively. is the gain.
  • the output signal amount of G (Gr, Gb) which is relatively small, is increased with respect to the output signal amount of R, B, which is relatively large. That way you can match the two.
  • an output signal amount proportional to the exposure time can be obtained for each pixel 20 of the pixel block 100 (100R, 100Gr, Gb, 100B), so that a more legible photographed image can be obtained.
  • the output signal of G (Gr, Gb) is is greater than the R and B output signal amounts.
  • the color-specific digital gain correction processing unit 51 of the signal amount adjustment unit 50 based on the information on the difference in the output signal amount stored in the storage unit 16, at the initial stage of startup of the imaging device 1, A low gain is set for the relatively large G (Gr, Gb) output signal amount, and a high gain is set for the relatively small R and B output signal amounts.
  • the image pickup device includes image pickup devices such as digital still cameras and video cameras, mobile terminal devices having an image pickup function such as mobile phones, and copying devices using an image pickup device as an image reading unit. It can be applied to various electronic devices having an imaging function such as a camera.
  • FIG. 14 is a block diagram showing a configuration example of an imaging device, which is an example of electronic equipment to which the present technology is applied.
  • An imaging device 200 is a device for imaging a subject, and includes an imaging optical system 201 including a lens group and the like, an imaging unit 202, a DSP (Digital Signal Processor) circuit 203, a display unit 204, and an operation unit 205. , a storage unit 206 and a power supply unit 207 . These are interconnected by bus wiring 208 .
  • the imaging element 200 for example, in addition to a digital camera such as a digital still camera, a smart phone, a personal computer, an in-vehicle camera, and the like having an imaging function are assumed.
  • the imaging unit 202 generates pixel data by photoelectric conversion.
  • the imaging unit 202 the imaging device according to the above-described embodiment is used.
  • the light from the subject is condensed by the imaging optical system 201 arranged on the incident light side and guided to its light receiving surface.
  • the imaging unit 202 supplies pixel data generated by photoelectric conversion to the downstream DSP circuit 203 .
  • the DSP circuit 203 executes predetermined signal processing on the pixel data from the imaging unit 202 .
  • the display unit 204 displays pixel data.
  • As the display unit 204 for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed.
  • the operation unit 205 generates an operation signal according to a user's operation.
  • the storage unit 206 stores various data such as pixel data.
  • the power supply unit 207 supplies power to the imaging unit 202, the DSP circuit 203, the display unit 204, and the like.
  • Embodiments of the present technology described above can be applied to various technologies as exemplified below.
  • FIG. 15 is a diagram showing an example of a field to which an embodiment of the present technology is applied.
  • the imaging device can be used as a device that captures an image for viewing, such as a digital camera or a mobile device with a camera function.
  • this imaging device includes an in-vehicle sensor that captures images of the surroundings and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's state, a surveillance camera that monitors running vehicles and roads, and an image sensor between vehicles. It can be used as a device for transportation, such as a ranging sensor that measures the distance of a vehicle.
  • this imaging device can be used as a device for home appliances such as televisions, refrigerators, air conditioners, etc., in order to capture a user's gesture and operate the device according to the gesture.
  • home appliances such as televisions, refrigerators, air conditioners, etc.
  • this imaging device can be used as a device for medical or healthcare purposes, such as an endoscope or an angiographic device that performs angiography by receiving infrared light.
  • this imaging device can be used as a security device such as a monitoring camera for crime prevention and a camera for personal authentication.
  • this imaging device can be used as a device used for beauty, such as a skin measuring instrument for photographing the skin and a microscope for photographing the scalp.
  • this imaging device can be used as a device for sports, such as an action camera or wearable camera for sports.
  • this imaging device can be used as an agricultural device such as a camera for monitoring the state of fields and crops.
  • the technology (the present technology) according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive train control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield in the vehicle interior, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 17 shows an example of the imaging range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided in the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the course of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above.
  • the imaging device 1 in FIG. 1 can be applied to the imaging unit 12031 .
  • the present technology can also have the following configuration.
  • the first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage.
  • a signal amount adjustment unit that adjusts an output signal amount output from each pixel of the first pixel block and the second pixel block;
  • the signal amount adjustment unit adjusts the output signal amount for the first color output from the first pixel block and the output signal amount for the second color output from the second pixel block.
  • image sensor that adjusts the amount of output signal so that (2)
  • the signal amount adjustment unit adjusts the output signal amount for the first color output from the first pixel block and the output signal amount for the second color output from the second pixel block.
  • the output signal amount is adjusted so that the output signal amount of the color with the smaller signal amount matches the output signal amount of the color with the larger signal amount with respect to the output signal amount.
  • the signal amount adjusting section is configured to set a first drive mode for individually reading signals of pixels of the first pixel block and the second pixel block, and signals of the two pixels of the pixel pair. in the second driving mode in which the second driving mode is read out by adding the second The imaging device according to (2) above, wherein the output signal amount is adjusted so that the output signal amount for each color is matched.
  • the signal amount adjustment section outputs signals from the second pixel block in a third driving mode for adding and reading signals of all pixels of the first pixel block and the second pixel block.
  • the signal amount adjustment unit performs the adjustment of the output signal amount in the digital domain after converting the analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal.
  • the imaging device according to (1) above which is performed by digital gain adjustment in .
  • the signal amount adjustment unit adjusts the output signal amount for each color before converting the analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal.
  • the imaging device according to (1) above which is performed by analog gain adjustment in an analog domain.
  • the analog-to-digital conversion unit which converts analog signals to digital signals, uses a ramp wave reference signal whose level changes with a predetermined slope as time elapses as a reference signal for analog-to-digital conversion. A slope-type analog-to-digital converter,
  • the two pixels are arranged side by side in a first direction; In each of the first pixel block and the second pixel block, the two pixel pairs aligned in a second direction crossing the first direction are arranged with a shift in the first direction.
  • a first pixel block having a plurality of pixels each including color filters of the same first color; a second pixel block each having a plurality of pixels including a color filter of a second color that is the same as that of the first pixel block and different from that of the first pixel block; a pixel block; an analog-to-digital converter that converts an analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal; each of the first pixel block and the second pixel block has a plurality of pixel pairs of two pixels; A plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs, The first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage.
  • the analog-digital conversion unit is a single-slope analog-digital conversion unit that uses the reference signal of the ramp wave provided from the reference signal generation unit as a reference signal for analog-digital conversion,
  • a plurality of reference signal generators for generating reference signals of ramp waves having different slopes are provided as the reference signal generators, further comprising a signal amount adjustment unit that adjusts an output signal amount output from each pixel of the first pixel block and the second pixel block;
  • the signal amount adjustment unit adjusts the first color output from the first pixel block based on the ramp wave reference signals with different slopes generated by the plurality of reference signal generation units.
  • An imaging device that adjusts an output signal amount so that the output signal amount and the output signal amount for the second color output from the second pixel block match.
  • the plurality of reference signal generation units include a reference signal generation unit for adjusting an output signal amount for the first color output from the first pixel block, and the second pixel block.
  • a first pixel block having a plurality of pixels each including color filters of the same first color; a second pixel block each having a plurality of pixels including a color filter of a second color that is the same as that of the first pixel block and different from that of the first pixel block; a pixel block; each of the first pixel block and the second pixel block has a plurality of pixel pairs of two pixels; A plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs,
  • the first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage.
  • An electronic device having an image pickup device that adjusts the output signal amount so that the
  • Imaging Device 11 Pixel Array Section 12 Driving Section 13 Reading Section 14 Reference Signal Generation Section 15 Signal Processing Section 16 Storage Section 17 Imaging Control Section 18 Data Receiving & Sorting Section 20 Pixel 21 Photoelectric Conversion Section (Photodiode) 22 transfer transistor 23 charge-voltage converter 24 reset transistor 25 amplification transistor 25 26 selection transistor 41, 43, 44 semiconductor substrate 50 signal amount adjustment unit 51 digital gain correction processing unit for each color 90 pixel pair 100 (100R, 100Gr, 100Gb, 100B) pixel block

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Abstract

An image capturing element according to the present invention is provided with: a first pixel block which has a plurality of pixels mutually including color filters of the same first color; and a second pixel block which has a plurality of pixels including color filters of a second color different from that of the first pixel block, and which has a different number of pixels than the number of pixels in the first pixel block. The first pixel block and the second pixel block are configured so as to share, among the plurality of pixels, pixel constituent elements downstream of a load voltage conversion unit. Also included is a signal quantity adjustment unit which adjusts the output signal quantities output by the pixels in the first pixel block and the second pixel block. The signal quantity adjustment unit adjusts output signal quantities such that the output signal quantity of the first color matches the output signal quantity of the second color.

Description

撮像素子および電子機器Image sensor and electronic equipment
 本技術は、撮像素子に関する。詳しくは、像面位相差を得る画素構造を有する撮像素子、および、当該撮像素子を有する電子機器に関する。 This technology relates to imaging devices. More specifically, the present invention relates to an image pickup device having a pixel structure that obtains an image plane phase difference, and an electronic device having the image pickup device.
 デジタルスチルカメラに代表される、撮像機能を備えた電子機器では、ピントを被写体に自動的に合わせるオートフォーカス方式が採用されている。このオートフォーカス方式の一つとして位相差方式があり、当該位相差方式の一つとして像面位相差方式がある(例えば、特許文献1参照。)。  Electronic devices equipped with imaging functions, typified by digital still cameras, employ an autofocus method that automatically focuses on the subject. One of the autofocus methods is a phase difference method, and one of the phase difference methods is an image plane phase difference method (see, for example, Patent Document 1).
国際公開第2016/098640号WO2016/098640
 上述の従来技術には、撮像画像を構成する画素信号を得るための通常画素と、像面位相差を得るための位相差検出画素とを備えた撮像素子が開示されている。撮像素子では、撮像画像の画質が高いことが望まれることから、今後、画素数の増加に伴って画素サイズの微細化が想定される。上述の従来技術では、位相差検出画素は、互いに隣接する2つの画素からなり、当該2つの画素に対してオンチップレンズが1つ形成された画素構造を基本の構成としている。したがって、撮像画像の高画質化に伴って画素サイズの微細化が図られたとしても、位相差検出画素の基本の画素構造を維持しつつ、高精度のオートフォーカスの実現に寄与できる撮像素子が望まれる。 The above-described conventional technology discloses an imaging device that includes normal pixels for obtaining pixel signals that form a captured image and phase difference detection pixels for obtaining an image plane phase difference. Since it is desired that the image quality of an image captured by an image sensor is high, it is expected that the pixel size will become finer in the future as the number of pixels increases. In the conventional technology described above, the phase difference detection pixel is composed of two pixels adjacent to each other, and the basic configuration is a pixel structure in which one on-chip lens is formed for the two pixels. Therefore, even if the pixel size is miniaturized with the improvement of the image quality of the captured image, there is an image sensor that can contribute to the realization of high-precision autofocus while maintaining the basic pixel structure of the phase difference detection pixel. desired.
 本技術は、このような状況に鑑みて生み出されたものであり、撮像画像の高画質化に伴って画素サイズの微細化が図られたとしても、位相差検出画素の基本の構成を維持しつつ、高精度のオートフォーカスの実現に寄与できるようにすることを目的とする。 This technology was created in view of this situation, and even if the pixel size is reduced as the quality of the captured image increases, the basic configuration of the phase difference detection pixel is maintained. It is an object of the present invention to contribute to realization of high-precision autofocus.
 本技術は、上述の問題点を解消するためになされたものであり、その第1の側面は、それぞれが、互いに同じ第1の色のカラーフィルタを含む複数の画素を有する第1の画素ブロックと、それぞれが、互いに同じで、かつ、上記第1の画素ブロックと異なる第2の色のカラーフィルタを含む複数の画素を有し、画素数が上記第1の画素ブロックの画素数と異なる第2の画素ブロックとを具備し、上記第1の画素ブロックおよび上記第2の画素ブロックは、それぞれが、2つの画素を対とする複数の画素ペアを有し、上記複数の画素ペアに対応するそれぞれの位置には複数のレンズが設けられており、上記第1の画素ブロックおよび上記第2の画素ブロックは、光電変換部で得られた電荷を電圧に変換する電荷電圧変換部以降の画素構成素子を複数の画素間で共有する画素共有の構成となっており、上記第1の画素ブロックおよび上記第2の画素ブロックの各画素から出力される出力信号量を調整する信号量調整部をさらに具備し、上記信号量調整部は、上記第1の画素ブロックから出力される上記第1の色についての出力信号量と、上記第2の画素ブロックから出力される上記第2の色についての出力信号量とが一致するように出力信号量の調整を行う撮像素子である。これにより、撮像画像の高画質化に伴って画素サイズの微細化が図られたとしても、位相差検出画素の基本の構成を維持しつつ、高精度のオートフォーカスの実現に寄与することができ、さらには、各色の画素ブロックの画素数が異なっていても、露光時間に比例した出力信号量を得ることができるという作用をもたらす。ここで、「一致する」とは、厳密に一致する場合の他、実質的に一致する場合も含む意味であり、設計上あるいは製造上生ずる種々のばらつきの存在は許容される。 The present technology has been made to solve the above-described problems, and a first aspect thereof is a first pixel block having a plurality of pixels each including a color filter of a first color that is the same as each other. each of which has a plurality of pixels including a color filter of a second color that is the same as that of the first pixel block and different from that of the first pixel block, and has a number of pixels different from that of the first pixel block. 2 pixel blocks, each of the first pixel block and the second pixel block having a plurality of pixel pairs of two pixels, corresponding to the plurality of pixel pairs. A plurality of lenses are provided at each position, and the first pixel block and the second pixel block have a pixel configuration after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage. It has a pixel-sharing configuration in which an element is shared among a plurality of pixels, and further includes a signal amount adjustment unit for adjusting an output signal amount output from each pixel of the first pixel block and the second pixel block. and the signal amount adjustment unit adjusts the output signal amount for the first color output from the first pixel block and the output signal amount for the second color output from the second pixel block. It is an imaging device that adjusts the output signal amount so that the signal amount matches the signal amount. As a result, even if the pixel size is reduced as the image quality of the captured image increases, it is possible to contribute to the realization of high-precision autofocus while maintaining the basic configuration of the phase difference detection pixel. Furthermore, even if the number of pixels in each color pixel block is different, there is an effect that an output signal amount proportional to the exposure time can be obtained. Here, "matching" means not only strictly matching but also substantially matching, and various variations caused by design or manufacturing are allowed.
 また、この第1の側面において、上記信号量調整部について、上記第1の画素ブロックから出力される上記第1の色についての出力信号量、および、上記第2の画素ブロックから出力される上記第2の色についての出力信号量に対して、信号量が小さい方の色の出力信号量が、信号量が大きい方の色の出力信号量に一致するように出力信号量の調整を行うようにしてもよい。これにより、各色の出力信号量の差分を吸収することができるという作用をもたらす。 Further, in the first aspect, the signal amount adjustment unit may adjust the output signal amount for the first color output from the first pixel block and the output signal amount for the first color output from the second pixel block. The output signal amount of the second color is adjusted so that the output signal amount of the color with the smaller signal amount matches the output signal amount of the color with the larger signal amount. can be This brings about the effect of being able to absorb the difference in the output signal amount of each color.
 また、この第1の側面において、上記信号量調整部について、上記第1の画素ブロックおよび上記第2の画素ブロックの各画素の信号を個々に読み出す第1の駆動モード、および、上記画素ペアの上記2つの画素の信号を加算して読み出す第2の駆動モードのとき、上記第1の画素ブロックから出力される上記第1の色についての出力信号量に対して、上記第2の画素ブロックから出力される上記第2の色についての出力信号量を一致させるように出力信号量の調整を行うようにしてもよい。これにより、第1の駆動モードおよび第2の駆動モードにおいて、各色の出力信号量の差分を吸収することができるという作用をもたらす。 Further, in the first aspect, the signal amount adjusting section is set to a first driving mode for individually reading signals of pixels of the first pixel block and the second pixel block, and a driving mode of the pixel pair. In the second drive mode for adding and reading out the signals of the two pixels, the output signal amount for the first color output from the first pixel block is The output signal amount may be adjusted so as to match the output signal amount for the output second color. This brings about the effect of being able to absorb the difference in the output signal amount of each color in the first drive mode and the second drive mode.
 また、この第1の側面において、上記信号量調整部について、上記第1の画素ブロックおよび上記第2の画素ブロックの全画素の信号を加算して読み出す第3の駆動モードのとき、上記第2の画素ブロックから出力される上記第2の色についての出力信号量に対して、上記第1の画素ブロックから出力される上記第1の色についての出力信号量を一致させるように出力信号量の調整を行うようにしてもよい。これにより、第3の駆動モードにおいて、各色の出力信号量の差分を吸収することができるという作用をもたらす。 Further, in the first aspect, in the third drive mode for adding and reading out the signals of all the pixels in the first pixel block and the second pixel block, the signal amount adjusting section may of the output signal amount so as to match the output signal amount of the first color output from the first pixel block with the output signal amount of the second color output from the pixel block of Adjustments may be made. As a result, in the third drive mode, it is possible to absorb the difference in the output signal amount of each color.
 また、この第1の側面において、上記信号量調整部について、上記出力信号量の調整を、上記第1の画素ブロックおよび上記第2の画素ブロックの各画素から出力されるアナログ信号をデジタル信号に変換した後のデジタル領域におけるデジタルゲイン調整によって行うようにしてもよい。これにより、各色の出力信号量の差分を吸収する処理をデジタル領域において行うことができるという作用をもたらす。 In the first aspect, the signal amount adjustment unit adjusts the output signal amount by converting the analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal. It may be performed by digital gain adjustment in the digital domain after conversion. This brings about the effect that the process of absorbing the difference in the output signal amount of each color can be performed in the digital domain.
 また、この第1の側面において、上記信号量調整部について、色別の出力信号量の調整を、上記第1の画素ブロックおよび上記第2の画素ブロックの各画素から出力されるアナログ信号をデジタル信号に変換する前のアナログ領域におけるアナログゲイン調整によって行うようにしてもよい。これにより、各色の出力信号量の差分を吸収する処理をアナログ領域において行うことができるという作用をもたらす。 Further, in the first aspect, the signal amount adjustment unit adjusts the output signal amount for each color by converting the analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal. It may be done by analog gain adjustment in the analog domain before conversion to signal. This brings about the effect that the process of absorbing the difference in the output signal amount of each color can be performed in the analog domain.
 また、この第1の側面において、アナログ信号をデジタル信号に変換するアナログ-デジタル変換部が、時間経過に応じて所定の傾きでレベルが変化するランプ波の参照信号を、アナログ-デジタル変換の際の基準信号として用いるシングルスロープ型のアナログ-デジタル変換部であり、上記信号量調整部について、上記ランプ波の参照信号の傾きを変えることによってアナログゲイン調整を行うようにしてもよい。これにより、ランプ波の参照信号の傾きを変えることによって各色の出力信号量の差分を吸収する処理を行うことができるという作用をもたらす。 Further, in the first aspect, the analog-to-digital converter that converts an analog signal to a digital signal converts a reference signal of a ramp wave whose level changes with a predetermined slope over time during analog-to-digital conversion. A single-slope type analog-to-digital conversion unit used as a reference signal for the signal amount adjustment unit may perform analog gain adjustment by changing the slope of the reference signal of the ramp wave. As a result, by changing the slope of the reference signal of the ramp wave, it is possible to absorb the difference in the output signal amount of each color.
 また、この第1の側面において、上記2つの画素について第1の方向に並設され、上記第1の画素ブロックおよび上記第2の画素ブロックのそれぞれにおいて、上記第1の方向と交差する第2の方向に並ぶ2つの上記画素ペアについて、上記第1の方向においてずれて配置するようにしてもよい。これにより、画素アレイ部における画素配置を密にすることができるという作用をもたらす。 Further, on the first side surface, the two pixels are arranged side by side in the first direction, and in each of the first pixel block and the second pixel block, a second pixel block intersects the first direction. The two pixel pairs lined up in the direction may be shifted in the first direction. This brings about an effect that the pixels can be arranged densely in the pixel array section.
 また、本技術の第2の側面は、それぞれが、互いに同じ第1の色のカラーフィルタを含む複数の画素を有する第1の画素ブロックと、それぞれが、互いに同じで、かつ、上記第1の画素ブロックと異なる第2の色のカラーフィルタを含む複数の画素を有し、画素数が上記第1の画素ブロックの画素数と異なる第2の画素ブロックと、上記第1の画素ブロックおよび上記第2の画素ブロックの各画素から出力されるアナログ信号をデジタル信号に変換するアナログ-デジタル変換部とを具備し、上記第1の画素ブロックおよび上記第2の画素ブロックは、それぞれが、2つの画素を対とする複数の画素ペアを有し、上記複数の画素ペアに対応するそれぞれの位置には複数のレンズが設けられており、上記第1の画素ブロックおよび上記第2の画素ブロックは、光電変換部で得られた電荷を電圧に変換する電荷電圧変換部以降の画素構成素子を複数の画素間で共有する画素共有の構成となっており、上記アナログ-デジタル変換部は、参照信号生成部から与えられるランプ波の参照信号を、アナログ-デジタル変換の際の基準信号として用いるシングルスロープ型のアナログ-デジタル変換部であり、上記参照信号生成部として、それぞれ、傾きが異なるランプ波の参照信号を生成する複数の参照信号生成部が設けられており、上記第1の画素ブロックおよび上記第2の画素ブロックの各画素から出力される出力信号量を調整する信号量調整部をさらに具備し、上記信号量調整部は、上記複数の参照信号生成部のそれぞれで生成される上記傾きが異なるランプ波の参照信号に基づいて、上記第1の画素ブロックから出力される上記第1の色についての出力信号量と、上記第2の画素ブロックから出力される上記第2の色についての出力信号量とが一致するように出力信号量の調整を行う撮像素子である。これにより、撮像画像の高画質化に伴って画素サイズの微細化が図られたとしても、位相差検出画素の基本の構成を維持しつつ、高精度のオートフォーカスの実現に寄与することができ、さらには、各色の画素ブロックの画素数が異なっていても、露光時間に比例した出力信号量を得ることができるという作用をもたらす。 In addition, a second aspect of the present technology includes: a first pixel block having a plurality of pixels each including a color filter of a first color that is the same as each other; a second pixel block having a plurality of pixels including a color filter of a second color different from that of the pixel block and having a number of pixels different from that of the first pixel block; and an analog-to-digital converter for converting an analog signal output from each pixel of two pixel blocks into a digital signal, wherein the first pixel block and the second pixel block each include two pixels. and a plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs, and the first pixel block and the second pixel block are photoelectric It has a pixel-sharing configuration in which the pixel-constituting elements after the charge-voltage conversion unit that converts the charge obtained by the conversion unit into voltage are shared among a plurality of pixels. A single-slope analog-to-digital conversion unit that uses a ramp wave reference signal given from as a reference signal in analog-to-digital conversion, and the reference signal generation unit is a ramp wave reference signal with a different slope. is provided with a plurality of reference signal generation units that generate the and further includes a signal amount adjustment unit that adjusts the output signal amount output from each pixel of the first pixel block and the second pixel block, The signal amount adjustment unit adjusts the first color output from the first pixel block based on the ramp wave reference signals with different slopes generated by the plurality of reference signal generation units. The imaging device adjusts the output signal amount so that the output signal amount and the output signal amount for the second color output from the second pixel block match. As a result, even if the pixel size is reduced as the image quality of the captured image increases, it is possible to contribute to the realization of high-precision autofocus while maintaining the basic configuration of the phase difference detection pixel. Furthermore, even if the number of pixels in each color pixel block is different, there is an effect that an output signal amount proportional to the exposure time can be obtained.
 また、この第2の側面において、上記複数の参照信号生成部について、上記第1の画素ブロックから出力される上記第1の色についての出力信号量を調整するための参照信号生成部、および、上記第2の画素ブロックから出力される上記第2の色についての出力信号量を調整するための参照信号生成部であるようにしてもよい。これにより、各画素ブロックから出力される各色の出力信号量の差分を吸収する処理を、2つの参照信号生成部で生成されるランプ波の参照信号の傾きを調整することによって行うことができるという作用をもたらす。 In the second aspect, among the plurality of reference signal generators, a reference signal generator for adjusting an output signal amount for the first color output from the first pixel block; It may be a reference signal generator for adjusting the output signal amount for the second color output from the second pixel block. As a result, the process of absorbing the difference in the output signal amount of each color output from each pixel block can be performed by adjusting the inclination of the reference signal of the ramp wave generated by the two reference signal generation units. bring about action.
 また、本技術の第3の側面は、それぞれが、互いに同じ第1の色のカラーフィルタを含む複数の画素を有する第1の画素ブロックと、それぞれが、互いに同じで、かつ、上記第1の画素ブロックと異なる第2の色のカラーフィルタを含む複数の画素を有し、画素数が上記第1の画素ブロックの画素数と異なる第2の画素ブロックとを具備し、上記第1の画素ブロックおよび上記第2の画素ブロックは、それぞれが、2つの画素を対とする複数の画素ペアを有し、上記複数の画素ペアに対応するそれぞれの位置には複数のレンズが設けられており、上記第1の画素ブロックおよび上記第2の画素ブロックは、光電変換部で得られた電荷を電圧に変換する電荷電圧変換部以降の画素構成素子を複数の画素間で共有する画素共有の構成となっており、上記第1の画素ブロックおよび上記第2の画素ブロックの各画素から出力される出力信号量を調整する信号量調整部をさらに具備し、上記信号量調整部は、上記第1の画素ブロックから出力される上記第1の色についての出力信号量と、上記第2の画素ブロックから出力される上記第2の色についての出力信号量とが一致するように出力信号量の調整を行う撮像素子を有する電子機器である。これにより、撮像素子において、撮像画像の高画質化に伴って画素サイズの微細化が図られたとしても、位相差検出画素の基本の構成を維持しつつ、高精度のオートフォーカスの実現に寄与することができ、さらには、各色の画素ブロックの画素数が異なっていても、露光時間に比例した出力信号量を得ることができるという作用をもたらす。 In addition, a third aspect of the present technology includes: a first pixel block having a plurality of pixels each including a color filter of a first color that is the same as each other; a second pixel block having a plurality of pixels including a color filter of a second color different from the pixel block and having a number of pixels different from that of the first pixel block; and the second pixel blocks each have a plurality of pixel pairs each having two pixels, and a plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs, and the The first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share the pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage. and further comprising a signal amount adjustment section for adjusting an output signal amount output from each pixel of the first pixel block and the second pixel block, wherein the signal amount adjustment section adjusts the output signal amount of the first pixel block. The output signal amount is adjusted so that the output signal amount for the first color output from the block and the output signal amount for the second color output from the second pixel block match. An electronic device having an image sensor. This contributes to the realization of high-precision autofocus while maintaining the basic configuration of the phase-difference detection pixels, even if the pixel size of the image sensor is reduced as the quality of the captured image increases. Furthermore, even if the number of pixels in each color pixel block is different, it is possible to obtain an output signal amount proportional to the exposure time.
本技術の第1の実施の形態における撮像素子の一構成例を示すブロック図である。It is a block diagram showing an example of 1 composition of an image sensor in a 1st embodiment of this art. 第1の実施の形態における撮像素子の画素アレイ部における画素配置の一例を示す平面図である。FIG. 2 is a plan view showing an example of pixel arrangement in a pixel array section of the image pickup device according to the first embodiment; 第1の実施の形態における撮像素子の画素アレイ部の概略断面構造の一例を示す断面図である。FIG. 2 is a cross-sectional view showing an example of a schematic cross-sectional structure of a pixel array portion of the image pickup device according to the first embodiment; 図2に示した緑色(Gr)の画素ブロックの回路構成の一例を示す回路図である。3 is a circuit diagram showing an example of a circuit configuration of a green (Gr) pixel block shown in FIG. 2; FIG. 図2に示した赤色(R)の画素ブロックの回路構成の一例を示す回路図である。3 is a circuit diagram showing an example of a circuit configuration of a red (R) pixel block shown in FIG. 2; FIG. 第1の実施の形態における撮像素子の読出部の構成の一例を示すブロック図である。3 is a block diagram showing an example of the configuration of a readout section of the image sensor in the first embodiment; FIG. 第1の実施の形態における撮像素子から出力される画像信号Spicの構造の一例を示す図である。FIG. 2 is a diagram showing an example of the structure of an image signal Spic output from an imaging element in the first embodiment; FIG. 平置型の半導体チップ構造および積層型の半導体チップ構造を模式的に示す斜視図である。1 is a perspective view schematically showing a flat-type semiconductor chip structure and a stacked-type semiconductor chip structure; FIG. 第1の実施の形態における撮像素子の信号量調整部の一構成例を示すブロック図である。4 is a block diagram showing one configuration example of a signal amount adjustment unit of the image sensor in the first embodiment; FIG. 全画素読出しモードおよびAFモードの場合における出力信号量の調整について説明する図である。FIG. 10 is a diagram illustrating adjustment of the output signal amount in the case of all-pixel readout mode and AF mode; 全画素加算モードの場合における出力信号量の調整について説明する図である。FIG. 10 is a diagram illustrating adjustment of the output signal amount in the case of all-pixel addition mode; 本技術の第2の実施の形態におけるアナログ-デジタル変換部の一構成例を示す回路図である。It is a circuit diagram showing a configuration example of an analog-digital conversion unit according to a second embodiment of the present technology. 高ゲイン時の参照信号RAMPの波形、低ゲインの参照信号RAMPの波形、信号線VSLの波形、および、カウンタのクロックのタイミング関係を示す波形図である。FIG. 3 is a waveform diagram showing timing relationships among a waveform of a reference signal RAMP at high gain, a waveform of a reference signal RAMP at low gain, a waveform of a signal line VSL, and clocks of a counter; 本技術を適用した電子機器の一例である撮像装置の一構成例を示すブロック図である。1 is a block diagram showing a configuration example of an imaging device, which is an example of electronic equipment to which the present technology is applied; FIG. 本技術の実施の形態が適用される分野の例を示す図である。It is a figure showing an example of a field to which an embodiment of this art is applied. 車両制御システムの概略的な構成例を示すブロック図である。1 is a block diagram showing a schematic configuration example of a vehicle control system; FIG. 撮像部の設置位置の一例を示す説明図である。FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit;
 以下、本技術を実施するための形態(以下、実施の形態と称する)について説明する。説明は以下の順序により行う。
 1.第1の実施の形態(色別の出力信号量の差分を吸収する制御:デジタルゲイン補正処理で行う例)
 2.第2の実施の形態(色別の出力信号量の差分を吸収する制御:アナログゲイン補正処理で行う例)
 3.変形例
 4.電子機器への適用例
 5.本技術の実施の形態の適用例
 6.移動体への応用例
 7.本技術がとることができる構成
Hereinafter, a form for carrying out the present technology (hereinafter referred to as an embodiment) will be described. Explanation will be given in the following order.
1. First Embodiment (Control for Absorbing Differences in Output Signal Amounts by Color: Example Performed by Digital Gain Correction Processing)
2. Second Embodiment (Control for Absorbing Differences in Output Signal Amounts by Color: Example of Analog Gain Correction Processing)
3. Modification 4. Application example to electronic equipment 5 . Application example of the embodiment of the present technology6. Example of application to a moving object 7. Possible configurations for this technology
 <1.第1の実施の形態>
 本技術の撮像素子としては、例えば、X-Yアドレス方式の撮像素子の一種であるCMOS(Complementary Metal Oxide Semiconductor)イメージセンサを例示することができる。CMOSイメージセンサは、CMOSプロセスを応用して、又は、部分的に使用して作製された撮像素子である。
<1. First Embodiment>
As an imaging element of the present technology, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a type of XY addressing imaging element, can be exemplified. A CMOS image sensor is an imaging device manufactured by applying or partially using a CMOS process.
[撮像素子の一構成例]
 図1は、本技術の第1の実施の形態における撮像素子の一構成例を示すブロック図である。この撮像素子1は、画素アレイ部11、駆動部12、読出部13、参照信号生成部14、信号処理部15、記憶部(データ格納部)16、および、撮像制御部17を備えた構成となっている。
[One configuration example of the imaging element]
FIG. 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology. The imaging device 1 includes a pixel array section 11, a driving section 12, a reading section 13, a reference signal generating section 14, a signal processing section 15, a storage section (data storage section) 16, and an imaging control section 17. It's becoming
 画素アレイ部11は、光電変換部(光電変換素子)を含む画素(画素回路)20が行方向および列方向に、即ち、行列状に2次元配置された構成となっている。ここで、行方向とは、画素行の画素20の配列方向を言い、列方向とは、画素列の画素20の配列方向を言う。画素20は、光電変換を行うことにより、受光した光量に応じた光電荷を生成し、蓄積する。画素20は、入射光の受光量に応じた画素電圧Vpixを含む信号SIGを生成する。 The pixel array section 11 has a configuration in which pixels (pixel circuits) 20 including photoelectric conversion sections (photoelectric conversion elements) are two-dimensionally arranged in row and column directions, that is, in a matrix. Here, the row direction refers to the arrangement direction of the pixels 20 in the pixel row, and the column direction refers to the arrangement direction of the pixels 20 in the pixel column. The pixels 20 perform photoelectric conversion to generate and store photocharges corresponding to the amount of received light. The pixel 20 generates a signal SIG containing a pixel voltage Vpix corresponding to the amount of incident light received.
 駆動部12は、シフトレジスタやアドレスデコーダなどによって構成され、画素アレイ部11の各画素20の選択に際して、撮像制御部17から供給されるタイミング制御信号に基づいて、画素行の走査や画素行のアドレスを制御する駆動を行う。この駆動部12による駆動の下に、画素アレイ部11の各画素20から、画素電圧Vpixを含む信号SIGが出力される。 The drive unit 12 is composed of a shift register, an address decoder, and the like, and when selecting each pixel 20 of the pixel array unit 11, based on a timing control signal supplied from the imaging control unit 17, scans the pixel rows and performs pixel row selection. Drive to control the address. A signal SIG including the pixel voltage Vpix is output from each pixel 20 of the pixel array section 11 under the driving by the driving section 12 .
 読出部13は、例えば、後述するシングルスロープ型のアナログ-デジタル変換部を備えており、撮像制御部17による制御の下に、画素アレイ部11の各画素20から信号線VSLを介して読み出される、画素電圧Vpixを含む信号SIGに対して、アナログ-デジタル変換(AD変換)を行う。読出部13は、アナログ-デジタル変換後の信号を画像信号Spic0として出力する。 The reading unit 13 includes, for example, a single-slope type analog-digital conversion unit, which will be described later. , the signal SIG including the pixel voltage Vpix is subjected to analog-to-digital conversion (AD conversion). The reading unit 13 outputs the analog-digital converted signal as the image signal Spic0.
 参照信号生成部14は、読出部13のシングルスロープ型のアナログ-デジタル変換部において、アナログ-デジタル変換の際の基準信号として用いられる参照信号RAMPを生成する。この参照信号RAMPは、時間経過に応じて所定の傾きでレベル(電圧)が変化する(例えば、単調減少する)、所謂、ランプ波の信号である。 The reference signal generation unit 14 generates a reference signal RAMP that is used as a reference signal for analog-to-digital conversion in the single-slope analog-to-digital conversion unit of the reading unit 13 . The reference signal RAMP is a so-called ramp wave signal whose level (voltage) changes (for example, monotonously decreases) with a predetermined slope over time.
 信号処理部15は、撮像制御部17による制御の下に、読出部13から供給される画像信号Spic0に対して所定の信号処理を行うことにより、画像信号Spicとして出力する。信号処理部15は、画像データ生成部151と、位相差データ生成部152とを有する構成となっている。 Under the control of the imaging control unit 17, the signal processing unit 15 performs predetermined signal processing on the image signal Spic0 supplied from the reading unit 13, and outputs it as an image signal Spic. The signal processing section 15 is configured to have an image data generation section 151 and a phase difference data generation section 152 .
 信号処理部15において、画像データ生成部151は、画像信号Spic0に基づいて、所定の画像処理を行うことにより、撮像画像を示す画像データDPを生成するように構成されている。位相差データ生成部152は、画像信号Spic0に基づいて、所定の画像処理を行うことにより、像面位相差を示す位相差データDFを生成するように構成されている。 In the signal processing unit 15, the image data generation unit 151 is configured to generate image data DP representing a captured image by performing predetermined image processing based on the image signal Spic0. The phase difference data generator 152 is configured to generate phase difference data DF indicating the image plane phase difference by performing predetermined image processing based on the image signal Spic0.
 信号処理部15は、画像データ生成部151によって生成された画像データDP、および、位相差データ生成部152によって生成された位相差データDFを含む画像信号Spicを出力する。 The signal processing unit 15 outputs an image signal Spic including the image data DP generated by the image data generation unit 151 and the phase difference data DF generated by the phase difference data generation unit 152 .
 記憶部(データ格納部)16は、例えば、信号処理部15での信号処理に当たって、その処理に必要なデータを一時的に記憶(格納)する。 For example, when the signal processing unit 15 performs signal processing, the storage unit (data storage unit) 16 temporarily stores (stores) data necessary for the processing.
 撮像制御部17は、外部から与えられる制御信号Sctlに基づいて、各種のタイミング信号、クロック信号、および、制御信号等を生成し、これら生成した信号を基に、駆動部12、読出部13、参照信号生成部14、および、信号処理部15等の駆動制御を行うことにより、撮像素子1の動作を制御する。撮像制御部17は、制御信号Sctlに基づいて、撮像素子1の撮像動作を制御する。 The imaging control unit 17 generates various timing signals, clock signals, control signals, etc. based on an externally applied control signal Sctl, and based on these generated signals, the driving unit 12, reading unit 13, The operation of the image sensor 1 is controlled by controlling the driving of the reference signal generation unit 14, the signal processing unit 15, and the like. The imaging control unit 17 controls the imaging operation of the imaging element 1 based on the control signal Sctl.
[画素の配置例]
 図2は、画素アレイ部11における画素20の配置の一例を示す平面図である。図2に示すように、画素アレイ部11は、複数の画素ブロック100と、複数のレンズ101とを有している。
[Example of pixel arrangement]
FIG. 2 is a plan view showing an example of arrangement of the pixels 20 in the pixel array section 11. As shown in FIG. As shown in FIG. 2 , the pixel array section 11 has a plurality of pixel blocks 100 and a plurality of lenses 101 .
 複数の画素ブロック100は、画素ブロック100R、画素ブロック100Gr、画素ブロック100Gb、および、画素ブロック100Bを含んでいる。画素アレイ部11では、複数の画素20は、4つの画素ブロック100(画素ブロック100R,100Gr,100Gb,100B)を単位(ユニットU)として配置されている。 The plurality of pixel blocks 100 includes pixel block 100R, pixel block 100Gr, pixel block 100Gb, and pixel block 100B. In the pixel array section 11, the plurality of pixels 20 are arranged in units (units U) of four pixel blocks 100 (pixel blocks 100R, 100Gr, 100Gb, and 100B).
 画素ブロック100Rは、赤色(R)のカラーフィルタ115(図3参照)を含む8個の画素20Rを有する。画素ブロック100Grは、緑色(G)のカラーフィルタ115を含む10個の画素20Grを有する。画素ブロック100Gbは、緑色(G)のカラーフィルタ115を含む10個の画素20Gbを有する。画素ブロック100Bは、青色(B)のカラーフィルタ115を含む8個の画素20Bを有する。図2では、カラーフィルタの色の違いを、網掛けを用いて表現している。 The pixel block 100R has eight pixels 20R including a red (R) color filter 115 (see FIG. 3). A pixel block 100Gr has ten pixels 20Gr including a green (G) color filter 115 . A pixel block 100Gb has ten pixels 20Gb including a green (G) color filter 115 . Pixel block 100B has eight pixels 20B including blue (B) color filter 115 . In FIG. 2, the difference in color of the color filters is expressed using hatching.
 画素ブロック100Rにおける8個の画素20Rの配置パターン、および、画素ブロック100Bにおける8個の画素20Bの配置パターンは、互いに同じである。画素ブロック100Grにおける10個の画素20Grの配置パターン、および、画素ブロック100Gbにおける10個の画素20Gbの配置パターンは、互いに同じである。ユニットUにおいて、画素ブロック100Grは左上に配置され、画素ブロック100Rは右上に配置され、画素ブロック100Bは左下に配置され、画素ブロック100Gbは右下に配置される。 The arrangement pattern of the eight pixels 20R in the pixel block 100R and the arrangement pattern of the eight pixels 20B in the pixel block 100B are the same. The arrangement pattern of the ten pixels 20Gr in the pixel block 100Gr and the arrangement pattern of the ten pixels 20Gb in the pixel block 100Gb are the same. In the unit U, the pixel block 100Gr is located at the upper left, the pixel block 100R is located at the upper right, the pixel block 100B is located at the lower left, and the pixel block 100Gb is located at the lower right.
 上述の画素ブロック100R、画素ブロック100Gr、画素ブロック100Gb、および、画素ブロック100Bの配列は、所謂、RGBベイヤー配列である。すなわち、画素ブロック100R、画素ブロック100Gr、画素ブロック100Gb、および、画素ブロック100Bは、画素ブロック100を単位として、RGBベイヤー配列による配列となっている。 The arrangement of the pixel block 100R, the pixel block 100Gr, the pixel block 100Gb, and the pixel block 100B is a so-called RGB Bayer arrangement. That is, the pixel block 100R, the pixel block 100Gr, the pixel block 100Gb, and the pixel block 100B are arrayed in the RGB Bayer array with the pixel block 100 as a unit.
 なお、赤色(R)および青色(B)は、特許請求の範囲に記載の第1の色の一例であり、緑色(Gr,Gb)は、特許請求の範囲に記載の第2の色の一例である。また、画素ブロック100Rおよび画素ブロック100Bは、特許請求の範囲に記載の第1の画素ブロックの一例であり、画素ブロック100Grおよび画素ブロック100Gbは、特許請求の範囲に記載の第2の画素ブロックの一例である。 Red (R) and blue (B) are examples of the first color described in the claims, and green (Gr, Gb) are examples of the second color described in the claims. is. The pixel block 100R and the pixel block 100B are examples of the first pixel block described in the claims, and the pixel block 100Gr and the pixel block 100Gb are examples of the second pixel block described in the claims. An example.
[画素アレイ部の断面構造例]
 図3は、画素アレイ部11の概略断面構造の一例を示す断面図である。図3に示すように、画素アレイ部11は、複数のレンズ101の他、半導体基板111、半導体領域112、絶縁層113、多層配線層114、カラーフィルタ115、および、遮光膜116を備えている。
[Example of cross-sectional structure of pixel array part]
FIG. 3 is a cross-sectional view showing an example of a schematic cross-sectional structure of the pixel array section 11. As shown in FIG. As shown in FIG. 3, the pixel array section 11 includes a plurality of lenses 101, a semiconductor substrate 111, a semiconductor region 112, an insulating layer 113, a multilayer wiring layer 114, a color filter 115, and a light shielding film 116. .
 半導体基板111は、撮像素子1が形成される支持基板であり、例えば、P型の半導体基板である。半導体領域112は、半導体基板111の基板内における、複数の画素20のそれぞれに対応する位置に設けられた半導体領域であり、N型の不純物がドーピングされることにより光電変換部(例えば、フォトダイオード)が形成される。絶縁層113は、半導体基板111の基板内における、XY平面において並設された複数の画素20の境界に設けられ、この例では、酸化膜などを用いて構成されるDTI(Deep Trench Isolation)である。 The semiconductor substrate 111 is a support substrate on which the imaging element 1 is formed, and is, for example, a P-type semiconductor substrate. The semiconductor region 112 is a semiconductor region provided at a position corresponding to each of the plurality of pixels 20 in the semiconductor substrate 111, and is doped with an N-type impurity to form a photoelectric conversion portion (for example, a photodiode). ) is formed. The insulating layer 113 is provided in the substrate of the semiconductor substrate 111 at the boundary of the plurality of pixels 20 arranged in parallel on the XY plane. be.
 多層配線層114は、画素アレイ部11の光入射側(レンズ101側)とは反対側の面における半導体基板111の上に設けられ、複数の配線層および層間絶縁膜を含む。多層配線層114における配線は、例えば、半導体基板111の表面に設けられた図示しないトランジスタと、駆動部12および読出部13とを接続するように構成されている。 The multilayer wiring layer 114 is provided on the semiconductor substrate 111 on the side opposite to the light incident side (lens 101 side) of the pixel array section 11, and includes a plurality of wiring layers and interlayer insulating films. The wiring in the multilayer wiring layer 114 is configured to connect, for example, a transistor (not shown) provided on the surface of the semiconductor substrate 111 to the driving section 12 and the reading section 13 .
 カラーフィルタ115は、画素アレイ部11の光入射側における半導体基板111の上に設けられる。ここで、XY平面において、第1の方向をX方向とし、第2の方向をY方向とするとき、遮光膜116は、画素アレイ部11における光入射側において、X方向に並設された2つの画素20を囲むように設けられる。以下、X方向に並設された2つの画素20を画素ペア90とも呼ぶこととする。 The color filter 115 is provided on the semiconductor substrate 111 on the light incident side of the pixel array section 11 . Here, in the XY plane, when the first direction is the X direction and the second direction is the Y direction, the light shielding films 116 are arranged side by side in the X direction on the light incident side of the pixel array section 11 . It is provided so as to surround one pixel 20 . The two pixels 20 arranged side by side in the X direction are hereinafter also referred to as a pixel pair 90 .
 複数のレンズ101は、所謂、オンチップレンズであり、画素アレイ部11の光入射側におけるカラーフィルタ115の上に設けられている。複数のレンズ101は、X方向に並設された2つの画素20(画素ペア90)の上部に設けられている。画素ブロック100Rの8個の画素20の上部には4つのレンズ101が設けられている。画素ブロック100Grの10個の画素20の上部には5つのレンズ101が設けられている。画素ブロック100Gbの10個の画素20の上部には5つのレンズ101が設けられている。画素ブロック100Bの8個の画素20の上部には4つのレンズ101が設けられている。 The multiple lenses 101 are so-called on-chip lenses, and are provided on the color filter 115 on the light incident side of the pixel array section 11 . A plurality of lenses 101 are provided above two pixels 20 (pixel pairs 90) arranged side by side in the X direction. Four lenses 101 are provided above the eight pixels 20 of the pixel block 100R. Five lenses 101 are provided above the ten pixels 20 of the pixel block 100Gr. Five lenses 101 are provided above the ten pixels 20 of the pixel block 100Gb. Four lenses 101 are provided above the eight pixels 20 of the pixel block 100B.
 複数のレンズ101は、X方向およびY方向において並設されている。Y方向に並ぶレンズ101は、X方向において、1つの画素20の分だけずれて配置されている。換言すれば、Y方向に並ぶ画素ペア90は、X方向において、1つの画素20の分だけずれて配置されている。 A plurality of lenses 101 are arranged side by side in the X direction and the Y direction. The lenses 101 arranged in the Y direction are arranged with a shift of one pixel 20 in the X direction. In other words, the pixel pairs 90 aligned in the Y direction are shifted by one pixel 20 in the X direction.
 この構成により、1つのレンズ101に対応する画素ペア90の2つの画素20においては、互いに像がずれる。撮像素子1は、複数の画素ペア90により検出された、所謂、像面位相差に基づいて位相差データDFを生成する。すなわち、1つのレンズ101に対応する画素ペア90の2つの画素20は、像面位相差に基づいて位相差データDFを生成するための位相差検出画素である。デジタルスチルカメラなどの撮像機能を備えた電子機器では、位相差データDFに基づいてデフォーカス量を決定し、当該デフォーカス量に基づいて、撮影レンズの位置を移動させる。このようにして、撮像機能を備えた電子機器では、オートフォーカスを実現することができる。 With this configuration, the images of the two pixels 20 of the pixel pair 90 corresponding to one lens 101 are shifted from each other. The imaging device 1 generates phase difference data DF based on so-called image plane phase differences detected by the plurality of pixel pairs 90 . That is, the two pixels 20 of the pixel pair 90 corresponding to one lens 101 are phase difference detection pixels for generating the phase difference data DF based on the image plane phase difference. 2. Description of the Related Art An electronic device having an imaging function such as a digital still camera determines the defocus amount based on the phase difference data DF, and moves the position of the photographing lens based on the defocus amount. In this manner, autofocus can be realized in an electronic device having an imaging function.
[画素ブロックの回路構成例]
 次に、画素ブロック100の回路構成例について、10個の画素20Grを有する緑色(Gr)の画素ブロック100Gr、および、8個の画素20Rを有する赤色(R)の画素ブロック100Rを例に挙げて説明する。図4は、緑色(Gr)の画素ブロック100Grの回路構成の一例を示す回路図である。図5は、赤色(R)の画素ブロック100Rの回路構成の一例を示す回路図である。
[Example of circuit configuration of pixel block]
Next, as an example of the circuit configuration of the pixel block 100, a green (Gr) pixel block 100Gr having ten pixels 20Gr and a red (R) pixel block 100R having eight pixels 20R are taken as examples. explain. FIG. 4 is a circuit diagram showing an example of the circuit configuration of the green (Gr) pixel block 100Gr. FIG. 5 is a circuit diagram showing an example of the circuit configuration of the red (R) pixel block 100R.
 画素アレイ部11は、複数の制御線TRGL、複数の制御線RSTL、複数の制御線SELL、および、複数の信号線VSLを有している。 The pixel array section 11 has a plurality of control lines TRGL, a plurality of control lines RSTL, a plurality of control lines SELL, and a plurality of signal lines VSL.
 制御線TRGLは、画素アレイ部11の画素行ごとに、行方向に沿って配線されており、一端が駆動部12の対応する出力端に接続されている。この制御線TRGLには、駆動部12から制御信号が適宜供給される。制御線RSTLは、画素アレイ部11の画素行ごとに、行方向に沿って配線されており、一端が駆動部12の対応する出力端に接続されている。この制御線RSTLには、駆動部12から制御信号が適宜供給される。 The control line TRGL is wired along the row direction for each pixel row of the pixel array section 11 , and one end is connected to the corresponding output terminal of the driving section 12 . A control signal is appropriately supplied from the drive unit 12 to the control line TRGL. The control line RSTL is wired along the row direction for each pixel row of the pixel array section 11 , and one end is connected to the corresponding output terminal of the driving section 12 . A control signal is appropriately supplied from the drive unit 12 to the control line RSTL.
 制御線SELLは、画素アレイ部11の画素行ごとに、行方向に沿って配線されており、一端が駆動部12の対応する出力端に接続されている。この制御線SELLには、駆動部12から制御信号が適宜供給される。信号線VSLは、画素アレイ部11の画素列ごとに、列方向に沿って配線されており、一端が読出部13に接続される。この信号線VSLは、画素20から出力される信号SIGを読出部13に伝送する。 The control line SELL is wired along the row direction for each pixel row of the pixel array section 11 , and one end is connected to the corresponding output terminal of the drive section 12 . A control signal is appropriately supplied from the drive unit 12 to the control line SELL. The signal line VSL is wired along the column direction for each pixel column of the pixel array section 11 , and one end is connected to the readout section 13 . This signal line VSL transmits the signal SIG output from the pixel 20 to the reading unit 13 .
 図4に示す緑色(Gr)の画素ブロック100Grは、10個の光電変換部21、および、10個の転送トランジスタ22を有している。画素ブロック100Grは、さらに、電荷電圧変換部23、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26を1個ずつ有している。 A green (Gr) pixel block 100Gr shown in FIG. 4 has ten photoelectric conversion units 21 and ten transfer transistors 22 . The pixel block 100Gr further has one charge-voltage converter 23, one reset transistor 24, one amplifier transistor 25, and one selection transistor 26. FIG.
 ここで、転送トランジスタ22、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26としては、例えば、N型MOS(Metal Oxide Semiconductor)電界効果トランジスタを用いることができる。ただし、ここで例示した転送トランジスタ22、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26の導電型の組み合わせは一例に過ぎず、これらの組み合わせに限られるものではない。 Here, as the transfer transistor 22, the reset transistor 24, the amplification transistor 25, and the selection transistor 26, for example, an N-type MOS (Metal Oxide Semiconductor) field effect transistor can be used. However, the combination of the conductivity types of the transfer transistor 22, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 illustrated here is merely an example, and the combination is not limited to these combinations.
 10個の光電変換部21および10個の転送トランジスタ22は、画素ブロック100Grに含まれる10個の画素20Grにそれぞれ対応している。そして、画素ブロック100Grは、電荷電圧変換部23、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26を、10個の画素20Gr間で共有する、所謂、画素共有の画素回路の構成となっている。 The 10 photoelectric conversion units 21 and the 10 transfer transistors 22 respectively correspond to the 10 pixels 20Gr included in the pixel block 100Gr. The pixel block 100Gr has a configuration of a so-called pixel shared pixel circuit in which the charge-voltage converter 23, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 are shared among the ten pixels 20Gr. there is
 光電変換部21は、PN接合のフォトダイオード(PD:Photo Diode)である。フォトダイオードは、アノード電極が低電位側電源(例えば、グランド)に接続されており、受光量に応じた量の電荷を生成し、生成した電荷を内部に蓄積する。フォトダイオード21のカソード電極は、転送トランジスタ22のソース電極に接続されている。 The photoelectric conversion unit 21 is a PN junction photodiode (PD: Photo Diode). The photodiode has an anode electrode connected to a low-potential power supply (for example, ground), generates an amount of charge corresponding to the amount of light received, and accumulates the generated charge inside. A cathode electrode of the photodiode 21 is connected to a source electrode of the transfer transistor 22 .
 転送トランジスタ22のゲート電極は制御線TRGLに接続され、ソース電極は光電変換部21のカソード電極に接続され、ドレイン電極は電荷電圧変換部23に接続されている。10個の転送トランジスタ22のゲート電極は、10本の制御線TRGL(この例では、制御線TRGL1~TRGL6,TRGL9~TRGL12)のうちの互いに異なる制御線TRGLに接続されている。 The transfer transistor 22 has a gate electrode connected to the control line TRGL, a source electrode connected to the cathode electrode of the photoelectric conversion unit 21 , and a drain electrode connected to the charge-voltage conversion unit 23 . Gate electrodes of ten transfer transistors 22 are connected to different control lines TRGL among ten control lines TRGL (control lines TRGL1 to TRGL6 and TRGL9 to TRGL12 in this example).
 電荷電圧変換部23は、転送トランジスタ22のドレイン領域と、リセットトランジスタ24のソース領域との間に形成される浮遊拡散(FD:Floating Diffusion)領域の容量CFDである。この電荷電圧変換部23は、光電変換部21で光電変換され、当該光電変換部21から転送トランジスタ22によって転送された電荷を電圧に変換する。 The charge-voltage converter 23 is a capacitance CFD of a floating diffusion (FD) region formed between the drain region of the transfer transistor 22 and the source region of the reset transistor 24 . The charge-voltage conversion unit 23 converts the charge photoelectrically converted by the photoelectric conversion unit 21 and transferred from the photoelectric conversion unit 21 by the transfer transistor 22 into a voltage.
 リセットトランジスタ24は、ゲート電極が制御線RSTLに接続され、ソース電極が電荷電圧変換部23に接続されている。リセットトランジスタ24のドレイン電極には、電源電圧VDDが供給されている。リセットトランジスタ24は、駆動部12から制御線RSTLを通して与えられる制御信号にしたがって、電荷電圧変換部23に蓄積された電荷をリセットする。 The reset transistor 24 has a gate electrode connected to the control line RSTL and a source electrode connected to the charge-voltage converter 23 . A power supply voltage V DD is supplied to the drain electrode of the reset transistor 24 . The reset transistor 24 resets the charge accumulated in the charge-voltage conversion section 23 according to a control signal given from the drive section 12 through the control line RSTL.
 増幅トランジスタ25は、ゲート電極が電荷電圧変換部23に接続され、ソース電極が選択トランジスタ26のドレイン電極に接続されている。増幅トランジスタ25のドレイン電極には、電源電圧VDDが供給されている。増幅トランジスタ25は、光電変換部21における光電変換によって得られる電荷を読み出す回路、即ち、ソースフォロワ回路の入力部となる。つまり、増幅トランジスタ25は、ソース電極が選択トランジスタ26を介して信号線VSLに接続されることにより、信号線VSLの一端に接続されている、後述する定電流源I(図6参照)とソースフォロワ回路を構成する。 The amplification transistor 25 has a gate electrode connected to the charge-voltage converter 23 and a source electrode connected to the drain electrode of the selection transistor 26 . A power supply voltage V DD is supplied to the drain electrode of the amplification transistor 25 . The amplification transistor 25 serves as an input section of a circuit for reading out charges obtained by photoelectric conversion in the photoelectric conversion section 21, that is, a source follower circuit. That is, the amplification transistor 25 is connected to one end of the signal line VSL by connecting the source electrode to the signal line VSL through the selection transistor 26, and the constant current source I (see FIG. 6) and the source are connected to one end of the signal line VSL. Construct a follower circuit.
 選択トランジスタ26は、ゲート電極が制御線SELLに接続され、ドレイン電極が増幅トランジスタ25のソース電極に接続され、ソース電極が信号線VSLに接続されている。そして、選択トランジスタ26は、駆動部12による選択走査の下に、画素アレイ部11におけるいずれかの画素20を選択する。 The selection transistor 26 has a gate electrode connected to the control line SELL, a drain electrode connected to the source electrode of the amplification transistor 25, and a source electrode connected to the signal line VSL. Then, the selection transistor 26 selects one of the pixels 20 in the pixel array section 11 under selective scanning by the driving section 12 .
 上述した回路構成において、画素20では、転送トランジスタ22およびリセットトランジスタ24がオン状態になることにより、光電変換部21に蓄積されていた電荷が排出される。そして、転送トランジスタ22およびリセットトランジスタ24がオフ状態になることにより、露光期間が開始され、光電変換部21において光電変換が行われ、受光量に応じた量の電荷が蓄積される。 In the circuit configuration described above, in the pixel 20, the transfer transistor 22 and the reset transistor 24 are turned on, thereby discharging the charge accumulated in the photoelectric conversion section 21. Then, when the transfer transistor 22 and the reset transistor 24 are turned off, an exposure period is started, photoelectric conversion is performed in the photoelectric conversion section 21, and an amount of charge corresponding to the amount of received light is accumulated.
 露光期間が終了した後に、画素20は、リセット電圧Vresetおよび画素電圧Vpixを含む信号SIGを、信号線VSLに出力する。具体的には、まず、選択トランジスタ26がオン状態になることにより、画素20が信号線VSLと電気的に接続される。これにより、増幅トランジスタ25は、読出部13の入力部において信号線VSLの一端に接続された後述する定電流源I(図6参照)に電気的に接続され、ソースフォロワとして動作する。 After the exposure period ends, the pixel 20 outputs the signal SIG including the reset voltage Vreset and the pixel voltage Vpix to the signal line VSL. Specifically, first, the pixel 20 is electrically connected to the signal line VSL by turning on the selection transistor 26 . Thereby, the amplification transistor 25 is electrically connected to a constant current source I (see FIG. 6), which will be described later, connected to one end of the signal line VSL at the input portion of the readout portion 13, and operates as a source follower.
 そして、画素20は、後述するように、リセットトランジスタ24がオン状態になることにより、電荷電圧変換部23の電圧がリセットされた後のP相(Pre-charge相)期間において、そのときの電荷電圧変換部23の電圧をリセット電圧Vresetとして出力する。また、画素20は、転送トランジスタ22がオン状態になることにより、光電変換部21から電荷電圧変換部23へ電荷が転送された後のD相(Data相)期間において、そのときの電荷電圧変換部23の電圧を画素電圧Vpixとして出力する。画素電圧Vpixとリセット電圧Vresetとの差電圧は、露光期間における画素20の受光量に対応する。このようにして、画素20は、これらのリセット電圧Vresetおよび画素電圧Vpixを含む信号SIGを、信号線VSLに出力する。 Then, as will be described later, the pixel 20 is in the P phase (Pre-charge phase) period after the voltage of the charge-voltage converter 23 is reset by turning on the reset transistor 24, and the charge at that time is The voltage of the voltage converter 23 is output as the reset voltage Vreset. In addition, the transfer transistor 22 is turned on, so that the pixel 20 performs the charge-voltage conversion during the D phase (data phase) period after the charge is transferred from the photoelectric conversion unit 21 to the charge-voltage conversion unit 23 . The voltage of the section 23 is output as the pixel voltage Vpix. A difference voltage between the pixel voltage Vpix and the reset voltage Vreset corresponds to the amount of light received by the pixel 20 during the exposure period. Thus, the pixel 20 outputs the signal SIG including the reset voltage Vreset and pixel voltage Vpix to the signal line VSL.
 図5に示す赤色(R)の画素ブロック100Rは、8個の光電変換部21、および、8個の転送トランジスタ22を有している。画素ブロック100Rは、さらに、電荷電圧変換部23、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26を1個ずつ有している。 A red (R) pixel block 100 R shown in FIG. 5 has eight photoelectric conversion units 21 and eight transfer transistors 22 . The pixel block 100R further has one charge-voltage converter 23, one reset transistor 24, one amplifier transistor 25, and one selection transistor 26. FIG.
 ここで、転送トランジスタ22、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26としては、例えば、N型MOS型電界効果トランジスタを用いることができる。ただし、ここで例示した転送トランジスタ22、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26の導電型の組み合わせは一例に過ぎず、これらの組み合わせに限られるものではない。 Here, as the transfer transistor 22, the reset transistor 24, the amplification transistor 25, and the selection transistor 26, for example, an N-type MOS field effect transistor can be used. However, the combination of the conductivity types of the transfer transistor 22, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 illustrated here is merely an example, and the combination is not limited to these combinations.
 8個の光電変換部21および8個の転送トランジスタ22は、画素ブロック100Rに含まれる8個の画素20Rにそれぞれ対応している。そして、画素ブロック100Rは、電荷電圧変換部23、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26を、10個の画素20R間で共有する画素回路の構成となっている。8個の転送トランジスタ22のゲート電極は、8本の制御線TRGL(この例では、制御線TRGL1,TRGL2,TRGL5~TRGL10)のうちの互いに異なる制御線TRGLに接続されている。 The eight photoelectric conversion units 21 and the eight transfer transistors 22 respectively correspond to the eight pixels 20R included in the pixel block 100R. The pixel block 100R has a pixel circuit configuration in which the charge-voltage converter 23, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 are shared among the ten pixels 20R. The gate electrodes of the eight transfer transistors 22 are connected to different control lines TRGL among the eight control lines TRGL (control lines TRGL1, TRGL2, TRGL5 to TRGL10 in this example).
 また、図示を省略するが、画素ブロック100Gbは、図4に図示した画素ブロック100Grと同様に、10個の光電変換部21、および、10個の転送トランジスタ22を有している。10個の光電変換部21、および、10個の転送トランジスタ22は、画素ブロック100Gbに含まれる10個の画素20Gbにそれぞれ対応している。転送トランジスタ22のゲート電極は、10本の制御線TRGLのうちの互いに異なる制御線TRGLに接続されている。 Although not shown, the pixel block 100Gb has 10 photoelectric conversion units 21 and 10 transfer transistors 22, like the pixel block 100Gr shown in FIG. Ten photoelectric conversion units 21 and ten transfer transistors 22 respectively correspond to ten pixels 20Gb included in the pixel block 100Gb. A gate electrode of the transfer transistor 22 is connected to different control lines TRGL among the ten control lines TRGL.
 画素ブロック100Gbは、さらに、電荷電圧変換部23、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26を1個ずつ有している。そして、画素ブロック100Gbは、電荷電圧変換部23、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26を、10個の画素20Gb間で共有する画素回路の構成となっている。 The pixel block 100Gb further has one charge-voltage converter 23, one reset transistor 24, one amplifier transistor 25, and one selection transistor 26. The pixel block 100Gb has a pixel circuit configuration in which the charge-voltage converter 23, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 are shared among the ten pixels 20Gb.
 また、画素ブロック100Bは、図5に図示した画素ブロック100Rと同様に、8個の光電変換部21、および、8個の転送トランジスタ22を有している。8個の光電変換部21、および、8個の転送トランジスタ22は、画素ブロック100Bに含まれる8個の画素20Bにそれぞれ対応している。転送トランジスタ22のゲート電極は、8本の制御線TRGLのうちの互いに異なる制御線TRGLに接続されている。 Also, the pixel block 100B has eight photoelectric conversion units 21 and eight transfer transistors 22, like the pixel block 100R shown in FIG. The eight photoelectric conversion units 21 and the eight transfer transistors 22 respectively correspond to the eight pixels 20B included in the pixel block 100B. A gate electrode of the transfer transistor 22 is connected to different control lines TRGL among the eight control lines TRGL.
 画素ブロック100Bは、さらに、電荷電圧変換部23、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26を1個ずつ有している。そして、画素ブロック100Bは、電荷電圧変換部23、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26を、8個の画素20B間で共有する画素回路の構成となっている。 The pixel block 100B further has one charge-voltage converter 23, one reset transistor 24, one amplifier transistor 25, and one selection transistor 26. The pixel block 100B has a pixel circuit configuration in which the charge-voltage converter 23, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 are shared among the eight pixels 20B.
[読出部の構成例]
 続いて、読出部13の構成例について説明する。図6は、第1の実施の形態における撮像素子1の読出部13の構成の一例を示すブロック図である。なお、図6には、読出部13に加えて、参照信号生成部14、信号処理部15、および、撮像制御部17についても図示している。
[Configuration example of reading unit]
Next, a configuration example of the reading unit 13 will be described. FIG. 6 is a block diagram showing an example of the configuration of the reading section 13 of the imaging device 1 according to the first embodiment. In addition to the reading unit 13, FIG. 6 also shows the reference signal generating unit 14, the signal processing unit 15, and the imaging control unit 17.
 読出部13には、画素アレイ部11の各画素20から、複数の信号線VSLを介して読み出される、画素電圧Vpixを含む信号SIGが入力される。なお、読出部13の入力部における複数の信号線VSLのそれぞれには、定電流源Iが接続されている。定電流源Iは、その一端が、対応する信号線VSLに接続され、他端が接地されており、対応する信号線VSLに所定の電流を流す作用をなす。 A signal SIG including a pixel voltage Vpix read from each pixel 20 of the pixel array section 11 via a plurality of signal lines VSL is input to the reading section 13 . A constant current source I is connected to each of the plurality of signal lines VSL in the input section of the reading section 13 . The constant current source I has one end connected to the corresponding signal line VSL and the other end grounded, and acts to supply a predetermined current to the corresponding signal line VSL.
 読出部13は、複数のアナログ-デジタル変換部31および転送制御部32を有している。複数のアナログ-デジタル変換部31は、それぞれ、複数の信号線VSLに対応して設けられており、対応する信号線VSLにおける信号SIGに対してアナログ-デジタル変換を行う。以下に、ある1つの信号線VSLに対応するアナログ-デジタル変換部31について説明する。 The reading unit 13 has a plurality of analog-digital conversion units 31 and transfer control units 32 . A plurality of analog-to-digital converters 31 are provided corresponding to the plurality of signal lines VSL, respectively, and perform analog-to-digital conversion on the signal SIG on the corresponding signal line VSL. The analog-digital converter 31 corresponding to one signal line VSL will be described below.
 アナログ-デジタル変換部31は、容量素子311,312、比較回路313、カウンタ314、および、ラッチ回路315を有する構成となっている。 The analog-digital conversion section 31 is configured to have capacitive elements 311 and 312, a comparison circuit 313, a counter 314, and a latch circuit 315.
 容量素子311は、一端が信号線VSLに接続され、他端が比較回路313の一方の入力端に接続されている。容量素子311には、画素アレイ部11の各画素20から信号線VSLを通して画素電圧Vpixを含む信号SIGが供給される。 The capacitive element 311 has one end connected to the signal line VSL and the other end connected to one input end of the comparison circuit 313 . A signal SIG including the pixel voltage Vpix is supplied from each pixel 20 of the pixel array section 11 to the capacitive element 311 through the signal line VSL.
 容量素子312は、一端が参照信号RAMPを伝送する信号線33に接続され、他端が比較回路313の他方の入力端に接続されている。容量素子312には、参照信号生成部14から信号線33を通して参照信号RAMPが供給される。 The capacitive element 312 has one end connected to the signal line 33 that transmits the reference signal RAMP, and the other end connected to the other input end of the comparison circuit 313 . A reference signal RAMP is supplied from the reference signal generator 14 to the capacitive element 312 through the signal line 33 .
 比較回路313は、画素アレイ部11の各画素20から信号線VSLおよび容量素子311を介して供給される信号SIGと、参照信号生成部13から信号線33および容量素子312を介して供給される参照信号RAMPとを比較し、その比較結果として信号Vcpを出力する。 The comparison circuit 313 is supplied with a signal SIG supplied from each pixel 20 of the pixel array section 11 via the signal line VSL and the capacitive element 311, and supplied from the reference signal generation section 13 via the signal line 33 and the capacitive element 312. It compares with the reference signal RAMP and outputs the signal Vcp as a result of the comparison.
 比較回路313は、撮像制御部17から信号線34を通して供給される制御信号AZに基づいて、容量素子311,312の電圧を設定することによって動作点を設定する。そして、動作点を設定した後に、比較回路313は、P相期間において、信号SIGに含まれるリセット電圧Vresetと、参照信号RAMPの電圧とを比較する比較動作を行う。また、比較回路313は、D相期間において、信号SIGに含まれる画素電圧Vpixと、参照信号RAMPの電圧とを比較する比較動作を行う。 The comparison circuit 313 sets the operating point by setting the voltages of the capacitive elements 311 and 312 based on the control signal AZ supplied from the imaging control section 17 through the signal line 34 . After setting the operating point, the comparison circuit 313 performs a comparison operation of comparing the reset voltage Vreset included in the signal SIG and the voltage of the reference signal RAMP in the P-phase period. Also, the comparison circuit 313 performs a comparison operation of comparing the pixel voltage Vpix included in the signal SIG with the voltage of the reference signal RAMP during the D-phase period.
 カウンタ314は、比較回路313から供給された信号Vcpに基づいて、撮像制御部17から供給されるクロック信号CLKのパルスをカウントするカウント動作を行う構成となっている。具体的には、カウンタ314は、P相期間において、比較回路313から出力される信号Vcpが遷移するまでクロック信号CLKのパルスをカウントすることによりカウント値CNTPを生成し、このカウント値CNTPを、複数のビットを有するデジタルコードとして出力する。また、カウンタ314は、D相期間において、比較回路313から出力される信号Vcpが遷移するまでクロック信号CLKのパルスをカウントすることによりカウント値CNTDを生成し、このカウント値CNTDを、複数のビットを有するデジタルコードとして出力する。 The counter 314 is configured to count pulses of the clock signal CLK supplied from the imaging control unit 17 based on the signal Vcp supplied from the comparison circuit 313 . Specifically, the counter 314 generates the count value CNTP by counting the pulses of the clock signal CLK until the signal Vcp output from the comparison circuit 313 transitions during the P-phase period. Output as a digital code with multiple bits. Further, the counter 314 generates a count value CNTD by counting the pulses of the clock signal CLK until the signal Vcp output from the comparison circuit 313 transitions during the D-phase period, and converts the count value CNTD into a plurality of bits. output as a digital code having
 ラッチ回路315は、カウンタ314から供給されたデジタルコードを一時的に保持するとともに、転送制御部32からの指示に基づいて、そのデジタルコードをバス配線35に出力する。 The latch circuit 315 temporarily holds the digital code supplied from the counter 314 and outputs the digital code to the bus wiring 35 based on the instruction from the transfer control section 32 .
 転送制御部32は、撮像制御部17から供給された制御信号CTLに基づいて、複数のアナログ-デジタル変換部31のラッチ回路315が、デジタルコードをバス配線35に順次出力させるように制御する。読出部13は、このバス配線35を用いて、複数のアナログ-デジタル変換部31から出力される複数のデジタルコードを、画像信号Spic0として、信号処理部15に順次転送するようになっている。 The transfer control unit 32 controls the latch circuits 315 of the plurality of analog-digital conversion units 31 to sequentially output the digital code to the bus wiring 35 based on the control signal CTL supplied from the imaging control unit 17 . The reading unit 13 uses the bus wiring 35 to sequentially transfer the plurality of digital codes output from the plurality of analog-digital conversion units 31 to the signal processing unit 15 as the image signal Spic0.
 信号処理部15は、撮像制御部17による制御の下に、読出部13から供給される画像信号Spic0に対して所定の信号処理を行うことにより、画像データDPおよび位相差データDFを含む画像信号Spicとして出力する。具体的には、信号処理部15は、図7に示すように、複数行分の画素20に係る位相差データDFを交互に配置することによって画像信号Spicを生成して出力する。 Under the control of the imaging control unit 17, the signal processing unit 15 performs predetermined signal processing on the image signal Spic0 supplied from the reading unit 13 to generate an image signal including the image data DP and the phase difference data DF. Output as Spic. Specifically, as shown in FIG. 7, the signal processing unit 15 generates and outputs the image signal Spic by alternately arranging the phase difference data DF related to the pixels 20 in a plurality of rows.
[半導体チップ構造]
 上述の構成の撮像素子1の半導体チップ構造としては、所謂、平置型の半導体チップ構造と、所謂、積層型の半導体チップ構造とを例示することができる。また、画素構造については、配線層が形成される側の基板面を表面(正面)とするとき、その反対側の裏面側から照射される光を取り込む裏面照射型の画素構造とすることもできるし、表面側から照射される光を取り込む表面照射型の画素構造とすることもできる。
[Semiconductor chip structure]
Examples of the semiconductor chip structure of the imaging device 1 having the above-described configuration include a so-called parallel-type semiconductor chip structure and a so-called stacked-type semiconductor chip structure. In addition, regarding the pixel structure, when the substrate surface on which the wiring layer is formed is defined as the front surface (front surface), it is also possible to adopt a back-illuminated pixel structure in which light emitted from the back surface on the opposite side is taken in. Alternatively, a surface-illuminated pixel structure that captures light emitted from the surface side may be employed.
 以下に、平置型の半導体チップ構造および積層型の半導体チップ構造の概略について説明する。 The outline of the parallel-type semiconductor chip structure and the stacked-type semiconductor chip structure will be described below.
(平置型の半導体チップ構造)
 図8におけるaは、撮像素子1の平置型のチップ構造を模式的に示す斜視図である。平置型の半導体チップ構造は、画素20が行列状に配置されてなる画素アレイ部11と同じ半導体基板(半導体チップ)41上に、画素アレイ部11の周辺回路部の各構成要素を形成した構造となっている。具体的には、画素アレイ部11と同じ半導体基板41上に、駆動部12、読出部13、参照信号生成部14、信号処理部15、および、撮像制御部17等が形成されている。半導体基板41の例えば左右両端部には、外部接続用や電源用のパッド42が設けられている。
(Horizontal type semiconductor chip structure)
A in FIG. 8 is a perspective view schematically showing a flat-type chip structure of the imaging device 1 . In the parallel-type semiconductor chip structure, each component of the peripheral circuit section of the pixel array section 11 is formed on the same semiconductor substrate (semiconductor chip) 41 as the pixel array section 11 in which the pixels 20 are arranged in a matrix. It has become. Specifically, on the same semiconductor substrate 41 as the pixel array section 11, the driving section 12, the reading section 13, the reference signal generating section 14, the signal processing section 15, the imaging control section 17, and the like are formed. Pads 42 for external connection and power supply are provided, for example, at both left and right ends of the semiconductor substrate 41 .
(積層型の半導体チップ構造)
 図8におけるbは、撮像素子1の積層型の半導体チップ構造を模式的に示す分解斜視図である。積層型の半導体チップ構造は、1層目の半導体基板43および2層目の半導体基板44の少なくとも2つの半導体基板が積層された構造となっている。
(Stacked semiconductor chip structure)
b in FIG. 8 is an exploded perspective view schematically showing the laminated semiconductor chip structure of the imaging device 1 . The laminated semiconductor chip structure has a structure in which at least two semiconductor substrates, ie, a first-layer semiconductor substrate 43 and a second-layer semiconductor substrate 44 are laminated.
 この積層型の半導体チップ構造において、1層目の半導体基板43は、画素20が行列状に2次元配置された画素アレイ部11が形成された画素チップである。1層目の半導体基板43の例えば左右両端部には、外部接続用や電源用のパッド42が設けられている。 In this stacked semiconductor chip structure, the semiconductor substrate 43 of the first layer is a pixel chip in which the pixel array section 11 in which the pixels 20 are two-dimensionally arranged in a matrix is formed. Pads 42 for external connection and power supply are provided, for example, at both left and right ends of the semiconductor substrate 43 of the first layer.
 2層目の半導体基板44は、画素アレイ部11の周辺回路部、即ち、駆動部12、読出部13、参照信号生成部14、信号処理部15、および、撮像制御部17等が形成された回路チップである。なお、駆動部12、読出部13、参照信号生成部14、信号処理部15、および、撮像制御部17等の配置については、一例であって、この配置例に限られるものではない。 The semiconductor substrate 44 of the second layer is formed with the peripheral circuit portion of the pixel array portion 11, that is, the driving portion 12, the reading portion 13, the reference signal generating portion 14, the signal processing portion 15, the imaging control portion 17, and the like. A circuit chip. Note that the arrangement of the driving section 12, the reading section 13, the reference signal generating section 14, the signal processing section 15, the imaging control section 17, etc. is an example, and is not limited to this arrangement example.
 1層目の半導体基板43上の画素アレイ部11と、2層目の半導体基板44上の周辺回路部とは、Cu-Cu接合を含む金属-金属接合、シリコン貫通電極(Through Silicon Via:TSV)、マイクロバンプなどから成る接合部45,46を介して電気的に接続される。 The pixel array portion 11 on the semiconductor substrate 43 of the first layer and the peripheral circuit portion on the semiconductor substrate 44 of the second layer are metal-metal junctions including Cu--Cu junctions, Through Silicon Via (TSV) ), and are electrically connected via bonding portions 45 and 46 composed of microbumps or the like.
 上述した積層型の半導体チップ構造によれば、1層目の半導体基板43には画素アレイ部11の作製に適したプロセスを適用でき、2層目の半導体基板44には回路部分の作製に適したプロセスを適用できる。これにより、撮像素子1の製造に当たって、プロセスの最適化を図ることができる。特に、回路部分の作製に当たっては、先端プロセスの適用が可能になるとともに、回路規模を拡大することもできる、というメリットがある。 According to the stacked semiconductor chip structure described above, a process suitable for manufacturing the pixel array section 11 can be applied to the semiconductor substrate 43 of the first layer, and a process suitable for manufacturing the circuit portion can be applied to the semiconductor substrate 44 of the second layer. process can be applied. As a result, the process can be optimized in manufacturing the imaging device 1 . In particular, when fabricating the circuit portion, there is an advantage that it is possible to apply advanced processes and to expand the scale of the circuit.
[画素ブロックおよび画素ペアについて]
 以上説明したように、第1の実施の形態における撮像素子1では、それぞれが、互いに同じ色のカラーフィルタを含む複数の画素20を有する画素ブロック100を複数設けている。画素ブロック100内の複数の画素20は、それぞれが2つの画素20を含む複数の画素ペア90に区分されている。そして、これらの複数の画素ペア90に対応する位置に複数のレンズ101をそれぞれ設けている。
[About pixel blocks and pixel pairs]
As described above, the image sensor 1 according to the first embodiment includes a plurality of pixel blocks 100 each having a plurality of pixels 20 including color filters of the same color. A plurality of pixels 20 in pixel block 100 are partitioned into a plurality of pixel pairs 90 each including two pixels 20 . A plurality of lenses 101 are provided at positions corresponding to the plurality of pixel pairs 90 .
 上述の構成により、第1の実施の形態における撮像素子1では、画素アレイ部11の全面に亘って、高い解像度で位相差データDFを生成することができる。したがって、このような撮像素子1が搭載されたデジタルスチルカメラなどの撮像機能を備えた電子機器では、精度が高いオートフォーカスを実現することができる。その結果、撮像素子1では、画質を高めることができるため、より見やすい撮像画像を得ることができる。 With the configuration described above, the imaging element 1 according to the first embodiment can generate the phase difference data DF with high resolution over the entire surface of the pixel array section 11 . Therefore, in an electronic device having an imaging function such as a digital still camera equipped with such an imaging device 1, highly accurate autofocus can be realized. As a result, the imaging device 1 can improve the image quality, so that a more legible captured image can be obtained.
 また、撮像素子1では、ある画素ブロック100における画素数を、他のある画素ブロック100における画素数よりも多く設定している。具体的には、第1の実施の形態の例では、画素ブロック100Grにおける画素20Grの数、および、画素ブロック100Gbにおける画素20Gbの数を、画素ブロック100Rにおける画素20Rの数、および、画素ブロック100Bにおける画素20Bの数よりも多く設定している。これにより、例えば、画素数が多い緑色の受光感度を高めることができるため、撮像画像の画質を高めることができ、より見やすい撮像画像を得ることができる。 Also, in the image sensor 1, the number of pixels in a certain pixel block 100 is set to be larger than the number of pixels in another certain pixel block 100. Specifically, in the example of the first embodiment, the number of pixels 20Gr in the pixel block 100Gr, the number of pixels 20Gb in the pixel block 100Gb, the number of pixels 20R in the pixel block 100R, and the number of pixels 20G in the pixel block 100B is set larger than the number of pixels 20B in . As a result, for example, it is possible to increase the light receiving sensitivity of green, which has a large number of pixels, so that the image quality of the captured image can be improved, and a more legible captured image can be obtained.
 また、第1の実施の形態における撮像素子1によれば、撮像画像の高画質化に伴って画素サイズの微細化が図られたとしても、位相差検出画素、即ち、画素ペア90の2つの画素20の基本の構成を維持しつつ、デジタルスチルカメラなどの撮像機能を備えた電子機器における高精度のオートフォーカスの実現に寄与することができる。 Further, according to the image sensor 1 in the first embodiment, even if the pixel size is reduced as the quality of the captured image is improved, the two phase difference detection pixels, that is, the pixel pairs 90 While maintaining the basic configuration of the pixel 20, it is possible to contribute to the realization of high-precision autofocus in an electronic device having an imaging function such as a digital still camera.
[撮像素子の駆動モードについて]
 第1の実施の形態における撮像素子1は、電荷電圧変換部23以降の画素構成素子、即ち、リセットトランジスタ24、増幅トランジスタ25、および、選択トランジスタ26を、複数の画素20間で共有する画素回路の構成となっている(図4、図5参照)。この画素共有の画素回路を有する撮像素子1では、駆動モードとして、例えば、第1の駆動モード、第2の駆動モード、および、第3の駆動モードの3つの駆動モードを設定可能な構成となっている。
[About the drive mode of the image sensor]
The image pickup device 1 according to the first embodiment is a pixel circuit in which a plurality of pixels 20 share the pixel constituent elements after the charge-voltage converter 23, that is, the reset transistor 24, the amplification transistor 25, and the selection transistor 26. (see FIGS. 4 and 5). The image sensor 1 having the pixel-sharing pixel circuit has a configuration in which three drive modes, for example, a first drive mode, a second drive mode, and a third drive mode, can be set as drive modes. ing.
 第1のモードは、電荷電圧変換部23以降の画素構成素子を共有する複数の画素20間で加算(画素加算)を行わずに、個々に読み出す全画素読出しモードである。第2の駆動モードは、画素ペア90の対となる2つの画素20間で加算を行って位相差データDFを生成するAF(オートフォーカス)モードである。第3の駆動モードは、電荷電圧変換部23以降の画素構成素子を共有する全画素20間で加算(画素加算)を行って読み出す全画素加算モードである。 The first mode is an all-pixel readout mode in which a plurality of pixels 20 sharing pixel constituent elements after the charge-voltage converter 23 are read out individually without addition (pixel addition). The second drive mode is an AF (autofocus) mode in which addition is performed between two pixels 20 forming a pair of pixel pairs 90 to generate phase difference data DF. A third drive mode is an all-pixel addition mode in which addition (pixel addition) is performed among all pixels 20 that share the pixel constituent elements after the charge-voltage converter 23 and readout is performed.
[色別の出力信号量の差分について]
 ところで、電荷電圧変換部23以降の画素構成素子を共有する構成の画素回路を有する撮像素子1では、図4や図5の場合のように、共有する画素数が異なると、電荷電圧変換部23に電気的に繋がる転送トランジスタ22の数が異なることになる。その結果、電荷電圧変換部23ごとで、電荷電圧変換部23の変換効率や全画素加算モード時の取り扱い電荷量が異なることになるため、アナログ-デジタル変換部31によるアナログ-デジタル変換後の色別の出力信号量に差分が生じ、露光時間に比例した出力信号量を得ることができないことになる。
[Regarding the difference in output signal level for each color]
By the way, in the imaging device 1 having a pixel circuit configured to share the pixel constituent elements after the charge-voltage converter 23, if the number of pixels to be shared is different as in the cases of FIGS. 4 and 5, the charge-voltage converter 23 The number of transfer transistors 22 electrically connected to . As a result, since the conversion efficiency of the charge-voltage converter 23 and the amount of charge handled in the all-pixel addition mode differ for each charge-voltage converter 23, the color after analog-to-digital conversion by the analog-to-digital converter 31 is different. A difference occurs in another output signal amount, and an output signal amount proportional to the exposure time cannot be obtained.
 電荷電圧変換部23の変換効率ηは、η=1/Cで与えられる。ここで、Cは、浮遊拡散領域(FD領域)の容量CFDを含む電荷電圧変換部23の容量である。緑色(Gr,Gb)の画素ブロック100Gr,100Gbの場合、赤色(R)の画素ブロック100Rおよび青色(B)の画素ブロック100Rよりも電荷電圧変換部23以降の画素構成素子を共有する画素数が多いために、電荷電圧変換部23に電気的に繋がる転送トランジスタ22の数が多くなる。 The conversion efficiency η of the charge-voltage converter 23 is given by η=1/C. Here, C is the capacitance of the charge-voltage converter 23 including the capacitance CFD of the floating diffusion region (FD region). In the case of the green (Gr, Gb) pixel blocks 100Gr and 100Gb, the number of pixels sharing the pixel constituent elements after the charge-voltage converter 23 is larger than the red (R) pixel block 100R and the blue (B) pixel block 100R. Therefore, the number of transfer transistors 22 electrically connected to the charge-voltage converter 23 is increased.
 電荷電圧変換部23に電気的に繋がる転送トランジスタ22の数が多くなると、電荷電圧変換部23の容量Cが大きくなるために、相対的に画素数が多い画素ブロック100Gr/Gbの変換効率の方が、相対的に画素数が少ない画素ブロック100R/Bの変換効率よりも小さくなる。また、画素ブロック100Gr/Gbと画素ブロック100R/Bとで、配線レイアウト(引き回し)が異なるために、その分だけ変換効率に差が生じる。さらに、加算を行う画素数が異なる駆動モードにおいて、電荷電圧変換部23で取り扱う電子数が色ごとで異なる。 As the number of transfer transistors 22 electrically connected to the charge-voltage converter 23 increases, the capacitance C of the charge-voltage converter 23 increases. is smaller than the conversion efficiency of the pixel block 100R/B having a relatively small number of pixels. In addition, since the pixel block 100Gr/Gb and the pixel block 100R/B have different wiring layouts (routing), a corresponding difference in conversion efficiency occurs. Furthermore, in drive modes in which the number of pixels to be added differs, the number of electrons handled by the charge-voltage converter 23 differs for each color.
[デジタルゲイン補正について]
 第1の実施の形態における撮像素子1では、全画素読出しモード、AFモード、および、全画素加算モードの各駆動モードにおいて、露光時間に比例した出力信号量を得ることを目的として、色別の出力信号量の差分を吸収する制御を行う。より具体的には、第1の実施の形態では、色別の出力信号量の差分を吸収する制御を、アナログ-デジタル変換部31によるアナログ-デジタル変換後のデジタル領域において、デジタルゲイン補正処理によって行うようにする。以下に、色別の出力信号量の差分を吸収するためのデジタルゲイン補正処理の具体例について説明する。
[About digital gain correction]
In the image sensor 1 according to the first embodiment, in each of the drive modes of the all-pixel readout mode, the AF mode, and the all-pixel addition mode, for the purpose of obtaining an output signal amount proportional to the exposure time, Control is performed to absorb the difference in output signal amount. More specifically, in the first embodiment, in the digital domain after the analog-to-digital conversion by the analog-to-digital converter 31, control to absorb the difference in the output signal amount for each color is performed by digital gain correction processing. to do. A specific example of the digital gain correction process for absorbing the difference in output signal amount for each color will be described below.
 色別の出力信号量の差分を吸収するための補正処理、即ち、デジタルゲイン補正処理を行うに当たっては、色別の出力信号量を取得する必要がある。この色別の出力信号量の取得は、撮像素子1の出荷前の調整段階において、外部の計測装置(図示を省略)を用いて行われる。具体的には、駆動モードごとの画素加算数、および、電荷電圧変換部23の使用する変換効率より、色別の出力信号量を取得する。このようにして予め取得された色別の出力信号量の情報は、図1に示す記憶部16に記憶されて出荷されることになる。  In order to perform correction processing for absorbing the difference in the output signal amount for each color, that is, digital gain correction processing, it is necessary to acquire the output signal amount for each color. Acquisition of the output signal amount for each color is performed using an external measuring device (not shown) in the adjustment stage before shipment of the imaging device 1 . Specifically, the output signal amount for each color is obtained from the pixel addition number for each drive mode and the conversion efficiency used by the charge-voltage converter 23 . The information of the output signal amount for each color obtained in advance in this manner is stored in the storage unit 16 shown in FIG. 1 and shipped.
 ここで、色別の出力信号量の差分について説明する。上述したように、相対的に画素数が多い画素ブロック100Gr/Gbの変換効率の方が、相対的に画素数が少ない画素ブロック100R/Bの変換効率よりも小さい。したがって、画素加算を行わずに、個々に読み出す全画素読出しモード、および、画素ペア90の対となる2つの画素20間で加算を行うAFモードの場合は、図10におけるaに示すように、R,B出力信号量の方がG(Gr,Gb)の出力信号量よりも多くなり、両者に出力信号量の差分が生じる。 Here, the difference in output signal amount for each color will be explained. As described above, the conversion efficiency of the pixel block 100Gr/Gb with a relatively large number of pixels is lower than the conversion efficiency of the pixel block 100R/B with a relatively small number of pixels. Therefore, in the case of the all-pixel readout mode in which pixels are read out individually without performing pixel addition, and the AF mode in which two pixels 20 forming a pair of pixels 90 are added together, as shown in a in FIG. The R and B output signal amounts are greater than the G (Gr, Gb) output signal amount, and a difference in output signal amount occurs between the two.
 一方、全画素20間で加算を行う全画素加算モードの場合には、加算する画素数が相対的に多い画素ブロック100Gr/Gbの方が、全画素加算によって電荷電圧変換部23で取り扱う電子数が多くなる。したがって、図11におけるaに示すように、G(Gr,Gb)の出力信号量の方がR,Bの出力信号量よりも多くなり、両者に出力信号量の差分が生じる。 On the other hand, in the case of the all-pixel addition mode in which addition is performed between all pixels 20, the pixel block 100Gr/Gb having a relatively large number of pixels to be added has the number of electrons handled by the charge-voltage converter 23 by all-pixel addition. will increase. Therefore, as shown by a in FIG. 11, the output signal amount of G (Gr, Gb) is larger than the output signal amount of R and B, and a difference in output signal amount is generated between them.
 図9は、第1の実施の形態における撮像素子1の信号量調整部50の一構成例を示すブロック図である。なお、図9には、信号量調整部50に加えて、読出部13、信号処理部15、および、記憶部16についても図示している。 FIG. 9 is a block diagram showing a configuration example of the signal amount adjustment section 50 of the imaging device 1 according to the first embodiment. In addition to the signal amount adjusting section 50, FIG. 9 also shows the reading section 13, the signal processing section 15, and the storage section 16. FIG.
 図1および図6では図示を省略しているが、通常、信号処理部15の前段には、データ受け取り&並べ替え部18が設けられている。データ受け取り&並べ替え部18は、信号処理部15から順に出力されるアナログ-デジタル変換後の画素データを受け取り、当該画素データを、画素ブロック100R、画素ブロック100Gr、画素ブロック100Gb、および、画素ブロック100BのRGBベイヤー配列に対応した画素配列に並べ替える処理を行う。 Although not shown in FIGS. 1 and 6, a data receiving and rearranging section 18 is normally provided in the preceding stage of the signal processing section 15. FIG. The data receiving and rearranging unit 18 receives analog-to-digital converted pixel data sequentially output from the signal processing unit 15, and divides the pixel data into a pixel block 100R, a pixel block 100Gr, a pixel block 100Gb, and a pixel block. A process of rearranging the pixels into a pixel array corresponding to the 100B RGB Bayer array is performed.
 信号量調整部50は、色別デジタルゲイン補正処理部51を有しており、当該色別デジタルゲイン補正処理部51による補正処理の下に、出荷前段階において予め取得され、記憶部16に記憶されている色別の出力信号量の情報に基づいて、色別の出力信号量の差分を吸収するための補正処理を行う。具体的には、色別デジタルゲイン補正処理部51は、データ受け取り&並べ替え部18において、例えば、並べ替え処理後の所定の色の画素の信号量を、色別の出力信号量を一致させ得るゲインによって調整することにより、色別の出力信号量の差分を吸収するゲイン調整を行う。ここで、「一致する」とは、厳密に一致する場合の他、実質的に一致する場合も含む意味であり、設計上あるいは製造上生ずる種々のばらつきの存在は許容される。 The signal amount adjustment unit 50 has a color-by-color digital gain correction processing unit 51. Under the correction processing by the color-by-color digital gain correction processing unit 51, the signal is acquired in advance at the stage before shipment and stored in the storage unit 16. Correction processing for absorbing the difference in the output signal amount for each color is performed based on the information on the output signal amount for each color. Specifically, the color-by-color digital gain correction processing unit 51 causes the data reception and rearrangement unit 18 to match the signal amounts of the pixels of a predetermined color after the rearrangement process with the output signal amounts of the respective colors. By adjusting the obtained gain, gain adjustment is performed to absorb the difference in output signal amount for each color. Here, "matching" means not only strictly matching but also substantially matching, and various variations caused by design or manufacturing are allowed.
 以下に、色別の出力信号量の差分を吸収するための色別デジタルゲイン補正処理について、より具体的に説明する。 The color-specific digital gain correction processing for absorbing the difference in the output signal amount for each color will be described in more detail below.
(全画素読出しモード/AFモードの場合)
 図10におけるaに示すように、画素ブロック100(100R,100Gr,Gb,100B)の各画素20の信号を個々に読み出す全画素読出しモード、および、画素ペア90の対となる2つの画素20の信号を加算して読み出すAFモードの場合、R,Bの出力信号量の方が、G(Gr,Gb)の出力信号量よりも多くなる。このように、色別の出力信号量に差分が生じるのは、先述したように、電荷電圧変換部23の変換効率に色別に違いが生じるからである。この出力信号量の差分の情報については、予め取得され、記憶部16に記憶されている。
(For all pixel readout mode/AF mode)
As shown in a in FIG. 10, there is an all-pixel readout mode for individually reading the signals of the pixels 20 of the pixel block 100 (100R, 100Gr, Gb, 100B), and two pixels 20 forming a pixel pair 90. In the AF mode in which signals are added and read out, the output signal amount of R and B is larger than the output signal amount of G (Gr, Gb). The reason why there is a difference in the output signal amount for each color is that the conversion efficiency of the charge-voltage converter 23 is different for each color, as described above. Information about the difference in output signal amount is acquired in advance and stored in the storage unit 16 .
 この全画素読出しモード/AFモードのケースでは、信号量調整部50の色別デジタルゲイン補正処理部51は、例えば、撮像素子1の立ち上げの初期段階で、記憶部16に記憶されている出力信号量の差分の情報に基づいて、図10におけるbに示すように、相対的に多い方のR,Bの出力信号量に対して、相対的に少ない方のG(Gr,Gb)の出力信号量を増加させて一致させるように、デジタルゲイン補正によって出力信号量の調整を行う。すなわち、このデジタルゲイン補正では、変換効率の差分をG(Gr,Gb)の出力信号量にゲイン倍する補正が行われる。 In the case of this all-pixel readout mode/AF mode, the color-by-color digital gain correction processing unit 51 of the signal amount adjustment unit 50, for example, at the initial stage of startup of the imaging device 1, outputs the output stored in the storage unit 16. Based on the information of the signal amount difference, as shown in b in FIG. The output signal amount is adjusted by digital gain correction so that the signal amount is increased and matched. That is, in this digital gain correction, correction is performed by multiplying the difference in conversion efficiency by the gain of the output signal amount of G(Gr, Gb).
 この色別デジタルゲイン補正処理による出力信号量の調整により、全画素読出しモードおよびAFモードの場合における、R,Bの出力信号量とG(Gr,Gb)の出力信号量との差分を吸収し、両者を一致させることができる。その結果、画素ブロック100(100R,100Gr,Gb,100B)の各画素20について、露光時間に比例した出力信号量を得ることができるため、より見やすい撮影画像を得ることができる。 The adjustment of the output signal amount by this color-by-color digital gain correction process absorbs the difference between the output signal amount of R, B and the output signal amount of G (Gr, Gb) in the case of all pixel readout mode and AF mode. , both can be matched. As a result, an output signal amount proportional to the exposure time can be obtained for each pixel 20 of the pixel block 100 (100R, 100Gr, Gb, 100B), so that a more legible photographed image can be obtained.
(全画素加算モードの場合)
 図11におけるaに示すように、画素ブロック100(100R,100Gr,Gb,100B)の全画素20の信号を加算して読み出す全画素加算モードの場合には、G(Gr,Gb)の出力信号量の方が、R,Bの出力信号量よりも多くなる。このように、色別の出力信号量に差分が生じるのは、主に、全画素加算によって電荷電圧変換部23で取り扱う電子数が多くなるからである。この出力信号量の差分の情報については、予め取得され、記憶部16に記憶されている。
(For all pixel addition mode)
As shown by a in FIG. 11, in the case of the all-pixel addition mode in which the signals of all the pixels 20 of the pixel block 100 (100R, 100Gr, Gb, 100B) are added and read out, the output signal of G (Gr, Gb) is is greater than the R and B output signal amounts. The reason why the output signal amount of each color differs in this way is mainly because the number of electrons handled by the charge-voltage converter 23 increases due to the addition of all pixels. Information about the difference in output signal amount is acquired in advance and stored in the storage unit 16 .
 この全画素加算モードのケースでは、信号量調整部50の色別デジタルゲイン補正処理部51は、例えば、撮像素子1の立ち上げの初期段階で、記憶部16に記憶されている出力信号量の差分の情報に基づいて、図11におけるbに示すように、相対的に多い方のG(Gr,Gb)の出力信号量に対して、相対的に少ない方のR,Bの出力信号量の出力信号量を増加させて一致させるように、デジタルゲイン補正によって出力信号量の調整を行う。すなわち、このデジタルゲイン補正では、変換効率×加算画素数の差分をR,Bの出力信号量に所定のゲインをかける補正が行われる。 In the case of this all-pixel addition mode, the color-by-color digital gain correction processing unit 51 of the signal amount adjustment unit 50 adjusts the output signal amount stored in the storage unit 16 at the initial stage of startup of the imaging device 1, for example. Based on the difference information, as shown in b in FIG. The output signal amount is adjusted by digital gain correction so that the output signal amount is increased and matched. That is, in this digital gain correction, a correction is performed by multiplying the R and B output signal amounts by a predetermined gain by the difference between the conversion efficiency and the number of pixels to be added.
 この色別デジタルゲイン補正処理による出力信号量の調整により、全画素加算モードの場合における、R,Bの出力信号量とG(Gr,Gb)の出力信号量との差分を吸収し、両者を一致させることができる。その結果、画素ブロック100(100R,100Gr,Gb,100B)の各画素20について、露光時間に比例した出力信号量を得ることができるため、より見やすい撮影画像を得ることができる。 By adjusting the output signal amount by this color-by-color digital gain correction process, the difference between the output signal amount of R and B and the output signal amount of G (Gr, Gb) in the case of all pixel addition mode is absorbed, and both are can be matched. As a result, an output signal amount proportional to the exposure time can be obtained for each pixel 20 of the pixel block 100 (100R, 100Gr, Gb, 100B), so that a more legible photographed image can be obtained.
<2.第2の実施の形態>
 図12は、本技術の第2の実施の形態におけるアナログ-デジタル変換部の一構成例を示す回路図である。第2の実施の形態は、色別の出力信号量の差分を吸収する制御をアナログゲイン補正で行う例である。なお、撮像素子1の全体構成については、上述の第1の実施の形態と同様であるため、詳細な説明は省略する。
<2. Second Embodiment>
FIG. 12 is a circuit diagram showing a configuration example of an analog-digital conversion unit according to the second embodiment of the present technology; The second embodiment is an example in which analog gain correction is performed to absorb the difference in output signal amount for each color. Note that the overall configuration of the imaging device 1 is the same as that of the above-described first embodiment, so detailed description thereof will be omitted.
 上述の第1の実施の形態では、画素ブロック100(100R,100Gr,Gb,100B)の各画素20の信号に対して、シングルスロープ型のアナログ-デジタル変換部31において、アナログ-デジタル変換の際の基準信号として用いられる参照信号RAMPを生成する参照信号生成部14が、各色共通に1個設けられた構成となっている。すなわち、第1の実施の形態では、各色の画素信号に対して、参照信号RAMPの傾きを共通とし、アナログ-デジタル変換部31でアナログ-デジタル変換後のデジタル領域で色別デジタルゲイン補正処理を行う構成となっている。 In the first embodiment described above, the signal of each pixel 20 of the pixel block 100 (100R, 100Gr, Gb, 100B) is subjected to analog-to-digital conversion by the single-slope analog-to-digital converter 31. A single reference signal generator 14 for generating a reference signal RAMP used as a reference signal is provided for each color. That is, in the first embodiment, the slope of the reference signal RAMP is common to the pixel signals of each color, and the digital gain correction process for each color is performed in the digital domain after the analog-to-digital conversion by the analog-to-digital converter 31. It is configured to do
 これに対して、第2の実施の形態では、複数の参照信号生成部14、本例では、R/B用の参照信号生成部14AおよびGr/Gb用の参照信号生成部14Bの2つの参照信号生成部を設けた構成となっている。R/B用の参照信号生成部14Aは、生成するランプ波の参照信号RAMPの傾きで決まるアナログゲインによって、画素ブロック100Rおよび画素ブロック100Bから出力されるR/Bの各色についての出力信号量を調整するための参照信号生成部である。Gr/Gb用の参照信号生成部14Bは、生成するランプ波の参照信号RAMPの傾きで決まるアナログゲインによって、画素ブロック100Grおよび画素ブロック100Gbから出力されるGr/Gbの各色についての出力信号量を調整するための参照信号生成部である。 On the other hand, in the second embodiment, a plurality of reference signal generators 14, in this example, two reference signal generators 14A for R/B and a reference signal generator 14B for Gr/Gb. It has a configuration in which a signal generator is provided. The R/B reference signal generation unit 14A determines the output signal amount for each color of R/B output from the pixel block 100R and the pixel block 100B by analog gain determined by the slope of the generated ramp wave reference signal RAMP. A reference signal generator for adjustment. The Gr/Gb reference signal generation unit 14B calculates the output signal amount for each color of Gr/Gb output from the pixel block 100Gr and the pixel block 100Gb, using an analog gain determined by the slope of the generated ramp wave reference signal RAMP. A reference signal generator for adjustment.
 図12には、信号量調整部50および記憶部16の他に、R/B用のDC発生部19AおよびGr/Gb用のDC発生部19Bも図示されている。R/B用のDC発生部19Aは、R/B用の参照信号生成部14Aから出力されるランプ波の参照信号RAMPに与えるDC(Direct Current:直流)電圧を発生する。Gr/Gb用のDC発生部19Bは、Gr/Gb用の参照信号生成部14Bから出力されるランプ波の参照信号RAMPに与えるDC電圧を発生する。 In addition to the signal amount adjusting section 50 and the storage section 16, FIG. 12 also shows a DC generating section 19A for R/B and a DC generating section 19B for Gr/Gb. The R/B DC generator 19A generates a DC (Direct Current) voltage to be applied to the ramp wave reference signal RAMP output from the R/B reference signal generator 14A. The Gr/Gb DC generator 19B generates a DC voltage to be applied to the ramp wave reference signal RAMP output from the Gr/Gb reference signal generator 14B.
 信号量調整部50は、色別デジタルゲイン補正処理部51を有しており、当該色別デジタルゲイン補正処理部51による補正処理の下に、出荷前段階において予め取得され、記憶部16に記憶されている色別の出力信号量の情報に基づいて、色別の出力信号量の差分を吸収するための補正処理を行う。具体的には、色別デジタルゲイン補正処理部51は、R/B用の参照信号生成部14AおよびGr/Gb用の参照信号生成部14Bのそれぞれで生成されるランプ波の参照信号RAMPの傾きで決まるアナログゲインを制御することにより、色別の出力信号量の差分を吸収するゲイン調整を行う。 The signal amount adjustment unit 50 has a color-by-color digital gain correction processing unit 51. Under the correction processing by the color-by-color digital gain correction processing unit 51, the signal is acquired in advance at the stage before shipment and stored in the storage unit 16. Correction processing for absorbing the difference in the output signal amount for each color is performed based on the information on the output signal amount for each color. Specifically, the color-by-color digital gain correction processing unit 51 adjusts the slope of the ramp wave reference signal RAMP generated by each of the R/B reference signal generation unit 14A and the Gr/Gb reference signal generation unit 14B. By controlling the analog gain determined by the gain adjustment that absorbs the difference in the amount of output signal for each color.
 図13は、高ゲイン時の参照信号RAMPの波形(RAMP波形)、低ゲインの参照信号RAMPの波形、信号線VSLの波形(VSL波形)、および、カウンタ314のクロック(カウンタクロック)のタイミング関係を示す波形図である。図13の波形図において、低ゲイン時は、実線で示すように、RAMP波形の傾きが急峻になり(即ち、1LSBの電圧レベルが大きくなり)、高ゲイン時は、破線で示すように、RAMP波形の傾きが緩やかになる(即ち、1LSBの電圧レベルが小さくなる)。また、低ゲイン時は、カウンタ314のカウント数が相対的に小であり、高ゲイン時は、カウンタ314のカウント数が相対的に大であり、したがって、出力が増えている(即ち、ゲインが掛かる)ことになる。 FIG. 13 shows timing relationships among the waveform of the reference signal RAMP at high gain (RAMP waveform), the waveform of the reference signal RAMP at low gain, the waveform of the signal line VSL (VSL waveform), and the clock of the counter 314 (counter clock). is a waveform diagram showing . In the waveform diagram of FIG. 13, when the gain is low, the slope of the RAMP waveform becomes steep (that is, the voltage level of 1LSB increases) as indicated by the solid line. The slope of the waveform becomes gentler (that is, the voltage level of 1LSB becomes smaller). Also, when the gain is low, the count of the counter 314 is relatively small, and when the gain is high, the count of the counter 314 is relatively large. hanging).
 信号量調整部50の色別デジタルゲイン補正処理部51によって行われる、色別の出力信号量の差分を吸収するための色別デジタルゲイン補正処理についての考え方は、基本的に、第1の実施の形態の場合と同じである。 The concept of the color-by-color digital gain correction processing for absorbing the difference in the output signal amount by color performed by the color-by-color digital gain correction processing unit 51 of the signal amount adjustment unit 50 is basically the same as that of the first embodiment. is the same as for the form of
(全画素読出しモード/AFモードの場合)
 図10におけるaに示すように、全画素読出しモードおよびAFモードの場合、R,Bの出力信号量の方が、G(Gr,Gb)の出力信号量よりも多くなる。このケースでは、信号量調整部50の色別デジタルゲイン補正処理部51は、例えば、撮像素子1の立ち上げの初期段階で、記憶部16に記憶されている出力信号量の差分の情報に基づいて、相対的に多い方のR,Bの出力信号量に対して低ゲインを設定し、相対的に少ない方のG(Gr,Gb)の出力信号量に対して高ゲインを設定する。
(For all pixel readout mode/AF mode)
As indicated by a in FIG. 10, in the all pixel readout mode and the AF mode, the output signal amounts of R and B are larger than the output signal amount of G (Gr, Gb). In this case, the color-by-color digital gain correction processing unit 51 of the signal amount adjustment unit 50, for example, in the initial stage of startup of the imaging device 1, based on the information of the difference in the output signal amount stored in the storage unit 16. A low gain is set for the relatively large R and B output signal amounts, and a high gain is set for the relatively small G (Gr, Gb) output signal amount.
 ここで設定される低ゲインおよび高ゲインは、R/B用の参照信号生成部13AおよびGr/Gb用の参照信号生成部13Bのそれぞれで生成されるランプ波の参照信号RAMPの傾きで決まるアナログゲインである。このゲイン調整により、図10におけるbに示すように、相対的に多い方のR,Bの出力信号量に対して、相対的に少ない方のG(Gr,Gb)の出力信号量を増加させることで、両者を一致させることができる。その結果、画素ブロック100(100R,100Gr,Gb,100B)の各画素20について、露光時間に比例した出力信号量を得ることができるため、より見やすい撮影画像を得ることができる。 The low gain and high gain set here are determined by the slope of the ramp wave reference signal RAMP generated by the R/B reference signal generation unit 13A and the Gr/Gb reference signal generation unit 13B, respectively. is the gain. By this gain adjustment, as shown in b in FIG. 10, the output signal amount of G (Gr, Gb), which is relatively small, is increased with respect to the output signal amount of R, B, which is relatively large. That way you can match the two. As a result, an output signal amount proportional to the exposure time can be obtained for each pixel 20 of the pixel block 100 (100R, 100Gr, Gb, 100B), so that a more legible photographed image can be obtained.
(全画素加算モードの場合)
 図11におけるaに示すように、画素ブロック100(100R,100Gr,Gb,100B)の全画素20の信号を加算して読み出す全画素加算モードの場合には、G(Gr,Gb)の出力信号量の方が、R,Bの出力信号量よりも多くなる。このケースでは、信号量調整部50の色別デジタルゲイン補正処理部51は、撮像素子1の立ち上げの初期段階で、記憶部16に記憶されている出力信号量の差分の情報に基づいて、相対的に多い方のG(Gr,Gb)の出力信号量に対して低ゲインを設定し、相対的に少ない方のR,Bの出力信号量に対して高ゲインを設定する。
(For all pixel addition mode)
As shown by a in FIG. 11, in the case of the all-pixel addition mode in which the signals of all the pixels 20 of the pixel block 100 (100R, 100Gr, Gb, 100B) are added and read out, the output signal of G (Gr, Gb) is is greater than the R and B output signal amounts. In this case, the color-specific digital gain correction processing unit 51 of the signal amount adjustment unit 50, based on the information on the difference in the output signal amount stored in the storage unit 16, at the initial stage of startup of the imaging device 1, A low gain is set for the relatively large G (Gr, Gb) output signal amount, and a high gain is set for the relatively small R and B output signal amounts.
 このゲイン調整により、図11におけるbに示すように、相対的に多い方のG(Gr,Gb)の出力信号量に対して、相対的に少ない方のR,Bの出力信号量を増加させることで、両者を一致させることができる。その結果、画素ブロック100(100R,100Gr,Gb,100B)の各画素20について、露光時間に比例した出力信号量を得ることができるため、より見やすい撮影画像を得ることができる。 By this gain adjustment, as shown in b in FIG. 11, the output signal amount of R and B, which are relatively small, is increased with respect to the output signal amount of G (Gr, Gb), which is relatively large. That way you can match the two. As a result, an output signal amount proportional to the exposure time can be obtained for each pixel 20 of the pixel block 100 (100R, 100Gr, Gb, 100B), so that a more legible photographed image can be obtained.
<3.変形例>
 なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は、実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。
<3. Variation>
In addition, the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the scope of claims have corresponding relationships. Similarly, the matters specifying the invention in the scope of claims and the matters in the embodiments of the present technology with the same names have corresponding relationships. However, the present technology is not limited to the embodiments, and can be embodied by various modifications to the embodiments without departing from the scope of the present technology.
<4.電子機器への適用例>
 以上説明した本技術の実施の形態に係る撮像素子については、デジタルスチルカメラやビデオカメラ等の撮像装置や、携帯電話機などの撮像機能を有する携帯端末装置や、画像読取部に撮像装置を用いる複写機などの撮像機能を備えた種々の電子機器に適用することができる。
<4. Examples of application to electronic devices>
The image pickup device according to the embodiments of the present technology described above includes image pickup devices such as digital still cameras and video cameras, mobile terminal devices having an image pickup function such as mobile phones, and copying devices using an image pickup device as an image reading unit. It can be applied to various electronic devices having an imaging function such as a camera.
(撮像装置の例)
 図14は、本技術を適用した電子機器の一例である撮像装置の一構成例を示すブロック図である。
(Example of imaging device)
FIG. 14 is a block diagram showing a configuration example of an imaging device, which is an example of electronic equipment to which the present technology is applied.
 本適用例に係る撮像素子200は、被写体を撮像するための装置であり、レンズ群等を含む撮像光学系201、撮像部202、DSP(Digital Signal Processor)回路203、表示部204、操作部205、記憶部206、および、電源部207を備える。これらは、バス配線208によって相互に接続される。撮像素子200としては、例えば、デジタルスチルカメラなどのデジタルカメラの他、撮像機能を持つスマートフォンやパーソナルコンピュータ、車載カメラ等が想定される。 An imaging device 200 according to this application example is a device for imaging a subject, and includes an imaging optical system 201 including a lens group and the like, an imaging unit 202, a DSP (Digital Signal Processor) circuit 203, a display unit 204, and an operation unit 205. , a storage unit 206 and a power supply unit 207 . These are interconnected by bus wiring 208 . As the imaging element 200, for example, in addition to a digital camera such as a digital still camera, a smart phone, a personal computer, an in-vehicle camera, and the like having an imaging function are assumed.
 撮像部202は、光電変換によって画素データを生成するものである。この撮像部202として、先述した実施の形態に係る撮像素子が用いられる。撮像部202には、入射光側に配された撮像光学系201によって、被写体からの光が集光されてその受光面に導かれる。撮像部202は、光電変換によって生成した画素データを後段のDSP回路203に供給する。 The imaging unit 202 generates pixel data by photoelectric conversion. As the imaging unit 202, the imaging device according to the above-described embodiment is used. In the imaging unit 202, the light from the subject is condensed by the imaging optical system 201 arranged on the incident light side and guided to its light receiving surface. The imaging unit 202 supplies pixel data generated by photoelectric conversion to the downstream DSP circuit 203 .
 DSP回路203は、撮像部202からの画素データに対して所定の信号処理を実行するものである。表示部204は、画素データを表示するものである。表示部204としては、例えば、液晶パネルや有機EL(Electro Luminescence)パネルが想定される。操作部205は、ユーザの操作にしたがって操作信号を生成するものである。記憶部206は、画素データなどの様々なデータを記憶するものである。電源部207は、撮像部202、DSP回路203、および、表示部204などに電源を供給するものである。 The DSP circuit 203 executes predetermined signal processing on the pixel data from the imaging unit 202 . The display unit 204 displays pixel data. As the display unit 204, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed. The operation unit 205 generates an operation signal according to a user's operation. The storage unit 206 stores various data such as pixel data. The power supply unit 207 supplies power to the imaging unit 202, the DSP circuit 203, the display unit 204, and the like.
<5.本技術の実施の形態の適用例>
 上述の本技術の実施の形態は、以下に例示するように様々な技術に適用することができる。
<5. Application Example of Embodiment of Present Technology>
Embodiments of the present technology described above can be applied to various technologies as exemplified below.
 図15は、本技術の実施の形態が適用される分野の例を示す図である。 FIG. 15 is a diagram showing an example of a field to which an embodiment of the present technology is applied.
 本技術の実施の形態における撮像装置は、例えば、デジタルカメラや、カメラ機能付きの携帯機器等の、鑑賞の用に供される画像を撮影する装置として用いられ得る。 The imaging device according to the embodiment of the present technology can be used as a device that captures an image for viewing, such as a digital camera or a mobile device with a camera function.
 また、この撮像装置は、自動停止等の安全運転や運転者の状態の認識等のために自動車の周囲または車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置として用いられ得る。 In addition, this imaging device includes an in-vehicle sensor that captures images of the surroundings and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's state, a surveillance camera that monitors running vehicles and roads, and an image sensor between vehicles. It can be used as a device for transportation, such as a ranging sensor that measures the distance of a vehicle.
 また、この撮像装置は、ユーザのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、テレビ、冷蔵庫、エアーコンディショナ等の家電に供される装置として用いられ得る。 In addition, this imaging device can be used as a device for home appliances such as televisions, refrigerators, air conditioners, etc., in order to capture a user's gesture and operate the device according to the gesture.
 また、この撮像装置は、内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置として用いられ得る。 In addition, this imaging device can be used as a device for medical or healthcare purposes, such as an endoscope or an angiographic device that performs angiography by receiving infrared light.
 また、この撮像装置は、防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置として用いられ得る。 In addition, this imaging device can be used as a security device such as a monitoring camera for crime prevention and a camera for personal authentication.
 また、この撮像装置は、肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供される装置として用いられ得る。 In addition, this imaging device can be used as a device used for beauty, such as a skin measuring instrument for photographing the skin and a microscope for photographing the scalp.
 また、この撮像装置は、スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置として用いられ得る。 Also, this imaging device can be used as a device for sports, such as an action camera or wearable camera for sports.
 また、この撮像装置は、畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置として用いられ得る。 In addition, this imaging device can be used as an agricultural device such as a camera for monitoring the state of fields and crops.
 <6.移動体への応用例>
 本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。
<6. Example of application to a moving object>
The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
 図16は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
 車両制御システム12000は、通信ネットワーク12001を介して接続された複数の電子制御ユニットを備える。図16に示した例では、車両制御システム12000は、駆動系制御ユニット12010、ボディ系制御ユニット12020、車外情報検出ユニット12030、車内情報検出ユニット12040、及び統合制御ユニット12050を備える。また、統合制御ユニット12050の機能構成として、マイクロコンピュータ12051、音声画像出力部12052、及び車載ネットワークI/F(interface)12053が図示されている。 A vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 16, the vehicle control system 12000 includes a drive train control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. Also, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
 駆動系制御ユニット12010は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット12010は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
 ボディ系制御ユニット12020は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット12020は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット12020には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット12020は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps. In this case, body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
 車外情報検出ユニット12030は、車両制御システム12000を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット12030には、撮像部12031が接続される。車外情報検出ユニット12030は、撮像部12031に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット12030は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 . The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
 撮像部12031は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部12031は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部12031が受光する光は、可視光であっても良いし、赤外線等の非可視光であっても良い。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
 車内情報検出ユニット12040は、車内の情報を検出する。車内情報検出ユニット12040には、例えば、運転者の状態を検出する運転者状態検出部12041が接続される。運転者状態検出部12041は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット12040は、運転者状態検出部12041から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The in-vehicle information detection unit 12040 detects in-vehicle information. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
 マイクロコンピュータ12051は、車外情報検出ユニット12030又は車内情報検出ユニット12040で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット12010に対して制御指令を出力することができる。例えば、マイクロコンピュータ12051は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むADAS(Advanced Driver Assistance System)の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit. A control command can be output to 12010 . For example, the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of
 また、マイクロコンピュータ12051は、車外情報検出ユニット12030又は車内情報検出ユニット12040で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 In addition, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
 また、マイクロコンピュータ12051は、車外情報検出ユニット12030で取得される車外の情報に基づいて、ボディ系制御ユニット12020に対して制御指令を出力することができる。例えば、マイクロコンピュータ12051は、車外情報検出ユニット12030で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 Also, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
 音声画像出力部12052は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図16の例では、出力装置として、オーディオスピーカ12061、表示部12062及びインストルメントパネル12063が例示されている。表示部12062は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle. In the example of FIG. 16, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.
 図17は、撮像部12031の設置位置の例を示す図である。 FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031. FIG.
 図17では、撮像部12031として、撮像部12101,12102,12103,12104,12105を有する。 In FIG. 17, the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
 撮像部12101,12102,12103,12104,12105は、例えば、車両12100のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部12101及び車室内のフロントガラスの上部に備えられる撮像部12105は、主として車両12100の前方の画像を取得する。サイドミラーに備えられる撮像部12102,12103は、主として車両12100の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部12104は、主として車両12100の後方の画像を取得する。車室内のフロントガラスの上部に備えられる撮像部12105は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield in the vehicle interior, for example. An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 . Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 . An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 . The imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
 なお、図17には、撮像部12101ないし12104の撮影範囲の一例が示されている。撮像範囲12111は、フロントノーズに設けられた撮像部12101の撮像範囲を示し、撮像範囲12112,12113は、それぞれサイドミラーに設けられた撮像部12102,12103の撮像範囲を示し、撮像範囲12114は、リアバンパ又はバックドアに設けられた撮像部12104の撮像範囲を示す。例えば、撮像部12101ないし12104で撮像された画像データが重ね合わせられることにより、車両12100を上方から見た俯瞰画像が得られる。 Note that FIG. 17 shows an example of the imaging range of the imaging units 12101 to 12104. FIG. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of an imaging unit 12104 provided in the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
 撮像部12101ないし12104の少なくとも1つは、距離情報を取得する機能を有していてもよい。例えば、撮像部12101ないし12104の少なくとも1つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
 例えば、マイクロコンピュータ12051は、撮像部12101ないし12104から得られた距離情報を基に、撮像範囲12111ないし12114内における各立体物までの距離と、この距離の時間的変化(車両12100に対する相対速度)を求めることにより、特に車両12100の進行路上にある最も近い立体物で、車両12100と略同じ方向に所定の速度(例えば、0km/h以上)で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ12051は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御(追従停止制御も含む)や自動加速制御(追従発進制御も含む)等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the course of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
 例えば、マイクロコンピュータ12051は、撮像部12101ないし12104から得られた距離情報を元に、立体物に関する立体物データを、2輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ12051は、車両12100の周辺の障害物を、車両12100のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ12051は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ12061や表示部12062を介してドライバに警報を出力することや、駆動系制御ユニット12010を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
 撮像部12101ないし12104の少なくとも1つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ12051は、撮像部12101ないし12104の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部12101ないし12104の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ12051が、撮像部12101ないし12104の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部12052は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部12062を制御する。また、音声画像出力部12052は、歩行者を示すアイコン等を所望の位置に表示するように表示部12062を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 . Such recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. This is done by a procedure that determines When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
 以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、例えば、撮像部12031に適用され得る。具体的には、図1の撮像素子1は、撮像部12031に適用することができる。撮像部12031に本開示に係る技術を適用することにより、露光時間に比例した出力信号量を得ることができ、より見やすい撮影画像を得ることができるため、ドライバの疲労を軽減することが可能になる。 An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, the imaging device 1 in FIG. 1 can be applied to the imaging unit 12031 . By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain an output signal amount proportional to the exposure time, and to obtain a more viewable photographed image, thereby reducing driver fatigue. Become.
 なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。 It should be noted that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the scope of claims have corresponding relationships. Similarly, the matters specifying the invention in the scope of claims and the matters in the embodiments of the present technology with the same names have corresponding relationships. However, the present technology is not limited to the embodiments, and can be embodied by various modifications to the embodiments without departing from the scope of the present technology.
 なお、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。 It should be noted that the effects described in this specification are only examples and are not limited, and other effects may also occur.
<7.本技術がとることができる構成>
 なお、本技術は以下のような構成もとることができる。
(1)それぞれが、互いに同じ第1の色のカラーフィルタを含む複数の画素を有する第1の画素ブロックと、
 それぞれが、互いに同じで、かつ、前記第1の画素ブロックと異なる第2の色のカラーフィルタを含む複数の画素を有し、画素数が前記第1の画素ブロックの画素数と異なる第2の画素ブロックと
を具備し、
 前記第1の画素ブロックおよび前記第2の画素ブロックは、それぞれが、2つの画素を対とする複数の画素ペアを有し、
 前記複数の画素ペアに対応するそれぞれの位置には複数のレンズが設けられており、
 前記第1の画素ブロックおよび前記第2の画素ブロックは、光電変換部で得られた電荷を電圧に変換する電荷電圧変換部以降の画素構成素子を複数の画素間で共有する画素共有の構成となっており、
 前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力される出力信号量を調整する信号量調整部
をさらに具備し、
 前記信号量調整部は、前記第1の画素ブロックから出力される前記第1の色についての出力信号量と、前記第2の画素ブロックから出力される前記第2の色についての出力信号量とが一致するように出力信号量の調整を行う
撮像素子。
(2)前記信号量調整部は、前記第1の画素ブロックから出力される前記第1の色についての出力信号量、および、前記第2の画素ブロックから出力される前記第2の色についての出力信号量に対して、信号量が小さい方の色の出力信号量が、信号量が大きい方の色の出力信号量に一致するように出力信号量の調整を行う
前記(1)に記載の撮像素子。
(3)前記信号量調整部は、前記第1の画素ブロックおよび前記第2の画素ブロックの各画素の信号を個々に読み出す第1の駆動モード、および、前記画素ペアの前記2つの画素の信号を加算して読み出す第2の駆動モードのとき、前記第1の画素ブロックから出力される前記第1の色についての出力信号量に対して、前記第2の画素ブロックから出力される前記第2の色についての出力信号量を一致させるように出力信号量の調整を行う
前記(2)に記載の撮像素子。
(4)前記信号量調整部は、前記第1の画素ブロックおよび前記第2の画素ブロックの全画素の信号を加算して読み出す第3の駆動モードのとき、前記第2の画素ブロックから出力される前記第2の色についての出力信号量に対して、前記第1の画素ブロックから出力される前記第1の色についての出力信号量を一致させるように出力信号量の調整を行う
前記(2)に記載の撮像素子。
(5)前記信号量調整部は、前記出力信号量の調整を、前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力されるアナログ信号をデジタル信号に変換した後のデジタル領域におけるデジタルゲイン調整によって行う
前記(1)に記載の撮像素子。
(6)前記信号量調整部は、色別の出力信号量の調整を、前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力されるアナログ信号をデジタル信号に変換する前のアナログ領域におけるアナログゲイン調整によって行う
前記(1)に記載の撮像素子。
(7)アナログ信号をデジタル信号に変換するアナログ-デジタル変換部は、時間経過に応じて所定の傾きでレベルが変化するランプ波の参照信号を、アナログ-デジタル変換の際の基準信号として用いるシングルスロープ型のアナログ-デジタル変換部であり、
 前記信号量調整部は、前記ランプ波の参照信号の傾きを変えることによってアナログゲイン調整を行う
前記(6)に記載の撮像素子。
(8)前記2つの画素は第1の方向に並設され、
 前記第1の画素ブロックおよび前記第2の画素ブロックのそれぞれにおいて、前記第1の方向と交差する第2の方向に並ぶ2つの前記画素ペアは、前記第1の方向においてずれて配置されている
前記(1)に記載の撮像素子。
(9)それぞれが、互いに同じ第1の色のカラーフィルタを含む複数の画素を有する第1の画素ブロックと、
 それぞれが、互いに同じで、かつ、前記第1の画素ブロックと異なる第2の色のカラーフィルタを含む複数の画素を有し、画素数が前記第1の画素ブロックの画素数と異なる第2の画素ブロックと、
 前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力されるアナログ信号をデジタル信号に変換するアナログ-デジタル変換部と
を具備し、
 前記第1の画素ブロックおよび前記第2の画素ブロックは、それぞれが、2つの画素を対とする複数の画素ペアを有し、
 前記複数の画素ペアに対応するそれぞれの位置には複数のレンズが設けられており、
 前記第1の画素ブロックおよび前記第2の画素ブロックは、光電変換部で得られた電荷を電圧に変換する電荷電圧変換部以降の画素構成素子を複数の画素間で共有する画素共有の構成となっており、
 前記アナログ-デジタル変換部は、参照信号生成部から与えられる前記ランプ波の参照信号を、アナログ-デジタル変換の際の基準信号として用いるシングルスロープ型のアナログ-デジタル変換部であり、
 前記参照信号生成部として、それぞれ、傾きが異なるランプ波の参照信号を生成する複数の参照信号生成部が設けられており、
 前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力される出力信号量を調整する信号量調整部
をさらに具備し、
 前記信号量調整部は、前記複数の参照信号生成部のそれぞれで生成される前記傾きが異なるランプ波の参照信号に基づいて、前記第1の画素ブロックから出力される前記第1の色についての出力信号量と、前記第2の画素ブロックから出力される前記第2の色についての出力信号量とが一致するように出力信号量の調整を行う
撮像素子。
(10)前記複数の参照信号生成部は、前記第1の画素ブロックから出力される前記第1の色についての出力信号量を調整するための参照信号生成部、および、前記第2の画素ブロックから出力される前記第2の色についての出力信号量を調整するための参照信号生成部である
前記(9)に記載の撮像素子。
(11)それぞれが、互いに同じ第1の色のカラーフィルタを含む複数の画素を有する第1の画素ブロックと、
 それぞれが、互いに同じで、かつ、前記第1の画素ブロックと異なる第2の色のカラーフィルタを含む複数の画素を有し、画素数が前記第1の画素ブロックの画素数と異なる第2の画素ブロックと
を具備し、
 前記第1の画素ブロックおよび前記第2の画素ブロックは、それぞれが、2つの画素を対とする複数の画素ペアを有し、
 前記複数の画素ペアに対応するそれぞれの位置には複数のレンズが設けられており、
 前記第1の画素ブロックおよび前記第2の画素ブロックは、光電変換部で得られた電荷を電圧に変換する電荷電圧変換部以降の画素構成素子を複数の画素間で共有する画素共有の構成となっており、
 前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力される出力信号量を調整する信号量調整部
をさらに具備し、
 前記信号量調整部は、前記第1の画素ブロックから出力される前記第1の色についての出力信号量と、前記第2の画素ブロックから出力される前記第2の色についての出力信号量とが一致するように出力信号量の調整を行う
撮像素子を有する電子機器。
<7. Configuration that this technology can take>
Note that the present technology can also have the following configuration.
(1) a first pixel block having a plurality of pixels each including color filters of a first color that are the same as each other;
a second pixel block each having a plurality of pixels including a color filter of a second color that is the same as that of the first pixel block and different from that of the first pixel block; a pixel block;
each of the first pixel block and the second pixel block has a plurality of pixel pairs of two pixels;
A plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs,
The first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage. and
further comprising a signal amount adjustment unit that adjusts an output signal amount output from each pixel of the first pixel block and the second pixel block;
The signal amount adjustment unit adjusts the output signal amount for the first color output from the first pixel block and the output signal amount for the second color output from the second pixel block. image sensor that adjusts the amount of output signal so that
(2) The signal amount adjustment unit adjusts the output signal amount for the first color output from the first pixel block and the output signal amount for the second color output from the second pixel block. The output signal amount is adjusted so that the output signal amount of the color with the smaller signal amount matches the output signal amount of the color with the larger signal amount with respect to the output signal amount. image sensor.
(3) The signal amount adjusting section is configured to set a first drive mode for individually reading signals of pixels of the first pixel block and the second pixel block, and signals of the two pixels of the pixel pair. in the second driving mode in which the second driving mode is read out by adding the second The imaging device according to (2) above, wherein the output signal amount is adjusted so that the output signal amount for each color is matched.
(4) The signal amount adjustment section outputs signals from the second pixel block in a third driving mode for adding and reading signals of all pixels of the first pixel block and the second pixel block. The (2 ).
(5) The signal amount adjustment unit performs the adjustment of the output signal amount in the digital domain after converting the analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal. The imaging device according to (1) above, which is performed by digital gain adjustment in .
(6) The signal amount adjustment unit adjusts the output signal amount for each color before converting the analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal. The imaging device according to (1) above, which is performed by analog gain adjustment in an analog domain.
(7) The analog-to-digital conversion unit, which converts analog signals to digital signals, uses a ramp wave reference signal whose level changes with a predetermined slope as time elapses as a reference signal for analog-to-digital conversion. A slope-type analog-to-digital converter,
The imaging device according to (6), wherein the signal amount adjustment unit performs analog gain adjustment by changing a slope of the reference signal of the ramp wave.
(8) the two pixels are arranged side by side in a first direction;
In each of the first pixel block and the second pixel block, the two pixel pairs aligned in a second direction crossing the first direction are arranged with a shift in the first direction. The imaging device according to (1) above.
(9) a first pixel block having a plurality of pixels each including color filters of the same first color;
a second pixel block each having a plurality of pixels including a color filter of a second color that is the same as that of the first pixel block and different from that of the first pixel block; a pixel block;
an analog-to-digital converter that converts an analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal;
each of the first pixel block and the second pixel block has a plurality of pixel pairs of two pixels;
A plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs,
The first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage. and
The analog-digital conversion unit is a single-slope analog-digital conversion unit that uses the reference signal of the ramp wave provided from the reference signal generation unit as a reference signal for analog-digital conversion,
A plurality of reference signal generators for generating reference signals of ramp waves having different slopes are provided as the reference signal generators,
further comprising a signal amount adjustment unit that adjusts an output signal amount output from each pixel of the first pixel block and the second pixel block;
The signal amount adjustment unit adjusts the first color output from the first pixel block based on the ramp wave reference signals with different slopes generated by the plurality of reference signal generation units. An imaging device that adjusts an output signal amount so that the output signal amount and the output signal amount for the second color output from the second pixel block match.
(10) The plurality of reference signal generation units include a reference signal generation unit for adjusting an output signal amount for the first color output from the first pixel block, and the second pixel block. The imaging device according to (9) above, which is a reference signal generation unit for adjusting the output signal amount for the second color output from.
(11) a first pixel block having a plurality of pixels each including color filters of the same first color;
a second pixel block each having a plurality of pixels including a color filter of a second color that is the same as that of the first pixel block and different from that of the first pixel block; a pixel block;
each of the first pixel block and the second pixel block has a plurality of pixel pairs of two pixels;
A plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs,
The first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage. and
further comprising a signal amount adjustment unit that adjusts an output signal amount output from each pixel of the first pixel block and the second pixel block;
The signal amount adjustment unit adjusts the output signal amount for the first color output from the first pixel block and the output signal amount for the second color output from the second pixel block. An electronic device having an image pickup device that adjusts the output signal amount so that the
 1 撮像素子
 11 画素アレイ部
 12 駆動部
 13 読出部
 14 参照信号生成部
 15 信号処理部
 16 記憶部
 17 撮像制御部
 18 データ受け取り&並べ替え部
 20 画素
 21 光電変換部(フォトダイオード)
 22 転送トランジスタ
 23 電荷電圧変換部
 24 リセットトランジスタ
 25 増幅トランジスタ25
 26 選択トランジスタ
 41,43,44 半導体基板
 50 信号量調整部
 51 色別デジタルゲイン補正処理部
 90 画素ペア
 100(100R,100Gr,100Gb,100B) 画素ブロック
1 Imaging Device 11 Pixel Array Section 12 Driving Section 13 Reading Section 14 Reference Signal Generation Section 15 Signal Processing Section 16 Storage Section 17 Imaging Control Section 18 Data Receiving & Sorting Section 20 Pixel 21 Photoelectric Conversion Section (Photodiode)
22 transfer transistor 23 charge-voltage converter 24 reset transistor 25 amplification transistor 25
26 selection transistor 41, 43, 44 semiconductor substrate 50 signal amount adjustment unit 51 digital gain correction processing unit for each color 90 pixel pair 100 (100R, 100Gr, 100Gb, 100B) pixel block

Claims (11)

  1.  それぞれが、互いに同じ第1の色のカラーフィルタを含む複数の画素を有する第1の画素ブロックと、
     それぞれが、互いに同じで、かつ、前記第1の画素ブロックと異なる第2の色のカラーフィルタを含む複数の画素を有し、画素数が前記第1の画素ブロックの画素数と異なる第2の画素ブロックと
    を具備し、
     前記第1の画素ブロックおよび前記第2の画素ブロックは、それぞれが、2つの画素を対とする複数の画素ペアを有し、
     前記複数の画素ペアに対応するそれぞれの位置には複数のレンズが設けられており、
     前記第1の画素ブロックおよび前記第2の画素ブロックは、光電変換部で得られた電荷を電圧に変換する電荷電圧変換部以降の画素構成素子を複数の画素間で共有する画素共有の構成となっており、
     前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力される出力信号量を調整する信号量調整部
    をさらに具備し、
     前記信号量調整部は、前記第1の画素ブロックから出力される前記第1の色についての出力信号量と、前記第2の画素ブロックから出力される前記第2の色についての出力信号量とが一致するように出力信号量の調整を行う
    撮像素子。
    a first pixel block having a plurality of pixels each including color filters of a first color that are the same as each other;
    a second pixel block each having a plurality of pixels including a color filter of a second color that is the same as that of the first pixel block and different from that of the first pixel block; a pixel block;
    each of the first pixel block and the second pixel block has a plurality of pixel pairs of two pixels;
    A plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs,
    The first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage. and
    further comprising a signal amount adjustment unit that adjusts an output signal amount output from each pixel of the first pixel block and the second pixel block;
    The signal amount adjustment unit adjusts the output signal amount for the first color output from the first pixel block and the output signal amount for the second color output from the second pixel block. image sensor that adjusts the amount of output signal so that
  2.  前記信号量調整部は、前記第1の画素ブロックから出力される前記第1の色についての出力信号量、および、前記第2の画素ブロックから出力される前記第2の色についての出力信号量に対して、信号量が小さい方の色の出力信号量が、信号量が大きい方の色の出力信号量に一致するように出力信号量の調整を行う
    請求項1に記載の撮像素子。
    The signal amount adjustment unit adjusts the output signal amount of the first color output from the first pixel block and the output signal amount of the second color output from the second pixel block. 2. The image pickup device according to claim 1, wherein the output signal amount is adjusted so that the output signal amount of the color with the smaller signal amount matches the output signal amount of the color with the larger signal amount.
  3.  前記信号量調整部は、前記第1の画素ブロックおよび前記第2の画素ブロックの各画素の信号を個々に読み出す第1の駆動モード、および、前記画素ペアの前記2つの画素の信号を加算して読み出す第2の駆動モードのとき、前記第1の画素ブロックから出力される前記第1の色についての出力信号量に対して、前記第2の画素ブロックから出力される前記第2の色についての出力信号量を一致させるように出力信号量の調整を行う
    請求項2に記載の撮像素子。
    The signal amount adjustment unit is configured to perform a first drive mode in which signals of pixels of the first pixel block and the second pixel block are individually read out, and signals of the two pixels of the pixel pair are added. in the second drive mode in which the second color output from the second pixel block is 3. The imaging device according to claim 2, wherein the output signal amount is adjusted so as to match the output signal amount of each.
  4.  前記信号量調整部は、前記第1の画素ブロックおよび前記第2の画素ブロックの全画素の信号を加算して読み出す第3の駆動モードのとき、前記第2の画素ブロックから出力される前記第2の色についての出力信号量に対して、前記第1の画素ブロックから出力される前記第1の色についての出力信号量を一致させるように出力信号量の調整を行う
    請求項2に記載の撮像素子。
    The signal amount adjusting section, in a third drive mode for adding and reading out signals of all pixels of the first pixel block and the second pixel block, outputs the second signal output from the second pixel block. 3. The method according to claim 2, wherein the output signal amount is adjusted so as to match the output signal amount for the first color output from the first pixel block with the output signal amount for the second color. image sensor.
  5.  前記信号量調整部は、前記出力信号量の調整を、前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力されるアナログ信号をデジタル信号に変換した後のデジタル領域におけるデジタルゲイン調整によって行う
    請求項1に記載の撮像素子。
    The signal amount adjustment unit adjusts the output signal amount by digital gain in a digital domain after converting analog signals output from each pixel of the first pixel block and the second pixel block into digital signals. 2. The imaging device according to claim 1, wherein the adjustment is performed.
  6.  前記信号量調整部は、色別の出力信号量の調整を、前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力されるアナログ信号をデジタル信号に変換する前のアナログ領域におけるアナログゲイン調整によって行う
    請求項1に記載の撮像素子。
    The signal amount adjustment unit adjusts the output signal amount for each color in an analog domain before converting the analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal. 2. The imaging device according to claim 1, wherein the adjustment is performed by analog gain adjustment.
  7.  アナログ信号をデジタル信号に変換するアナログ-デジタル変換部は、時間経過に応じて所定の傾きでレベルが変化するランプ波の参照信号を、アナログ-デジタル変換の際の基準信号として用いるシングルスロープ型のアナログ-デジタル変換部であり、
     前記信号量調整部は、前記ランプ波の参照信号の傾きを変えることによってアナログゲイン調整を行う
    請求項6に記載の撮像素子。
    The analog-to-digital converter, which converts analog signals to digital signals, is a single-slope reference signal that uses a ramp wave reference signal whose level changes with the passage of time with a predetermined slope as a reference signal for analog-to-digital conversion. an analog-to-digital converter,
    7. The image pickup device according to claim 6, wherein the signal amount adjustment section performs analog gain adjustment by changing a slope of the reference signal of the ramp wave.
  8.  前記2つの画素は第1の方向に並設され、
     前記第1の画素ブロックおよび前記第2の画素ブロックのそれぞれにおいて、前記第1の方向と交差する第2の方向に並ぶ2つの前記画素ペアは、前記第1の方向においてずれて配置されている
    請求項1に記載の撮像素子。
    the two pixels are arranged side by side in a first direction;
    In each of the first pixel block and the second pixel block, the two pixel pairs aligned in a second direction crossing the first direction are arranged with a shift in the first direction. The imaging device according to claim 1 .
  9.  それぞれが、互いに同じ第1の色のカラーフィルタを含む複数の画素を有する第1の画素ブロックと、
     それぞれが、互いに同じで、かつ、前記第1の画素ブロックと異なる第2の色のカラーフィルタを含む複数の画素を有し、画素数が前記第1の画素ブロックの画素数と異なる第2の画素ブロックと、
     前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力されるアナログ信号をデジタル信号に変換するアナログ-デジタル変換部と
    を具備し、
     前記第1の画素ブロックおよび前記第2の画素ブロックは、それぞれが、2つの画素を対とする複数の画素ペアを有し、
     前記複数の画素ペアに対応するそれぞれの位置には複数のレンズが設けられており、
     前記第1の画素ブロックおよび前記第2の画素ブロックは、光電変換部で得られた電荷を電圧に変換する電荷電圧変換部以降の画素構成素子を複数の画素間で共有する画素共有の構成となっており、
     前記アナログ-デジタル変換部は、参照信号生成部から与えられるランプ波の参照信号を、アナログ-デジタル変換の際の基準信号として用いるシングルスロープ型のアナログ-デジタル変換部であり、
     前記参照信号生成部として、それぞれ、傾きが異なるランプ波の参照信号を生成する複数の参照信号生成部が設けられており、
     前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力される出力信号量を調整する信号量調整部
    をさらに具備し、
     前記信号量調整部は、前記複数の参照信号生成部のそれぞれで生成される前記傾きが異なるランプ波の参照信号に基づいて、前記第1の画素ブロックから出力される前記第1の色についての出力信号量と、前記第2の画素ブロックから出力される前記第2の色についての出力信号量とが一致するように出力信号量の調整を行う
    撮像素子。
    a first pixel block having a plurality of pixels each including color filters of a first color that are the same as each other;
    a second pixel block each having a plurality of pixels including a color filter of a second color that is the same as that of the first pixel block and different from that of the first pixel block; a pixel block;
    an analog-to-digital converter that converts an analog signal output from each pixel of the first pixel block and the second pixel block into a digital signal;
    each of the first pixel block and the second pixel block has a plurality of pixel pairs of two pixels;
    A plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs,
    The first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage. and
    The analog-digital conversion unit is a single-slope analog-digital conversion unit that uses a ramp wave reference signal provided from the reference signal generation unit as a reference signal for analog-digital conversion,
    A plurality of reference signal generators for generating reference signals of ramp waves having different slopes are provided as the reference signal generators,
    further comprising a signal amount adjustment unit that adjusts an output signal amount output from each pixel of the first pixel block and the second pixel block;
    The signal amount adjustment unit adjusts the first color output from the first pixel block based on the ramp wave reference signals with different slopes generated by the plurality of reference signal generation units. An imaging device that adjusts an output signal amount so that the output signal amount and the output signal amount for the second color output from the second pixel block match.
  10.  前記複数の参照信号生成部は、前記第1の画素ブロックから出力される前記第1の色についての出力信号量を調整するための参照信号生成部、および、前記第2の画素ブロックから出力される前記第2の色についての出力信号量を調整するための参照信号生成部である
    請求項9に記載の撮像素子。
    The plurality of reference signal generation units include a reference signal generation unit for adjusting an output signal amount for the first color output from the first pixel block, and a reference signal generation unit for adjusting an output signal amount for the first color output from the first pixel block. 10. The image sensor according to claim 9, which is a reference signal generation unit for adjusting the output signal amount for the second color.
  11.  それぞれが、互いに同じ第1の色のカラーフィルタを含む複数の画素を有する第1の画素ブロックと、
     それぞれが、互いに同じで、かつ、前記第1の画素ブロックと異なる第2の色のカラーフィルタを含む複数の画素を有し、画素数が前記第1の画素ブロックの画素数と異なる第2の画素ブロックと
    を具備し、
     前記第1の画素ブロックおよび前記第2の画素ブロックは、それぞれが、2つの画素を対とする複数の画素ペアを有し、
     前記複数の画素ペアに対応するそれぞれの位置には複数のレンズが設けられており、
     前記第1の画素ブロックおよび前記第2の画素ブロックは、光電変換部で得られた電荷を電圧に変換する電荷電圧変換部以降の画素構成素子を複数の画素間で共有する画素共有の構成となっており、
     前記第1の画素ブロックおよび前記第2の画素ブロックの各画素から出力される出力信号量を調整する信号量調整部
    をさらに具備し、
     前記信号量調整部は、前記第1の画素ブロックから出力される前記第1の色についての出力信号量と、前記第2の画素ブロックから出力される前記第2の色についての出力信号量とが一致するように出力信号量の調整を行う
    撮像素子を有する電子機器。
    a first pixel block having a plurality of pixels each including color filters of a first color that are the same as each other;
    a second pixel block each having a plurality of pixels including a color filter of a second color that is the same as that of the first pixel block and different from that of the first pixel block; a pixel block;
    each of the first pixel block and the second pixel block has a plurality of pixel pairs of two pixels;
    A plurality of lenses are provided at respective positions corresponding to the plurality of pixel pairs,
    The first pixel block and the second pixel block have a pixel-sharing configuration in which a plurality of pixels share pixel constituent elements after the charge-voltage conversion unit that converts the charge obtained by the photoelectric conversion unit into voltage. and
    further comprising a signal amount adjustment unit that adjusts an output signal amount output from each pixel of the first pixel block and the second pixel block;
    The signal amount adjustment unit adjusts the output signal amount for the first color output from the first pixel block and the output signal amount for the second color output from the second pixel block. An electronic device having an image pickup device that adjusts the output signal amount so that the
PCT/JP2022/043667 2022-01-07 2022-11-28 Image capturing element and electronic device WO2023132151A1 (en)

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JP2015201834A (en) * 2014-03-31 2015-11-12 ソニー株式会社 Solid-state imaging apparatus, drive control method and image processing method of the same, and electronic apparatus
JP2016052041A (en) * 2014-09-01 2016-04-11 ソニー株式会社 Solid-state imaging device, signal processing method therefor, and electronic apparatus
JP2020017552A (en) * 2018-07-23 2020-01-30 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device, imaging device, and method of controlling solid-state imaging device

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JP2015002531A (en) * 2013-06-18 2015-01-05 キヤノン株式会社 Imaging apparatus, imaging system, signal processing method, program, storage medium
JP2015201834A (en) * 2014-03-31 2015-11-12 ソニー株式会社 Solid-state imaging apparatus, drive control method and image processing method of the same, and electronic apparatus
JP2016052041A (en) * 2014-09-01 2016-04-11 ソニー株式会社 Solid-state imaging device, signal processing method therefor, and electronic apparatus
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